1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _smuio_11_0_0_SH_MASK_HEADER 22 #define _smuio_11_0_0_SH_MASK_HEADER 23 24 25 // addressBlock: smuio_smuio_SmuSmuioDec 26 //SMUSVI0_TEL_PLANE0 27 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR__SHIFT 0x0 28 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT 0x10 29 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_IDDCOR_MASK 0x000000FFL 30 #define SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK 0x01FF0000L 31 //SMUIO_MCM_CONFIG 32 #define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0 33 #define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2 34 #define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x5 35 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x6 36 #define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L 37 #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000001CL 38 #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000020L 39 #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x000000C0L 40 //CKSVII2C_IC_CON 41 #define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT 0x0 42 #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT 0x1 43 #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT 0x3 44 #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT 0x4 45 #define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5 46 #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT 0x6 47 #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT 0x7 48 #define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT 0x8 49 #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT 0x9 50 #define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK 0x00000001L 51 #define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK 0x00000006L 52 #define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK 0x00000008L 53 #define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK 0x00000010L 54 #define CKSVII2C_IC_CON__IC_RESTART_EN_MASK 0x00000020L 55 #define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK 0x00000040L 56 #define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK 0x00000080L 57 #define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK 0x00000100L 58 #define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK 0x00000200L 59 //CKSVII2C_IC_TAR 60 #define CKSVII2C_IC_TAR__IC_TAR__SHIFT 0x0 61 #define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa 62 #define CKSVII2C_IC_TAR__SPECIAL__SHIFT 0xb 63 #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT 0xc 64 #define CKSVII2C_IC_TAR__IC_TAR_MASK 0x000003FFL 65 #define CKSVII2C_IC_TAR__GC_OR_START_MASK 0x00000400L 66 #define CKSVII2C_IC_TAR__SPECIAL_MASK 0x00000800L 67 #define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK 0x00001000L 68 //CKSVII2C_IC_SAR 69 #define CKSVII2C_IC_SAR__IC_SAR__SHIFT 0x0 70 #define CKSVII2C_IC_SAR__IC_SAR_MASK 0x000003FFL 71 //CKSVII2C_IC_HS_MADDR 72 #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT 0x0 73 #define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK 0x00000007L 74 //CKSVII2C_IC_DATA_CMD 75 #define CKSVII2C_IC_DATA_CMD__DAT__SHIFT 0x0 76 #define CKSVII2C_IC_DATA_CMD__CMD__SHIFT 0x8 77 #define CKSVII2C_IC_DATA_CMD__STOP__SHIFT 0x9 78 #define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa 79 #define CKSVII2C_IC_DATA_CMD__DAT_MASK 0x000000FFL 80 #define CKSVII2C_IC_DATA_CMD__CMD_MASK 0x00000100L 81 #define CKSVII2C_IC_DATA_CMD__STOP_MASK 0x00000200L 82 #define CKSVII2C_IC_DATA_CMD__RESTART_MASK 0x00000400L 83 //CKSVII2C_IC_SS_SCL_HCNT 84 #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT 0x0 85 #define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK 0x0000FFFFL 86 //CKSVII2C_IC_SS_SCL_LCNT 87 #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT 0x0 88 #define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK 0x0000FFFFL 89 //CKSVII2C_IC_FS_SCL_HCNT 90 #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT 0x0 91 #define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK 0x0000FFFFL 92 //CKSVII2C_IC_FS_SCL_LCNT 93 #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT 0x0 94 #define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK 0x0000FFFFL 95 //CKSVII2C_IC_HS_SCL_HCNT 96 #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT 0x0 97 #define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK 0x0000FFFFL 98 //CKSVII2C_IC_HS_SCL_LCNT 99 #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT 0x0 100 #define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK 0x0000FFFFL 101 //CKSVII2C_IC_INTR_STAT 102 #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT 0x0 103 #define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT 0x1 104 #define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT 0x2 105 #define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT 0x3 106 #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT 0x4 107 #define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT 0x5 108 #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT 0x6 109 #define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT 0x7 110 #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT 0x8 111 #define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT 0x9 112 #define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa 113 #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT 0xb 114 #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT 0xc 115 #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd 116 #define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK 0x00000001L 117 #define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK 0x00000002L 118 #define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK 0x00000004L 119 #define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK 0x00000008L 120 #define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L 121 #define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK 0x00000020L 122 #define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK 0x00000040L 123 #define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK 0x00000080L 124 #define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK 0x00000100L 125 #define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK 0x00000200L 126 #define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK 0x00000400L 127 #define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK 0x00000800L 128 #define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK 0x00001000L 129 #define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L 130 //CKSVII2C_IC_INTR_MASK 131 #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT 0x0 132 #define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT 0x1 133 #define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT 0x2 134 #define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT 0x3 135 #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT 0x4 136 #define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT 0x5 137 #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT 0x6 138 #define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT 0x7 139 #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT 0x8 140 #define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT 0x9 141 #define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa 142 #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT 0xb 143 #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT 0xc 144 #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT 0xd 145 #define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK 0x00000001L 146 #define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK 0x00000002L 147 #define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK 0x00000004L 148 #define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK 0x00000008L 149 #define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK 0x00000010L 150 #define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK 0x00000020L 151 #define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK 0x00000040L 152 #define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK 0x00000080L 153 #define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK 0x00000100L 154 #define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK 0x00000200L 155 #define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK 0x00000400L 156 #define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK 0x00000800L 157 #define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK 0x00001000L 158 #define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK 0x00002000L 159 //CKSVII2C_IC_RAW_INTR_STAT 160 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_UNDER__SHIFT 0x0 161 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_OVER__SHIFT 0x1 162 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_FULL__SHIFT 0x2 163 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_OVER__SHIFT 0x3 164 #define CKSVII2C_IC__RAW_INTR_STAT__R_TX_EMPTY__SHIFT 0x4 165 #define CKSVII2C_IC_RAW_INTR_STAT__R_RD_REQ__SHIFT 0x5 166 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_ABRT__SHIFT 0x6 167 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_DONE__SHIFT 0x7 168 #define CKSVII2C_IC_RAW_INTR_STAT__R_ACTIVITY__SHIFT 0x8 169 #define CKSVII2C_IC_RAW_INTR_STAT__R_STOP_DET__SHIFT 0x9 170 #define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET__SHIFT 0xa 171 #define CKSVII2C_IC_RAW_INTR_STAT__R_GEN_CALL__SHIFT 0xb 172 #define CKSVII2C_IC_RAW_INTR_STAT__R_RESTART_DET__SHIFT 0xc 173 #define CKSVII2C_IC_RAW_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd 174 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_UNDER_MASK 0x00000001L 175 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_OVER_MASK 0x00000002L 176 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_FULL_MASK 0x00000004L 177 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_OVER_MASK 0x00000008L 178 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L 179 #define CKSVII2C_IC_RAW_INTR_STAT__R_RD_REQ_MASK 0x00000020L 180 #define CKSVII2C_IC_RAW_INTR_STAT__R_TX_ABRT_MASK 0x00000040L 181 #define CKSVII2C_IC_RAW_INTR_STAT__R_RX_DONE_MASK 0x00000080L 182 #define CKSVII2C_IC_RAW_INTR_STAT__R_ACTIVITY_MASK 0x00000100L 183 #define CKSVII2C_IC_RAW_INTR_STAT__R_STOP_DET_MASK 0x00000200L 184 #define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET_MASK 0x00000400L 185 #define CKSVII2C_IC_RAW_INTR_STAT__R_GEN_CALL_MASK 0x00000800L 186 #define CKSVII2C_IC_RAW_INTR_STAT__R_RESTART_DET_MASK 0x00001000L 187 #define CKSVII2C_IC_RAW_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L 188 //CKSVII2C_IC_RX_TL 189 //CKSVII2C_IC_TX_TL 190 //CKSVII2C_IC_CLR_INTR 191 //CKSVII2C_IC_CLR_RX_UNDER 192 //CKSVII2C_IC_CLR_RX_OVER 193 //CKSVII2C_IC_CLR_TX_OVER 194 //CKSVII2C_IC_CLR_RD_REQ 195 //CKSVII2C_IC_CLR_TX_ABRT 196 //CKSVII2C_IC_CLR_RX_DONE 197 //CKSVII2C_IC_CLR_ACTIVITY 198 #define CKSVII2C_IC_CLR_ACTIVITY__CLR_ACTIVITY__SHIFT 0x0 199 #define CKSVII2C_IC_CLR_ACTIVITY__CLR_ACTIVITY_MASK 0x00000001L 200 //CKSVII2C_IC_CLR_STOP_DET 201 //CKSVII2C_IC_CLR_START_DET 202 //CKSVII2C_IC_CLR_GEN_CALL 203 //CKSVII2C_IC_ENABLE 204 #define CKSVII2C_IC_ENABLE__ENABLE__SHIFT 0x0 205 #define CKSVII2C_IC_ENABLE__ABORT__SHIFT 0x1 206 #define CKSVII2C_IC_ENABLE__ENABLE_MASK 0x00000001L 207 #define CKSVII2C_IC_ENABLE__ABORT_MASK 0x00000002L 208 //CKSVII2C_IC_STATUS 209 #define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT 0x0 210 #define CKSVII2C_IC_STATUS__TFNF__SHIFT 0x1 211 #define CKSVII2C_IC_STATUS__TFE__SHIFT 0x2 212 #define CKSVII2C_IC_STATUS__RFNE__SHIFT 0x3 213 #define CKSVII2C_IC_STATUS__RFF__SHIFT 0x4 214 #define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT 0x5 215 #define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT 0x6 216 #define CKSVII2C_IC_STATUS__ACTIVITY_MASK 0x00000001L 217 #define CKSVII2C_IC_STATUS__TFNF_MASK 0x00000002L 218 #define CKSVII2C_IC_STATUS__TFE_MASK 0x00000004L 219 #define CKSVII2C_IC_STATUS__RFNE_MASK 0x00000008L 220 #define CKSVII2C_IC_STATUS__RFF_MASK 0x00000010L 221 #define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK 0x00000020L 222 #define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK 0x00000040L 223 //CKSVII2C_IC_TXFLR 224 //CKSVII2C_IC_RXFLR 225 //CKSVII2C_IC_SDA_HOLD 226 #define CKSVII2C_IC_SDA_HOLD__IC_SDA_HOLD__SHIFT 0x0 227 #define CKSVII2C_IC_SDA_HOLD__IC_SDA_HOLD_MASK 0x00FFFFFFL 228 //CKSVII2C_IC_TX_ABRT_SOURCE 229 230 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_7B_ADDR_NOACK__SHIFT 0x0 231 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR1_NOACK__SHIFT 0x1 232 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR2_NOACK__SHIFT 0x2 233 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_TXDATA_NOACK__SHIFT 0x3 234 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_7B_ADDR_NOACK_MASK 0x00000001L 235 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR1_NOACK_MASK 0x00000002L 236 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR2_NOACK_MASK 0x00000004L 237 #define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_TXDATA_NOACK_MASK 0x00000008L 238 //CKSVII2C_IC_SLV_DATA_NACK_ONLY 239 //CKSVII2C_IC_DMA_CR 240 //CKSVII2C_IC_DMA_TDLR 241 //CKSVII2C_IC_DMA_RDLR 242 //CKSVII2C_IC_SDA_SETUP 243 #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT 0x0 244 #define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK 0x000000FFL 245 //CKSVII2C_IC_ACK_GENERAL_CALL 246 #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL__SHIFT 0x0 247 #define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL_MASK 0x00000001L 248 //CKSVII2C_IC_ENABLE_STATUS 249 #define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT 0x0 250 #define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_ABORTED__SHIFT 0x1 251 #define CKSVII2C_IC_ENABLE_STATUS__SLV_FIFO_FILLED_AND_FLUSHED__SHIFT 0x2 252 #define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK 0x00000001L 253 #define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_ABORTED_MASK 0x00000002L 254 #define CKSVII2C_IC_ENABLE_STATUS__SLV_FIFO_FILLED_AND_FLUSHED_MASK 0x00000004L 255 //CKSVII2C_IC_FS_SPKLEN 256 #define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN__SHIFT 0x0 257 #define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN_MASK 0x000000FFL 258 //CKSVII2C_IC_HS_SPKLEN 259 #define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN__SHIFT 0x0 260 #define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN_MASK 0x000000FFL 261 //CKSVII2C_IC_CLR_RESTART_DET 262 //CKSVII2C_IC_COMP_PARAM_1 263 #define CKSVII2C_IC_COMP_PARAM_1__COMP_PARAM_1__SHIFT 0x0 264 #define CKSVII2C_IC_COMP_PARAM_1__COMP_PARAM_1_MASK 0xFFFFFFFFL 265 //CKSVII2C_IC_COMP_VERSION 266 #define CKSVII2C_IC_COMP_VERSION__COMP_VERSION__SHIFT 0x0 267 #define CKSVII2C_IC_COMP_VERSION__COMP_VERSION_MASK 0xFFFFFFFFL 268 //CKSVII2C_IC_COMP_TYPE 269 #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT 0x0 270 #define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK 0xFFFFFFFFL 271 //CKSVII2C1_IC_CON 272 #define CKSVII2C1_IC_CON__IC1_MASTER_MODE__SHIFT 0x0 273 #define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE__SHIFT 0x1 274 #define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE__SHIFT 0x3 275 #define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER__SHIFT 0x4 276 #define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT 0x5 277 #define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE__SHIFT 0x6 278 #define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED__SHIFT 0x7 279 #define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL__SHIFT 0x8 280 #define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL__SHIFT 0x9 281 #define CKSVII2C1_IC_CON__IC1_MASTER_MODE_MASK 0x00000001L 282 #define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE_MASK 0x00000006L 283 #define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE_MASK 0x00000008L 284 #define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER_MASK 0x00000010L 285 #define CKSVII2C1_IC_CON__IC1_RESTART_EN_MASK 0x00000020L 286 #define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE_MASK 0x00000040L 287 #define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED_MASK 0x00000080L 288 #define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL_MASK 0x00000100L 289 #define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL_MASK 0x00000200L 290 //CKSVII2C1_IC_TAR 291 #define CKSVII2C1_IC_TAR__IC1_TAR__SHIFT 0x0 292 #define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa 293 #define CKSVII2C1_IC_TAR__SPECIAL1__SHIFT 0xb 294 #define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER__SHIFT 0xc 295 #define CKSVII2C1_IC_TAR__IC1_TAR_MASK 0x000003FFL 296 #define CKSVII2C1_IC_TAR__GC1_OR_START_MASK 0x00000400L 297 #define CKSVII2C1_IC_TAR__SPECIAL1_MASK 0x00000800L 298 #define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER_MASK 0x00001000L 299 //CKSVII2C1_IC_SAR 300 #define CKSVII2C1_IC_SAR__IC1_SAR__SHIFT 0x0 301 #define CKSVII2C1_IC_SAR__IC1_SAR_MASK 0x000003FFL 302 //CKSVII2C1_IC_HS_MADDR 303 #define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR__SHIFT 0x0 304 #define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR_MASK 0x00000007L 305 //CKSVII2C1_IC_DATA_CMD 306 #define CKSVII2C1_IC_DATA_CMD__DAT1__SHIFT 0x0 307 #define CKSVII2C1_IC_DATA_CMD__CMD1__SHIFT 0x8 308 #define CKSVII2C1_IC_DATA_CMD__STOP1__SHIFT 0x9 309 #define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa 310 #define CKSVII2C1_IC_DATA_CMD__DAT1_MASK 0x000000FFL 311 #define CKSVII2C1_IC_DATA_CMD__CMD1_MASK 0x00000100L 312 #define CKSVII2C1_IC_DATA_CMD__STOP1_MASK 0x00000200L 313 #define CKSVII2C1_IC_DATA_CMD__RESTART1_MASK 0x00000400L 314 //CKSVII2C1_IC_SS_SCL_HCNT 315 #define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT__SHIFT 0x0 316 #define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT_MASK 0x0000FFFFL 317 //CKSVII2C1_IC_SS_SCL_LCNT 318 #define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT__SHIFT 0x0 319 #define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT_MASK 0x0000FFFFL 320 //CKSVII2C1_IC_FS_SCL_HCNT 321 #define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT__SHIFT 0x0 322 #define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT_MASK 0x0000FFFFL 323 //CKSVII2C1_IC_FS_SCL_LCNT 324 #define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT__SHIFT 0x0 325 #define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT_MASK 0x0000FFFFL 326 //CKSVII2C1_IC_HS_SCL_HCNT 327 #define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT__SHIFT 0x0 328 #define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT_MASK 0x0000FFFFL 329 //CKSVII2C1_IC_HS_SCL_LCNT 330 #define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT__SHIFT 0x0 331 #define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT_MASK 0x0000FFFFL 332 //CKSVII2C1_IC_INTR_STAT 333 #define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER__SHIFT 0x0 334 #define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER__SHIFT 0x1 335 #define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL__SHIFT 0x2 336 #define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER__SHIFT 0x3 337 #define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY__SHIFT 0x4 338 #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT 0x5 339 #define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT__SHIFT 0x6 340 #define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE__SHIFT 0x7 341 #define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY__SHIFT 0x8 342 #define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET__SHIFT 0x9 343 #define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa 344 #define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL__SHIFT 0xb 345 #define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET__SHIFT 0xc 346 #define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD__SHIFT 0xd 347 #define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER_MASK 0x00000001L 348 #define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER_MASK 0x00000002L 349 #define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL_MASK 0x00000004L 350 #define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER_MASK 0x00000008L 351 #define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY_MASK 0x00000010L 352 #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ_MASK 0x00000020L 353 #define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT_MASK 0x00000040L 354 #define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE_MASK 0x00000080L 355 #define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY_MASK 0x00000100L 356 #define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET_MASK 0x00000200L 357 #define CKSVII2C1_IC_INTR_STAT__R1_START_DET_MASK 0x00000400L 358 #define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL_MASK 0x00000800L 359 #define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET_MASK 0x00001000L 360 #define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD_MASK 0x00002000L 361 //CKSVII2C1_IC_INTR_MASK 362 #define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER__SHIFT 0x0 363 #define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER__SHIFT 0x1 364 #define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL__SHIFT 0x2 365 #define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER__SHIFT 0x3 366 #define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY__SHIFT 0x4 367 #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT 0x5 368 #define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT__SHIFT 0x6 369 #define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE__SHIFT 0x7 370 #define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY__SHIFT 0x8 371 #define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET__SHIFT 0x9 372 #define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa 373 #define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL__SHIFT 0xb 374 #define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET__SHIFT 0xc 375 #define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD__SHIFT 0xd 376 #define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER_MASK 0x00000001L 377 #define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER_MASK 0x00000002L 378 #define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL_MASK 0x00000004L 379 #define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER_MASK 0x00000008L 380 #define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY_MASK 0x00000010L 381 #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ_MASK 0x00000020L 382 #define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT_MASK 0x00000040L 383 #define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE_MASK 0x00000080L 384 #define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY_MASK 0x00000100L 385 #define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET_MASK 0x00000200L 386 #define CKSVII2C1_IC_INTR_MASK__M1_START_DET_MASK 0x00000400L 387 #define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL_MASK 0x00000800L 388 #define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET_MASK 0x00001000L 389 #define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD_MASK 0x00002000L 390 //CKSVII2C1_IC_RAW_INTR_STAT 391 //CKSVII2C1_IC_RX_TL 392 //CKSVII2C1_IC_TX_TL 393 //CKSVII2C1_IC_CLR_INTR 394 //CKSVII2C1_IC_CLR_RX_UNDER 395 //CKSVII2C1_IC_CLR_RX_OVER 396 //CKSVII2C1_IC_CLR_TX_OVER 397 //CKSVII2C1_IC_CLR_RD_REQ 398 //CKSVII2C1_IC_CLR_TX_ABRT 399 //CKSVII2C1_IC_CLR_RX_DONE 400 //CKSVII2C1_IC_CLR_ACTIVITY 401 //CKSVII2C1_IC_CLR_STOP_DET 402 //CKSVII2C1_IC_CLR_START_DET 403 //CKSVII2C1_IC_CLR_GEN_CALL 404 //CKSVII2C1_IC_ENABLE 405 #define CKSVII2C1_IC_ENABLE__ENABLE1__SHIFT 0x0 406 #define CKSVII2C1_IC_ENABLE__ABORT1__SHIFT 0x1 407 #define CKSVII2C1_IC_ENABLE__ENABLE1_MASK 0x00000001L 408 #define CKSVII2C1_IC_ENABLE__ABORT1_MASK 0x00000002L 409 //CKSVII2C1_IC_STATUS 410 #define CKSVII2C1_IC_STATUS__ACTIVITY1__SHIFT 0x0 411 #define CKSVII2C1_IC_STATUS__TFNF1__SHIFT 0x1 412 #define CKSVII2C1_IC_STATUS__TFE1__SHIFT 0x2 413 #define CKSVII2C1_IC_STATUS__RFNE1__SHIFT 0x3 414 #define CKSVII2C1_IC_STATUS__RFF1__SHIFT 0x4 415 #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT 0x5 416 #define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY__SHIFT 0x6 417 #define CKSVII2C1_IC_STATUS__ACTIVITY1_MASK 0x00000001L 418 #define CKSVII2C1_IC_STATUS__TFNF1_MASK 0x00000002L 419 #define CKSVII2C1_IC_STATUS__TFE1_MASK 0x00000004L 420 #define CKSVII2C1_IC_STATUS__RFNE1_MASK 0x00000008L 421 #define CKSVII2C1_IC_STATUS__RFF1_MASK 0x00000010L 422 #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY_MASK 0x00000020L 423 #define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY_MASK 0x00000040L 424 //CKSVII2C1_IC_TXFLR 425 //CKSVII2C1_IC_RXFLR 426 //CKSVII2C1_IC_SDA_HOLD 427 #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_HOLD__SHIFT 0x0 428 #define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_HOLD_MASK 0x00FFFFFFL 429 //CKSVII2C1_IC_TX_ABRT_SOURCE 430 //CKSVII2C1_IC_SLV_DATA_NACK_ONLY 431 //CKSVII2C1_IC_DMA_CR 432 //CKSVII2C1_IC_DMA_TDLR 433 //CKSVII2C1_IC_DMA_RDLR 434 //CKSVII2C1_IC_SDA_SETUP 435 #define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP__SHIFT 0x0 436 #define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP_MASK 0x000000FFL 437 //CKSVII2C1_IC_ACK_GENERAL_CALL 438 #define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL__SHIFT 0x0 439 #define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL_MASK 0x00000001L 440 //CKSVII2C1_IC_ENABLE_STATUS 441 #define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN__SHIFT 0x0 442 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_ABORTED__SHIFT 0x1 443 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_FIFO_FILLED_AND_FLUSHED__SHIFT 0x2 444 #define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN_MASK 0x00000001L 445 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_ABORTED_MASK 0x00000002L 446 #define CKSVII2C1_IC_ENABLE_STATUS__SLV1_FIFO_FILLED_AND_FLUSHED_MASK 0x00000004L 447 //SMUIO_MP_RESET_INTR 448 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0 449 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L 450 //SMUIO_SOC_HALT 451 #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN__SHIFT 0x2 452 #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN__SHIFT 0x3 453 #define SMUIO_SOC_HALT__WDT_FORCE_PWROK_EN_MASK 0x00000004L 454 #define SMUIO_SOC_HALT__WDT_FORCE_RESETn_EN_MASK 0x00000008L 455 //SMUIO_PWRMGT 456 #define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0 457 #define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x4 458 #define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L 459 #define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000010L 460 //ROM_CNTL 461 #define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0 462 #define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x14 463 #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x15 464 #define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x16 465 #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x17 466 #define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 467 #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c 468 #define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L 469 #define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00100000L 470 #define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00200000L 471 #define ROM_CNTL__SPI_FAST_MODE_MASK 0x00400000L 472 #define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00800000L 473 #define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F000000L 474 #define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L 475 //PAGE_MIRROR_CNTL 476 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 477 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 478 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 479 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a 480 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x00FFFFFFL 481 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x01000000L 482 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L 483 #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L 484 //ROM_STATUS 485 #define ROM_STATUS__ROM_BUSY__SHIFT 0x0 486 #define ROM_STATUS__ROM_BUSY_MASK 0x00000001L 487 //CGTT_ROM_CLK_CTRL0 488 #define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 489 #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 490 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 491 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 492 #define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL 493 #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L 494 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L 495 #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L 496 //ROM_INDEX 497 #define ROM_INDEX__ROM_INDEX__SHIFT 0x0 498 #define ROM_INDEX__ROM_INDEX_MASK 0x00FFFFFFL 499 //ROM_DATA 500 #define ROM_DATA__ROM_DATA__SHIFT 0x0 501 #define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL 502 //ROM_START 503 #define ROM_START__ROM_START__SHIFT 0x0 504 #define ROM_START__ROM_START_MASK 0x00FFFFFFL 505 //ROM_SW_CNTL 506 #define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 507 #define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 508 #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 509 #define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL 510 #define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00030000L 511 #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00040000L 512 //ROM_SW_STATUS 513 #define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 514 #define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L 515 //ROM_SW_COMMAND 516 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 517 #define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 518 #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL 519 #define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L 520 //ROM_SW_DATA_1 521 #define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 522 #define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL 523 //ROM_SW_DATA_2 524 #define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 525 #define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL 526 //ROM_SW_DATA_3 527 #define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 528 #define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL 529 //ROM_SW_DATA_4 530 #define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 531 #define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL 532 //ROM_SW_DATA_5 533 #define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 534 #define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL 535 //ROM_SW_DATA_6 536 #define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 537 #define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL 538 //ROM_SW_DATA_7 539 #define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 540 #define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL 541 //ROM_SW_DATA_8 542 #define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 543 #define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL 544 //ROM_SW_DATA_9 545 #define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 546 #define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL 547 //ROM_SW_DATA_10 548 #define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 549 #define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL 550 //ROM_SW_DATA_11 551 #define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 552 #define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL 553 //ROM_SW_DATA_12 554 #define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 555 #define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL 556 //ROM_SW_DATA_13 557 #define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 558 #define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL 559 //ROM_SW_DATA_14 560 #define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 561 #define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL 562 //ROM_SW_DATA_15 563 #define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 564 #define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL 565 //ROM_SW_DATA_16 566 #define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 567 #define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL 568 //ROM_SW_DATA_17 569 #define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 570 #define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL 571 //ROM_SW_DATA_18 572 #define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 573 #define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL 574 //ROM_SW_DATA_19 575 #define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 576 #define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL 577 //ROM_SW_DATA_20 578 #define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 579 #define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL 580 //ROM_SW_DATA_21 581 #define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 582 #define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL 583 //ROM_SW_DATA_22 584 #define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 585 #define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL 586 //ROM_SW_DATA_23 587 #define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 588 #define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL 589 //ROM_SW_DATA_24 590 #define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 591 #define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL 592 //ROM_SW_DATA_25 593 #define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 594 #define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL 595 //ROM_SW_DATA_26 596 #define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 597 #define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL 598 //ROM_SW_DATA_27 599 #define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 600 #define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL 601 //ROM_SW_DATA_28 602 #define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 603 #define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL 604 //ROM_SW_DATA_29 605 #define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 606 #define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL 607 //ROM_SW_DATA_30 608 #define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 609 #define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL 610 //ROM_SW_DATA_31 611 #define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 612 #define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL 613 //ROM_SW_DATA_32 614 #define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 615 #define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL 616 //ROM_SW_DATA_33 617 #define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 618 #define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL 619 //ROM_SW_DATA_34 620 #define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 621 #define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL 622 //ROM_SW_DATA_35 623 #define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 624 #define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL 625 //ROM_SW_DATA_36 626 #define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 627 #define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL 628 //ROM_SW_DATA_37 629 #define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 630 #define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL 631 //ROM_SW_DATA_38 632 #define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 633 #define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL 634 //ROM_SW_DATA_39 635 #define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 636 #define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL 637 //ROM_SW_DATA_40 638 #define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 639 #define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL 640 //ROM_SW_DATA_41 641 #define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 642 #define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL 643 //ROM_SW_DATA_42 644 #define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 645 #define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL 646 //ROM_SW_DATA_43 647 #define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 648 #define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL 649 //ROM_SW_DATA_44 650 #define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 651 #define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL 652 //ROM_SW_DATA_45 653 #define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 654 #define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL 655 //ROM_SW_DATA_46 656 #define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 657 #define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL 658 //ROM_SW_DATA_47 659 #define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 660 #define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL 661 //ROM_SW_DATA_48 662 #define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 663 #define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL 664 //ROM_SW_DATA_49 665 #define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 666 #define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL 667 //ROM_SW_DATA_50 668 #define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 669 #define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL 670 //ROM_SW_DATA_51 671 #define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 672 #define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL 673 //ROM_SW_DATA_52 674 #define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 675 #define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL 676 //ROM_SW_DATA_53 677 #define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 678 #define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL 679 //ROM_SW_DATA_54 680 #define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 681 #define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL 682 //ROM_SW_DATA_55 683 #define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 684 #define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL 685 //ROM_SW_DATA_56 686 #define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 687 #define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL 688 //ROM_SW_DATA_57 689 #define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 690 #define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL 691 //ROM_SW_DATA_58 692 #define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 693 #define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL 694 //ROM_SW_DATA_59 695 #define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 696 #define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL 697 //ROM_SW_DATA_60 698 #define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 699 #define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL 700 //ROM_SW_DATA_61 701 #define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 702 #define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL 703 //ROM_SW_DATA_62 704 #define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 705 #define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL 706 //ROM_SW_DATA_63 707 #define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 708 #define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL 709 //ROM_SW_DATA_64 710 #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 711 #define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL 712 //SMU_GPIOPAD_SW_INT_STAT 713 #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 714 #define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L 715 //SMU_GPIOPAD_MASK 716 #define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 717 #define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL 718 //SMU_GPIOPAD_A 719 #define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0 720 #define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL 721 //SMU_GPIOPAD_TXIMPSEL 722 #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0 723 #define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL 724 //SMU_GPIOPAD_EN 725 #define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0 726 #define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL 727 //SMU_GPIOPAD_Y 728 #define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0 729 #define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL 730 //SMU_GPIOPAD_RXEN 731 #define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0 732 #define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL 733 //SMU_GPIOPAD_RCVR_SEL0 734 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0 735 #define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL 736 //SMU_GPIOPAD_RCVR_SEL1 737 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0 738 #define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL 739 //SMU_GPIOPAD_PU_EN 740 #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 741 #define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL 742 //SMU_GPIOPAD_PD_EN 743 #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 744 #define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL 745 //SMU_GPIOPAD_PINSTRAPS 746 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 747 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 748 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 749 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 750 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 751 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 752 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 753 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 754 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 755 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 756 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa 757 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb 758 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc 759 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd 760 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe 761 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf 762 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 763 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 764 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 765 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 766 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 767 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 768 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 769 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 770 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 771 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 772 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a 773 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b 774 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c 775 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d 776 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e 777 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L 778 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L 779 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L 780 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L 781 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L 782 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L 783 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L 784 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L 785 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L 786 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L 787 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L 788 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L 789 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L 790 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L 791 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L 792 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L 793 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L 794 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L 795 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L 796 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L 797 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L 798 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L 799 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L 800 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L 801 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L 802 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L 803 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L 804 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L 805 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L 806 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L 807 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L 808 //DFT_PINSTRAPS 809 #define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0 810 #define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000000FFL 811 //SMU_GPIOPAD_INT_STAT_EN 812 #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 813 #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f 814 #define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL 815 #define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L 816 //SMU_GPIOPAD_INT_STAT 817 #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 818 #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f 819 #define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL 820 #define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L 821 //SMU_GPIOPAD_INT_STAT_AK 822 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 823 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 824 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 825 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 826 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 827 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 828 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 829 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 830 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 831 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 832 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa 833 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb 834 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc 835 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd 836 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe 837 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf 838 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 839 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 840 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 841 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 842 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 843 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 844 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 845 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 846 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 847 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 848 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a 849 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b 850 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c 851 #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f 852 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L 853 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L 854 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L 855 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L 856 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L 857 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L 858 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L 859 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L 860 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L 861 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L 862 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L 863 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L 864 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L 865 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L 866 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L 867 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L 868 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L 869 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L 870 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L 871 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L 872 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L 873 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L 874 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L 875 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L 876 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L 877 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L 878 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L 879 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L 880 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L 881 #define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L 882 //SMU_GPIOPAD_INT_EN 883 #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 884 #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f 885 #define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL 886 #define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L 887 //SMU_GPIOPAD_INT_TYPE 888 #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 889 #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f 890 #define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL 891 #define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L 892 //SMU_GPIOPAD_INT_POLARITY 893 #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 894 #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f 895 #define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL 896 #define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L 897 //ROM_CC_BIF_PINSTRAP 898 #define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN__SHIFT 0x0 899 #define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE__SHIFT 0x1 900 #define ROM_CC_BIF_PINSTRAP__ROM_CONFIG__SHIFT 0x4 901 #define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A__SHIFT 0x7 902 #define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN__SHIFT 0x8 903 #define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS__SHIFT 0x9 904 #define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING__SHIFT 0xa 905 #define ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN_MASK 0x00000001L 906 #define ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_MASK 0x0000000EL 907 #define ROM_CC_BIF_PINSTRAP__ROM_CONFIG_MASK 0x00000070L 908 #define ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A_MASK 0x00000080L 909 #define ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN_MASK 0x00000100L 910 #define ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_MASK 0x00000200L 911 #define ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING_MASK 0x00000400L 912 //IO_SMUIO_PINSTRAP 913 #define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x0 914 #define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x3 915 #define IO_SMUIO_PINSTRAP__BOARD_CONFIG__SHIFT 0x5 916 #define IO_SMUIO_PINSTRAP__SMBUS_ADDR__SHIFT 0x8 917 #define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L 918 #define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L 919 #define IO_SMUIO_PINSTRAP__BOARD_CONFIG_MASK 0x000000E0L 920 #define IO_SMUIO_PINSTRAP__SMBUS_ADDR_MASK 0x00000100L 921 //SMUIO_PCC_CONTROL 922 #define SMUIO_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0 923 #define SMUIO_PCC_CONTROL__PCC_POLARITY_MASK 0x00000001L 924 //SMUIO_PCC_GPIO_SELECT 925 #define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 926 #define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL 927 //SMUIO_GPIO_INT0_SELECT 928 #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0 929 #define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL 930 //SMUIO_GPIO_INT1_SELECT 931 #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0 932 #define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL 933 //SMUIO_GPIO_INT2_SELECT 934 #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0 935 #define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL 936 //SMUIO_GPIO_INT3_SELECT 937 #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0 938 #define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL 939 //SMU_GPIOPAD_MP_INT0_STAT 940 #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0 941 #define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL 942 //SMU_GPIOPAD_MP_INT1_STAT 943 #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0 944 #define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL 945 //SMU_GPIOPAD_MP_INT2_STAT 946 #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0 947 #define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL 948 //SMU_GPIOPAD_MP_INT3_STAT 949 #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0 950 #define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL 951 //SMIO_INDEX 952 #define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0 953 #define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L 954 //S0_VID_SMIO_CNTL 955 #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0 956 #define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL 957 //S1_VID_SMIO_CNTL 958 #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0 959 #define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL 960 //OPEN_DRAIN_SELECT 961 #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0 962 #define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f 963 #define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL 964 #define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L 965 //SMIO_ENABLE 966 #define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0 967 #define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL 968 //SMU_GPIOPAD_S0 969 #define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0 970 #define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL 971 //SMU_GPIOPAD_S1 972 #define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0 973 #define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL 974 //SMU_GPIOPAD_SCL_EN 975 #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0 976 #define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL 977 //SMU_GPIOPAD_SDA_EN 978 #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0 979 #define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL 980 //SMU_GPIOPAD_SCHMEN 981 #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0 982 #define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL 983 984 985 // addressBlock: smuio_smuio_pwr_SmuSmuioDec 986 //IP_DISCOVERY_VERSION 987 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0 988 #define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL 989 //SOC_GAP_PWROK 990 #define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0 991 #define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L 992 //GFX_GAP_PWROK 993 #define GFX_GAP_PWROK__gfx_gap_pwrok__SHIFT 0x0 994 #define GFX_GAP_PWROK__gfx_gap_pwrok_MASK 0x00000001L 995 //PWROK_REFCLK_GAP_CYCLES 996 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0 997 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8 998 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL 999 #define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L 1000 //GOLDEN_TSC_INCREMENT_UPPER 1001 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0 1002 #define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL 1003 //GOLDEN_TSC_INCREMENT_LOWER 1004 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0 1005 #define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL 1006 //GOLDEN_TSC_COUNT_UPPER 1007 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0 1008 #define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL 1009 //GOLDEN_TSC_COUNT_LOWER 1010 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0 1011 #define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL 1012 //SOC_GOLDEN_TSC_SHADOW_UPPER 1013 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper__SHIFT 0x0 1014 #define SOC_GOLDEN_TSC_SHADOW_UPPER__SOCGoldenTscShadowUpper_MASK 0x00FFFFFFL 1015 //SOC_GOLDEN_TSC_SHADOW_LOWER 1016 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower__SHIFT 0x0 1017 #define SOC_GOLDEN_TSC_SHADOW_LOWER__SOCGoldenTscShadowLower_MASK 0xFFFFFFFFL 1018 //GFX_GOLDEN_TSC_SHADOW_UPPER 1019 #define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper__SHIFT 0x0 1020 #define GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper_MASK 0x00FFFFFFL 1021 //GFX_GOLDEN_TSC_SHADOW_LOWER 1022 #define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower__SHIFT 0x0 1023 #define GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower_MASK 0xFFFFFFFFL 1024 //PWR_VIRT_RESET_REQ 1025 #define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 1026 #define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f 1027 #define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL 1028 #define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L 1029 //SCRATCH_REGISTER0 1030 #define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0 1031 #define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL 1032 //SCRATCH_REGISTER1 1033 #define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0 1034 #define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL 1035 //SCRATCH_REGISTER2 1036 #define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0 1037 #define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL 1038 //SCRATCH_REGISTER3 1039 #define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0 1040 #define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL 1041 //SCRATCH_REGISTER4 1042 #define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0 1043 #define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL 1044 //SCRATCH_REGISTER5 1045 #define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0 1046 #define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL 1047 //SCRATCH_REGISTER6 1048 #define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0 1049 #define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL 1050 //SCRATCH_REGISTER7 1051 #define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0 1052 #define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL 1053 //PWR_DISP_TIMER_CONTROL 1054 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 1055 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 1056 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 1057 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 1058 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 1059 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 1060 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 1061 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 1062 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 1063 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 1064 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 1065 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 1066 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 1067 #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 1068 //PWR_DISP_TIMER2_CONTROL 1069 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 1070 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 1071 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 1072 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 1073 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 1074 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 1075 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 1076 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL 1077 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 1078 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L 1079 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L 1080 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L 1081 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L 1082 #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L 1083 //PWR_DISP_TIMER_GLOBAL_CONTROL 1084 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 1085 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa 1086 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL 1087 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L 1088 //PWR_IH_CONTROL 1089 #define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0 1090 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5 1091 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6 1092 #define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL 1093 #define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L 1094 #define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L 1095 1096 #endif 1097