1*8630f839SAlex Deucher /* 2*8630f839SAlex Deucher * UVD_4_2 Register documentation 3*8630f839SAlex Deucher * 4*8630f839SAlex Deucher * Copyright (C) 2014 Advanced Micro Devices, Inc. 5*8630f839SAlex Deucher * 6*8630f839SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 7*8630f839SAlex Deucher * copy of this software and associated documentation files (the "Software"), 8*8630f839SAlex Deucher * to deal in the Software without restriction, including without limitation 9*8630f839SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10*8630f839SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 11*8630f839SAlex Deucher * Software is furnished to do so, subject to the following conditions: 12*8630f839SAlex Deucher * 13*8630f839SAlex Deucher * The above copyright notice and this permission notice shall be included 14*8630f839SAlex Deucher * in all copies or substantial portions of the Software. 15*8630f839SAlex Deucher * 16*8630f839SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17*8630f839SAlex Deucher * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18*8630f839SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19*8630f839SAlex Deucher * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20*8630f839SAlex Deucher * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21*8630f839SAlex Deucher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22*8630f839SAlex Deucher */ 23*8630f839SAlex Deucher 24*8630f839SAlex Deucher #ifndef UVD_4_2_SH_MASK_H 25*8630f839SAlex Deucher #define UVD_4_2_SH_MASK_H 26*8630f839SAlex Deucher 27*8630f839SAlex Deucher #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28*8630f839SAlex Deucher #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29*8630f839SAlex Deucher #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30*8630f839SAlex Deucher #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31*8630f839SAlex Deucher #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32*8630f839SAlex Deucher #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33*8630f839SAlex Deucher #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34*8630f839SAlex Deucher #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35*8630f839SAlex Deucher #define UVD_SEMA_CMD__MODE_MASK 0x40 36*8630f839SAlex Deucher #define UVD_SEMA_CMD__MODE__SHIFT 0x6 37*8630f839SAlex Deucher #define UVD_SEMA_CMD__VMID_EN_MASK 0x80 38*8630f839SAlex Deucher #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 39*8630f839SAlex Deucher #define UVD_SEMA_CMD__VMID_MASK 0xf00 40*8630f839SAlex Deucher #define UVD_SEMA_CMD__VMID__SHIFT 0x8 41*8630f839SAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 42*8630f839SAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 43*8630f839SAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe 44*8630f839SAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 45*8630f839SAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 46*8630f839SAlex Deucher #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 47*8630f839SAlex Deucher #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff 48*8630f839SAlex Deucher #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 49*8630f839SAlex Deucher #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff 50*8630f839SAlex Deucher #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 51*8630f839SAlex Deucher #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 52*8630f839SAlex Deucher #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 53*8630f839SAlex Deucher #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 54*8630f839SAlex Deucher #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 55*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 56*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 57*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 58*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 59*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 60*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 61*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 62*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 63*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 64*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 65*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 66*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 67*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 68*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 69*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 70*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 71*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 72*8630f839SAlex Deucher #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 73*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 74*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 75*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 76*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 77*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 78*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 79*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 80*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 81*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 82*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 83*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 84*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 85*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 86*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 87*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 88*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 89*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 90*8630f839SAlex Deucher #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 91*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 92*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 93*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 94*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 95*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 96*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 97*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 98*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 99*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 100*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 101*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 102*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 103*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 104*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 105*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 106*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 107*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 108*8630f839SAlex Deucher #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 109*8630f839SAlex Deucher #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 110*8630f839SAlex Deucher #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 111*8630f839SAlex Deucher #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 112*8630f839SAlex Deucher #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 113*8630f839SAlex Deucher #define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff 114*8630f839SAlex Deucher #define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 115*8630f839SAlex Deucher #define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 116*8630f839SAlex Deucher #define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 117*8630f839SAlex Deucher #define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 118*8630f839SAlex Deucher #define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f 119*8630f839SAlex Deucher #define UVD_CTX_INDEX__INDEX_MASK 0x1ff 120*8630f839SAlex Deucher #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 121*8630f839SAlex Deucher #define UVD_CTX_DATA__DATA_MASK 0xffffffff 122*8630f839SAlex Deucher #define UVD_CTX_DATA__DATA__SHIFT 0x0 123*8630f839SAlex Deucher #define UVD_CGC_GATE__SYS_MASK 0x1 124*8630f839SAlex Deucher #define UVD_CGC_GATE__SYS__SHIFT 0x0 125*8630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_MASK 0x2 126*8630f839SAlex Deucher #define UVD_CGC_GATE__UDEC__SHIFT 0x1 127*8630f839SAlex Deucher #define UVD_CGC_GATE__MPEG2_MASK 0x4 128*8630f839SAlex Deucher #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 129*8630f839SAlex Deucher #define UVD_CGC_GATE__REGS_MASK 0x8 130*8630f839SAlex Deucher #define UVD_CGC_GATE__REGS__SHIFT 0x3 131*8630f839SAlex Deucher #define UVD_CGC_GATE__RBC_MASK 0x10 132*8630f839SAlex Deucher #define UVD_CGC_GATE__RBC__SHIFT 0x4 133*8630f839SAlex Deucher #define UVD_CGC_GATE__LMI_MC_MASK 0x20 134*8630f839SAlex Deucher #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 135*8630f839SAlex Deucher #define UVD_CGC_GATE__LMI_UMC_MASK 0x40 136*8630f839SAlex Deucher #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 137*8630f839SAlex Deucher #define UVD_CGC_GATE__IDCT_MASK 0x80 138*8630f839SAlex Deucher #define UVD_CGC_GATE__IDCT__SHIFT 0x7 139*8630f839SAlex Deucher #define UVD_CGC_GATE__MPRD_MASK 0x100 140*8630f839SAlex Deucher #define UVD_CGC_GATE__MPRD__SHIFT 0x8 141*8630f839SAlex Deucher #define UVD_CGC_GATE__MPC_MASK 0x200 142*8630f839SAlex Deucher #define UVD_CGC_GATE__MPC__SHIFT 0x9 143*8630f839SAlex Deucher #define UVD_CGC_GATE__LBSI_MASK 0x400 144*8630f839SAlex Deucher #define UVD_CGC_GATE__LBSI__SHIFT 0xa 145*8630f839SAlex Deucher #define UVD_CGC_GATE__LRBBM_MASK 0x800 146*8630f839SAlex Deucher #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 147*8630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 148*8630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 149*8630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 150*8630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 151*8630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 152*8630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 153*8630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 154*8630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 155*8630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 156*8630f839SAlex Deucher #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 157*8630f839SAlex Deucher #define UVD_CGC_GATE__WCB_MASK 0x20000 158*8630f839SAlex Deucher #define UVD_CGC_GATE__WCB__SHIFT 0x11 159*8630f839SAlex Deucher #define UVD_CGC_GATE__VCPU_MASK 0x40000 160*8630f839SAlex Deucher #define UVD_CGC_GATE__VCPU__SHIFT 0x12 161*8630f839SAlex Deucher #define UVD_CGC_GATE__SCPU_MASK 0x80000 162*8630f839SAlex Deucher #define UVD_CGC_GATE__SCPU__SHIFT 0x13 163*8630f839SAlex Deucher #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 164*8630f839SAlex Deucher #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 165*8630f839SAlex Deucher #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 166*8630f839SAlex Deucher #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 167*8630f839SAlex Deucher #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 168*8630f839SAlex Deucher #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 169*8630f839SAlex Deucher #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 170*8630f839SAlex Deucher #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 171*8630f839SAlex Deucher #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 172*8630f839SAlex Deucher #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 173*8630f839SAlex Deucher #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 174*8630f839SAlex Deucher #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 175*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 176*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 177*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 178*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 179*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 180*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 181*8630f839SAlex Deucher #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 182*8630f839SAlex Deucher #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 183*8630f839SAlex Deucher #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 184*8630f839SAlex Deucher #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 185*8630f839SAlex Deucher #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 186*8630f839SAlex Deucher #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 187*8630f839SAlex Deucher #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 188*8630f839SAlex Deucher #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 189*8630f839SAlex Deucher #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 190*8630f839SAlex Deucher #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 191*8630f839SAlex Deucher #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 192*8630f839SAlex Deucher #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 193*8630f839SAlex Deucher #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 194*8630f839SAlex Deucher #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 195*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 196*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 197*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 198*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 199*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 200*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 201*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 202*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 203*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 204*8630f839SAlex Deucher #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 205*8630f839SAlex Deucher #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 206*8630f839SAlex Deucher #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 207*8630f839SAlex Deucher #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 208*8630f839SAlex Deucher #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 209*8630f839SAlex Deucher #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 210*8630f839SAlex Deucher #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 211*8630f839SAlex Deucher #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 212*8630f839SAlex Deucher #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 213*8630f839SAlex Deucher #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 214*8630f839SAlex Deucher #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 215*8630f839SAlex Deucher #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 216*8630f839SAlex Deucher #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 217*8630f839SAlex Deucher #define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 218*8630f839SAlex Deucher #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b 219*8630f839SAlex Deucher #define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 220*8630f839SAlex Deucher #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c 221*8630f839SAlex Deucher #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 222*8630f839SAlex Deucher #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 223*8630f839SAlex Deucher #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c 224*8630f839SAlex Deucher #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 225*8630f839SAlex Deucher #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 226*8630f839SAlex Deucher #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 227*8630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 228*8630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 229*8630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 230*8630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 231*8630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 232*8630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 233*8630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 234*8630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 235*8630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 236*8630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 237*8630f839SAlex Deucher #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 238*8630f839SAlex Deucher #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 239*8630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 240*8630f839SAlex Deucher #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 241*8630f839SAlex Deucher #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 242*8630f839SAlex Deucher #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 243*8630f839SAlex Deucher #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 244*8630f839SAlex Deucher #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 245*8630f839SAlex Deucher #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 246*8630f839SAlex Deucher #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 247*8630f839SAlex Deucher #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 248*8630f839SAlex Deucher #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 249*8630f839SAlex Deucher #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 250*8630f839SAlex Deucher #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 251*8630f839SAlex Deucher #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 252*8630f839SAlex Deucher #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 253*8630f839SAlex Deucher #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 254*8630f839SAlex Deucher #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 255*8630f839SAlex Deucher #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 256*8630f839SAlex Deucher #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 257*8630f839SAlex Deucher #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 258*8630f839SAlex Deucher #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 259*8630f839SAlex Deucher #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 260*8630f839SAlex Deucher #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 261*8630f839SAlex Deucher #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 262*8630f839SAlex Deucher #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 263*8630f839SAlex Deucher #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 264*8630f839SAlex Deucher #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 265*8630f839SAlex Deucher #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 266*8630f839SAlex Deucher #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 267*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 268*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 269*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 270*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 271*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 272*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 273*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 274*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 275*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 276*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 277*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 278*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 279*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 280*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 281*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 282*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 283*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 284*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 285*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 286*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 287*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 288*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 289*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 290*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 291*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 292*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 293*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 294*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 295*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 296*8630f839SAlex Deucher #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 297*8630f839SAlex Deucher #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 298*8630f839SAlex Deucher #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 299*8630f839SAlex Deucher #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 300*8630f839SAlex Deucher #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 301*8630f839SAlex Deucher #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 302*8630f839SAlex Deucher #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 303*8630f839SAlex Deucher #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 304*8630f839SAlex Deucher #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 305*8630f839SAlex Deucher #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 306*8630f839SAlex Deucher #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 307*8630f839SAlex Deucher #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 308*8630f839SAlex Deucher #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 309*8630f839SAlex Deucher #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 310*8630f839SAlex Deucher #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 311*8630f839SAlex Deucher #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 312*8630f839SAlex Deucher #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 313*8630f839SAlex Deucher #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 314*8630f839SAlex Deucher #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 315*8630f839SAlex Deucher #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 316*8630f839SAlex Deucher #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 317*8630f839SAlex Deucher #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 318*8630f839SAlex Deucher #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 319*8630f839SAlex Deucher #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 320*8630f839SAlex Deucher #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 321*8630f839SAlex Deucher #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 322*8630f839SAlex Deucher #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 323*8630f839SAlex Deucher #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 324*8630f839SAlex Deucher #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 325*8630f839SAlex Deucher #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 326*8630f839SAlex Deucher #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 327*8630f839SAlex Deucher #define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 328*8630f839SAlex Deucher #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 329*8630f839SAlex Deucher #define UVD_MASTINT_EN__SYS_EN_MASK 0x4 330*8630f839SAlex Deucher #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 331*8630f839SAlex Deucher #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 332*8630f839SAlex Deucher #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 333*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf 334*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 335*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 336*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 337*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 338*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 339*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 340*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc 341*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 342*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 343*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 344*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 345*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 346*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 347*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 348*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c 349*8630f839SAlex Deucher #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff 350*8630f839SAlex Deucher #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 351*8630f839SAlex Deucher #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 352*8630f839SAlex Deucher #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 353*8630f839SAlex Deucher #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 354*8630f839SAlex Deucher #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 355*8630f839SAlex Deucher #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 356*8630f839SAlex Deucher #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 357*8630f839SAlex Deucher #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 358*8630f839SAlex Deucher #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 359*8630f839SAlex Deucher #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 360*8630f839SAlex Deucher #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 361*8630f839SAlex Deucher #define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 362*8630f839SAlex Deucher #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 363*8630f839SAlex Deucher #define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 364*8630f839SAlex Deucher #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 365*8630f839SAlex Deucher #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 366*8630f839SAlex Deucher #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 367*8630f839SAlex Deucher #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 368*8630f839SAlex Deucher #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 369*8630f839SAlex Deucher #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 370*8630f839SAlex Deucher #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 371*8630f839SAlex Deucher #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 372*8630f839SAlex Deucher #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 373*8630f839SAlex Deucher #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 374*8630f839SAlex Deucher #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 375*8630f839SAlex Deucher #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 376*8630f839SAlex Deucher #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 377*8630f839SAlex Deucher #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 378*8630f839SAlex Deucher #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 379*8630f839SAlex Deucher #define UVD_LMI_CTRL__RFU_MASK 0xf8000000 380*8630f839SAlex Deucher #define UVD_LMI_CTRL__RFU__SHIFT 0x1b 381*8630f839SAlex Deucher #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 382*8630f839SAlex Deucher #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 383*8630f839SAlex Deucher #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 384*8630f839SAlex Deucher #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 385*8630f839SAlex Deucher #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 386*8630f839SAlex Deucher #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 387*8630f839SAlex Deucher #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 388*8630f839SAlex Deucher #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 389*8630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 390*8630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 391*8630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 392*8630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 393*8630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 394*8630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 395*8630f839SAlex Deucher #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 396*8630f839SAlex Deucher #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 397*8630f839SAlex Deucher #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 398*8630f839SAlex Deucher #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 399*8630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 400*8630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 401*8630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 402*8630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 403*8630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 404*8630f839SAlex Deucher #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 405*8630f839SAlex Deucher #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 406*8630f839SAlex Deucher #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 407*8630f839SAlex Deucher #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 408*8630f839SAlex Deucher #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 409*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 410*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 411*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc 412*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 413*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 414*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 415*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 416*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 417*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 418*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 419*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 420*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 421*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 422*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 423*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 424*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 425*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 426*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 427*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 428*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 429*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 430*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 431*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 432*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 433*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 434*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 435*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 436*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 437*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 438*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 439*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 440*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 441*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc 442*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 443*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 444*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 445*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 446*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 447*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 448*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 449*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 450*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 451*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 452*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 453*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 454*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 455*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 456*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 457*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 458*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 459*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 460*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 461*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 462*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 463*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 464*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 465*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 466*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 467*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 468*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 469*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 470*8630f839SAlex Deucher #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 471*8630f839SAlex Deucher #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 472*8630f839SAlex Deucher #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 473*8630f839SAlex Deucher #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 474*8630f839SAlex Deucher #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 475*8630f839SAlex Deucher #define UVD_MPC_CNTL__DBG_MUX_MASK 0x700 476*8630f839SAlex Deucher #define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 477*8630f839SAlex Deucher #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 478*8630f839SAlex Deucher #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 479*8630f839SAlex Deucher #define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 480*8630f839SAlex Deucher #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 481*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f 482*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 483*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 484*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 485*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 486*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 487*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 488*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 489*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 490*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 491*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f 492*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 493*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 494*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 495*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 496*8630f839SAlex Deucher #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 497*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f 498*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 499*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 500*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 501*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 502*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 503*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 504*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 505*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 506*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 507*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f 508*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 509*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 510*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 511*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 512*8630f839SAlex Deucher #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 513*8630f839SAlex Deucher #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 514*8630f839SAlex Deucher #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 515*8630f839SAlex Deucher #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 516*8630f839SAlex Deucher #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 517*8630f839SAlex Deucher #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 518*8630f839SAlex Deucher #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 519*8630f839SAlex Deucher #define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 520*8630f839SAlex Deucher #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 521*8630f839SAlex Deucher #define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 522*8630f839SAlex Deucher #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 523*8630f839SAlex Deucher #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff 524*8630f839SAlex Deucher #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 525*8630f839SAlex Deucher #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff 526*8630f839SAlex Deucher #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 527*8630f839SAlex Deucher #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff 528*8630f839SAlex Deucher #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 529*8630f839SAlex Deucher #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff 530*8630f839SAlex Deucher #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 531*8630f839SAlex Deucher #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff 532*8630f839SAlex Deucher #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 533*8630f839SAlex Deucher #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff 534*8630f839SAlex Deucher #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 535*8630f839SAlex Deucher #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf 536*8630f839SAlex Deucher #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 537*8630f839SAlex Deucher #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 538*8630f839SAlex Deucher #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 539*8630f839SAlex Deucher #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 540*8630f839SAlex Deucher #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 541*8630f839SAlex Deucher #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 542*8630f839SAlex Deucher #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 543*8630f839SAlex Deucher #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 544*8630f839SAlex Deucher #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 545*8630f839SAlex Deucher #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 546*8630f839SAlex Deucher #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 547*8630f839SAlex Deucher #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 548*8630f839SAlex Deucher #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 549*8630f839SAlex Deucher #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 550*8630f839SAlex Deucher #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 551*8630f839SAlex Deucher #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 552*8630f839SAlex Deucher #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 553*8630f839SAlex Deucher #define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 554*8630f839SAlex Deucher #define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 555*8630f839SAlex Deucher #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 556*8630f839SAlex Deucher #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 557*8630f839SAlex Deucher #define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x20000 558*8630f839SAlex Deucher #define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x11 559*8630f839SAlex Deucher #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 560*8630f839SAlex Deucher #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 561*8630f839SAlex Deucher #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 562*8630f839SAlex Deucher #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 563*8630f839SAlex Deucher #define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 564*8630f839SAlex Deucher #define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 565*8630f839SAlex Deucher #define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000 566*8630f839SAlex Deucher #define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x1d 567*8630f839SAlex Deucher #define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 568*8630f839SAlex Deucher #define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 569*8630f839SAlex Deucher #define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 570*8630f839SAlex Deucher #define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f 571*8630f839SAlex Deucher #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 572*8630f839SAlex Deucher #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 573*8630f839SAlex Deucher #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 574*8630f839SAlex Deucher #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 575*8630f839SAlex Deucher #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 576*8630f839SAlex Deucher #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 577*8630f839SAlex Deucher #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 578*8630f839SAlex Deucher #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 579*8630f839SAlex Deucher #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 580*8630f839SAlex Deucher #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 581*8630f839SAlex Deucher #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 582*8630f839SAlex Deucher #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 583*8630f839SAlex Deucher #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 584*8630f839SAlex Deucher #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 585*8630f839SAlex Deucher #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 586*8630f839SAlex Deucher #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 587*8630f839SAlex Deucher #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 588*8630f839SAlex Deucher #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 589*8630f839SAlex Deucher #define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x200 590*8630f839SAlex Deucher #define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x9 591*8630f839SAlex Deucher #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 592*8630f839SAlex Deucher #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 593*8630f839SAlex Deucher #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 594*8630f839SAlex Deucher #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 595*8630f839SAlex Deucher #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 596*8630f839SAlex Deucher #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 597*8630f839SAlex Deucher #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 598*8630f839SAlex Deucher #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 599*8630f839SAlex Deucher #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 600*8630f839SAlex Deucher #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 601*8630f839SAlex Deucher #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 602*8630f839SAlex Deucher #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 603*8630f839SAlex Deucher #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 604*8630f839SAlex Deucher #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 605*8630f839SAlex Deucher #define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0 606*8630f839SAlex Deucher #define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x6 607*8630f839SAlex Deucher #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 608*8630f839SAlex Deucher #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 609*8630f839SAlex Deucher #define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0 610*8630f839SAlex Deucher #define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x6 611*8630f839SAlex Deucher #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 612*8630f839SAlex Deucher #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 613*8630f839SAlex Deucher #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 614*8630f839SAlex Deucher #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 615*8630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f 616*8630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 617*8630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 618*8630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 619*8630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 620*8630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 621*8630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 622*8630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 623*8630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 624*8630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 625*8630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 626*8630f839SAlex Deucher #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 627*8630f839SAlex Deucher #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff 628*8630f839SAlex Deucher #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 629*8630f839SAlex Deucher #define UVD_STATUS__RBC_BUSY_MASK 0x1 630*8630f839SAlex Deucher #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 631*8630f839SAlex Deucher #define UVD_STATUS__VCPU_REPORT_MASK 0xfe 632*8630f839SAlex Deucher #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 633*8630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 634*8630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 635*8630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 636*8630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 637*8630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 638*8630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 639*8630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 640*8630f839SAlex Deucher #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 641*8630f839SAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 642*8630f839SAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 643*8630f839SAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe 644*8630f839SAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 645*8630f839SAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 646*8630f839SAlex Deucher #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 647*8630f839SAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 648*8630f839SAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 649*8630f839SAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe 650*8630f839SAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 651*8630f839SAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 652*8630f839SAlex Deucher #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 653*8630f839SAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 654*8630f839SAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 655*8630f839SAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe 656*8630f839SAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 657*8630f839SAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 658*8630f839SAlex Deucher #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 659*8630f839SAlex Deucher #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff 660*8630f839SAlex Deucher #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 661*8630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 662*8630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 663*8630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 664*8630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 665*8630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 666*8630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 667*8630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 668*8630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 669*8630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 670*8630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 671*8630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 672*8630f839SAlex Deucher #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 673*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 674*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 675*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc 676*8630f839SAlex Deucher #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 677*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf 678*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 679*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 680*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 681*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 682*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 683*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 684*8630f839SAlex Deucher #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc 685*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 686*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 687*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 688*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 689*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 690*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 691*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 692*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 693*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 694*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 695*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 696*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 697*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 698*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 699*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 700*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 701*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 702*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 703*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 704*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 705*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 706*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 707*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 708*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb 709*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 710*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 711*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 712*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 713*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 714*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 715*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 716*8630f839SAlex Deucher #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 717*8630f839SAlex Deucher #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 718*8630f839SAlex Deucher #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 719*8630f839SAlex Deucher #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 720*8630f839SAlex Deucher #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 721*8630f839SAlex Deucher #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c 722*8630f839SAlex Deucher #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 723*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff 724*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 725*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 726*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 727*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 728*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 729*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 730*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa 731*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 732*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb 733*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 734*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc 735*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 736*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd 737*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 738*8630f839SAlex Deucher #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c 739*8630f839SAlex Deucher #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff 740*8630f839SAlex Deucher #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 741*8630f839SAlex Deucher #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff 742*8630f839SAlex Deucher #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 743*8630f839SAlex Deucher #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1 744*8630f839SAlex Deucher #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 745*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 746*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 747*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 748*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 749*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 750*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 751*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 752*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 753*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 754*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 755*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 756*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 757*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 758*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 759*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 760*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 761*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 762*8630f839SAlex Deucher #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 763*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 764*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 765*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 766*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 767*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 768*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 769*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 770*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 771*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 772*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 773*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 774*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 775*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 776*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 777*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 778*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 779*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 780*8630f839SAlex Deucher #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 781*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 782*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 783*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 784*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 785*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 786*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 787*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 788*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 789*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 790*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 791*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 792*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 793*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 794*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 795*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 796*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 797*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 798*8630f839SAlex Deucher #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 799*8630f839SAlex Deucher 800*8630f839SAlex Deucher #endif /* UVD_4_2_SH_MASK_H */ 801