1 /****************************************************************************\ 2 * 3 * File Name atomfirmware.h 4 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 5 * 6 * Description header file of general definitions for OS nd pre-OS video drivers 7 * 8 * Copyright 2014 Advanced Micro Devices, Inc. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software 11 * and associated documentation files (the "Software"), to deal in the Software without restriction, 12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 14 * subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 \****************************************************************************/ 28 29 /*IMPORTANT NOTES 30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 33 */ 34 35 #ifndef _ATOMFIRMWARE_H_ 36 #define _ATOMFIRMWARE_H_ 37 38 enum atom_bios_header_version_def{ 39 ATOM_MAJOR_VERSION =0x0003, 40 ATOM_MINOR_VERSION =0x0003, 41 }; 42 43 #ifdef _H2INC 44 #ifndef uint32_t 45 typedef unsigned long uint32_t; 46 #endif 47 48 #ifndef uint16_t 49 typedef unsigned short uint16_t; 50 #endif 51 52 #ifndef uint8_t 53 typedef unsigned char uint8_t; 54 #endif 55 #endif 56 57 enum atom_crtc_def{ 58 ATOM_CRTC1 =0, 59 ATOM_CRTC2 =1, 60 ATOM_CRTC3 =2, 61 ATOM_CRTC4 =3, 62 ATOM_CRTC5 =4, 63 ATOM_CRTC6 =5, 64 ATOM_CRTC_INVALID =0xff, 65 }; 66 67 enum atom_ppll_def{ 68 ATOM_PPLL0 =2, 69 ATOM_GCK_DFS =8, 70 ATOM_FCH_CLK =9, 71 ATOM_DP_DTO =11, 72 ATOM_COMBOPHY_PLL0 =20, 73 ATOM_COMBOPHY_PLL1 =21, 74 ATOM_COMBOPHY_PLL2 =22, 75 ATOM_COMBOPHY_PLL3 =23, 76 ATOM_COMBOPHY_PLL4 =24, 77 ATOM_COMBOPHY_PLL5 =25, 78 ATOM_PPLL_INVALID =0xff, 79 }; 80 81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 82 enum atom_dig_def{ 83 ASIC_INT_DIG1_ENCODER_ID =0x03, 84 ASIC_INT_DIG2_ENCODER_ID =0x09, 85 ASIC_INT_DIG3_ENCODER_ID =0x0a, 86 ASIC_INT_DIG4_ENCODER_ID =0x0b, 87 ASIC_INT_DIG5_ENCODER_ID =0x0c, 88 ASIC_INT_DIG6_ENCODER_ID =0x0d, 89 ASIC_INT_DIG7_ENCODER_ID =0x0e, 90 }; 91 92 //ucEncoderMode 93 enum atom_encode_mode_def 94 { 95 ATOM_ENCODER_MODE_DP =0, 96 ATOM_ENCODER_MODE_DP_SST =0, 97 ATOM_ENCODER_MODE_LVDS =1, 98 ATOM_ENCODER_MODE_DVI =2, 99 ATOM_ENCODER_MODE_HDMI =3, 100 ATOM_ENCODER_MODE_DP_AUDIO =5, 101 ATOM_ENCODER_MODE_DP_MST =5, 102 ATOM_ENCODER_MODE_CRT =15, 103 ATOM_ENCODER_MODE_DVO =16, 104 }; 105 106 enum atom_encoder_refclk_src_def{ 107 ENCODER_REFCLK_SRC_P1PLL =0, 108 ENCODER_REFCLK_SRC_P2PLL =1, 109 ENCODER_REFCLK_SRC_P3PLL =2, 110 ENCODER_REFCLK_SRC_EXTCLK =3, 111 ENCODER_REFCLK_SRC_INVALID =0xff, 112 }; 113 114 enum atom_scaler_def{ 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 118 }; 119 120 enum atom_operation_def{ 121 ATOM_DISABLE = 0, 122 ATOM_ENABLE = 1, 123 ATOM_INIT = 7, 124 ATOM_GET_STATUS = 8, 125 }; 126 127 enum atom_embedded_display_op_def{ 128 ATOM_LCD_BL_OFF = 2, 129 ATOM_LCD_BL_OM = 3, 130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 131 ATOM_LCD_SELFTEST_START = 5, 132 ATOM_LCD_SELFTEST_STOP = 6, 133 }; 134 135 enum atom_spread_spectrum_mode{ 136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 137 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 139 ATOM_INT_OR_EXT_SS_MASK = 0x02, 140 ATOM_INTERNAL_SS_MASK = 0x00, 141 ATOM_EXTERNAL_SS_MASK = 0x02, 142 }; 143 144 /* define panel bit per color */ 145 enum atom_panel_bit_per_color{ 146 PANEL_BPC_UNDEFINE =0x00, 147 PANEL_6BIT_PER_COLOR =0x01, 148 PANEL_8BIT_PER_COLOR =0x02, 149 PANEL_10BIT_PER_COLOR =0x03, 150 PANEL_12BIT_PER_COLOR =0x04, 151 PANEL_16BIT_PER_COLOR =0x05, 152 }; 153 154 //ucVoltageType 155 enum atom_voltage_type 156 { 157 VOLTAGE_TYPE_VDDC = 1, 158 VOLTAGE_TYPE_MVDDC = 2, 159 VOLTAGE_TYPE_MVDDQ = 3, 160 VOLTAGE_TYPE_VDDCI = 4, 161 VOLTAGE_TYPE_VDDGFX = 5, 162 VOLTAGE_TYPE_PCC = 6, 163 VOLTAGE_TYPE_MVPP = 7, 164 VOLTAGE_TYPE_LEDDPM = 8, 165 VOLTAGE_TYPE_PCC_MVDD = 9, 166 VOLTAGE_TYPE_PCIE_VDDC = 10, 167 VOLTAGE_TYPE_PCIE_VDDR = 11, 168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 178 }; 179 180 enum atom_dgpu_vram_type{ 181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, 183 }; 184 185 enum atom_dp_vs_preemph_def{ 186 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 187 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 188 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 189 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 190 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 191 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 192 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 193 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 194 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 195 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 196 }; 197 198 199 /* 200 enum atom_string_def{ 201 asic_bus_type_pcie_string = "PCI_EXPRESS", 202 atom_fire_gl_string = "FGL", 203 atom_bios_string = "ATOM" 204 }; 205 */ 206 207 #pragma pack(1) /* BIOS data must use byte aligment*/ 208 209 enum atombios_image_offset{ 210 OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048, 211 OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002, 212 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94, 213 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/ 214 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f, 215 OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e, 216 }; 217 218 /**************************************************************************** 219 * Common header for all tables (Data table, Command function). 220 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 221 * And the pointer actually points to this header. 222 ****************************************************************************/ 223 224 struct atom_common_table_header 225 { 226 uint16_t structuresize; 227 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 228 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 229 }; 230 231 /**************************************************************************** 232 * Structure stores the ROM header. 233 ****************************************************************************/ 234 struct atom_rom_header_v2_2 235 { 236 struct atom_common_table_header table_header; 237 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 238 uint16_t bios_segment_address; 239 uint16_t protectedmodeoffset; 240 uint16_t configfilenameoffset; 241 uint16_t crc_block_offset; 242 uint16_t vbios_bootupmessageoffset; 243 uint16_t int10_offset; 244 uint16_t pcibusdevinitcode; 245 uint16_t iobaseaddress; 246 uint16_t subsystem_vendor_id; 247 uint16_t subsystem_id; 248 uint16_t pci_info_offset; 249 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position 250 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position 251 uint16_t reserved; 252 uint32_t pspdirtableoffset; 253 }; 254 255 /*==============================hw function portion======================================================================*/ 256 257 258 /**************************************************************************** 259 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time 260 * The real functionality of each function is associated with the parameter structure version when defined 261 * For all internal cmd function definitions, please reference to atomstruct.h 262 ****************************************************************************/ 263 struct atom_master_list_of_command_functions_v2_1{ 264 uint16_t asic_init; //Function 265 uint16_t cmd_function1; //used as an internal one 266 uint16_t cmd_function2; //used as an internal one 267 uint16_t cmd_function3; //used as an internal one 268 uint16_t digxencodercontrol; //Function 269 uint16_t cmd_function5; //used as an internal one 270 uint16_t cmd_function6; //used as an internal one 271 uint16_t cmd_function7; //used as an internal one 272 uint16_t cmd_function8; //used as an internal one 273 uint16_t cmd_function9; //used as an internal one 274 uint16_t setengineclock; //Function 275 uint16_t setmemoryclock; //Function 276 uint16_t setpixelclock; //Function 277 uint16_t enabledisppowergating; //Function 278 uint16_t cmd_function14; //used as an internal one 279 uint16_t cmd_function15; //used as an internal one 280 uint16_t cmd_function16; //used as an internal one 281 uint16_t cmd_function17; //used as an internal one 282 uint16_t cmd_function18; //used as an internal one 283 uint16_t cmd_function19; //used as an internal one 284 uint16_t cmd_function20; //used as an internal one 285 uint16_t cmd_function21; //used as an internal one 286 uint16_t cmd_function22; //used as an internal one 287 uint16_t cmd_function23; //used as an internal one 288 uint16_t cmd_function24; //used as an internal one 289 uint16_t cmd_function25; //used as an internal one 290 uint16_t cmd_function26; //used as an internal one 291 uint16_t cmd_function27; //used as an internal one 292 uint16_t cmd_function28; //used as an internal one 293 uint16_t cmd_function29; //used as an internal one 294 uint16_t cmd_function30; //used as an internal one 295 uint16_t cmd_function31; //used as an internal one 296 uint16_t cmd_function32; //used as an internal one 297 uint16_t cmd_function33; //used as an internal one 298 uint16_t blankcrtc; //Function 299 uint16_t enablecrtc; //Function 300 uint16_t cmd_function36; //used as an internal one 301 uint16_t cmd_function37; //used as an internal one 302 uint16_t cmd_function38; //used as an internal one 303 uint16_t cmd_function39; //used as an internal one 304 uint16_t cmd_function40; //used as an internal one 305 uint16_t getsmuclockinfo; //Function 306 uint16_t selectcrtc_source; //Function 307 uint16_t cmd_function43; //used as an internal one 308 uint16_t cmd_function44; //used as an internal one 309 uint16_t cmd_function45; //used as an internal one 310 uint16_t setdceclock; //Function 311 uint16_t getmemoryclock; //Function 312 uint16_t getengineclock; //Function 313 uint16_t setcrtc_usingdtdtiming; //Function 314 uint16_t externalencodercontrol; //Function 315 uint16_t cmd_function51; //used as an internal one 316 uint16_t cmd_function52; //used as an internal one 317 uint16_t cmd_function53; //used as an internal one 318 uint16_t processi2cchanneltransaction;//Function 319 uint16_t cmd_function55; //used as an internal one 320 uint16_t cmd_function56; //used as an internal one 321 uint16_t cmd_function57; //used as an internal one 322 uint16_t cmd_function58; //used as an internal one 323 uint16_t cmd_function59; //used as an internal one 324 uint16_t computegpuclockparam; //Function 325 uint16_t cmd_function61; //used as an internal one 326 uint16_t cmd_function62; //used as an internal one 327 uint16_t dynamicmemorysettings; //Function function 328 uint16_t memorytraining; //Function function 329 uint16_t cmd_function65; //used as an internal one 330 uint16_t cmd_function66; //used as an internal one 331 uint16_t setvoltage; //Function 332 uint16_t cmd_function68; //used as an internal one 333 uint16_t readefusevalue; //Function 334 uint16_t cmd_function70; //used as an internal one 335 uint16_t cmd_function71; //used as an internal one 336 uint16_t cmd_function72; //used as an internal one 337 uint16_t cmd_function73; //used as an internal one 338 uint16_t cmd_function74; //used as an internal one 339 uint16_t cmd_function75; //used as an internal one 340 uint16_t dig1transmittercontrol; //Function 341 uint16_t cmd_function77; //used as an internal one 342 uint16_t processauxchanneltransaction;//Function 343 uint16_t cmd_function79; //used as an internal one 344 uint16_t getvoltageinfo; //Function 345 }; 346 347 struct atom_master_command_function_v2_1 348 { 349 struct atom_common_table_header table_header; 350 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 351 }; 352 353 /**************************************************************************** 354 * Structures used in every command function 355 ****************************************************************************/ 356 struct atom_function_attribute 357 { 358 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 359 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 360 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 361 }; 362 363 364 /**************************************************************************** 365 * Common header for all hw functions. 366 * Every function pointed by _master_list_of_hw_function has this common header. 367 * And the pointer actually points to this header. 368 ****************************************************************************/ 369 struct atom_rom_hw_function_header 370 { 371 struct atom_common_table_header func_header; 372 struct atom_function_attribute func_attrib; 373 }; 374 375 376 /*==============================sw data table portion======================================================================*/ 377 /**************************************************************************** 378 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 379 * The real name of each table is given when its data structure version is defined 380 ****************************************************************************/ 381 struct atom_master_list_of_data_tables_v2_1{ 382 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 383 uint16_t multimedia_info; 384 uint16_t smc_dpm_info; 385 uint16_t sw_datatable3; 386 uint16_t firmwareinfo; /* Shared by various SW components */ 387 uint16_t sw_datatable5; 388 uint16_t lcd_info; /* Shared by various SW components */ 389 uint16_t sw_datatable7; 390 uint16_t smu_info; 391 uint16_t sw_datatable9; 392 uint16_t sw_datatable10; 393 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 394 uint16_t gpio_pin_lut; /* Shared by various SW components */ 395 uint16_t sw_datatable13; 396 uint16_t gfx_info; 397 uint16_t powerplayinfo; /* Shared by various SW components */ 398 uint16_t sw_datatable16; 399 uint16_t sw_datatable17; 400 uint16_t sw_datatable18; 401 uint16_t sw_datatable19; 402 uint16_t sw_datatable20; 403 uint16_t sw_datatable21; 404 uint16_t displayobjectinfo; /* Shared by various SW components */ 405 uint16_t indirectioaccess; /* used as an internal one */ 406 uint16_t umc_info; /* Shared by various SW components */ 407 uint16_t sw_datatable25; 408 uint16_t sw_datatable26; 409 uint16_t dce_info; /* Shared by various SW components */ 410 uint16_t vram_info; /* Shared by various SW components */ 411 uint16_t sw_datatable29; 412 uint16_t integratedsysteminfo; /* Shared by various SW components */ 413 uint16_t asic_profiling_info; /* Shared by various SW components */ 414 uint16_t voltageobject_info; /* shared by various SW components */ 415 uint16_t sw_datatable33; 416 uint16_t sw_datatable34; 417 }; 418 419 420 struct atom_master_data_table_v2_1 421 { 422 struct atom_common_table_header table_header; 423 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 424 }; 425 426 427 struct atom_dtd_format 428 { 429 uint16_t pixclk; 430 uint16_t h_active; 431 uint16_t h_blanking_time; 432 uint16_t v_active; 433 uint16_t v_blanking_time; 434 uint16_t h_sync_offset; 435 uint16_t h_sync_width; 436 uint16_t v_sync_offset; 437 uint16_t v_syncwidth; 438 uint16_t reserved; 439 uint16_t reserved0; 440 uint8_t h_border; 441 uint8_t v_border; 442 uint16_t miscinfo; 443 uint8_t atom_mode_id; 444 uint8_t refreshrate; 445 }; 446 447 /* atom_dtd_format.modemiscinfo defintion */ 448 enum atom_dtd_format_modemiscinfo{ 449 ATOM_HSYNC_POLARITY = 0x0002, 450 ATOM_VSYNC_POLARITY = 0x0004, 451 ATOM_H_REPLICATIONBY2 = 0x0010, 452 ATOM_V_REPLICATIONBY2 = 0x0020, 453 ATOM_INTERLACE = 0x0080, 454 ATOM_COMPOSITESYNC = 0x0040, 455 }; 456 457 458 /* utilitypipeline 459 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 460 * the location of it can't change 461 */ 462 463 464 /* 465 *************************************************************************** 466 Data Table firmwareinfo structure 467 *************************************************************************** 468 */ 469 470 struct atom_firmware_info_v3_1 471 { 472 struct atom_common_table_header table_header; 473 uint32_t firmware_revision; 474 uint32_t bootup_sclk_in10khz; 475 uint32_t bootup_mclk_in10khz; 476 uint32_t firmware_capability; // enum atombios_firmware_capability 477 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 478 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 479 uint16_t bootup_vddc_mv; 480 uint16_t bootup_vddci_mv; 481 uint16_t bootup_mvddc_mv; 482 uint16_t bootup_vddgfx_mv; 483 uint8_t mem_module_id; 484 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 485 uint8_t reserved1[2]; 486 uint32_t mc_baseaddr_high; 487 uint32_t mc_baseaddr_low; 488 uint32_t reserved2[6]; 489 }; 490 491 /* Total 32bit cap indication */ 492 enum atombios_firmware_capability 493 { 494 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 495 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 496 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 497 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, 498 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, 499 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, 500 }; 501 502 enum atom_cooling_solution_id{ 503 AIR_COOLING = 0x00, 504 LIQUID_COOLING = 0x01 505 }; 506 507 struct atom_firmware_info_v3_2 { 508 struct atom_common_table_header table_header; 509 uint32_t firmware_revision; 510 uint32_t bootup_sclk_in10khz; 511 uint32_t bootup_mclk_in10khz; 512 uint32_t firmware_capability; // enum atombios_firmware_capability 513 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 514 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 515 uint16_t bootup_vddc_mv; 516 uint16_t bootup_vddci_mv; 517 uint16_t bootup_mvddc_mv; 518 uint16_t bootup_vddgfx_mv; 519 uint8_t mem_module_id; 520 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 521 uint8_t reserved1[2]; 522 uint32_t mc_baseaddr_high; 523 uint32_t mc_baseaddr_low; 524 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 525 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 526 uint8_t board_i2c_feature_slave_addr; 527 uint8_t reserved3; 528 uint16_t bootup_mvddq_mv; 529 uint16_t bootup_mvpp_mv; 530 uint32_t zfbstartaddrin16mb; 531 uint32_t reserved2[3]; 532 }; 533 534 struct atom_firmware_info_v3_3 535 { 536 struct atom_common_table_header table_header; 537 uint32_t firmware_revision; 538 uint32_t bootup_sclk_in10khz; 539 uint32_t bootup_mclk_in10khz; 540 uint32_t firmware_capability; // enum atombios_firmware_capability 541 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 542 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 543 uint16_t bootup_vddc_mv; 544 uint16_t bootup_vddci_mv; 545 uint16_t bootup_mvddc_mv; 546 uint16_t bootup_vddgfx_mv; 547 uint8_t mem_module_id; 548 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 549 uint8_t reserved1[2]; 550 uint32_t mc_baseaddr_high; 551 uint32_t mc_baseaddr_low; 552 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 553 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 554 uint8_t board_i2c_feature_slave_addr; 555 uint8_t reserved3; 556 uint16_t bootup_mvddq_mv; 557 uint16_t bootup_mvpp_mv; 558 uint32_t zfbstartaddrin16mb; 559 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 560 uint32_t reserved2[2]; 561 }; 562 563 /* 564 *************************************************************************** 565 Data Table lcd_info structure 566 *************************************************************************** 567 */ 568 569 struct lcd_info_v2_1 570 { 571 struct atom_common_table_header table_header; 572 struct atom_dtd_format lcd_timing; 573 uint16_t backlight_pwm; 574 uint16_t special_handle_cap; 575 uint16_t panel_misc; 576 uint16_t lvds_max_slink_pclk; 577 uint16_t lvds_ss_percentage; 578 uint16_t lvds_ss_rate_10hz; 579 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 580 uint8_t pwr_on_de_to_vary_bl; 581 uint8_t pwr_down_vary_bloff_to_de; 582 uint8_t pwr_down_de_to_digoff; 583 uint8_t pwr_off_delay; 584 uint8_t pwr_on_vary_bl_to_blon; 585 uint8_t pwr_down_bloff_to_vary_bloff; 586 uint8_t panel_bpc; 587 uint8_t dpcd_edp_config_cap; 588 uint8_t dpcd_max_link_rate; 589 uint8_t dpcd_max_lane_count; 590 uint8_t dpcd_max_downspread; 591 uint8_t min_allowed_bl_level; 592 uint8_t max_allowed_bl_level; 593 uint8_t bootup_bl_level; 594 uint8_t dplvdsrxid; 595 uint32_t reserved1[8]; 596 }; 597 598 /* lcd_info_v2_1.panel_misc defintion */ 599 enum atom_lcd_info_panel_misc{ 600 ATOM_PANEL_MISC_FPDI =0x0002, 601 }; 602 603 //uceDPToLVDSRxId 604 enum atom_lcd_info_dptolvds_rx_id 605 { 606 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 607 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 608 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 609 }; 610 611 612 /* 613 *************************************************************************** 614 Data Table gpio_pin_lut structure 615 *************************************************************************** 616 */ 617 618 struct atom_gpio_pin_assignment 619 { 620 uint32_t data_a_reg_index; 621 uint8_t gpio_bitshift; 622 uint8_t gpio_mask_bitshift; 623 uint8_t gpio_id; 624 uint8_t reserved; 625 }; 626 627 /* atom_gpio_pin_assignment.gpio_id definition */ 628 enum atom_gpio_pin_assignment_gpio_id { 629 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 630 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 631 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 632 633 /* gpio_id pre-define id for multiple usage */ 634 /* GPIO use to control PCIE_VDDC in certain SLT board */ 635 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 636 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ 637 PP_AC_DC_SWITCH_GPIO_PINID = 60, 638 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 639 VDDC_VRHOT_GPIO_PINID = 61, 640 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 641 VDDC_PCC_GPIO_PINID = 62, 642 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 643 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 644 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 645 DRAM_SELF_REFRESH_GPIO_PINID = 64, 646 /* Thermal interrupt output->system thermal chip GPIO pin */ 647 THERMAL_INT_OUTPUT_GPIO_PINID =65, 648 }; 649 650 651 struct atom_gpio_pin_lut_v2_1 652 { 653 struct atom_common_table_header table_header; 654 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 655 struct atom_gpio_pin_assignment gpio_pin[8]; 656 }; 657 658 659 /* 660 *************************************************************************** 661 Data Table vram_usagebyfirmware structure 662 *************************************************************************** 663 */ 664 665 struct vram_usagebyfirmware_v2_1 666 { 667 struct atom_common_table_header table_header; 668 uint32_t start_address_in_kb; 669 uint16_t used_by_firmware_in_kb; 670 uint16_t used_by_driver_in_kb; 671 }; 672 673 674 /* 675 *************************************************************************** 676 Data Table displayobjectinfo structure 677 *************************************************************************** 678 */ 679 680 enum atom_object_record_type_id 681 { 682 ATOM_I2C_RECORD_TYPE =1, 683 ATOM_HPD_INT_RECORD_TYPE =2, 684 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9, 685 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16, 686 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17, 687 ATOM_ENCODER_CAP_RECORD_TYPE=20, 688 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21, 689 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22, 690 ATOM_RECORD_END_TYPE =0xFF, 691 }; 692 693 struct atom_common_record_header 694 { 695 uint8_t record_type; //An emun to indicate the record type 696 uint8_t record_size; //The size of the whole record in byte 697 }; 698 699 struct atom_i2c_record 700 { 701 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 702 uint8_t i2c_id; 703 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 704 }; 705 706 struct atom_hpd_int_record 707 { 708 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 709 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 710 uint8_t plugin_pin_state; 711 }; 712 713 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 714 enum atom_encoder_caps_def 715 { 716 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 717 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 718 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 719 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 720 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 721 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 722 }; 723 724 struct atom_encoder_caps_record 725 { 726 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 727 uint32_t encodercaps; 728 }; 729 730 enum atom_connector_caps_def 731 { 732 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 733 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 734 }; 735 736 struct atom_disp_connector_caps_record 737 { 738 struct atom_common_record_header record_header; 739 uint32_t connectcaps; 740 }; 741 742 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 743 struct atom_gpio_pin_control_pair 744 { 745 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 746 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 747 }; 748 749 struct atom_object_gpio_cntl_record 750 { 751 struct atom_common_record_header record_header; 752 uint8_t flag; // Future expnadibility 753 uint8_t number_of_pins; // Number of GPIO pins used to control the object 754 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 755 }; 756 757 //Definitions for GPIO pin state 758 enum atom_gpio_pin_control_pinstate_def 759 { 760 GPIO_PIN_TYPE_INPUT = 0x00, 761 GPIO_PIN_TYPE_OUTPUT = 0x10, 762 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 763 764 //For GPIO_PIN_TYPE_OUTPUT the following is defined 765 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 766 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 767 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 768 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 769 }; 770 771 // Indexes to GPIO array in GLSync record 772 // GLSync record is for Frame Lock/Gen Lock feature. 773 enum atom_glsync_record_gpio_index_def 774 { 775 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 776 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 777 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 778 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 779 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 780 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 781 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 782 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 783 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 784 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 785 }; 786 787 788 struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 789 { 790 struct atom_common_record_header record_header; 791 uint8_t hpd_pin_map[8]; 792 }; 793 794 struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 795 { 796 struct atom_common_record_header record_header; 797 uint8_t aux_ddc_map[8]; 798 }; 799 800 struct atom_connector_forced_tmds_cap_record 801 { 802 struct atom_common_record_header record_header; 803 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 804 uint8_t maxtmdsclkrate_in2_5mhz; 805 uint8_t reserved; 806 }; 807 808 struct atom_connector_layout_info 809 { 810 uint16_t connectorobjid; 811 uint8_t connector_type; 812 uint8_t position; 813 }; 814 815 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 816 enum atom_connector_layout_info_connector_type_def 817 { 818 CONNECTOR_TYPE_DVI_D = 1, 819 820 CONNECTOR_TYPE_HDMI = 4, 821 CONNECTOR_TYPE_DISPLAY_PORT = 5, 822 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 823 }; 824 825 struct atom_bracket_layout_record 826 { 827 struct atom_common_record_header record_header; 828 uint8_t bracketlen; 829 uint8_t bracketwidth; 830 uint8_t conn_num; 831 uint8_t reserved; 832 struct atom_connector_layout_info conn_info[1]; 833 }; 834 835 enum atom_display_device_tag_def{ 836 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 837 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 838 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 839 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 840 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 841 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 842 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 843 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 844 }; 845 846 struct atom_display_object_path_v2 847 { 848 uint16_t display_objid; //Connector Object ID or Misc Object ID 849 uint16_t disp_recordoffset; 850 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 851 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 852 uint16_t encoder_recordoffset; 853 uint16_t extencoder_recordoffset; 854 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 855 uint8_t priority_id; 856 uint8_t reserved; 857 }; 858 859 struct display_object_info_table_v1_4 860 { 861 struct atom_common_table_header table_header; 862 uint16_t supporteddevices; 863 uint8_t number_of_path; 864 uint8_t reserved; 865 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 866 }; 867 868 869 /* 870 *************************************************************************** 871 Data Table dce_info structure 872 *************************************************************************** 873 */ 874 struct atom_display_controller_info_v4_1 875 { 876 struct atom_common_table_header table_header; 877 uint32_t display_caps; 878 uint32_t bootup_dispclk_10khz; 879 uint16_t dce_refclk_10khz; 880 uint16_t i2c_engine_refclk_10khz; 881 uint16_t dvi_ss_percentage; // in unit of 0.001% 882 uint16_t dvi_ss_rate_10hz; 883 uint16_t hdmi_ss_percentage; // in unit of 0.001% 884 uint16_t hdmi_ss_rate_10hz; 885 uint16_t dp_ss_percentage; // in unit of 0.001% 886 uint16_t dp_ss_rate_10hz; 887 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 888 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 889 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 890 uint8_t ss_reserved; 891 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 892 uint8_t reserved1[3]; 893 uint16_t dpphy_refclk_10khz; 894 uint16_t reserved2; 895 uint8_t dceip_min_ver; 896 uint8_t dceip_max_ver; 897 uint8_t max_disp_pipe_num; 898 uint8_t max_vbios_active_disp_pipe_num; 899 uint8_t max_ppll_num; 900 uint8_t max_disp_phy_num; 901 uint8_t max_aux_pairs; 902 uint8_t remotedisplayconfig; 903 uint8_t reserved3[8]; 904 }; 905 906 907 struct atom_display_controller_info_v4_2 908 { 909 struct atom_common_table_header table_header; 910 uint32_t display_caps; 911 uint32_t bootup_dispclk_10khz; 912 uint16_t dce_refclk_10khz; 913 uint16_t i2c_engine_refclk_10khz; 914 uint16_t dvi_ss_percentage; // in unit of 0.001% 915 uint16_t dvi_ss_rate_10hz; 916 uint16_t hdmi_ss_percentage; // in unit of 0.001% 917 uint16_t hdmi_ss_rate_10hz; 918 uint16_t dp_ss_percentage; // in unit of 0.001% 919 uint16_t dp_ss_rate_10hz; 920 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 921 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 922 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 923 uint8_t ss_reserved; 924 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 925 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 926 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 927 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 928 uint16_t dpphy_refclk_10khz; 929 uint16_t reserved2; 930 uint8_t dcnip_min_ver; 931 uint8_t dcnip_max_ver; 932 uint8_t max_disp_pipe_num; 933 uint8_t max_vbios_active_disp_pipe_num; 934 uint8_t max_ppll_num; 935 uint8_t max_disp_phy_num; 936 uint8_t max_aux_pairs; 937 uint8_t remotedisplayconfig; 938 uint8_t reserved3[8]; 939 }; 940 941 942 enum dce_info_caps_def 943 { 944 // only for VBIOS 945 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02, 946 // only for VBIOS 947 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04, 948 // only for VBIOS 949 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, 950 951 }; 952 953 /* 954 *************************************************************************** 955 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 956 *************************************************************************** 957 */ 958 struct atom_ext_display_path 959 { 960 uint16_t device_tag; //A bit vector to show what devices are supported 961 uint16_t device_acpi_enum; //16bit device ACPI id. 962 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 963 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 964 uint8_t hpdlut_index; //An index into external HPD pin LUT 965 uint16_t ext_encoder_objid; //external encoder object id 966 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 967 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 968 uint16_t caps; 969 uint16_t reserved; 970 }; 971 972 //usCaps 973 enum ext_display_path_cap_def 974 { 975 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =0x0001, 976 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =0x0002, 977 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =0x007C, 978 }; 979 980 struct atom_external_display_connection_info 981 { 982 struct atom_common_table_header table_header; 983 uint8_t guid[16]; // a GUID is a 16 byte long string 984 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 985 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 986 uint8_t stereopinid; // use for eDP panel 987 uint8_t remotedisplayconfig; 988 uint8_t edptolvdsrxid; 989 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 990 uint8_t reserved[3]; // for potential expansion 991 }; 992 993 /* 994 *************************************************************************** 995 Data Table integratedsysteminfo structure 996 *************************************************************************** 997 */ 998 999 struct atom_camera_dphy_timing_param 1000 { 1001 uint8_t profile_id; // SENSOR_PROFILES 1002 uint32_t param; 1003 }; 1004 1005 struct atom_camera_dphy_elec_param 1006 { 1007 uint16_t param[3]; 1008 }; 1009 1010 struct atom_camera_module_info 1011 { 1012 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 1013 uint8_t module_name[8]; 1014 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 1015 }; 1016 1017 struct atom_camera_flashlight_info 1018 { 1019 uint8_t flashlight_id; // 0: Rear, 1: Front 1020 uint8_t name[8]; 1021 }; 1022 1023 struct atom_camera_data 1024 { 1025 uint32_t versionCode; 1026 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 1027 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 1028 struct atom_camera_dphy_elec_param dphy_param; 1029 uint32_t crc_val; // CRC 1030 }; 1031 1032 1033 struct atom_14nm_dpphy_dvihdmi_tuningset 1034 { 1035 uint32_t max_symclk_in10khz; 1036 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1037 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1038 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1039 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1040 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1041 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 1042 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 1043 }; 1044 1045 struct atom_14nm_dpphy_dp_setting{ 1046 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1047 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1048 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1049 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1050 }; 1051 1052 struct atom_14nm_dpphy_dp_tuningset{ 1053 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1054 uint8_t version; 1055 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 1056 uint16_t reserved; 1057 struct atom_14nm_dpphy_dp_setting dptuning[10]; 1058 }; 1059 1060 struct atom_14nm_dig_transmitter_info_header_v4_0{ 1061 struct atom_common_table_header table_header; 1062 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1063 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1064 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1065 }; 1066 1067 struct atom_14nm_combphy_tmds_vs_set 1068 { 1069 uint8_t sym_clk; 1070 uint8_t dig_mode; 1071 uint8_t phy_sel; 1072 uint16_t common_mar_deemph_nom__margin_deemph_val; 1073 uint8_t common_seldeemph60__deemph_6db_4_val; 1074 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1075 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1076 uint8_t margin_deemph_lane0__deemph_sel_val; 1077 }; 1078 1079 struct atom_i2c_reg_info { 1080 uint8_t ucI2cRegIndex; 1081 uint8_t ucI2cRegVal; 1082 }; 1083 1084 struct atom_hdmi_retimer_redriver_set { 1085 uint8_t HdmiSlvAddr; 1086 uint8_t HdmiRegNum; 1087 uint8_t Hdmi6GRegNum; 1088 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use 1089 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. 1090 }; 1091 1092 struct atom_integrated_system_info_v1_11 1093 { 1094 struct atom_common_table_header table_header; 1095 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1096 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1097 uint32_t system_config; 1098 uint32_t cpucapinfo; 1099 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1100 uint16_t gpuclk_ss_type; 1101 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1102 uint16_t lvds_ss_rate_10hz; 1103 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1104 uint16_t hdmi_ss_rate_10hz; 1105 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1106 uint16_t dvi_ss_rate_10hz; 1107 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1108 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1109 uint16_t backlight_pwm_hz; // pwm frequency in hz 1110 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1111 uint8_t umachannelnumber; // number of memory channels 1112 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1113 uint8_t pwr_on_de_to_vary_bl; 1114 uint8_t pwr_down_vary_bloff_to_de; 1115 uint8_t pwr_down_de_to_digoff; 1116 uint8_t pwr_off_delay; 1117 uint8_t pwr_on_vary_bl_to_blon; 1118 uint8_t pwr_down_bloff_to_vary_bloff; 1119 uint8_t min_allowed_bl_level; 1120 uint8_t htc_hyst_limit; 1121 uint8_t htc_tmp_limit; 1122 uint8_t reserved1; 1123 uint8_t reserved2; 1124 struct atom_external_display_connection_info extdispconninfo; 1125 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1126 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1127 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1128 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set 1129 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set 1130 struct atom_camera_data camera_info; 1131 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1132 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1133 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1134 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1135 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set 1136 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set 1137 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set 1138 uint32_t reserved[66]; 1139 }; 1140 1141 1142 // system_config 1143 enum atom_system_vbiosmisc_def{ 1144 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1145 }; 1146 1147 1148 // gpucapinfo 1149 enum atom_system_gpucapinf_def{ 1150 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, 1151 }; 1152 1153 //dpphy_override 1154 enum atom_sysinfo_dpphy_override_def{ 1155 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1156 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1157 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1158 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1159 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1160 }; 1161 1162 //lvds_misc 1163 enum atom_sys_info_lvds_misc_def 1164 { 1165 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1166 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1167 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1168 }; 1169 1170 1171 //memorytype DMI Type 17 offset 12h - Memory Type 1172 enum atom_dmi_t17_mem_type_def{ 1173 OtherMemType = 0x01, ///< Assign 01 to Other 1174 UnknownMemType, ///< Assign 02 to Unknown 1175 DramMemType, ///< Assign 03 to DRAM 1176 EdramMemType, ///< Assign 04 to EDRAM 1177 VramMemType, ///< Assign 05 to VRAM 1178 SramMemType, ///< Assign 06 to SRAM 1179 RamMemType, ///< Assign 07 to RAM 1180 RomMemType, ///< Assign 08 to ROM 1181 FlashMemType, ///< Assign 09 to Flash 1182 EepromMemType, ///< Assign 10 to EEPROM 1183 FepromMemType, ///< Assign 11 to FEPROM 1184 EpromMemType, ///< Assign 12 to EPROM 1185 CdramMemType, ///< Assign 13 to CDRAM 1186 ThreeDramMemType, ///< Assign 14 to 3DRAM 1187 SdramMemType, ///< Assign 15 to SDRAM 1188 SgramMemType, ///< Assign 16 to SGRAM 1189 RdramMemType, ///< Assign 17 to RDRAM 1190 DdrMemType, ///< Assign 18 to DDR 1191 Ddr2MemType, ///< Assign 19 to DDR2 1192 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1193 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1194 Fbd2MemType, ///< Assign 25 to FBD2 1195 Ddr4MemType, ///< Assign 26 to DDR4 1196 LpDdrMemType, ///< Assign 27 to LPDDR 1197 LpDdr2MemType, ///< Assign 28 to LPDDR2 1198 LpDdr3MemType, ///< Assign 29 to LPDDR3 1199 LpDdr4MemType, ///< Assign 30 to LPDDR4 1200 }; 1201 1202 1203 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1204 struct atom_fusion_system_info_v4 1205 { 1206 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1207 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1208 }; 1209 1210 1211 /* 1212 *************************************************************************** 1213 Data Table gfx_info structure 1214 *************************************************************************** 1215 */ 1216 1217 struct atom_gfx_info_v2_2 1218 { 1219 struct atom_common_table_header table_header; 1220 uint8_t gfxip_min_ver; 1221 uint8_t gfxip_max_ver; 1222 uint8_t max_shader_engines; 1223 uint8_t max_tile_pipes; 1224 uint8_t max_cu_per_sh; 1225 uint8_t max_sh_per_se; 1226 uint8_t max_backends_per_se; 1227 uint8_t max_texture_channel_caches; 1228 uint32_t regaddr_cp_dma_src_addr; 1229 uint32_t regaddr_cp_dma_src_addr_hi; 1230 uint32_t regaddr_cp_dma_dst_addr; 1231 uint32_t regaddr_cp_dma_dst_addr_hi; 1232 uint32_t regaddr_cp_dma_command; 1233 uint32_t regaddr_cp_status; 1234 uint32_t regaddr_rlc_gpu_clock_32; 1235 uint32_t rlc_gpu_timer_refclk; 1236 }; 1237 1238 struct atom_gfx_info_v2_3 { 1239 struct atom_common_table_header table_header; 1240 uint8_t gfxip_min_ver; 1241 uint8_t gfxip_max_ver; 1242 uint8_t max_shader_engines; 1243 uint8_t max_tile_pipes; 1244 uint8_t max_cu_per_sh; 1245 uint8_t max_sh_per_se; 1246 uint8_t max_backends_per_se; 1247 uint8_t max_texture_channel_caches; 1248 uint32_t regaddr_cp_dma_src_addr; 1249 uint32_t regaddr_cp_dma_src_addr_hi; 1250 uint32_t regaddr_cp_dma_dst_addr; 1251 uint32_t regaddr_cp_dma_dst_addr_hi; 1252 uint32_t regaddr_cp_dma_command; 1253 uint32_t regaddr_cp_status; 1254 uint32_t regaddr_rlc_gpu_clock_32; 1255 uint32_t rlc_gpu_timer_refclk; 1256 uint8_t active_cu_per_sh; 1257 uint8_t active_rb_per_se; 1258 uint16_t gcgoldenoffset; 1259 uint32_t rm21_sram_vmin_value; 1260 }; 1261 1262 struct atom_gfx_info_v2_4 1263 { 1264 struct atom_common_table_header table_header; 1265 uint8_t gfxip_min_ver; 1266 uint8_t gfxip_max_ver; 1267 uint8_t max_shader_engines; 1268 uint8_t reserved; 1269 uint8_t max_cu_per_sh; 1270 uint8_t max_sh_per_se; 1271 uint8_t max_backends_per_se; 1272 uint8_t max_texture_channel_caches; 1273 uint32_t regaddr_cp_dma_src_addr; 1274 uint32_t regaddr_cp_dma_src_addr_hi; 1275 uint32_t regaddr_cp_dma_dst_addr; 1276 uint32_t regaddr_cp_dma_dst_addr_hi; 1277 uint32_t regaddr_cp_dma_command; 1278 uint32_t regaddr_cp_status; 1279 uint32_t regaddr_rlc_gpu_clock_32; 1280 uint32_t rlc_gpu_timer_refclk; 1281 uint8_t active_cu_per_sh; 1282 uint8_t active_rb_per_se; 1283 uint16_t gcgoldenoffset; 1284 uint16_t gc_num_gprs; 1285 uint16_t gc_gsprim_buff_depth; 1286 uint16_t gc_parameter_cache_depth; 1287 uint16_t gc_wave_size; 1288 uint16_t gc_max_waves_per_simd; 1289 uint16_t gc_lds_size; 1290 uint8_t gc_num_max_gs_thds; 1291 uint8_t gc_gs_table_depth; 1292 uint8_t gc_double_offchip_lds_buffer; 1293 uint8_t gc_max_scratch_slots_per_cu; 1294 uint32_t sram_rm_fuses_val; 1295 uint32_t sram_custom_rm_fuses_val; 1296 }; 1297 1298 /* 1299 *************************************************************************** 1300 Data Table smu_info structure 1301 *************************************************************************** 1302 */ 1303 struct atom_smu_info_v3_1 1304 { 1305 struct atom_common_table_header table_header; 1306 uint8_t smuip_min_ver; 1307 uint8_t smuip_max_ver; 1308 uint8_t smu_rsd1; 1309 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1310 uint16_t sclk_ss_percentage; 1311 uint16_t sclk_ss_rate_10hz; 1312 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1313 uint16_t gpuclk_ss_rate_10hz; 1314 uint32_t core_refclk_10khz; 1315 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1316 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1317 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1318 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1319 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1320 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1321 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1322 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1323 }; 1324 1325 struct atom_smu_info_v3_2 { 1326 struct atom_common_table_header table_header; 1327 uint8_t smuip_min_ver; 1328 uint8_t smuip_max_ver; 1329 uint8_t smu_rsd1; 1330 uint8_t gpuclk_ss_mode; 1331 uint16_t sclk_ss_percentage; 1332 uint16_t sclk_ss_rate_10hz; 1333 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1334 uint16_t gpuclk_ss_rate_10hz; 1335 uint32_t core_refclk_10khz; 1336 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1337 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1338 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1339 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1340 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1341 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1342 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1343 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1344 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1345 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1346 uint16_t smugoldenoffset; 1347 uint32_t gpupll_vco_freq_10khz; 1348 uint32_t bootup_smnclk_10khz; 1349 uint32_t bootup_socclk_10khz; 1350 uint32_t bootup_mp0clk_10khz; 1351 uint32_t bootup_mp1clk_10khz; 1352 uint32_t bootup_lclk_10khz; 1353 uint32_t bootup_dcefclk_10khz; 1354 uint32_t ctf_threshold_override_value; 1355 uint32_t reserved[5]; 1356 }; 1357 1358 struct atom_smu_info_v3_3 { 1359 struct atom_common_table_header table_header; 1360 uint8_t smuip_min_ver; 1361 uint8_t smuip_max_ver; 1362 uint8_t waflclk_ss_mode; 1363 uint8_t gpuclk_ss_mode; 1364 uint16_t sclk_ss_percentage; 1365 uint16_t sclk_ss_rate_10hz; 1366 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1367 uint16_t gpuclk_ss_rate_10hz; 1368 uint32_t core_refclk_10khz; 1369 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1370 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1371 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1372 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1373 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1374 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1375 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1376 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1377 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1378 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1379 uint16_t smugoldenoffset; 1380 uint32_t gpupll_vco_freq_10khz; 1381 uint32_t bootup_smnclk_10khz; 1382 uint32_t bootup_socclk_10khz; 1383 uint32_t bootup_mp0clk_10khz; 1384 uint32_t bootup_mp1clk_10khz; 1385 uint32_t bootup_lclk_10khz; 1386 uint32_t bootup_dcefclk_10khz; 1387 uint32_t ctf_threshold_override_value; 1388 uint32_t syspll3_0_vco_freq_10khz; 1389 uint32_t syspll3_1_vco_freq_10khz; 1390 uint32_t bootup_fclk_10khz; 1391 uint32_t bootup_waflclk_10khz; 1392 uint32_t smu_info_caps; 1393 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1394 uint16_t smuinitoffset; 1395 uint32_t reserved; 1396 }; 1397 1398 /* 1399 *************************************************************************** 1400 Data Table smc_dpm_info structure 1401 *************************************************************************** 1402 */ 1403 struct atom_smc_dpm_info_v4_1 1404 { 1405 struct atom_common_table_header table_header; 1406 uint8_t liquid1_i2c_address; 1407 uint8_t liquid2_i2c_address; 1408 uint8_t vr_i2c_address; 1409 uint8_t plx_i2c_address; 1410 1411 uint8_t liquid_i2c_linescl; 1412 uint8_t liquid_i2c_linesda; 1413 uint8_t vr_i2c_linescl; 1414 uint8_t vr_i2c_linesda; 1415 1416 uint8_t plx_i2c_linescl; 1417 uint8_t plx_i2c_linesda; 1418 uint8_t vrsensorpresent; 1419 uint8_t liquidsensorpresent; 1420 1421 uint16_t maxvoltagestepgfx; 1422 uint16_t maxvoltagestepsoc; 1423 1424 uint8_t vddgfxvrmapping; 1425 uint8_t vddsocvrmapping; 1426 uint8_t vddmem0vrmapping; 1427 uint8_t vddmem1vrmapping; 1428 1429 uint8_t gfxulvphasesheddingmask; 1430 uint8_t soculvphasesheddingmask; 1431 uint8_t padding8_v[2]; 1432 1433 uint16_t gfxmaxcurrent; 1434 uint8_t gfxoffset; 1435 uint8_t padding_telemetrygfx; 1436 1437 uint16_t socmaxcurrent; 1438 uint8_t socoffset; 1439 uint8_t padding_telemetrysoc; 1440 1441 uint16_t mem0maxcurrent; 1442 uint8_t mem0offset; 1443 uint8_t padding_telemetrymem0; 1444 1445 uint16_t mem1maxcurrent; 1446 uint8_t mem1offset; 1447 uint8_t padding_telemetrymem1; 1448 1449 uint8_t acdcgpio; 1450 uint8_t acdcpolarity; 1451 uint8_t vr0hotgpio; 1452 uint8_t vr0hotpolarity; 1453 1454 uint8_t vr1hotgpio; 1455 uint8_t vr1hotpolarity; 1456 uint8_t padding1; 1457 uint8_t padding2; 1458 1459 uint8_t ledpin0; 1460 uint8_t ledpin1; 1461 uint8_t ledpin2; 1462 uint8_t padding8_4; 1463 1464 uint8_t pllgfxclkspreadenabled; 1465 uint8_t pllgfxclkspreadpercent; 1466 uint16_t pllgfxclkspreadfreq; 1467 1468 uint8_t uclkspreadenabled; 1469 uint8_t uclkspreadpercent; 1470 uint16_t uclkspreadfreq; 1471 1472 uint8_t socclkspreadenabled; 1473 uint8_t socclkspreadpercent; 1474 uint16_t socclkspreadfreq; 1475 1476 uint8_t acggfxclkspreadenabled; 1477 uint8_t acggfxclkspreadpercent; 1478 uint16_t acggfxclkspreadfreq; 1479 1480 uint8_t Vr2_I2C_address; 1481 uint8_t padding_vr2[3]; 1482 1483 uint32_t boardreserved[9]; 1484 }; 1485 1486 /* 1487 *************************************************************************** 1488 Data Table smc_dpm_info structure 1489 *************************************************************************** 1490 */ 1491 struct atom_smc_dpm_info_v4_3 1492 { 1493 struct atom_common_table_header table_header; 1494 uint8_t liquid1_i2c_address; 1495 uint8_t liquid2_i2c_address; 1496 uint8_t vr_i2c_address; 1497 uint8_t plx_i2c_address; 1498 1499 uint8_t liquid_i2c_linescl; 1500 uint8_t liquid_i2c_linesda; 1501 uint8_t vr_i2c_linescl; 1502 uint8_t vr_i2c_linesda; 1503 1504 uint8_t plx_i2c_linescl; 1505 uint8_t plx_i2c_linesda; 1506 uint8_t vrsensorpresent; 1507 uint8_t liquidsensorpresent; 1508 1509 uint16_t maxvoltagestepgfx; 1510 uint16_t maxvoltagestepsoc; 1511 1512 uint8_t vddgfxvrmapping; 1513 uint8_t vddsocvrmapping; 1514 uint8_t vddmem0vrmapping; 1515 uint8_t vddmem1vrmapping; 1516 1517 uint8_t gfxulvphasesheddingmask; 1518 uint8_t soculvphasesheddingmask; 1519 uint8_t externalsensorpresent; 1520 uint8_t padding8_v; 1521 1522 uint16_t gfxmaxcurrent; 1523 uint8_t gfxoffset; 1524 uint8_t padding_telemetrygfx; 1525 1526 uint16_t socmaxcurrent; 1527 uint8_t socoffset; 1528 uint8_t padding_telemetrysoc; 1529 1530 uint16_t mem0maxcurrent; 1531 uint8_t mem0offset; 1532 uint8_t padding_telemetrymem0; 1533 1534 uint16_t mem1maxcurrent; 1535 uint8_t mem1offset; 1536 uint8_t padding_telemetrymem1; 1537 1538 uint8_t acdcgpio; 1539 uint8_t acdcpolarity; 1540 uint8_t vr0hotgpio; 1541 uint8_t vr0hotpolarity; 1542 1543 uint8_t vr1hotgpio; 1544 uint8_t vr1hotpolarity; 1545 uint8_t padding1; 1546 uint8_t padding2; 1547 1548 uint8_t ledpin0; 1549 uint8_t ledpin1; 1550 uint8_t ledpin2; 1551 uint8_t padding8_4; 1552 1553 uint8_t pllgfxclkspreadenabled; 1554 uint8_t pllgfxclkspreadpercent; 1555 uint16_t pllgfxclkspreadfreq; 1556 1557 uint8_t uclkspreadenabled; 1558 uint8_t uclkspreadpercent; 1559 uint16_t uclkspreadfreq; 1560 1561 uint8_t fclkspreadenabled; 1562 uint8_t fclkspreadpercent; 1563 uint16_t fclkspreadfreq; 1564 1565 uint8_t fllgfxclkspreadenabled; 1566 uint8_t fllgfxclkspreadpercent; 1567 uint16_t fllgfxclkspreadfreq; 1568 1569 uint32_t boardreserved[10]; 1570 }; 1571 1572 struct smudpm_i2ccontrollerconfig_t { 1573 uint32_t enabled; 1574 uint32_t slaveaddress; 1575 uint32_t controllerport; 1576 uint32_t controllername; 1577 uint32_t thermalthrottler; 1578 uint32_t i2cprotocol; 1579 uint32_t i2cspeed; 1580 }; 1581 1582 struct atom_smc_dpm_info_v4_4 1583 { 1584 struct atom_common_table_header table_header; 1585 uint32_t i2c_padding[3]; 1586 1587 uint16_t maxvoltagestepgfx; 1588 uint16_t maxvoltagestepsoc; 1589 1590 uint8_t vddgfxvrmapping; 1591 uint8_t vddsocvrmapping; 1592 uint8_t vddmem0vrmapping; 1593 uint8_t vddmem1vrmapping; 1594 1595 uint8_t gfxulvphasesheddingmask; 1596 uint8_t soculvphasesheddingmask; 1597 uint8_t externalsensorpresent; 1598 uint8_t padding8_v; 1599 1600 uint16_t gfxmaxcurrent; 1601 uint8_t gfxoffset; 1602 uint8_t padding_telemetrygfx; 1603 1604 uint16_t socmaxcurrent; 1605 uint8_t socoffset; 1606 uint8_t padding_telemetrysoc; 1607 1608 uint16_t mem0maxcurrent; 1609 uint8_t mem0offset; 1610 uint8_t padding_telemetrymem0; 1611 1612 uint16_t mem1maxcurrent; 1613 uint8_t mem1offset; 1614 uint8_t padding_telemetrymem1; 1615 1616 1617 uint8_t acdcgpio; 1618 uint8_t acdcpolarity; 1619 uint8_t vr0hotgpio; 1620 uint8_t vr0hotpolarity; 1621 1622 uint8_t vr1hotgpio; 1623 uint8_t vr1hotpolarity; 1624 uint8_t padding1; 1625 uint8_t padding2; 1626 1627 1628 uint8_t ledpin0; 1629 uint8_t ledpin1; 1630 uint8_t ledpin2; 1631 uint8_t padding8_4; 1632 1633 1634 uint8_t pllgfxclkspreadenabled; 1635 uint8_t pllgfxclkspreadpercent; 1636 uint16_t pllgfxclkspreadfreq; 1637 1638 1639 uint8_t uclkspreadenabled; 1640 uint8_t uclkspreadpercent; 1641 uint16_t uclkspreadfreq; 1642 1643 1644 uint8_t fclkspreadenabled; 1645 uint8_t fclkspreadpercent; 1646 uint16_t fclkspreadfreq; 1647 1648 1649 uint8_t fllgfxclkspreadenabled; 1650 uint8_t fllgfxclkspreadpercent; 1651 uint16_t fllgfxclkspreadfreq; 1652 1653 1654 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 1655 1656 1657 uint32_t boardreserved[10]; 1658 }; 1659 1660 /* 1661 *************************************************************************** 1662 Data Table asic_profiling_info structure 1663 *************************************************************************** 1664 */ 1665 struct atom_asic_profiling_info_v4_1 1666 { 1667 struct atom_common_table_header table_header; 1668 uint32_t maxvddc; 1669 uint32_t minvddc; 1670 uint32_t avfs_meannsigma_acontant0; 1671 uint32_t avfs_meannsigma_acontant1; 1672 uint32_t avfs_meannsigma_acontant2; 1673 uint16_t avfs_meannsigma_dc_tol_sigma; 1674 uint16_t avfs_meannsigma_platform_mean; 1675 uint16_t avfs_meannsigma_platform_sigma; 1676 uint32_t gb_vdroop_table_cksoff_a0; 1677 uint32_t gb_vdroop_table_cksoff_a1; 1678 uint32_t gb_vdroop_table_cksoff_a2; 1679 uint32_t gb_vdroop_table_ckson_a0; 1680 uint32_t gb_vdroop_table_ckson_a1; 1681 uint32_t gb_vdroop_table_ckson_a2; 1682 uint32_t avfsgb_fuse_table_cksoff_m1; 1683 uint32_t avfsgb_fuse_table_cksoff_m2; 1684 uint32_t avfsgb_fuse_table_cksoff_b; 1685 uint32_t avfsgb_fuse_table_ckson_m1; 1686 uint32_t avfsgb_fuse_table_ckson_m2; 1687 uint32_t avfsgb_fuse_table_ckson_b; 1688 uint16_t max_voltage_0_25mv; 1689 uint8_t enable_gb_vdroop_table_cksoff; 1690 uint8_t enable_gb_vdroop_table_ckson; 1691 uint8_t enable_gb_fuse_table_cksoff; 1692 uint8_t enable_gb_fuse_table_ckson; 1693 uint16_t psm_age_comfactor; 1694 uint8_t enable_apply_avfs_cksoff_voltage; 1695 uint8_t reserved; 1696 uint32_t dispclk2gfxclk_a; 1697 uint32_t dispclk2gfxclk_b; 1698 uint32_t dispclk2gfxclk_c; 1699 uint32_t pixclk2gfxclk_a; 1700 uint32_t pixclk2gfxclk_b; 1701 uint32_t pixclk2gfxclk_c; 1702 uint32_t dcefclk2gfxclk_a; 1703 uint32_t dcefclk2gfxclk_b; 1704 uint32_t dcefclk2gfxclk_c; 1705 uint32_t phyclk2gfxclk_a; 1706 uint32_t phyclk2gfxclk_b; 1707 uint32_t phyclk2gfxclk_c; 1708 }; 1709 1710 struct atom_asic_profiling_info_v4_2 { 1711 struct atom_common_table_header table_header; 1712 uint32_t maxvddc; 1713 uint32_t minvddc; 1714 uint32_t avfs_meannsigma_acontant0; 1715 uint32_t avfs_meannsigma_acontant1; 1716 uint32_t avfs_meannsigma_acontant2; 1717 uint16_t avfs_meannsigma_dc_tol_sigma; 1718 uint16_t avfs_meannsigma_platform_mean; 1719 uint16_t avfs_meannsigma_platform_sigma; 1720 uint32_t gb_vdroop_table_cksoff_a0; 1721 uint32_t gb_vdroop_table_cksoff_a1; 1722 uint32_t gb_vdroop_table_cksoff_a2; 1723 uint32_t gb_vdroop_table_ckson_a0; 1724 uint32_t gb_vdroop_table_ckson_a1; 1725 uint32_t gb_vdroop_table_ckson_a2; 1726 uint32_t avfsgb_fuse_table_cksoff_m1; 1727 uint32_t avfsgb_fuse_table_cksoff_m2; 1728 uint32_t avfsgb_fuse_table_cksoff_b; 1729 uint32_t avfsgb_fuse_table_ckson_m1; 1730 uint32_t avfsgb_fuse_table_ckson_m2; 1731 uint32_t avfsgb_fuse_table_ckson_b; 1732 uint16_t max_voltage_0_25mv; 1733 uint8_t enable_gb_vdroop_table_cksoff; 1734 uint8_t enable_gb_vdroop_table_ckson; 1735 uint8_t enable_gb_fuse_table_cksoff; 1736 uint8_t enable_gb_fuse_table_ckson; 1737 uint16_t psm_age_comfactor; 1738 uint8_t enable_apply_avfs_cksoff_voltage; 1739 uint8_t reserved; 1740 uint32_t dispclk2gfxclk_a; 1741 uint32_t dispclk2gfxclk_b; 1742 uint32_t dispclk2gfxclk_c; 1743 uint32_t pixclk2gfxclk_a; 1744 uint32_t pixclk2gfxclk_b; 1745 uint32_t pixclk2gfxclk_c; 1746 uint32_t dcefclk2gfxclk_a; 1747 uint32_t dcefclk2gfxclk_b; 1748 uint32_t dcefclk2gfxclk_c; 1749 uint32_t phyclk2gfxclk_a; 1750 uint32_t phyclk2gfxclk_b; 1751 uint32_t phyclk2gfxclk_c; 1752 uint32_t acg_gb_vdroop_table_a0; 1753 uint32_t acg_gb_vdroop_table_a1; 1754 uint32_t acg_gb_vdroop_table_a2; 1755 uint32_t acg_avfsgb_fuse_table_m1; 1756 uint32_t acg_avfsgb_fuse_table_m2; 1757 uint32_t acg_avfsgb_fuse_table_b; 1758 uint8_t enable_acg_gb_vdroop_table; 1759 uint8_t enable_acg_gb_fuse_table; 1760 uint32_t acg_dispclk2gfxclk_a; 1761 uint32_t acg_dispclk2gfxclk_b; 1762 uint32_t acg_dispclk2gfxclk_c; 1763 uint32_t acg_pixclk2gfxclk_a; 1764 uint32_t acg_pixclk2gfxclk_b; 1765 uint32_t acg_pixclk2gfxclk_c; 1766 uint32_t acg_dcefclk2gfxclk_a; 1767 uint32_t acg_dcefclk2gfxclk_b; 1768 uint32_t acg_dcefclk2gfxclk_c; 1769 uint32_t acg_phyclk2gfxclk_a; 1770 uint32_t acg_phyclk2gfxclk_b; 1771 uint32_t acg_phyclk2gfxclk_c; 1772 }; 1773 1774 /* 1775 *************************************************************************** 1776 Data Table multimedia_info structure 1777 *************************************************************************** 1778 */ 1779 struct atom_multimedia_info_v2_1 1780 { 1781 struct atom_common_table_header table_header; 1782 uint8_t uvdip_min_ver; 1783 uint8_t uvdip_max_ver; 1784 uint8_t vceip_min_ver; 1785 uint8_t vceip_max_ver; 1786 uint16_t uvd_enc_max_input_width_pixels; 1787 uint16_t uvd_enc_max_input_height_pixels; 1788 uint16_t vce_enc_max_input_width_pixels; 1789 uint16_t vce_enc_max_input_height_pixels; 1790 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 1791 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 1792 }; 1793 1794 1795 /* 1796 *************************************************************************** 1797 Data Table umc_info structure 1798 *************************************************************************** 1799 */ 1800 struct atom_umc_info_v3_1 1801 { 1802 struct atom_common_table_header table_header; 1803 uint32_t ucode_version; 1804 uint32_t ucode_rom_startaddr; 1805 uint32_t ucode_length; 1806 uint16_t umc_reg_init_offset; 1807 uint16_t customer_ucode_name_offset; 1808 uint16_t mclk_ss_percentage; 1809 uint16_t mclk_ss_rate_10hz; 1810 uint8_t umcip_min_ver; 1811 uint8_t umcip_max_ver; 1812 uint8_t vram_type; //enum of atom_dgpu_vram_type 1813 uint8_t umc_config; 1814 uint32_t mem_refclk_10khz; 1815 }; 1816 1817 // umc_info.umc_config 1818 enum atom_umc_config_def { 1819 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001, 1820 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002, 1821 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004, 1822 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008, 1823 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010, 1824 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020, 1825 }; 1826 1827 struct atom_umc_info_v3_2 1828 { 1829 struct atom_common_table_header table_header; 1830 uint32_t ucode_version; 1831 uint32_t ucode_rom_startaddr; 1832 uint32_t ucode_length; 1833 uint16_t umc_reg_init_offset; 1834 uint16_t customer_ucode_name_offset; 1835 uint16_t mclk_ss_percentage; 1836 uint16_t mclk_ss_rate_10hz; 1837 uint8_t umcip_min_ver; 1838 uint8_t umcip_max_ver; 1839 uint8_t vram_type; //enum of atom_dgpu_vram_type 1840 uint8_t umc_config; 1841 uint32_t mem_refclk_10khz; 1842 uint32_t pstate_uclk_10khz[4]; 1843 uint16_t umcgoldenoffset; 1844 uint16_t densitygoldenoffset; 1845 }; 1846 1847 struct atom_umc_info_v3_3 1848 { 1849 struct atom_common_table_header table_header; 1850 uint32_t ucode_reserved; 1851 uint32_t ucode_rom_startaddr; 1852 uint32_t ucode_length; 1853 uint16_t umc_reg_init_offset; 1854 uint16_t customer_ucode_name_offset; 1855 uint16_t mclk_ss_percentage; 1856 uint16_t mclk_ss_rate_10hz; 1857 uint8_t umcip_min_ver; 1858 uint8_t umcip_max_ver; 1859 uint8_t vram_type; //enum of atom_dgpu_vram_type 1860 uint8_t umc_config; 1861 uint32_t mem_refclk_10khz; 1862 uint32_t pstate_uclk_10khz[4]; 1863 uint16_t umcgoldenoffset; 1864 uint16_t densitygoldenoffset; 1865 uint32_t reserved[4]; 1866 }; 1867 1868 /* 1869 *************************************************************************** 1870 Data Table vram_info structure 1871 *************************************************************************** 1872 */ 1873 struct atom_vram_module_v9 1874 { 1875 // Design Specific Values 1876 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 1877 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 1878 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 1879 uint16_t reserved[3]; 1880 uint16_t mem_voltage; // mem_voltage 1881 uint16_t vram_module_size; // Size of atom_vram_module_v9 1882 uint8_t ext_memory_id; // Current memory module ID 1883 uint8_t memory_type; // enum of atom_dgpu_vram_type 1884 uint8_t channel_num; // Number of mem. channels supported in this module 1885 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 1886 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 1887 uint8_t tunningset_id; // MC phy registers set per. 1888 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 1889 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 1890 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id 1891 uint8_t vram_rsd2; // reserved 1892 char dram_pnstring[20]; // part number end with '0'. 1893 }; 1894 1895 struct atom_vram_info_header_v2_3 1896 { 1897 struct atom_common_table_header table_header; 1898 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 1899 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 1900 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 1901 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 1902 uint16_t dram_data_remap_tbloffset; // reserved for now 1903 uint16_t tmrs_seq_offset; // offset of HBM tmrs 1904 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 1905 uint16_t vram_rsd2; 1906 uint8_t vram_module_num; // indicate number of VRAM module 1907 uint8_t vram_rsd1[2]; 1908 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 1909 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 1910 }; 1911 1912 struct atom_umc_register_addr_info{ 1913 uint32_t umc_register_addr:24; 1914 uint32_t umc_reg_type_ind:1; 1915 uint32_t umc_reg_rsvd:7; 1916 }; 1917 1918 //atom_umc_register_addr_info. 1919 enum atom_umc_register_addr_info_flag{ 1920 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 1921 }; 1922 1923 union atom_umc_register_addr_info_access 1924 { 1925 struct atom_umc_register_addr_info umc_reg_addr; 1926 uint32_t u32umc_reg_addr; 1927 }; 1928 1929 struct atom_umc_reg_setting_id_config{ 1930 uint32_t memclockrange:24; 1931 uint32_t mem_blk_id:8; 1932 }; 1933 1934 union atom_umc_reg_setting_id_config_access 1935 { 1936 struct atom_umc_reg_setting_id_config umc_id_access; 1937 uint32_t u32umc_id_access; 1938 }; 1939 1940 struct atom_umc_reg_setting_data_block{ 1941 union atom_umc_reg_setting_id_config_access block_id; 1942 uint32_t u32umc_reg_data[1]; 1943 }; 1944 1945 struct atom_umc_init_reg_block{ 1946 uint16_t umc_reg_num; 1947 uint16_t reserved; 1948 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 1949 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 1950 }; 1951 1952 1953 /* 1954 *************************************************************************** 1955 Data Table voltageobject_info structure 1956 *************************************************************************** 1957 */ 1958 struct atom_i2c_data_entry 1959 { 1960 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 1961 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 1962 }; 1963 1964 struct atom_voltage_object_header_v4{ 1965 uint8_t voltage_type; //enum atom_voltage_type 1966 uint8_t voltage_mode; //enum atom_voltage_object_mode 1967 uint16_t object_size; //Size of Object 1968 }; 1969 1970 // atom_voltage_object_header_v4.voltage_mode 1971 enum atom_voltage_object_mode 1972 { 1973 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 1974 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 1975 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 1976 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 1977 VOLTAGE_OBJ_EVV = 8, 1978 VOLTAGE_OBJ_MERGED_POWER = 9, 1979 }; 1980 1981 struct atom_i2c_voltage_object_v4 1982 { 1983 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 1984 uint8_t regulator_id; //Indicate Voltage Regulator Id 1985 uint8_t i2c_id; 1986 uint8_t i2c_slave_addr; 1987 uint8_t i2c_control_offset; 1988 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 1989 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 1990 uint8_t reserved[2]; 1991 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 1992 }; 1993 1994 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 1995 enum atom_i2c_voltage_control_flag 1996 { 1997 VOLTAGE_DATA_ONE_BYTE = 0, 1998 VOLTAGE_DATA_TWO_BYTE = 1, 1999 }; 2000 2001 2002 struct atom_voltage_gpio_map_lut 2003 { 2004 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 2005 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 2006 }; 2007 2008 struct atom_gpio_voltage_object_v4 2009 { 2010 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 2011 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 2012 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table 2013 uint8_t phase_delay_us; // phase delay in unit of micro second 2014 uint8_t reserved; 2015 uint32_t gpio_mask_val; // GPIO Mask value 2016 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 2017 }; 2018 2019 struct atom_svid2_voltage_object_v4 2020 { 2021 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 2022 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 2023 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 2024 uint8_t psi0_enable; // 2025 uint8_t maxvstep; 2026 uint8_t telemetry_offset; 2027 uint8_t telemetry_gain; 2028 uint16_t reserved1; 2029 }; 2030 2031 struct atom_merged_voltage_object_v4 2032 { 2033 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 2034 uint8_t merged_powerrail_type; //enum atom_voltage_type 2035 uint8_t reserved[3]; 2036 }; 2037 2038 union atom_voltage_object_v4{ 2039 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 2040 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 2041 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 2042 struct atom_merged_voltage_object_v4 merged_voltage_obj; 2043 }; 2044 2045 struct atom_voltage_objects_info_v4_1 2046 { 2047 struct atom_common_table_header table_header; 2048 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 2049 }; 2050 2051 2052 /* 2053 *************************************************************************** 2054 All Command Function structure definition 2055 *************************************************************************** 2056 */ 2057 2058 /* 2059 *************************************************************************** 2060 Structures used by asic_init 2061 *************************************************************************** 2062 */ 2063 2064 struct asic_init_engine_parameters 2065 { 2066 uint32_t sclkfreqin10khz:24; 2067 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 2068 }; 2069 2070 struct asic_init_mem_parameters 2071 { 2072 uint32_t mclkfreqin10khz:24; 2073 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 2074 }; 2075 2076 struct asic_init_parameters_v2_1 2077 { 2078 struct asic_init_engine_parameters engineparam; 2079 struct asic_init_mem_parameters memparam; 2080 }; 2081 2082 struct asic_init_ps_allocation_v2_1 2083 { 2084 struct asic_init_parameters_v2_1 param; 2085 uint32_t reserved[16]; 2086 }; 2087 2088 2089 enum atom_asic_init_engine_flag 2090 { 2091 b3NORMAL_ENGINE_INIT = 0, 2092 b3SRIOV_SKIP_ASIC_INIT = 0x02, 2093 b3SRIOV_LOAD_UCODE = 0x40, 2094 }; 2095 2096 enum atom_asic_init_mem_flag 2097 { 2098 b3NORMAL_MEM_INIT = 0, 2099 b3DRAM_SELF_REFRESH_EXIT =0x20, 2100 }; 2101 2102 /* 2103 *************************************************************************** 2104 Structures used by setengineclock 2105 *************************************************************************** 2106 */ 2107 2108 struct set_engine_clock_parameters_v2_1 2109 { 2110 uint32_t sclkfreqin10khz:24; 2111 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 2112 uint32_t reserved[10]; 2113 }; 2114 2115 struct set_engine_clock_ps_allocation_v2_1 2116 { 2117 struct set_engine_clock_parameters_v2_1 clockinfo; 2118 uint32_t reserved[10]; 2119 }; 2120 2121 2122 enum atom_set_engine_mem_clock_flag 2123 { 2124 b3NORMAL_CHANGE_CLOCK = 0, 2125 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 2126 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 2127 }; 2128 2129 /* 2130 *************************************************************************** 2131 Structures used by getengineclock 2132 *************************************************************************** 2133 */ 2134 struct get_engine_clock_parameter 2135 { 2136 uint32_t sclk_10khz; // current engine speed in 10KHz unit 2137 uint32_t reserved; 2138 }; 2139 2140 /* 2141 *************************************************************************** 2142 Structures used by setmemoryclock 2143 *************************************************************************** 2144 */ 2145 struct set_memory_clock_parameters_v2_1 2146 { 2147 uint32_t mclkfreqin10khz:24; 2148 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 2149 uint32_t reserved[10]; 2150 }; 2151 2152 struct set_memory_clock_ps_allocation_v2_1 2153 { 2154 struct set_memory_clock_parameters_v2_1 clockinfo; 2155 uint32_t reserved[10]; 2156 }; 2157 2158 2159 /* 2160 *************************************************************************** 2161 Structures used by getmemoryclock 2162 *************************************************************************** 2163 */ 2164 struct get_memory_clock_parameter 2165 { 2166 uint32_t mclk_10khz; // current engine speed in 10KHz unit 2167 uint32_t reserved; 2168 }; 2169 2170 2171 2172 /* 2173 *************************************************************************** 2174 Structures used by setvoltage 2175 *************************************************************************** 2176 */ 2177 2178 struct set_voltage_parameters_v1_4 2179 { 2180 uint8_t voltagetype; /* enum atom_voltage_type */ 2181 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 2182 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 2183 }; 2184 2185 //set_voltage_parameters_v2_1.voltagemode 2186 enum atom_set_voltage_command{ 2187 ATOM_SET_VOLTAGE = 0, 2188 ATOM_INIT_VOLTAGE_REGULATOR = 3, 2189 ATOM_SET_VOLTAGE_PHASE = 4, 2190 ATOM_GET_LEAKAGE_ID = 8, 2191 }; 2192 2193 struct set_voltage_ps_allocation_v1_4 2194 { 2195 struct set_voltage_parameters_v1_4 setvoltageparam; 2196 uint32_t reserved[10]; 2197 }; 2198 2199 2200 /* 2201 *************************************************************************** 2202 Structures used by computegpuclockparam 2203 *************************************************************************** 2204 */ 2205 2206 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 2207 enum atom_gpu_clock_type 2208 { 2209 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 2210 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 2211 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 2212 }; 2213 2214 struct compute_gpu_clock_input_parameter_v1_8 2215 { 2216 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 2217 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 2218 uint32_t reserved[5]; 2219 }; 2220 2221 2222 struct compute_gpu_clock_output_parameter_v1_8 2223 { 2224 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 2225 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 2226 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 2227 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 2228 uint16_t pll_ss_slew_frac; 2229 uint8_t pll_ss_enable; 2230 uint8_t reserved; 2231 uint32_t reserved1[2]; 2232 }; 2233 2234 2235 2236 /* 2237 *************************************************************************** 2238 Structures used by ReadEfuseValue 2239 *************************************************************************** 2240 */ 2241 2242 struct read_efuse_input_parameters_v3_1 2243 { 2244 uint16_t efuse_start_index; 2245 uint8_t reserved; 2246 uint8_t bitslen; 2247 }; 2248 2249 // ReadEfuseValue input/output parameter 2250 union read_efuse_value_parameters_v3_1 2251 { 2252 struct read_efuse_input_parameters_v3_1 efuse_info; 2253 uint32_t efusevalue; 2254 }; 2255 2256 2257 /* 2258 *************************************************************************** 2259 Structures used by getsmuclockinfo 2260 *************************************************************************** 2261 */ 2262 struct atom_get_smu_clock_info_parameters_v3_1 2263 { 2264 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 2265 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 2266 uint8_t command; // enum of atom_get_smu_clock_info_command 2267 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 2268 }; 2269 2270 enum atom_get_smu_clock_info_command 2271 { 2272 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 2273 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 2274 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 2275 }; 2276 2277 enum atom_smu9_syspll0_clock_id 2278 { 2279 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 2280 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 2281 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 2282 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 2283 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 2284 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 2285 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 2286 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 2287 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 2288 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 2289 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 2290 }; 2291 2292 enum atom_smu11_syspll_id { 2293 SMU11_SYSPLL0_ID = 0, 2294 SMU11_SYSPLL1_0_ID = 1, 2295 SMU11_SYSPLL1_1_ID = 2, 2296 SMU11_SYSPLL1_2_ID = 3, 2297 SMU11_SYSPLL2_ID = 4, 2298 SMU11_SYSPLL3_0_ID = 5, 2299 SMU11_SYSPLL3_1_ID = 6, 2300 }; 2301 2302 enum atom_smu11_syspll0_clock_id { 2303 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK 2304 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 2305 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 2306 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK 2307 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK 2308 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 2309 }; 2310 2311 enum atom_smu11_syspll1_0_clock_id { 2312 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 2313 }; 2314 2315 enum atom_smu11_syspll1_1_clock_id { 2316 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b 2317 }; 2318 2319 enum atom_smu11_syspll1_2_clock_id { 2320 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK 2321 }; 2322 2323 enum atom_smu11_syspll2_clock_id { 2324 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK 2325 }; 2326 2327 enum atom_smu11_syspll3_0_clock_id { 2328 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK 2329 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK 2330 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK 2331 }; 2332 2333 enum atom_smu11_syspll3_1_clock_id { 2334 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK 2335 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK 2336 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK 2337 }; 2338 2339 struct atom_get_smu_clock_info_output_parameters_v3_1 2340 { 2341 union { 2342 uint32_t smu_clock_freq_hz; 2343 uint32_t syspllvcofreq_10khz; 2344 uint32_t sysspllrefclk_10khz; 2345 }atom_smu_outputclkfreq; 2346 }; 2347 2348 2349 2350 /* 2351 *************************************************************************** 2352 Structures used by dynamicmemorysettings 2353 *************************************************************************** 2354 */ 2355 2356 enum atom_dynamic_memory_setting_command 2357 { 2358 COMPUTE_MEMORY_PLL_PARAM = 1, 2359 COMPUTE_ENGINE_PLL_PARAM = 2, 2360 ADJUST_MC_SETTING_PARAM = 3, 2361 }; 2362 2363 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 2364 struct dynamic_mclk_settings_parameters_v2_1 2365 { 2366 uint32_t mclk_10khz:24; //Input= target mclk 2367 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 2368 uint32_t reserved; 2369 }; 2370 2371 /* when command = COMPUTE_ENGINE_PLL_PARAM */ 2372 struct dynamic_sclk_settings_parameters_v2_1 2373 { 2374 uint32_t sclk_10khz:24; //Input= target mclk 2375 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 2376 uint32_t mclk_10khz; 2377 uint32_t reserved; 2378 }; 2379 2380 union dynamic_memory_settings_parameters_v2_1 2381 { 2382 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 2383 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 2384 }; 2385 2386 2387 2388 /* 2389 *************************************************************************** 2390 Structures used by memorytraining 2391 *************************************************************************** 2392 */ 2393 2394 enum atom_umc6_0_ucode_function_call_enum_id 2395 { 2396 UMC60_UCODE_FUNC_ID_REINIT = 0, 2397 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 2398 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 2399 }; 2400 2401 2402 struct memory_training_parameters_v2_1 2403 { 2404 uint8_t ucode_func_id; 2405 uint8_t ucode_reserved[3]; 2406 uint32_t reserved[5]; 2407 }; 2408 2409 2410 /* 2411 *************************************************************************** 2412 Structures used by setpixelclock 2413 *************************************************************************** 2414 */ 2415 2416 struct set_pixel_clock_parameter_v1_7 2417 { 2418 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 2419 2420 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 2421 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 2422 // indicate which graphic encoder will be used. 2423 uint8_t encoder_mode; // Encoder mode: 2424 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 2425 uint8_t crtc_id; // enum of atom_crtc_def 2426 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 2427 uint8_t reserved1[2]; 2428 uint32_t reserved2; 2429 }; 2430 2431 //ucMiscInfo 2432 enum atom_set_pixel_clock_v1_7_misc_info 2433 { 2434 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 2435 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 2436 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 2437 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 2438 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 2439 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 2440 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 2441 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 2442 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 2443 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 2444 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 2445 }; 2446 2447 /* deep_color_ratio */ 2448 enum atom_set_pixel_clock_v1_7_deepcolor_ratio 2449 { 2450 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2451 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2452 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2453 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2454 }; 2455 2456 /* 2457 *************************************************************************** 2458 Structures used by setdceclock 2459 *************************************************************************** 2460 */ 2461 2462 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 2463 struct set_dce_clock_parameters_v2_1 2464 { 2465 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 2466 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 2467 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 2468 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 2469 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 2470 }; 2471 2472 //ucDCEClkType 2473 enum atom_set_dce_clock_clock_type 2474 { 2475 DCE_CLOCK_TYPE_DISPCLK = 0, 2476 DCE_CLOCK_TYPE_DPREFCLK = 1, 2477 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 2478 }; 2479 2480 //ucDCEClkFlag when ucDCEClkType == DPREFCLK 2481 enum atom_set_dce_clock_dprefclk_flag 2482 { 2483 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 2484 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 2485 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 2486 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 2487 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 2488 }; 2489 2490 //ucDCEClkFlag when ucDCEClkType == PIXCLK 2491 enum atom_set_dce_clock_pixclk_flag 2492 { 2493 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 2494 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2495 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2496 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2497 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2498 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 2499 }; 2500 2501 struct set_dce_clock_ps_allocation_v2_1 2502 { 2503 struct set_dce_clock_parameters_v2_1 param; 2504 uint32_t ulReserved[2]; 2505 }; 2506 2507 2508 /****************************************************************************/ 2509 // Structures used by BlankCRTC 2510 /****************************************************************************/ 2511 struct blank_crtc_parameters 2512 { 2513 uint8_t crtc_id; // enum atom_crtc_def 2514 uint8_t blanking; // enum atom_blank_crtc_command 2515 uint16_t reserved; 2516 uint32_t reserved1; 2517 }; 2518 2519 enum atom_blank_crtc_command 2520 { 2521 ATOM_BLANKING = 1, 2522 ATOM_BLANKING_OFF = 0, 2523 }; 2524 2525 /****************************************************************************/ 2526 // Structures used by enablecrtc 2527 /****************************************************************************/ 2528 struct enable_crtc_parameters 2529 { 2530 uint8_t crtc_id; // enum atom_crtc_def 2531 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 2532 uint8_t padding[2]; 2533 }; 2534 2535 2536 /****************************************************************************/ 2537 // Structure used by EnableDispPowerGating 2538 /****************************************************************************/ 2539 struct enable_disp_power_gating_parameters_v2_1 2540 { 2541 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 2542 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 2543 uint8_t padding[2]; 2544 }; 2545 2546 struct enable_disp_power_gating_ps_allocation 2547 { 2548 struct enable_disp_power_gating_parameters_v2_1 param; 2549 uint32_t ulReserved[4]; 2550 }; 2551 2552 /****************************************************************************/ 2553 // Structure used in setcrtc_usingdtdtiming 2554 /****************************************************************************/ 2555 struct set_crtc_using_dtd_timing_parameters 2556 { 2557 uint16_t h_size; 2558 uint16_t h_blanking_time; 2559 uint16_t v_size; 2560 uint16_t v_blanking_time; 2561 uint16_t h_syncoffset; 2562 uint16_t h_syncwidth; 2563 uint16_t v_syncoffset; 2564 uint16_t v_syncwidth; 2565 uint16_t modemiscinfo; 2566 uint8_t h_border; 2567 uint8_t v_border; 2568 uint8_t crtc_id; // enum atom_crtc_def 2569 uint8_t encoder_mode; // atom_encode_mode_def 2570 uint8_t padding[2]; 2571 }; 2572 2573 2574 /****************************************************************************/ 2575 // Structures used by processi2cchanneltransaction 2576 /****************************************************************************/ 2577 struct process_i2c_channel_transaction_parameters 2578 { 2579 uint8_t i2cspeed_khz; 2580 union { 2581 uint8_t regindex; 2582 uint8_t status; /* enum atom_process_i2c_flag */ 2583 } regind_status; 2584 uint16_t i2c_data_out; 2585 uint8_t flag; /* enum atom_process_i2c_status */ 2586 uint8_t trans_bytes; 2587 uint8_t slave_addr; 2588 uint8_t i2c_id; 2589 }; 2590 2591 //ucFlag 2592 enum atom_process_i2c_flag 2593 { 2594 HW_I2C_WRITE = 1, 2595 HW_I2C_READ = 0, 2596 I2C_2BYTE_ADDR = 0x02, 2597 HW_I2C_SMBUS_BYTE_WR = 0x04, 2598 }; 2599 2600 //status 2601 enum atom_process_i2c_status 2602 { 2603 HW_ASSISTED_I2C_STATUS_FAILURE =2, 2604 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 2605 }; 2606 2607 2608 /****************************************************************************/ 2609 // Structures used by processauxchanneltransaction 2610 /****************************************************************************/ 2611 2612 struct process_aux_channel_transaction_parameters_v1_2 2613 { 2614 uint16_t aux_request; 2615 uint16_t dataout; 2616 uint8_t channelid; 2617 union { 2618 uint8_t reply_status; 2619 uint8_t aux_delay; 2620 } aux_status_delay; 2621 uint8_t dataout_len; 2622 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 2623 }; 2624 2625 2626 /****************************************************************************/ 2627 // Structures used by selectcrtc_source 2628 /****************************************************************************/ 2629 2630 struct select_crtc_source_parameters_v2_3 2631 { 2632 uint8_t crtc_id; // enum atom_crtc_def 2633 uint8_t encoder_id; // enum atom_dig_def 2634 uint8_t encode_mode; // enum atom_encode_mode_def 2635 uint8_t dst_bpc; // enum atom_panel_bit_per_color 2636 }; 2637 2638 2639 /****************************************************************************/ 2640 // Structures used by digxencodercontrol 2641 /****************************************************************************/ 2642 2643 // ucAction: 2644 enum atom_dig_encoder_control_action 2645 { 2646 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 2647 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 2648 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 2649 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 2650 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 2651 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 2652 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 2653 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 2654 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 2655 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 2656 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 2657 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 2658 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 2659 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 2660 }; 2661 2662 //define ucPanelMode 2663 enum atom_dig_encoder_control_panelmode 2664 { 2665 DP_PANEL_MODE_DISABLE = 0x00, 2666 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 2667 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 2668 }; 2669 2670 //ucDigId 2671 enum atom_dig_encoder_control_v5_digid 2672 { 2673 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 2674 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 2675 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 2676 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 2677 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 2678 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 2679 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 2680 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 2681 }; 2682 2683 struct dig_encoder_stream_setup_parameters_v1_5 2684 { 2685 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2686 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 2687 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 2688 uint8_t lanenum; // Lane number 2689 uint32_t pclk_10khz; // Pixel Clock in 10Khz 2690 uint8_t bitpercolor; 2691 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 2692 uint8_t reserved[2]; 2693 }; 2694 2695 struct dig_encoder_link_setup_parameters_v1_5 2696 { 2697 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2698 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 2699 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 2700 uint8_t lanenum; // Lane number 2701 uint8_t symclk_10khz; // Symbol Clock in 10Khz 2702 uint8_t hpd_sel; 2703 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 2704 uint8_t reserved[2]; 2705 }; 2706 2707 struct dp_panel_mode_set_parameters_v1_5 2708 { 2709 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2710 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 2711 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 2712 uint8_t reserved1; 2713 uint32_t reserved2[2]; 2714 }; 2715 2716 struct dig_encoder_generic_cmd_parameters_v1_5 2717 { 2718 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2719 uint8_t action; // = rest of generic encoder command which does not carry any parameters 2720 uint8_t reserved1[2]; 2721 uint32_t reserved2[2]; 2722 }; 2723 2724 union dig_encoder_control_parameters_v1_5 2725 { 2726 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 2727 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 2728 struct dig_encoder_link_setup_parameters_v1_5 link_param; 2729 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 2730 }; 2731 2732 /* 2733 *************************************************************************** 2734 Structures used by dig1transmittercontrol 2735 *************************************************************************** 2736 */ 2737 struct dig_transmitter_control_parameters_v1_6 2738 { 2739 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 2740 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 2741 union { 2742 uint8_t digmode; // enum atom_encode_mode_def 2743 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 2744 } mode_laneset; 2745 uint8_t lanenum; // Lane number 1, 2, 4, 8 2746 uint32_t symclk_10khz; // Symbol Clock in 10Khz 2747 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 2748 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 2749 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 2750 uint8_t reserved; 2751 uint32_t reserved1; 2752 }; 2753 2754 struct dig_transmitter_control_ps_allocation_v1_6 2755 { 2756 struct dig_transmitter_control_parameters_v1_6 param; 2757 uint32_t reserved[4]; 2758 }; 2759 2760 //ucAction 2761 enum atom_dig_transmitter_control_action 2762 { 2763 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 2764 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 2765 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 2766 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 2767 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 2768 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 2769 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 2770 ATOM_TRANSMITTER_ACTION_INIT = 7, 2771 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 2772 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 2773 ATOM_TRANSMITTER_ACTION_SETUP = 10, 2774 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 2775 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 2776 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 2777 }; 2778 2779 // digfe_sel 2780 enum atom_dig_transmitter_control_digfe_sel 2781 { 2782 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 2783 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 2784 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 2785 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 2786 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 2787 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 2788 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 2789 }; 2790 2791 2792 //ucHPDSel 2793 enum atom_dig_transmitter_control_hpd_sel 2794 { 2795 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 2796 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 2797 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 2798 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 2799 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 2800 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 2801 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 2802 }; 2803 2804 // ucDPLaneSet 2805 enum atom_dig_transmitter_control_dplaneset 2806 { 2807 DP_LANE_SET__0DB_0_4V = 0x00, 2808 DP_LANE_SET__0DB_0_6V = 0x01, 2809 DP_LANE_SET__0DB_0_8V = 0x02, 2810 DP_LANE_SET__0DB_1_2V = 0x03, 2811 DP_LANE_SET__3_5DB_0_4V = 0x08, 2812 DP_LANE_SET__3_5DB_0_6V = 0x09, 2813 DP_LANE_SET__3_5DB_0_8V = 0x0a, 2814 DP_LANE_SET__6DB_0_4V = 0x10, 2815 DP_LANE_SET__6DB_0_6V = 0x11, 2816 DP_LANE_SET__9_5DB_0_4V = 0x18, 2817 }; 2818 2819 2820 2821 /****************************************************************************/ 2822 // Structures used by ExternalEncoderControl V2.4 2823 /****************************************************************************/ 2824 2825 struct external_encoder_control_parameters_v2_4 2826 { 2827 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 2828 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 2829 uint8_t action; // 2830 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 2831 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 2832 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 2833 uint8_t hpd_id; 2834 }; 2835 2836 2837 // ucAction 2838 enum external_encoder_control_action_def 2839 { 2840 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 2841 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 2842 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 2843 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 2844 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 2845 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 2846 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 2847 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 2848 }; 2849 2850 // ucConfig 2851 enum external_encoder_control_v2_4_config_def 2852 { 2853 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 2854 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 2855 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 2856 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 2857 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 2858 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 2859 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 2860 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 2861 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 2862 }; 2863 2864 struct external_encoder_control_ps_allocation_v2_4 2865 { 2866 struct external_encoder_control_parameters_v2_4 sExtEncoder; 2867 uint32_t reserved[2]; 2868 }; 2869 2870 2871 /* 2872 *************************************************************************** 2873 AMD ACPI Table 2874 2875 *************************************************************************** 2876 */ 2877 2878 struct amd_acpi_description_header{ 2879 uint32_t signature; 2880 uint32_t tableLength; //Length 2881 uint8_t revision; 2882 uint8_t checksum; 2883 uint8_t oemId[6]; 2884 uint8_t oemTableId[8]; //UINT64 OemTableId; 2885 uint32_t oemRevision; 2886 uint32_t creatorId; 2887 uint32_t creatorRevision; 2888 }; 2889 2890 struct uefi_acpi_vfct{ 2891 struct amd_acpi_description_header sheader; 2892 uint8_t tableUUID[16]; //0x24 2893 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 2894 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 2895 uint32_t reserved[4]; //0x3C 2896 }; 2897 2898 struct vfct_image_header{ 2899 uint32_t pcibus; //0x4C 2900 uint32_t pcidevice; //0x50 2901 uint32_t pcifunction; //0x54 2902 uint16_t vendorid; //0x58 2903 uint16_t deviceid; //0x5A 2904 uint16_t ssvid; //0x5C 2905 uint16_t ssid; //0x5E 2906 uint32_t revision; //0x60 2907 uint32_t imagelength; //0x64 2908 }; 2909 2910 2911 struct gop_vbios_content { 2912 struct vfct_image_header vbiosheader; 2913 uint8_t vbioscontent[1]; 2914 }; 2915 2916 struct gop_lib1_content { 2917 struct vfct_image_header lib1header; 2918 uint8_t lib1content[1]; 2919 }; 2920 2921 2922 2923 /* 2924 *************************************************************************** 2925 Scratch Register definitions 2926 Each number below indicates which scratch regiser request, Active and 2927 Connect all share the same definitions as display_device_tag defines 2928 *************************************************************************** 2929 */ 2930 2931 enum scratch_register_def{ 2932 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 2933 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 2934 ATOM_ACTIVE_INFO_DEF = 3, 2935 ATOM_LCD_INFO_DEF = 4, 2936 ATOM_DEVICE_REQ_INFO_DEF = 5, 2937 ATOM_ACC_CHANGE_INFO_DEF = 6, 2938 ATOM_PRE_OS_MODE_INFO_DEF = 7, 2939 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 2940 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 2941 }; 2942 2943 enum scratch_device_connect_info_bit_def{ 2944 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 2945 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 2946 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 2947 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 2948 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 2949 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 2950 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 2951 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 2952 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 2953 }; 2954 2955 enum scratch_bl_bri_level_info_bit_def{ 2956 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 2957 #ifndef _H2INC 2958 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 2959 ATOM_DEVICE_DPMS_STATE =0x00010000, 2960 #endif 2961 }; 2962 2963 enum scratch_active_info_bits_def{ 2964 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 2965 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 2966 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 2967 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 2968 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 2969 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 2970 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 2971 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 2972 }; 2973 2974 enum scratch_device_req_info_bits_def{ 2975 ATOM_DISPLAY_LCD1_REQ =0x0002, 2976 ATOM_DISPLAY_DFP1_REQ =0x0008, 2977 ATOM_DISPLAY_DFP2_REQ =0x0080, 2978 ATOM_DISPLAY_DFP3_REQ =0x0200, 2979 ATOM_DISPLAY_DFP4_REQ =0x0400, 2980 ATOM_DISPLAY_DFP5_REQ =0x0800, 2981 ATOM_DISPLAY_DFP6_REQ =0x0040, 2982 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 2983 }; 2984 2985 enum scratch_acc_change_info_bitshift_def{ 2986 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 2987 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 2988 }; 2989 2990 enum scratch_acc_change_info_bits_def{ 2991 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 2992 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 2993 }; 2994 2995 enum scratch_pre_os_mode_info_bits_def{ 2996 ATOM_PRE_OS_MODE_MASK =0x00000003, 2997 ATOM_PRE_OS_MODE_VGA =0x00000000, 2998 ATOM_PRE_OS_MODE_VESA =0x00000001, 2999 ATOM_PRE_OS_MODE_GOP =0x00000002, 3000 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 3001 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 3002 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 3003 ATOM_ASIC_INIT_COMPLETE =0x00000200, 3004 #ifndef _H2INC 3005 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 3006 #endif 3007 }; 3008 3009 3010 3011 /* 3012 *************************************************************************** 3013 ATOM firmware ID header file 3014 !! Please keep it at end of the atomfirmware.h !! 3015 *************************************************************************** 3016 */ 3017 #include "atomfirmwareid.h" 3018 #pragma pack() 3019 3020 #endif 3021 3022