1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 32 enum smu_event_type { 33 SMU_EVENT_RESET_COMPLETE = 0, 34 }; 35 36 struct amd_vce_state { 37 /* vce clocks */ 38 u32 evclk; 39 u32 ecclk; 40 /* gpu clocks */ 41 u32 sclk; 42 u32 mclk; 43 u8 clk_idx; 44 u8 pstate; 45 }; 46 47 48 enum amd_dpm_forced_level { 49 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 50 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 51 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 52 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 53 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 54 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 56 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 57 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 58 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 59 }; 60 61 enum amd_pm_state_type { 62 /* not used for dpm */ 63 POWER_STATE_TYPE_DEFAULT, 64 POWER_STATE_TYPE_POWERSAVE, 65 /* user selectable states */ 66 POWER_STATE_TYPE_BATTERY, 67 POWER_STATE_TYPE_BALANCED, 68 POWER_STATE_TYPE_PERFORMANCE, 69 /* internal states */ 70 POWER_STATE_TYPE_INTERNAL_UVD, 71 POWER_STATE_TYPE_INTERNAL_UVD_SD, 72 POWER_STATE_TYPE_INTERNAL_UVD_HD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 74 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 75 POWER_STATE_TYPE_INTERNAL_BOOT, 76 POWER_STATE_TYPE_INTERNAL_THERMAL, 77 POWER_STATE_TYPE_INTERNAL_ACPI, 78 POWER_STATE_TYPE_INTERNAL_ULV, 79 POWER_STATE_TYPE_INTERNAL_3DPERF, 80 }; 81 82 #define AMD_MAX_VCE_LEVELS 6 83 84 enum amd_vce_level { 85 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 86 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 87 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 88 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 89 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 90 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 91 }; 92 93 enum amd_fan_ctrl_mode { 94 AMD_FAN_CTRL_NONE = 0, 95 AMD_FAN_CTRL_MANUAL = 1, 96 AMD_FAN_CTRL_AUTO = 2, 97 }; 98 99 enum pp_clock_type { 100 PP_SCLK, 101 PP_MCLK, 102 PP_PCIE, 103 PP_SOCCLK, 104 PP_FCLK, 105 PP_DCEFCLK, 106 PP_VCLK, 107 PP_VCLK1, 108 PP_DCLK, 109 PP_DCLK1, 110 OD_SCLK, 111 OD_MCLK, 112 OD_VDDC_CURVE, 113 OD_RANGE, 114 OD_VDDGFX_OFFSET, 115 OD_CCLK, 116 }; 117 118 enum amd_pp_sensors { 119 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 120 AMDGPU_PP_SENSOR_CPU_CLK, 121 AMDGPU_PP_SENSOR_VDDNB, 122 AMDGPU_PP_SENSOR_VDDGFX, 123 AMDGPU_PP_SENSOR_UVD_VCLK, 124 AMDGPU_PP_SENSOR_UVD_DCLK, 125 AMDGPU_PP_SENSOR_VCE_ECCLK, 126 AMDGPU_PP_SENSOR_GPU_LOAD, 127 AMDGPU_PP_SENSOR_MEM_LOAD, 128 AMDGPU_PP_SENSOR_GFX_MCLK, 129 AMDGPU_PP_SENSOR_GPU_TEMP, 130 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 131 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 132 AMDGPU_PP_SENSOR_MEM_TEMP, 133 AMDGPU_PP_SENSOR_VCE_POWER, 134 AMDGPU_PP_SENSOR_UVD_POWER, 135 AMDGPU_PP_SENSOR_GPU_POWER, 136 AMDGPU_PP_SENSOR_SS_APU_SHARE, 137 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 138 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 139 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 140 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 141 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 142 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 143 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 144 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 145 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 146 }; 147 148 enum amd_pp_task { 149 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 150 AMD_PP_TASK_ENABLE_USER_STATE, 151 AMD_PP_TASK_READJUST_POWER_STATE, 152 AMD_PP_TASK_COMPLETE_INIT, 153 AMD_PP_TASK_MAX 154 }; 155 156 enum PP_SMC_POWER_PROFILE { 157 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 158 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 159 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 160 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 161 PP_SMC_POWER_PROFILE_VR = 0x4, 162 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 163 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 164 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 165 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 166 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 167 PP_SMC_POWER_PROFILE_COUNT, 168 }; 169 170 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 171 172 173 174 enum { 175 PP_GROUP_UNKNOWN = 0, 176 PP_GROUP_GFX = 1, 177 PP_GROUP_SYS, 178 PP_GROUP_MAX 179 }; 180 181 enum PP_OD_DPM_TABLE_COMMAND { 182 PP_OD_EDIT_SCLK_VDDC_TABLE, 183 PP_OD_EDIT_MCLK_VDDC_TABLE, 184 PP_OD_EDIT_CCLK_VDDC_TABLE, 185 PP_OD_EDIT_VDDC_CURVE, 186 PP_OD_RESTORE_DEFAULT_TABLE, 187 PP_OD_COMMIT_DPM_TABLE, 188 PP_OD_EDIT_VDDGFX_OFFSET 189 }; 190 191 struct pp_states_info { 192 uint32_t nums; 193 uint32_t states[16]; 194 }; 195 196 enum PP_HWMON_TEMP { 197 PP_TEMP_EDGE = 0, 198 PP_TEMP_JUNCTION, 199 PP_TEMP_MEM, 200 PP_TEMP_MAX 201 }; 202 203 enum pp_mp1_state { 204 PP_MP1_STATE_NONE, 205 PP_MP1_STATE_SHUTDOWN, 206 PP_MP1_STATE_UNLOAD, 207 PP_MP1_STATE_RESET, 208 }; 209 210 enum pp_df_cstate { 211 DF_CSTATE_DISALLOW = 0, 212 DF_CSTATE_ALLOW, 213 }; 214 215 /** 216 * DOC: amdgpu_pp_power 217 * 218 * APU power is managed to system-level requirements through the PPT 219 * (package power tracking) feature. PPT is intended to limit power to the 220 * requirements of the power source and could be dynamically updated to 221 * maximize APU performance within the system power budget. 222 * 223 * Two types of power measurement can be requested, where supported, with 224 * :c:type:`enum pp_power_type <pp_power_type>`. 225 */ 226 227 /** 228 * enum pp_power_limit_level - Used to query the power limits 229 * 230 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 231 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 232 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 233 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 234 */ 235 enum pp_power_limit_level 236 { 237 PP_PWR_LIMIT_MIN = -1, 238 PP_PWR_LIMIT_CURRENT, 239 PP_PWR_LIMIT_DEFAULT, 240 PP_PWR_LIMIT_MAX, 241 }; 242 243 /** 244 * enum pp_power_type - Used to specify the type of the requested power 245 * 246 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 247 * moving average of APU power (default ~5000 ms). 248 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 249 * where supported. 250 */ 251 enum pp_power_type 252 { 253 PP_PWR_TYPE_SUSTAINED, 254 PP_PWR_TYPE_FAST, 255 }; 256 257 #define PP_GROUP_MASK 0xF0000000 258 #define PP_GROUP_SHIFT 28 259 260 #define PP_BLOCK_MASK 0x0FFFFF00 261 #define PP_BLOCK_SHIFT 8 262 263 #define PP_BLOCK_GFX_CG 0x01 264 #define PP_BLOCK_GFX_MG 0x02 265 #define PP_BLOCK_GFX_3D 0x04 266 #define PP_BLOCK_GFX_RLC 0x08 267 #define PP_BLOCK_GFX_CP 0x10 268 #define PP_BLOCK_SYS_BIF 0x01 269 #define PP_BLOCK_SYS_MC 0x02 270 #define PP_BLOCK_SYS_ROM 0x04 271 #define PP_BLOCK_SYS_DRM 0x08 272 #define PP_BLOCK_SYS_HDP 0x10 273 #define PP_BLOCK_SYS_SDMA 0x20 274 275 #define PP_STATE_MASK 0x0000000F 276 #define PP_STATE_SHIFT 0 277 #define PP_STATE_SUPPORT_MASK 0x000000F0 278 #define PP_STATE_SUPPORT_SHIFT 0 279 280 #define PP_STATE_CG 0x01 281 #define PP_STATE_LS 0x02 282 #define PP_STATE_DS 0x04 283 #define PP_STATE_SD 0x08 284 #define PP_STATE_SUPPORT_CG 0x10 285 #define PP_STATE_SUPPORT_LS 0x20 286 #define PP_STATE_SUPPORT_DS 0x40 287 #define PP_STATE_SUPPORT_SD 0x80 288 289 #define PP_CG_MSG_ID(group, block, support, state) \ 290 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 291 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 292 293 #define XGMI_MODE_PSTATE_D3 0 294 #define XGMI_MODE_PSTATE_D0 1 295 296 #define NUM_HBM_INSTANCES 4 297 298 struct seq_file; 299 enum amd_pp_clock_type; 300 struct amd_pp_simple_clock_info; 301 struct amd_pp_display_configuration; 302 struct amd_pp_clock_info; 303 struct pp_display_clock_request; 304 struct pp_clock_levels_with_voltage; 305 struct pp_clock_levels_with_latency; 306 struct amd_pp_clocks; 307 struct pp_smu_wm_range_sets; 308 struct pp_smu_nv_clock_table; 309 struct dpm_clocks; 310 311 struct amd_pm_funcs { 312 /* export for dpm on ci and si */ 313 int (*pre_set_power_state)(void *handle); 314 int (*set_power_state)(void *handle); 315 void (*post_set_power_state)(void *handle); 316 void (*display_configuration_changed)(void *handle); 317 void (*print_power_state)(void *handle, void *ps); 318 bool (*vblank_too_short)(void *handle); 319 void (*enable_bapm)(void *handle, bool enable); 320 int (*check_state_equal)(void *handle, 321 void *cps, 322 void *rps, 323 bool *equal); 324 /* export for sysfs */ 325 int (*set_fan_control_mode)(void *handle, u32 mode); 326 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 327 int (*set_fan_speed_pwm)(void *handle, u32 speed); 328 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 329 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 330 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 331 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 332 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 333 int (*get_sclk_od)(void *handle); 334 int (*set_sclk_od)(void *handle, uint32_t value); 335 int (*get_mclk_od)(void *handle); 336 int (*set_mclk_od)(void *handle, uint32_t value); 337 int (*read_sensor)(void *handle, int idx, void *value, int *size); 338 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 339 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 340 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 341 enum amd_pm_state_type (*get_current_power_state)(void *handle); 342 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 343 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 344 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 345 int (*get_pp_table)(void *handle, char **table); 346 int (*set_pp_table)(void *handle, const char *buf, size_t size); 347 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 348 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 349 /* export to amdgpu */ 350 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 351 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 352 enum amd_pm_state_type *user_state); 353 int (*load_firmware)(void *handle); 354 int (*wait_for_fw_loading_complete)(void *handle); 355 int (*set_powergating_by_smu)(void *handle, 356 uint32_t block_type, bool gate); 357 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 358 int (*set_power_limit)(void *handle, uint32_t n); 359 int (*get_power_limit)(void *handle, uint32_t *limit, 360 enum pp_power_limit_level pp_limit_level, 361 enum pp_power_type power_type); 362 int (*get_power_profile_mode)(void *handle, char *buf); 363 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 364 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 365 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 366 long *input, uint32_t size); 367 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 368 int (*smu_i2c_bus_access)(void *handle, bool acquire); 369 int (*gfx_state_change_set)(void *handle, uint32_t state); 370 /* export to DC */ 371 u32 (*get_sclk)(void *handle, bool low); 372 u32 (*get_mclk)(void *handle, bool low); 373 int (*display_configuration_change)(void *handle, 374 const struct amd_pp_display_configuration *input); 375 int (*get_display_power_level)(void *handle, 376 struct amd_pp_simple_clock_info *output); 377 int (*get_current_clocks)(void *handle, 378 struct amd_pp_clock_info *clocks); 379 int (*get_clock_by_type)(void *handle, 380 enum amd_pp_clock_type type, 381 struct amd_pp_clocks *clocks); 382 int (*get_clock_by_type_with_latency)(void *handle, 383 enum amd_pp_clock_type type, 384 struct pp_clock_levels_with_latency *clocks); 385 int (*get_clock_by_type_with_voltage)(void *handle, 386 enum amd_pp_clock_type type, 387 struct pp_clock_levels_with_voltage *clocks); 388 int (*set_watermarks_for_clocks_ranges)(void *handle, 389 void *clock_ranges); 390 int (*display_clock_voltage_request)(void *handle, 391 struct pp_display_clock_request *clock); 392 int (*get_display_mode_validation_clocks)(void *handle, 393 struct amd_pp_simple_clock_info *clocks); 394 int (*notify_smu_enable_pwe)(void *handle); 395 int (*enable_mgpu_fan_boost)(void *handle); 396 int (*set_active_display_count)(void *handle, uint32_t count); 397 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 398 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 399 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 400 int (*get_asic_baco_capability)(void *handle, bool *cap); 401 int (*get_asic_baco_state)(void *handle, int *state); 402 int (*set_asic_baco_state)(void *handle, int state); 403 int (*get_ppfeature_status)(void *handle, char *buf); 404 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 405 int (*asic_reset_mode_2)(void *handle); 406 int (*asic_reset_enable_gfx_features)(void *handle); 407 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 408 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 409 ssize_t (*get_gpu_metrics)(void *handle, void **table); 410 int (*set_watermarks_for_clock_ranges)(void *handle, 411 struct pp_smu_wm_range_sets *ranges); 412 int (*display_disable_memory_clock_switch)(void *handle, 413 bool disable_memory_clock_switch); 414 int (*get_max_sustainable_clocks_by_dc)(void *handle, 415 struct pp_smu_nv_clock_table *max_clocks); 416 int (*get_uclk_dpm_states)(void *handle, 417 unsigned int *clock_values_in_khz, 418 unsigned int *num_states); 419 int (*get_dpm_clock_table)(void *handle, 420 struct dpm_clocks *clock_table); 421 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 422 void (*pm_compute_clocks)(void *handle); 423 }; 424 425 struct metrics_table_header { 426 uint16_t structure_size; 427 uint8_t format_revision; 428 uint8_t content_revision; 429 }; 430 431 /* 432 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 433 * Use gpu_metrics_v1_1 or later instead. 434 */ 435 struct gpu_metrics_v1_0 { 436 struct metrics_table_header common_header; 437 438 /* Driver attached timestamp (in ns) */ 439 uint64_t system_clock_counter; 440 441 /* Temperature */ 442 uint16_t temperature_edge; 443 uint16_t temperature_hotspot; 444 uint16_t temperature_mem; 445 uint16_t temperature_vrgfx; 446 uint16_t temperature_vrsoc; 447 uint16_t temperature_vrmem; 448 449 /* Utilization */ 450 uint16_t average_gfx_activity; 451 uint16_t average_umc_activity; // memory controller 452 uint16_t average_mm_activity; // UVD or VCN 453 454 /* Power/Energy */ 455 uint16_t average_socket_power; 456 uint32_t energy_accumulator; 457 458 /* Average clocks */ 459 uint16_t average_gfxclk_frequency; 460 uint16_t average_socclk_frequency; 461 uint16_t average_uclk_frequency; 462 uint16_t average_vclk0_frequency; 463 uint16_t average_dclk0_frequency; 464 uint16_t average_vclk1_frequency; 465 uint16_t average_dclk1_frequency; 466 467 /* Current clocks */ 468 uint16_t current_gfxclk; 469 uint16_t current_socclk; 470 uint16_t current_uclk; 471 uint16_t current_vclk0; 472 uint16_t current_dclk0; 473 uint16_t current_vclk1; 474 uint16_t current_dclk1; 475 476 /* Throttle status */ 477 uint32_t throttle_status; 478 479 /* Fans */ 480 uint16_t current_fan_speed; 481 482 /* Link width/speed */ 483 uint8_t pcie_link_width; 484 uint8_t pcie_link_speed; // in 0.1 GT/s 485 }; 486 487 struct gpu_metrics_v1_1 { 488 struct metrics_table_header common_header; 489 490 /* Temperature */ 491 uint16_t temperature_edge; 492 uint16_t temperature_hotspot; 493 uint16_t temperature_mem; 494 uint16_t temperature_vrgfx; 495 uint16_t temperature_vrsoc; 496 uint16_t temperature_vrmem; 497 498 /* Utilization */ 499 uint16_t average_gfx_activity; 500 uint16_t average_umc_activity; // memory controller 501 uint16_t average_mm_activity; // UVD or VCN 502 503 /* Power/Energy */ 504 uint16_t average_socket_power; 505 uint64_t energy_accumulator; 506 507 /* Driver attached timestamp (in ns) */ 508 uint64_t system_clock_counter; 509 510 /* Average clocks */ 511 uint16_t average_gfxclk_frequency; 512 uint16_t average_socclk_frequency; 513 uint16_t average_uclk_frequency; 514 uint16_t average_vclk0_frequency; 515 uint16_t average_dclk0_frequency; 516 uint16_t average_vclk1_frequency; 517 uint16_t average_dclk1_frequency; 518 519 /* Current clocks */ 520 uint16_t current_gfxclk; 521 uint16_t current_socclk; 522 uint16_t current_uclk; 523 uint16_t current_vclk0; 524 uint16_t current_dclk0; 525 uint16_t current_vclk1; 526 uint16_t current_dclk1; 527 528 /* Throttle status */ 529 uint32_t throttle_status; 530 531 /* Fans */ 532 uint16_t current_fan_speed; 533 534 /* Link width/speed */ 535 uint16_t pcie_link_width; 536 uint16_t pcie_link_speed; // in 0.1 GT/s 537 538 uint16_t padding; 539 540 uint32_t gfx_activity_acc; 541 uint32_t mem_activity_acc; 542 543 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 544 }; 545 546 struct gpu_metrics_v1_2 { 547 struct metrics_table_header common_header; 548 549 /* Temperature */ 550 uint16_t temperature_edge; 551 uint16_t temperature_hotspot; 552 uint16_t temperature_mem; 553 uint16_t temperature_vrgfx; 554 uint16_t temperature_vrsoc; 555 uint16_t temperature_vrmem; 556 557 /* Utilization */ 558 uint16_t average_gfx_activity; 559 uint16_t average_umc_activity; // memory controller 560 uint16_t average_mm_activity; // UVD or VCN 561 562 /* Power/Energy */ 563 uint16_t average_socket_power; 564 uint64_t energy_accumulator; 565 566 /* Driver attached timestamp (in ns) */ 567 uint64_t system_clock_counter; 568 569 /* Average clocks */ 570 uint16_t average_gfxclk_frequency; 571 uint16_t average_socclk_frequency; 572 uint16_t average_uclk_frequency; 573 uint16_t average_vclk0_frequency; 574 uint16_t average_dclk0_frequency; 575 uint16_t average_vclk1_frequency; 576 uint16_t average_dclk1_frequency; 577 578 /* Current clocks */ 579 uint16_t current_gfxclk; 580 uint16_t current_socclk; 581 uint16_t current_uclk; 582 uint16_t current_vclk0; 583 uint16_t current_dclk0; 584 uint16_t current_vclk1; 585 uint16_t current_dclk1; 586 587 /* Throttle status (ASIC dependent) */ 588 uint32_t throttle_status; 589 590 /* Fans */ 591 uint16_t current_fan_speed; 592 593 /* Link width/speed */ 594 uint16_t pcie_link_width; 595 uint16_t pcie_link_speed; // in 0.1 GT/s 596 597 uint16_t padding; 598 599 uint32_t gfx_activity_acc; 600 uint32_t mem_activity_acc; 601 602 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 603 604 /* PMFW attached timestamp (10ns resolution) */ 605 uint64_t firmware_timestamp; 606 }; 607 608 struct gpu_metrics_v1_3 { 609 struct metrics_table_header common_header; 610 611 /* Temperature */ 612 uint16_t temperature_edge; 613 uint16_t temperature_hotspot; 614 uint16_t temperature_mem; 615 uint16_t temperature_vrgfx; 616 uint16_t temperature_vrsoc; 617 uint16_t temperature_vrmem; 618 619 /* Utilization */ 620 uint16_t average_gfx_activity; 621 uint16_t average_umc_activity; // memory controller 622 uint16_t average_mm_activity; // UVD or VCN 623 624 /* Power/Energy */ 625 uint16_t average_socket_power; 626 uint64_t energy_accumulator; 627 628 /* Driver attached timestamp (in ns) */ 629 uint64_t system_clock_counter; 630 631 /* Average clocks */ 632 uint16_t average_gfxclk_frequency; 633 uint16_t average_socclk_frequency; 634 uint16_t average_uclk_frequency; 635 uint16_t average_vclk0_frequency; 636 uint16_t average_dclk0_frequency; 637 uint16_t average_vclk1_frequency; 638 uint16_t average_dclk1_frequency; 639 640 /* Current clocks */ 641 uint16_t current_gfxclk; 642 uint16_t current_socclk; 643 uint16_t current_uclk; 644 uint16_t current_vclk0; 645 uint16_t current_dclk0; 646 uint16_t current_vclk1; 647 uint16_t current_dclk1; 648 649 /* Throttle status */ 650 uint32_t throttle_status; 651 652 /* Fans */ 653 uint16_t current_fan_speed; 654 655 /* Link width/speed */ 656 uint16_t pcie_link_width; 657 uint16_t pcie_link_speed; // in 0.1 GT/s 658 659 uint16_t padding; 660 661 uint32_t gfx_activity_acc; 662 uint32_t mem_activity_acc; 663 664 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 665 666 /* PMFW attached timestamp (10ns resolution) */ 667 uint64_t firmware_timestamp; 668 669 /* Voltage (mV) */ 670 uint16_t voltage_soc; 671 uint16_t voltage_gfx; 672 uint16_t voltage_mem; 673 674 uint16_t padding1; 675 676 /* Throttle status (ASIC independent) */ 677 uint64_t indep_throttle_status; 678 }; 679 680 /* 681 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 682 * Use gpu_metrics_v2_1 or later instead. 683 */ 684 struct gpu_metrics_v2_0 { 685 struct metrics_table_header common_header; 686 687 /* Driver attached timestamp (in ns) */ 688 uint64_t system_clock_counter; 689 690 /* Temperature */ 691 uint16_t temperature_gfx; // gfx temperature on APUs 692 uint16_t temperature_soc; // soc temperature on APUs 693 uint16_t temperature_core[8]; // CPU core temperature on APUs 694 uint16_t temperature_l3[2]; 695 696 /* Utilization */ 697 uint16_t average_gfx_activity; 698 uint16_t average_mm_activity; // UVD or VCN 699 700 /* Power/Energy */ 701 uint16_t average_socket_power; // dGPU + APU power on A + A platform 702 uint16_t average_cpu_power; 703 uint16_t average_soc_power; 704 uint16_t average_gfx_power; 705 uint16_t average_core_power[8]; // CPU core power on APUs 706 707 /* Average clocks */ 708 uint16_t average_gfxclk_frequency; 709 uint16_t average_socclk_frequency; 710 uint16_t average_uclk_frequency; 711 uint16_t average_fclk_frequency; 712 uint16_t average_vclk_frequency; 713 uint16_t average_dclk_frequency; 714 715 /* Current clocks */ 716 uint16_t current_gfxclk; 717 uint16_t current_socclk; 718 uint16_t current_uclk; 719 uint16_t current_fclk; 720 uint16_t current_vclk; 721 uint16_t current_dclk; 722 uint16_t current_coreclk[8]; // CPU core clocks 723 uint16_t current_l3clk[2]; 724 725 /* Throttle status */ 726 uint32_t throttle_status; 727 728 /* Fans */ 729 uint16_t fan_pwm; 730 731 uint16_t padding; 732 }; 733 734 struct gpu_metrics_v2_1 { 735 struct metrics_table_header common_header; 736 737 /* Temperature */ 738 uint16_t temperature_gfx; // gfx temperature on APUs 739 uint16_t temperature_soc; // soc temperature on APUs 740 uint16_t temperature_core[8]; // CPU core temperature on APUs 741 uint16_t temperature_l3[2]; 742 743 /* Utilization */ 744 uint16_t average_gfx_activity; 745 uint16_t average_mm_activity; // UVD or VCN 746 747 /* Driver attached timestamp (in ns) */ 748 uint64_t system_clock_counter; 749 750 /* Power/Energy */ 751 uint16_t average_socket_power; // dGPU + APU power on A + A platform 752 uint16_t average_cpu_power; 753 uint16_t average_soc_power; 754 uint16_t average_gfx_power; 755 uint16_t average_core_power[8]; // CPU core power on APUs 756 757 /* Average clocks */ 758 uint16_t average_gfxclk_frequency; 759 uint16_t average_socclk_frequency; 760 uint16_t average_uclk_frequency; 761 uint16_t average_fclk_frequency; 762 uint16_t average_vclk_frequency; 763 uint16_t average_dclk_frequency; 764 765 /* Current clocks */ 766 uint16_t current_gfxclk; 767 uint16_t current_socclk; 768 uint16_t current_uclk; 769 uint16_t current_fclk; 770 uint16_t current_vclk; 771 uint16_t current_dclk; 772 uint16_t current_coreclk[8]; // CPU core clocks 773 uint16_t current_l3clk[2]; 774 775 /* Throttle status */ 776 uint32_t throttle_status; 777 778 /* Fans */ 779 uint16_t fan_pwm; 780 781 uint16_t padding[3]; 782 }; 783 784 struct gpu_metrics_v2_2 { 785 struct metrics_table_header common_header; 786 787 /* Temperature */ 788 uint16_t temperature_gfx; // gfx temperature on APUs 789 uint16_t temperature_soc; // soc temperature on APUs 790 uint16_t temperature_core[8]; // CPU core temperature on APUs 791 uint16_t temperature_l3[2]; 792 793 /* Utilization */ 794 uint16_t average_gfx_activity; 795 uint16_t average_mm_activity; // UVD or VCN 796 797 /* Driver attached timestamp (in ns) */ 798 uint64_t system_clock_counter; 799 800 /* Power/Energy */ 801 uint16_t average_socket_power; // dGPU + APU power on A + A platform 802 uint16_t average_cpu_power; 803 uint16_t average_soc_power; 804 uint16_t average_gfx_power; 805 uint16_t average_core_power[8]; // CPU core power on APUs 806 807 /* Average clocks */ 808 uint16_t average_gfxclk_frequency; 809 uint16_t average_socclk_frequency; 810 uint16_t average_uclk_frequency; 811 uint16_t average_fclk_frequency; 812 uint16_t average_vclk_frequency; 813 uint16_t average_dclk_frequency; 814 815 /* Current clocks */ 816 uint16_t current_gfxclk; 817 uint16_t current_socclk; 818 uint16_t current_uclk; 819 uint16_t current_fclk; 820 uint16_t current_vclk; 821 uint16_t current_dclk; 822 uint16_t current_coreclk[8]; // CPU core clocks 823 uint16_t current_l3clk[2]; 824 825 /* Throttle status (ASIC dependent) */ 826 uint32_t throttle_status; 827 828 /* Fans */ 829 uint16_t fan_pwm; 830 831 uint16_t padding[3]; 832 833 /* Throttle status (ASIC independent) */ 834 uint64_t indep_throttle_status; 835 }; 836 837 struct gpu_metrics_v2_3 { 838 struct metrics_table_header common_header; 839 840 /* Temperature */ 841 uint16_t temperature_gfx; // gfx temperature on APUs 842 uint16_t temperature_soc; // soc temperature on APUs 843 uint16_t temperature_core[8]; // CPU core temperature on APUs 844 uint16_t temperature_l3[2]; 845 846 /* Utilization */ 847 uint16_t average_gfx_activity; 848 uint16_t average_mm_activity; // UVD or VCN 849 850 /* Driver attached timestamp (in ns) */ 851 uint64_t system_clock_counter; 852 853 /* Power/Energy */ 854 uint16_t average_socket_power; // dGPU + APU power on A + A platform 855 uint16_t average_cpu_power; 856 uint16_t average_soc_power; 857 uint16_t average_gfx_power; 858 uint16_t average_core_power[8]; // CPU core power on APUs 859 860 /* Average clocks */ 861 uint16_t average_gfxclk_frequency; 862 uint16_t average_socclk_frequency; 863 uint16_t average_uclk_frequency; 864 uint16_t average_fclk_frequency; 865 uint16_t average_vclk_frequency; 866 uint16_t average_dclk_frequency; 867 868 /* Current clocks */ 869 uint16_t current_gfxclk; 870 uint16_t current_socclk; 871 uint16_t current_uclk; 872 uint16_t current_fclk; 873 uint16_t current_vclk; 874 uint16_t current_dclk; 875 uint16_t current_coreclk[8]; // CPU core clocks 876 uint16_t current_l3clk[2]; 877 878 /* Throttle status (ASIC dependent) */ 879 uint32_t throttle_status; 880 881 /* Fans */ 882 uint16_t fan_pwm; 883 884 uint16_t padding[3]; 885 886 /* Throttle status (ASIC independent) */ 887 uint64_t indep_throttle_status; 888 889 /* Average Temperature */ 890 uint16_t average_temperature_gfx; // average gfx temperature on APUs 891 uint16_t average_temperature_soc; // average soc temperature on APUs 892 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 893 uint16_t average_temperature_l3[2]; 894 }; 895 #endif 896