1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include <linux/acpi_amd_wbrf.h> 26 #include <linux/units.h> 27 28 #include "amdgpu.h" 29 #include "kgd_pp_interface.h" 30 #include "dm_pp_interface.h" 31 #include "dm_pp_smu.h" 32 #include "smu_types.h" 33 #include "linux/firmware.h" 34 35 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 36 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 37 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 38 #define SMU_FW_NAME_LEN 0x24 39 40 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 41 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 42 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 43 44 // Power Throttlers 45 #define SMU_THROTTLER_PPT0_BIT 0 46 #define SMU_THROTTLER_PPT1_BIT 1 47 #define SMU_THROTTLER_PPT2_BIT 2 48 #define SMU_THROTTLER_PPT3_BIT 3 49 #define SMU_THROTTLER_SPL_BIT 4 50 #define SMU_THROTTLER_FPPT_BIT 5 51 #define SMU_THROTTLER_SPPT_BIT 6 52 #define SMU_THROTTLER_SPPT_APU_BIT 7 53 54 // Current Throttlers 55 #define SMU_THROTTLER_TDC_GFX_BIT 16 56 #define SMU_THROTTLER_TDC_SOC_BIT 17 57 #define SMU_THROTTLER_TDC_MEM_BIT 18 58 #define SMU_THROTTLER_TDC_VDD_BIT 19 59 #define SMU_THROTTLER_TDC_CVIP_BIT 20 60 #define SMU_THROTTLER_EDC_CPU_BIT 21 61 #define SMU_THROTTLER_EDC_GFX_BIT 22 62 #define SMU_THROTTLER_APCC_BIT 23 63 64 // Temperature 65 #define SMU_THROTTLER_TEMP_GPU_BIT 32 66 #define SMU_THROTTLER_TEMP_CORE_BIT 33 67 #define SMU_THROTTLER_TEMP_MEM_BIT 34 68 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 69 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 70 #define SMU_THROTTLER_TEMP_SOC_BIT 37 71 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 72 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 73 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 74 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 75 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 76 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 77 #define SMU_THROTTLER_VRHOT0_BIT 44 78 #define SMU_THROTTLER_VRHOT1_BIT 45 79 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 80 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 81 82 // Other 83 #define SMU_THROTTLER_PPM_BIT 56 84 #define SMU_THROTTLER_FIT_BIT 57 85 86 struct smu_hw_power_state { 87 unsigned int magic; 88 }; 89 90 struct smu_power_state; 91 92 enum smu_state_ui_label { 93 SMU_STATE_UI_LABEL_NONE, 94 SMU_STATE_UI_LABEL_BATTERY, 95 SMU_STATE_UI_TABEL_MIDDLE_LOW, 96 SMU_STATE_UI_LABEL_BALLANCED, 97 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 98 SMU_STATE_UI_LABEL_PERFORMANCE, 99 SMU_STATE_UI_LABEL_BACO, 100 }; 101 102 enum smu_state_classification_flag { 103 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 104 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 105 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 106 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 107 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 108 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 109 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 110 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 111 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 112 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 113 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 114 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 115 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 116 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 117 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 118 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 119 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 120 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 121 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 122 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 123 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 124 }; 125 126 struct smu_state_classification_block { 127 enum smu_state_ui_label ui_label; 128 enum smu_state_classification_flag flags; 129 int bios_index; 130 bool temporary_state; 131 bool to_be_deleted; 132 }; 133 134 struct smu_state_pcie_block { 135 unsigned int lanes; 136 }; 137 138 enum smu_refreshrate_source { 139 SMU_REFRESHRATE_SOURCE_EDID, 140 SMU_REFRESHRATE_SOURCE_EXPLICIT 141 }; 142 143 struct smu_state_display_block { 144 bool disable_frame_modulation; 145 bool limit_refreshrate; 146 enum smu_refreshrate_source refreshrate_source; 147 int explicit_refreshrate; 148 int edid_refreshrate_index; 149 bool enable_vari_bright; 150 }; 151 152 struct smu_state_memory_block { 153 bool dll_off; 154 uint8_t m3arb; 155 uint8_t unused[3]; 156 }; 157 158 struct smu_state_software_algorithm_block { 159 bool disable_load_balancing; 160 bool enable_sleep_for_timestamps; 161 }; 162 163 struct smu_temperature_range { 164 int min; 165 int max; 166 int edge_emergency_max; 167 int hotspot_min; 168 int hotspot_crit_max; 169 int hotspot_emergency_max; 170 int mem_min; 171 int mem_crit_max; 172 int mem_emergency_max; 173 int software_shutdown_temp; 174 int software_shutdown_temp_offset; 175 }; 176 177 struct smu_state_validation_block { 178 bool single_display_only; 179 bool disallow_on_dc; 180 uint8_t supported_power_levels; 181 }; 182 183 struct smu_uvd_clocks { 184 uint32_t vclk; 185 uint32_t dclk; 186 }; 187 188 /** 189 * Structure to hold a SMU Power State. 190 */ 191 struct smu_power_state { 192 uint32_t id; 193 struct list_head ordered_list; 194 struct list_head all_states_list; 195 196 struct smu_state_classification_block classification; 197 struct smu_state_validation_block validation; 198 struct smu_state_pcie_block pcie; 199 struct smu_state_display_block display; 200 struct smu_state_memory_block memory; 201 struct smu_state_software_algorithm_block software; 202 struct smu_uvd_clocks uvd_clocks; 203 struct smu_hw_power_state hardware; 204 }; 205 206 enum smu_power_src_type { 207 SMU_POWER_SOURCE_AC, 208 SMU_POWER_SOURCE_DC, 209 SMU_POWER_SOURCE_COUNT, 210 }; 211 212 enum smu_ppt_limit_type { 213 SMU_DEFAULT_PPT_LIMIT = 0, 214 SMU_FAST_PPT_LIMIT, 215 }; 216 217 enum smu_ppt_limit_level { 218 SMU_PPT_LIMIT_MIN = -1, 219 SMU_PPT_LIMIT_CURRENT, 220 SMU_PPT_LIMIT_DEFAULT, 221 SMU_PPT_LIMIT_MAX, 222 }; 223 224 enum smu_memory_pool_size { 225 SMU_MEMORY_POOL_SIZE_ZERO = 0, 226 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 227 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 228 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 229 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 230 }; 231 232 struct smu_user_dpm_profile { 233 uint32_t fan_mode; 234 uint32_t power_limit; 235 uint32_t fan_speed_pwm; 236 uint32_t fan_speed_rpm; 237 uint32_t flags; 238 uint32_t user_od; 239 240 /* user clock state information */ 241 uint32_t clk_mask[SMU_CLK_COUNT]; 242 uint32_t clk_dependency; 243 }; 244 245 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 246 do { \ 247 tables[table_id].size = s; \ 248 tables[table_id].align = a; \ 249 tables[table_id].domain = d; \ 250 } while (0) 251 252 struct smu_table { 253 uint64_t size; 254 uint32_t align; 255 uint8_t domain; 256 uint64_t mc_address; 257 void *cpu_addr; 258 struct amdgpu_bo *bo; 259 uint32_t version; 260 }; 261 262 enum smu_perf_level_designation { 263 PERF_LEVEL_ACTIVITY, 264 PERF_LEVEL_POWER_CONTAINMENT, 265 }; 266 267 struct smu_performance_level { 268 uint32_t core_clock; 269 uint32_t memory_clock; 270 uint32_t vddc; 271 uint32_t vddci; 272 uint32_t non_local_mem_freq; 273 uint32_t non_local_mem_width; 274 }; 275 276 struct smu_clock_info { 277 uint32_t min_mem_clk; 278 uint32_t max_mem_clk; 279 uint32_t min_eng_clk; 280 uint32_t max_eng_clk; 281 uint32_t min_bus_bandwidth; 282 uint32_t max_bus_bandwidth; 283 }; 284 285 struct smu_bios_boot_up_values { 286 uint32_t revision; 287 uint32_t gfxclk; 288 uint32_t uclk; 289 uint32_t socclk; 290 uint32_t dcefclk; 291 uint32_t eclk; 292 uint32_t vclk; 293 uint32_t dclk; 294 uint16_t vddc; 295 uint16_t vddci; 296 uint16_t mvddc; 297 uint16_t vdd_gfx; 298 uint8_t cooling_id; 299 uint32_t pp_table_id; 300 uint32_t format_revision; 301 uint32_t content_revision; 302 uint32_t fclk; 303 uint32_t lclk; 304 uint32_t firmware_caps; 305 }; 306 307 enum smu_table_id { 308 SMU_TABLE_PPTABLE = 0, 309 SMU_TABLE_WATERMARKS, 310 SMU_TABLE_CUSTOM_DPM, 311 SMU_TABLE_DPMCLOCKS, 312 SMU_TABLE_AVFS, 313 SMU_TABLE_AVFS_PSM_DEBUG, 314 SMU_TABLE_AVFS_FUSE_OVERRIDE, 315 SMU_TABLE_PMSTATUSLOG, 316 SMU_TABLE_SMU_METRICS, 317 SMU_TABLE_DRIVER_SMU_CONFIG, 318 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 319 SMU_TABLE_OVERDRIVE, 320 SMU_TABLE_I2C_COMMANDS, 321 SMU_TABLE_PACE, 322 SMU_TABLE_ECCINFO, 323 SMU_TABLE_COMBO_PPTABLE, 324 SMU_TABLE_WIFIBAND, 325 SMU_TABLE_COUNT, 326 }; 327 328 struct smu_table_context { 329 void *power_play_table; 330 uint32_t power_play_table_size; 331 void *hardcode_pptable; 332 unsigned long metrics_time; 333 void *metrics_table; 334 void *clocks_table; 335 void *watermarks_table; 336 337 void *max_sustainable_clocks; 338 struct smu_bios_boot_up_values boot_values; 339 void *driver_pptable; 340 void *combo_pptable; 341 void *ecc_table; 342 void *driver_smu_config_table; 343 struct smu_table tables[SMU_TABLE_COUNT]; 344 /* 345 * The driver table is just a staging buffer for 346 * uploading/downloading content from the SMU. 347 * 348 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 349 * SMU_MSG_TransferTableDram2Smu instructs SMU 350 * which content driver is interested. 351 */ 352 struct smu_table driver_table; 353 struct smu_table memory_pool; 354 struct smu_table dummy_read_1_table; 355 uint8_t thermal_controller_type; 356 357 void *overdrive_table; 358 void *boot_overdrive_table; 359 void *user_overdrive_table; 360 361 uint32_t gpu_metrics_table_size; 362 void *gpu_metrics_table; 363 }; 364 365 struct smu_dpm_context { 366 uint32_t dpm_context_size; 367 void *dpm_context; 368 void *golden_dpm_context; 369 enum amd_dpm_forced_level dpm_level; 370 enum amd_dpm_forced_level saved_dpm_level; 371 enum amd_dpm_forced_level requested_dpm_level; 372 struct smu_power_state *dpm_request_power_state; 373 struct smu_power_state *dpm_current_power_state; 374 struct mclock_latency_table *mclk_latency_table; 375 }; 376 377 struct smu_power_gate { 378 bool uvd_gated; 379 bool vce_gated; 380 atomic_t vcn_gated; 381 atomic_t jpeg_gated; 382 atomic_t vpe_gated; 383 atomic_t umsch_mm_gated; 384 }; 385 386 struct smu_power_context { 387 void *power_context; 388 uint32_t power_context_size; 389 struct smu_power_gate power_gate; 390 }; 391 392 #define SMU_FEATURE_MAX (64) 393 struct smu_feature { 394 uint32_t feature_num; 395 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 396 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 397 }; 398 399 struct smu_clocks { 400 uint32_t engine_clock; 401 uint32_t memory_clock; 402 uint32_t bus_bandwidth; 403 uint32_t engine_clock_in_sr; 404 uint32_t dcef_clock; 405 uint32_t dcef_clock_in_sr; 406 }; 407 408 #define MAX_REGULAR_DPM_NUM 16 409 struct mclk_latency_entries { 410 uint32_t frequency; 411 uint32_t latency; 412 }; 413 struct mclock_latency_table { 414 uint32_t count; 415 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 416 }; 417 418 enum smu_reset_mode { 419 SMU_RESET_MODE_0, 420 SMU_RESET_MODE_1, 421 SMU_RESET_MODE_2, 422 }; 423 424 enum smu_baco_state { 425 SMU_BACO_STATE_ENTER = 0, 426 SMU_BACO_STATE_EXIT, 427 SMU_BACO_STATE_NONE, 428 }; 429 430 struct smu_baco_context { 431 uint32_t state; 432 bool platform_support; 433 bool maco_support; 434 }; 435 436 struct smu_freq_info { 437 uint32_t min; 438 uint32_t max; 439 uint32_t freq_level; 440 }; 441 442 struct pstates_clk_freq { 443 uint32_t min; 444 uint32_t standard; 445 uint32_t peak; 446 struct smu_freq_info custom; 447 struct smu_freq_info curr; 448 }; 449 450 struct smu_umd_pstate_table { 451 struct pstates_clk_freq gfxclk_pstate; 452 struct pstates_clk_freq socclk_pstate; 453 struct pstates_clk_freq uclk_pstate; 454 struct pstates_clk_freq vclk_pstate; 455 struct pstates_clk_freq dclk_pstate; 456 struct pstates_clk_freq fclk_pstate; 457 }; 458 459 struct cmn2asic_msg_mapping { 460 int valid_mapping; 461 int map_to; 462 int valid_in_vf; 463 }; 464 465 struct cmn2asic_mapping { 466 int valid_mapping; 467 int map_to; 468 }; 469 470 struct stb_context { 471 uint32_t stb_buf_size; 472 bool enabled; 473 spinlock_t lock; 474 }; 475 476 #define WORKLOAD_POLICY_MAX 7 477 478 /* 479 * Configure wbrf event handling pace as there can be only one 480 * event processed every SMU_WBRF_EVENT_HANDLING_PACE ms. 481 */ 482 #define SMU_WBRF_EVENT_HANDLING_PACE 10 483 484 struct smu_context { 485 struct amdgpu_device *adev; 486 struct amdgpu_irq_src irq_source; 487 488 const struct pptable_funcs *ppt_funcs; 489 const struct cmn2asic_msg_mapping *message_map; 490 const struct cmn2asic_mapping *clock_map; 491 const struct cmn2asic_mapping *feature_map; 492 const struct cmn2asic_mapping *table_map; 493 const struct cmn2asic_mapping *pwr_src_map; 494 const struct cmn2asic_mapping *workload_map; 495 struct mutex message_lock; 496 uint64_t pool_size; 497 498 struct smu_table_context smu_table; 499 struct smu_dpm_context smu_dpm; 500 struct smu_power_context smu_power; 501 struct smu_feature smu_feature; 502 struct amd_pp_display_configuration *display_config; 503 struct smu_baco_context smu_baco; 504 struct smu_temperature_range thermal_range; 505 void *od_settings; 506 507 struct smu_umd_pstate_table pstate_table; 508 uint32_t pstate_sclk; 509 uint32_t pstate_mclk; 510 511 bool od_enabled; 512 uint32_t current_power_limit; 513 uint32_t default_power_limit; 514 uint32_t max_power_limit; 515 uint32_t min_power_limit; 516 517 /* soft pptable */ 518 uint32_t ppt_offset_bytes; 519 uint32_t ppt_size_bytes; 520 uint8_t *ppt_start_addr; 521 522 bool support_power_containment; 523 bool disable_watermark; 524 525 #define WATERMARKS_EXIST (1 << 0) 526 #define WATERMARKS_LOADED (1 << 1) 527 uint32_t watermarks_bitmap; 528 uint32_t hard_min_uclk_req_from_dal; 529 bool disable_uclk_switch; 530 531 uint32_t workload_mask; 532 uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 533 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 534 uint32_t power_profile_mode; 535 uint32_t default_power_profile_mode; 536 bool pm_enabled; 537 bool is_apu; 538 539 uint32_t smc_driver_if_version; 540 uint32_t smc_fw_if_version; 541 uint32_t smc_fw_version; 542 543 bool uploading_custom_pp_table; 544 bool dc_controlled_by_gpio; 545 546 struct work_struct throttling_logging_work; 547 atomic64_t throttle_int_counter; 548 struct work_struct interrupt_work; 549 550 unsigned fan_max_rpm; 551 unsigned manual_fan_speed_pwm; 552 553 uint32_t gfx_default_hard_min_freq; 554 uint32_t gfx_default_soft_max_freq; 555 uint32_t gfx_actual_hard_min_freq; 556 uint32_t gfx_actual_soft_max_freq; 557 558 /* APU only */ 559 uint32_t cpu_default_soft_min_freq; 560 uint32_t cpu_default_soft_max_freq; 561 uint32_t cpu_actual_soft_min_freq; 562 uint32_t cpu_actual_soft_max_freq; 563 uint32_t cpu_core_id_select; 564 uint16_t cpu_core_num; 565 566 struct smu_user_dpm_profile user_dpm_profile; 567 568 struct stb_context stb_context; 569 570 struct firmware pptable_firmware; 571 572 u32 param_reg; 573 u32 msg_reg; 574 u32 resp_reg; 575 576 u32 debug_param_reg; 577 u32 debug_msg_reg; 578 u32 debug_resp_reg; 579 580 struct delayed_work swctf_delayed_work; 581 582 enum pp_xgmi_plpd_mode plpd_mode; 583 584 /* data structures for wbrf feature support */ 585 bool wbrf_supported; 586 struct notifier_block wbrf_notifier; 587 struct delayed_work wbrf_delayed_work; 588 }; 589 590 struct i2c_adapter; 591 592 /** 593 * struct pptable_funcs - Callbacks used to interact with the SMU. 594 */ 595 struct pptable_funcs { 596 /** 597 * @run_btc: Calibrate voltage/frequency curve to fit the system's 598 * power delivery and voltage margins. Required for adaptive 599 * voltage frequency scaling (AVFS). 600 */ 601 int (*run_btc)(struct smu_context *smu); 602 603 /** 604 * @get_allowed_feature_mask: Get allowed feature mask. 605 * &feature_mask: Array to store feature mask. 606 * &num: Elements in &feature_mask. 607 */ 608 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 609 610 /** 611 * @get_current_power_state: Get the current power state. 612 * 613 * Return: Current power state on success, negative errno on failure. 614 */ 615 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 616 617 /** 618 * @set_default_dpm_table: Retrieve the default overdrive settings from 619 * the SMU. 620 */ 621 int (*set_default_dpm_table)(struct smu_context *smu); 622 623 int (*set_power_state)(struct smu_context *smu); 624 625 /** 626 * @populate_umd_state_clk: Populate the UMD power state table with 627 * defaults. 628 */ 629 int (*populate_umd_state_clk)(struct smu_context *smu); 630 631 /** 632 * @print_clk_levels: Print DPM clock levels for a clock domain 633 * to buffer. Star current level. 634 * 635 * Used for sysfs interfaces. 636 * Return: Number of characters written to the buffer 637 */ 638 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 639 640 /** 641 * @emit_clk_levels: Print DPM clock levels for a clock domain 642 * to buffer using sysfs_emit_at. Star current level. 643 * 644 * Used for sysfs interfaces. 645 * &buf: sysfs buffer 646 * &offset: offset within buffer to start printing, which is updated by the 647 * function. 648 * 649 * Return: 0 on Success or Negative to indicate an error occurred. 650 */ 651 int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset); 652 653 /** 654 * @force_clk_levels: Set a range of allowed DPM levels for a clock 655 * domain. 656 * &clk_type: Clock domain. 657 * &mask: Range of allowed DPM levels. 658 */ 659 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 660 661 /** 662 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 663 * &type: Type of edit. 664 * &input: Edit parameters. 665 * &size: Size of &input. 666 */ 667 int (*od_edit_dpm_table)(struct smu_context *smu, 668 enum PP_OD_DPM_TABLE_COMMAND type, 669 long *input, uint32_t size); 670 671 /** 672 * @restore_user_od_settings: Restore the user customized 673 * OD settings on S3/S4/Runpm resume. 674 */ 675 int (*restore_user_od_settings)(struct smu_context *smu); 676 677 /** 678 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 679 * domain. 680 */ 681 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 682 enum smu_clk_type clk_type, 683 struct 684 pp_clock_levels_with_latency 685 *clocks); 686 /** 687 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 688 * domain. 689 */ 690 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 691 enum amd_pp_clock_type type, 692 struct 693 pp_clock_levels_with_voltage 694 *clocks); 695 696 /** 697 * @get_power_profile_mode: Print all power profile modes to 698 * buffer. Star current mode. 699 */ 700 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 701 702 /** 703 * @set_power_profile_mode: Set a power profile mode. Also used to 704 * create/set custom power profile modes. 705 * &input: Power profile mode parameters. 706 * &size: Size of &input. 707 */ 708 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 709 710 /** 711 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 712 * management. 713 */ 714 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 715 716 /** 717 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 718 * management. 719 */ 720 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 721 722 /** 723 * @set_gfx_power_up_by_imu: Enable GFX engine with IMU 724 */ 725 int (*set_gfx_power_up_by_imu)(struct smu_context *smu); 726 727 /** 728 * @read_sensor: Read data from a sensor. 729 * &sensor: Sensor to read data from. 730 * &data: Sensor reading. 731 * &size: Size of &data. 732 */ 733 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 734 void *data, uint32_t *size); 735 736 /** 737 * @get_apu_thermal_limit: get apu core limit from smu 738 * &limit: current limit temperature in millidegrees Celsius 739 */ 740 int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit); 741 742 /** 743 * @set_apu_thermal_limit: update all controllers with new limit 744 * &limit: limit temperature to be setted, in millidegrees Celsius 745 */ 746 int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit); 747 748 /** 749 * @pre_display_config_changed: Prepare GPU for a display configuration 750 * change. 751 * 752 * Disable display tracking and pin memory clock speed to maximum. Used 753 * in display component synchronization. 754 */ 755 int (*pre_display_config_changed)(struct smu_context *smu); 756 757 /** 758 * @display_config_changed: Notify the SMU of the current display 759 * configuration. 760 * 761 * Allows SMU to properly track blanking periods for memory clock 762 * adjustment. Used in display component synchronization. 763 */ 764 int (*display_config_changed)(struct smu_context *smu); 765 766 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 767 768 /** 769 * @notify_smc_display_config: Applies display requirements to the 770 * current power state. 771 * 772 * Optimize deep sleep DCEFclk and mclk for the current display 773 * configuration. Used in display component synchronization. 774 */ 775 int (*notify_smc_display_config)(struct smu_context *smu); 776 777 /** 778 * @is_dpm_running: Check if DPM is running. 779 * 780 * Return: True if DPM is running, false otherwise. 781 */ 782 bool (*is_dpm_running)(struct smu_context *smu); 783 784 /** 785 * @get_fan_speed_pwm: Get the current fan speed in PWM. 786 */ 787 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 788 789 /** 790 * @get_fan_speed_rpm: Get the current fan speed in rpm. 791 */ 792 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 793 794 /** 795 * @set_watermarks_table: Configure and upload the watermarks tables to 796 * the SMU. 797 */ 798 int (*set_watermarks_table)(struct smu_context *smu, 799 struct pp_smu_wm_range_sets *clock_ranges); 800 801 /** 802 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 803 */ 804 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 805 806 /** 807 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 808 * &clocks_in_khz: Array of DPM levels. 809 * &num_states: Elements in &clocks_in_khz. 810 */ 811 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 812 813 /** 814 * @set_default_od_settings: Set the overdrive tables to defaults. 815 */ 816 int (*set_default_od_settings)(struct smu_context *smu); 817 818 /** 819 * @set_performance_level: Set a performance level. 820 */ 821 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 822 823 /** 824 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 825 * clock switching. 826 * 827 * Disabling this feature forces memory clock speed to maximum. 828 * Enabling sets the minimum memory clock capable of driving the 829 * current display configuration. 830 */ 831 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 832 833 /** 834 * @dump_pptable: Print the power play table to the system log. 835 */ 836 void (*dump_pptable)(struct smu_context *smu); 837 838 /** 839 * @get_power_limit: Get the device's power limits. 840 */ 841 int (*get_power_limit)(struct smu_context *smu, 842 uint32_t *current_power_limit, 843 uint32_t *default_power_limit, 844 uint32_t *max_power_limit, 845 uint32_t *min_power_limit); 846 847 /** 848 * @get_ppt_limit: Get the device's ppt limits. 849 */ 850 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 851 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 852 853 /** 854 * @set_df_cstate: Set data fabric cstate. 855 */ 856 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 857 858 /** 859 * @select_xgmi_plpd_policy: Select xgmi per-link power down policy. 860 */ 861 int (*select_xgmi_plpd_policy)(struct smu_context *smu, 862 enum pp_xgmi_plpd_mode mode); 863 864 /** 865 * @update_pcie_parameters: Update and upload the system's PCIe 866 * capabilites to the SMU. 867 * &pcie_gen_cap: Maximum allowed PCIe generation. 868 * &pcie_width_cap: Maximum allowed PCIe width. 869 */ 870 int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap); 871 872 /** 873 * @i2c_init: Initialize i2c. 874 * 875 * The i2c bus is used internally by the SMU voltage regulators and 876 * other devices. The i2c's EEPROM also stores bad page tables on boards 877 * with ECC. 878 */ 879 int (*i2c_init)(struct smu_context *smu); 880 881 /** 882 * @i2c_fini: Tear down i2c. 883 */ 884 void (*i2c_fini)(struct smu_context *smu); 885 886 /** 887 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 888 */ 889 void (*get_unique_id)(struct smu_context *smu); 890 891 /** 892 * @get_dpm_clock_table: Get a copy of the DPM clock table. 893 * 894 * Used by display component in bandwidth and watermark calculations. 895 */ 896 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 897 898 /** 899 * @init_microcode: Request the SMU's firmware from the kernel. 900 */ 901 int (*init_microcode)(struct smu_context *smu); 902 903 /** 904 * @load_microcode: Load firmware onto the SMU. 905 */ 906 int (*load_microcode)(struct smu_context *smu); 907 908 /** 909 * @fini_microcode: Release the SMU's firmware. 910 */ 911 void (*fini_microcode)(struct smu_context *smu); 912 913 /** 914 * @init_smc_tables: Initialize the SMU tables. 915 */ 916 int (*init_smc_tables)(struct smu_context *smu); 917 918 /** 919 * @fini_smc_tables: Release the SMU tables. 920 */ 921 int (*fini_smc_tables)(struct smu_context *smu); 922 923 /** 924 * @init_power: Initialize the power gate table context. 925 */ 926 int (*init_power)(struct smu_context *smu); 927 928 /** 929 * @fini_power: Release the power gate table context. 930 */ 931 int (*fini_power)(struct smu_context *smu); 932 933 /** 934 * @check_fw_status: Check the SMU's firmware status. 935 * 936 * Return: Zero if check passes, negative errno on failure. 937 */ 938 int (*check_fw_status)(struct smu_context *smu); 939 940 /** 941 * @set_mp1_state: put SMU into a correct state for comming 942 * resume from runpm or gpu reset. 943 */ 944 int (*set_mp1_state)(struct smu_context *smu, 945 enum pp_mp1_state mp1_state); 946 947 /** 948 * @setup_pptable: Initialize the power play table and populate it with 949 * default values. 950 */ 951 int (*setup_pptable)(struct smu_context *smu); 952 953 /** 954 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 955 */ 956 int (*get_vbios_bootup_values)(struct smu_context *smu); 957 958 /** 959 * @check_fw_version: Print driver and SMU interface versions to the 960 * system log. 961 * 962 * Interface mismatch is not a critical failure. 963 */ 964 int (*check_fw_version)(struct smu_context *smu); 965 966 /** 967 * @powergate_sdma: Power up/down system direct memory access. 968 */ 969 int (*powergate_sdma)(struct smu_context *smu, bool gate); 970 971 /** 972 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 973 * gating. 974 */ 975 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 976 977 /** 978 * @write_pptable: Write the power play table to the SMU. 979 */ 980 int (*write_pptable)(struct smu_context *smu); 981 982 /** 983 * @set_driver_table_location: Send the location of the driver table to 984 * the SMU. 985 */ 986 int (*set_driver_table_location)(struct smu_context *smu); 987 988 /** 989 * @set_tool_table_location: Send the location of the tool table to the 990 * SMU. 991 */ 992 int (*set_tool_table_location)(struct smu_context *smu); 993 994 /** 995 * @notify_memory_pool_location: Send the location of the memory pool to 996 * the SMU. 997 */ 998 int (*notify_memory_pool_location)(struct smu_context *smu); 999 1000 /** 1001 * @system_features_control: Enable/disable all SMU features. 1002 */ 1003 int (*system_features_control)(struct smu_context *smu, bool en); 1004 1005 /** 1006 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 1007 * &msg: Type of message. 1008 * ¶m: Message parameter. 1009 * &read_arg: SMU response (optional). 1010 */ 1011 int (*send_smc_msg_with_param)(struct smu_context *smu, 1012 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 1013 1014 /** 1015 * @send_smc_msg: Send a message to the SMU. 1016 * &msg: Type of message. 1017 * &read_arg: SMU response (optional). 1018 */ 1019 int (*send_smc_msg)(struct smu_context *smu, 1020 enum smu_message_type msg, 1021 uint32_t *read_arg); 1022 1023 /** 1024 * @init_display_count: Notify the SMU of the number of display 1025 * components in current display configuration. 1026 */ 1027 int (*init_display_count)(struct smu_context *smu, uint32_t count); 1028 1029 /** 1030 * @set_allowed_mask: Notify the SMU of the features currently allowed 1031 * by the driver. 1032 */ 1033 int (*set_allowed_mask)(struct smu_context *smu); 1034 1035 /** 1036 * @get_enabled_mask: Get a mask of features that are currently enabled 1037 * on the SMU. 1038 * &feature_mask: Enabled feature mask. 1039 */ 1040 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1041 1042 /** 1043 * @feature_is_enabled: Test if a feature is enabled. 1044 * 1045 * Return: One if enabled, zero if disabled. 1046 */ 1047 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 1048 1049 /** 1050 * @disable_all_features_with_exception: Disable all features with 1051 * exception to those in &mask. 1052 */ 1053 int (*disable_all_features_with_exception)(struct smu_context *smu, 1054 enum smu_feature_mask mask); 1055 1056 /** 1057 * @notify_display_change: General interface call to let SMU know about DC change 1058 */ 1059 int (*notify_display_change)(struct smu_context *smu); 1060 1061 /** 1062 * @set_power_limit: Set power limit in watts. 1063 */ 1064 int (*set_power_limit)(struct smu_context *smu, 1065 enum smu_ppt_limit_type limit_type, 1066 uint32_t limit); 1067 1068 /** 1069 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1070 * table with values from the SMU. 1071 */ 1072 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1073 1074 /** 1075 * @enable_thermal_alert: Enable thermal alert interrupts. 1076 */ 1077 int (*enable_thermal_alert)(struct smu_context *smu); 1078 1079 /** 1080 * @disable_thermal_alert: Disable thermal alert interrupts. 1081 */ 1082 int (*disable_thermal_alert)(struct smu_context *smu); 1083 1084 /** 1085 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1086 * clock speed in MHz. 1087 */ 1088 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1089 1090 /** 1091 * @display_clock_voltage_request: Set a hard minimum frequency 1092 * for a clock domain. 1093 */ 1094 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1095 pp_display_clock_request 1096 *clock_req); 1097 1098 /** 1099 * @get_fan_control_mode: Get the current fan control mode. 1100 */ 1101 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1102 1103 /** 1104 * @set_fan_control_mode: Set the fan control mode. 1105 */ 1106 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1107 1108 /** 1109 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1110 */ 1111 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1112 1113 /** 1114 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1115 */ 1116 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1117 1118 /** 1119 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1120 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1121 */ 1122 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1123 1124 /** 1125 * @gfx_off_control: Enable/disable graphics engine poweroff. 1126 */ 1127 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1128 1129 1130 /** 1131 * @get_gfx_off_status: Get graphics engine poweroff status. 1132 * 1133 * Return: 1134 * 0 - GFXOFF(default). 1135 * 1 - Transition out of GFX State. 1136 * 2 - Not in GFXOFF. 1137 * 3 - Transition into GFXOFF. 1138 */ 1139 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1140 1141 /** 1142 * @gfx_off_entrycount: total GFXOFF entry count at the time of 1143 * query since system power-up 1144 */ 1145 u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount); 1146 1147 /** 1148 * @set_gfx_off_residency: set 1 to start logging, 0 to stop logging 1149 */ 1150 u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start); 1151 1152 /** 1153 * @get_gfx_off_residency: Average GFXOFF residency % during the logging interval 1154 */ 1155 u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency); 1156 1157 /** 1158 * @register_irq_handler: Register interupt request handlers. 1159 */ 1160 int (*register_irq_handler)(struct smu_context *smu); 1161 1162 /** 1163 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1164 */ 1165 int (*set_azalia_d3_pme)(struct smu_context *smu); 1166 1167 /** 1168 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1169 * clock speeds table. 1170 * 1171 * Provides a way for the display component (DC) to get the max 1172 * sustainable clocks from the SMU. 1173 */ 1174 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1175 1176 /** 1177 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off). 1178 */ 1179 bool (*baco_is_support)(struct smu_context *smu); 1180 1181 /** 1182 * @baco_get_state: Get the current BACO state. 1183 * 1184 * Return: Current BACO state. 1185 */ 1186 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1187 1188 /** 1189 * @baco_set_state: Enter/exit BACO. 1190 */ 1191 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1192 1193 /** 1194 * @baco_enter: Enter BACO. 1195 */ 1196 int (*baco_enter)(struct smu_context *smu); 1197 1198 /** 1199 * @baco_exit: Exit Baco. 1200 */ 1201 int (*baco_exit)(struct smu_context *smu); 1202 1203 /** 1204 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1205 */ 1206 bool (*mode1_reset_is_support)(struct smu_context *smu); 1207 /** 1208 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1209 */ 1210 bool (*mode2_reset_is_support)(struct smu_context *smu); 1211 1212 /** 1213 * @mode1_reset: Perform mode1 reset. 1214 * 1215 * Complete GPU reset. 1216 */ 1217 int (*mode1_reset)(struct smu_context *smu); 1218 1219 /** 1220 * @mode2_reset: Perform mode2 reset. 1221 * 1222 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1223 * IPs reset varies by asic. 1224 */ 1225 int (*mode2_reset)(struct smu_context *smu); 1226 /* for gfx feature enablement after mode2 reset */ 1227 int (*enable_gfx_features)(struct smu_context *smu); 1228 1229 /** 1230 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1231 * domain in MHz. 1232 */ 1233 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1234 1235 /** 1236 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1237 * domain in MHz. 1238 */ 1239 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 1240 1241 /** 1242 * @set_power_source: Notify the SMU of the current power source. 1243 */ 1244 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1245 1246 /** 1247 * @log_thermal_throttling_event: Print a thermal throttling warning to 1248 * the system's log. 1249 */ 1250 void (*log_thermal_throttling_event)(struct smu_context *smu); 1251 1252 /** 1253 * @get_pp_feature_mask: Print a human readable table of enabled 1254 * features to buffer. 1255 */ 1256 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1257 1258 /** 1259 * @set_pp_feature_mask: Request the SMU enable/disable features to 1260 * match those enabled in &new_mask. 1261 */ 1262 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1263 1264 /** 1265 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1266 * 1267 * Return: Size of &table 1268 */ 1269 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1270 1271 /** 1272 * @get_pm_metrics: Get one snapshot of power management metrics from 1273 * PMFW. 1274 * 1275 * Return: Size of the metrics sample 1276 */ 1277 ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics, 1278 size_t size); 1279 1280 /** 1281 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1282 */ 1283 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1284 1285 /** 1286 * @gfx_ulv_control: Enable/disable ultra low voltage. 1287 */ 1288 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1289 1290 /** 1291 * @deep_sleep_control: Enable/disable deep sleep. 1292 */ 1293 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1294 1295 /** 1296 * @get_fan_parameters: Get fan parameters. 1297 * 1298 * Get maximum fan speed from the power play table. 1299 */ 1300 int (*get_fan_parameters)(struct smu_context *smu); 1301 1302 /** 1303 * @post_init: Helper function for asic specific workarounds. 1304 */ 1305 int (*post_init)(struct smu_context *smu); 1306 1307 /** 1308 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1309 */ 1310 void (*interrupt_work)(struct smu_context *smu); 1311 1312 /** 1313 * @gpo_control: Enable/disable graphics power optimization if supported. 1314 */ 1315 int (*gpo_control)(struct smu_context *smu, bool enablement); 1316 1317 /** 1318 * @gfx_state_change_set: Send the current graphics state to the SMU. 1319 */ 1320 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1321 1322 /** 1323 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1324 * parameters to defaults. 1325 */ 1326 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1327 1328 /** 1329 * @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR. 1330 */ 1331 int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable); 1332 1333 /** 1334 * @wait_for_event: Wait for events from SMU. 1335 */ 1336 int (*wait_for_event)(struct smu_context *smu, 1337 enum smu_event_type event, uint64_t event_arg); 1338 1339 /** 1340 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1341 * of SMUBUS table. 1342 */ 1343 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1344 1345 /** 1346 * @send_rma_reason: message rma reason event to SMU. 1347 */ 1348 int (*send_rma_reason)(struct smu_context *smu); 1349 1350 /** 1351 * @get_ecc_table: message SMU to get ECC INFO table. 1352 */ 1353 ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); 1354 1355 1356 /** 1357 * @stb_collect_info: Collects Smart Trace Buffers data. 1358 */ 1359 int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size); 1360 1361 /** 1362 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings. 1363 */ 1364 int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table); 1365 1366 /** 1367 * @set_config_table: Apply the input DriverSmuConfig table settings. 1368 */ 1369 int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table); 1370 1371 /** 1372 * @sned_hbm_bad_channel_flag: message SMU to update bad channel info 1373 * of SMUBUS table. 1374 */ 1375 int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size); 1376 1377 /** 1378 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP 1379 */ 1380 int (*init_pptable_microcode)(struct smu_context *smu); 1381 1382 /** 1383 * @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power 1384 * management. 1385 */ 1386 int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable); 1387 1388 /** 1389 * @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power 1390 * management. 1391 */ 1392 int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable); 1393 1394 /** 1395 * @notify_rlc_state: Notify RLC power state to SMU. 1396 */ 1397 int (*notify_rlc_state)(struct smu_context *smu, bool en); 1398 1399 /** 1400 * @is_asic_wbrf_supported: check whether PMFW supports the wbrf feature 1401 */ 1402 bool (*is_asic_wbrf_supported)(struct smu_context *smu); 1403 1404 /** 1405 * @enable_uclk_shadow: Enable the uclk shadow feature on wbrf supported 1406 */ 1407 int (*enable_uclk_shadow)(struct smu_context *smu, bool enable); 1408 1409 /** 1410 * @set_wbrf_exclusion_ranges: notify SMU the wifi bands occupied 1411 */ 1412 int (*set_wbrf_exclusion_ranges)(struct smu_context *smu, 1413 struct freq_band_range *exclusion_ranges); 1414 }; 1415 1416 typedef enum { 1417 METRICS_CURR_GFXCLK, 1418 METRICS_CURR_SOCCLK, 1419 METRICS_CURR_UCLK, 1420 METRICS_CURR_VCLK, 1421 METRICS_CURR_VCLK1, 1422 METRICS_CURR_DCLK, 1423 METRICS_CURR_DCLK1, 1424 METRICS_CURR_FCLK, 1425 METRICS_CURR_DCEFCLK, 1426 METRICS_AVERAGE_CPUCLK, 1427 METRICS_AVERAGE_GFXCLK, 1428 METRICS_AVERAGE_SOCCLK, 1429 METRICS_AVERAGE_FCLK, 1430 METRICS_AVERAGE_UCLK, 1431 METRICS_AVERAGE_VCLK, 1432 METRICS_AVERAGE_DCLK, 1433 METRICS_AVERAGE_VCLK1, 1434 METRICS_AVERAGE_DCLK1, 1435 METRICS_AVERAGE_GFXACTIVITY, 1436 METRICS_AVERAGE_MEMACTIVITY, 1437 METRICS_AVERAGE_VCNACTIVITY, 1438 METRICS_AVERAGE_SOCKETPOWER, 1439 METRICS_TEMPERATURE_EDGE, 1440 METRICS_TEMPERATURE_HOTSPOT, 1441 METRICS_TEMPERATURE_MEM, 1442 METRICS_TEMPERATURE_VRGFX, 1443 METRICS_TEMPERATURE_VRSOC, 1444 METRICS_TEMPERATURE_VRMEM, 1445 METRICS_THROTTLER_STATUS, 1446 METRICS_CURR_FANSPEED, 1447 METRICS_VOLTAGE_VDDSOC, 1448 METRICS_VOLTAGE_VDDGFX, 1449 METRICS_SS_APU_SHARE, 1450 METRICS_SS_DGPU_SHARE, 1451 METRICS_UNIQUE_ID_UPPER32, 1452 METRICS_UNIQUE_ID_LOWER32, 1453 METRICS_PCIE_RATE, 1454 METRICS_PCIE_WIDTH, 1455 METRICS_CURR_FANPWM, 1456 METRICS_CURR_SOCKETPOWER, 1457 METRICS_AVERAGE_VPECLK, 1458 METRICS_AVERAGE_IPUCLK, 1459 METRICS_AVERAGE_MPIPUCLK, 1460 METRICS_THROTTLER_RESIDENCY_PROCHOT, 1461 METRICS_THROTTLER_RESIDENCY_SPL, 1462 METRICS_THROTTLER_RESIDENCY_FPPT, 1463 METRICS_THROTTLER_RESIDENCY_SPPT, 1464 METRICS_THROTTLER_RESIDENCY_THM_CORE, 1465 METRICS_THROTTLER_RESIDENCY_THM_GFX, 1466 METRICS_THROTTLER_RESIDENCY_THM_SOC, 1467 } MetricsMember_t; 1468 1469 enum smu_cmn2asic_mapping_type { 1470 CMN2ASIC_MAPPING_MSG, 1471 CMN2ASIC_MAPPING_CLK, 1472 CMN2ASIC_MAPPING_FEATURE, 1473 CMN2ASIC_MAPPING_TABLE, 1474 CMN2ASIC_MAPPING_PWR, 1475 CMN2ASIC_MAPPING_WORKLOAD, 1476 }; 1477 1478 enum smu_baco_seq { 1479 BACO_SEQ_BACO = 0, 1480 BACO_SEQ_MSR, 1481 BACO_SEQ_BAMACO, 1482 BACO_SEQ_ULPS, 1483 BACO_SEQ_COUNT, 1484 }; 1485 1486 #define MSG_MAP(msg, index, valid_in_vf) \ 1487 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)} 1488 1489 #define CLK_MAP(clk, index) \ 1490 [SMU_##clk] = {1, (index)} 1491 1492 #define FEA_MAP(fea) \ 1493 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1494 1495 #define FEA_MAP_REVERSE(fea) \ 1496 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1497 1498 #define FEA_MAP_HALF_REVERSE(fea) \ 1499 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1500 1501 #define TAB_MAP(tab) \ 1502 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1503 1504 #define TAB_MAP_VALID(tab) \ 1505 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1506 1507 #define TAB_MAP_INVALID(tab) \ 1508 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1509 1510 #define PWR_MAP(tab) \ 1511 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1512 1513 #define WORKLOAD_MAP(profile, workload) \ 1514 [profile] = {1, (workload)} 1515 1516 /** 1517 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1518 * 1519 * @dst: Pointer to destination struct 1520 * @first_dst_member: The member name in @dst where the overwrite begins 1521 * @last_dst_member: The member name in @dst where the overwrite ends after 1522 * @src: Pointer to the source struct 1523 * @first_src_member: The member name in @src where the copy begins 1524 * 1525 */ 1526 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1527 src, first_src_member) \ 1528 ({ \ 1529 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1530 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1531 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1532 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1533 __dst_offset; \ 1534 BUILD_BUG_ON(__src_size != __dst_size); \ 1535 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1536 (u8 *)(src) + __src_offset, \ 1537 __dst_size); \ 1538 }) 1539 1540 typedef struct { 1541 uint16_t LowFreq; 1542 uint16_t HighFreq; 1543 } WifiOneBand_t; 1544 1545 typedef struct { 1546 uint32_t WifiBandEntryNum; 1547 WifiOneBand_t WifiBandEntry[11]; 1548 uint32_t MmHubPadding[8]; 1549 } WifiBandEntryTable_t; 1550 1551 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1552 int smu_get_power_limit(void *handle, 1553 uint32_t *limit, 1554 enum pp_power_limit_level pp_limit_level, 1555 enum pp_power_type pp_power_type); 1556 1557 bool smu_mode1_reset_is_support(struct smu_context *smu); 1558 bool smu_mode2_reset_is_support(struct smu_context *smu); 1559 int smu_mode1_reset(struct smu_context *smu); 1560 1561 extern const struct amd_ip_funcs smu_ip_funcs; 1562 1563 bool is_support_sw_smu(struct amdgpu_device *adev); 1564 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1565 int smu_write_watermarks_table(struct smu_context *smu); 1566 1567 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1568 uint32_t *min, uint32_t *max); 1569 1570 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1571 uint32_t min, uint32_t max); 1572 1573 int smu_set_gfx_power_up_by_imu(struct smu_context *smu); 1574 1575 int smu_set_ac_dc(struct smu_context *smu); 1576 1577 int smu_set_xgmi_plpd_mode(struct smu_context *smu, 1578 enum pp_xgmi_plpd_mode mode); 1579 1580 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value); 1581 1582 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value); 1583 1584 int smu_set_residency_gfxoff(struct smu_context *smu, bool value); 1585 1586 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value); 1587 1588 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable); 1589 1590 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 1591 uint64_t event_arg); 1592 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc); 1593 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size); 1594 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev); 1595 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size); 1596 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size); 1597 int smu_send_rma_reason(struct smu_context *smu); 1598 #endif 1599 #endif 1600