1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SMU13_DRIVER_IF_SMU_13_0_7_H 24 #define SMU13_DRIVER_IF_SMU_13_0_7_H 25 26 // *** IMPORTANT *** 27 // PMFW TEAM: Always increment the interface version on any change to this file 28 #define SMU13_DRIVER_IF_VERSION 0x2C 29 30 //Increment this version if SkuTable_t or BoardTable_t change 31 #define PPTABLE_VERSION 0x20 32 33 #define NUM_GFXCLK_DPM_LEVELS 16 34 #define NUM_SOCCLK_DPM_LEVELS 8 35 #define NUM_MP0CLK_DPM_LEVELS 2 36 #define NUM_DCLK_DPM_LEVELS 8 37 #define NUM_VCLK_DPM_LEVELS 8 38 #define NUM_DISPCLK_DPM_LEVELS 8 39 #define NUM_DPPCLK_DPM_LEVELS 8 40 #define NUM_DPREFCLK_DPM_LEVELS 8 41 #define NUM_DCFCLK_DPM_LEVELS 8 42 #define NUM_DTBCLK_DPM_LEVELS 8 43 #define NUM_UCLK_DPM_LEVELS 4 44 #define NUM_LINK_LEVELS 3 45 #define NUM_FCLK_DPM_LEVELS 8 46 #define NUM_OD_FAN_MAX_POINTS 6 47 48 // Feature Control Defines 49 #define FEATURE_FW_DATA_READ_BIT 0 50 #define FEATURE_DPM_GFXCLK_BIT 1 51 #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 52 #define FEATURE_DPM_UCLK_BIT 3 53 #define FEATURE_DPM_FCLK_BIT 4 54 #define FEATURE_DPM_SOCCLK_BIT 5 55 #define FEATURE_DPM_MP0CLK_BIT 6 56 #define FEATURE_DPM_LINK_BIT 7 57 #define FEATURE_DPM_DCN_BIT 8 58 #define FEATURE_VMEMP_SCALING_BIT 9 59 #define FEATURE_VDDIO_MEM_SCALING_BIT 10 60 #define FEATURE_DS_GFXCLK_BIT 11 61 #define FEATURE_DS_SOCCLK_BIT 12 62 #define FEATURE_DS_FCLK_BIT 13 63 #define FEATURE_DS_LCLK_BIT 14 64 #define FEATURE_DS_DCFCLK_BIT 15 65 #define FEATURE_DS_UCLK_BIT 16 66 #define FEATURE_GFX_ULV_BIT 17 67 #define FEATURE_FW_DSTATE_BIT 18 68 #define FEATURE_GFXOFF_BIT 19 69 #define FEATURE_BACO_BIT 20 70 #define FEATURE_MM_DPM_BIT 21 71 #define FEATURE_SOC_MPCLK_DS_BIT 22 72 #define FEATURE_BACO_MPCLK_DS_BIT 23 73 #define FEATURE_THROTTLERS_BIT 24 74 #define FEATURE_SMARTSHIFT_BIT 25 75 #define FEATURE_GTHR_BIT 26 76 #define FEATURE_ACDC_BIT 27 77 #define FEATURE_VR0HOT_BIT 28 78 #define FEATURE_FW_CTF_BIT 29 79 #define FEATURE_FAN_CONTROL_BIT 30 80 #define FEATURE_GFX_DCS_BIT 31 81 #define FEATURE_GFX_READ_MARGIN_BIT 32 82 #define FEATURE_LED_DISPLAY_BIT 33 83 #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 84 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 85 #define FEATURE_OPTIMIZED_VMIN_BIT 36 86 #define FEATURE_GFX_IMU_BIT 37 87 #define FEATURE_BOOT_TIME_CAL_BIT 38 88 #define FEATURE_GFX_PCC_DFLL_BIT 39 89 #define FEATURE_SOC_CG_BIT 40 90 #define FEATURE_DF_CSTATE_BIT 41 91 #define FEATURE_GFX_EDC_BIT 42 92 #define FEATURE_BOOT_POWER_OPT_BIT 43 93 #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 94 #define FEATURE_DS_VCN_BIT 45 95 #define FEATURE_BACO_CG_BIT 46 96 #define FEATURE_MEM_TEMP_READ_BIT 47 97 #define FEATURE_ATHUB_MMHUB_PG_BIT 48 98 #define FEATURE_SOC_PCC_BIT 49 99 #define FEATURE_SPARE_50_BIT 50 100 #define FEATURE_SPARE_51_BIT 51 101 #define FEATURE_SPARE_52_BIT 52 102 #define FEATURE_SPARE_53_BIT 53 103 #define FEATURE_SPARE_54_BIT 54 104 #define FEATURE_SPARE_55_BIT 55 105 #define FEATURE_SPARE_56_BIT 56 106 #define FEATURE_SPARE_57_BIT 57 107 #define FEATURE_SPARE_58_BIT 58 108 #define FEATURE_SPARE_59_BIT 59 109 #define FEATURE_SPARE_60_BIT 60 110 #define FEATURE_SPARE_61_BIT 61 111 #define FEATURE_SPARE_62_BIT 62 112 #define FEATURE_SPARE_63_BIT 63 113 #define NUM_FEATURES 64 114 115 #define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL 116 #define ALLOWED_FEATURE_CTRL_SCPM (1 << FEATURE_DPM_GFXCLK_BIT) | \ 117 (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 118 (1 << FEATURE_DPM_UCLK_BIT) | \ 119 (1 << FEATURE_DPM_FCLK_BIT) | \ 120 (1 << FEATURE_DPM_SOCCLK_BIT) | \ 121 (1 << FEATURE_DPM_MP0CLK_BIT) | \ 122 (1 << FEATURE_DPM_LINK_BIT) | \ 123 (1 << FEATURE_DPM_DCN_BIT) | \ 124 (1 << FEATURE_DS_GFXCLK_BIT) | \ 125 (1 << FEATURE_DS_SOCCLK_BIT) | \ 126 (1 << FEATURE_DS_FCLK_BIT) | \ 127 (1 << FEATURE_DS_LCLK_BIT) | \ 128 (1 << FEATURE_DS_DCFCLK_BIT) | \ 129 (1 << FEATURE_DS_UCLK_BIT) 130 131 //For use with feature control messages 132 typedef enum { 133 FEATURE_PWR_ALL, 134 FEATURE_PWR_S5, 135 FEATURE_PWR_BACO, 136 FEATURE_PWR_SOC, 137 FEATURE_PWR_GFX, 138 FEATURE_PWR_DOMAIN_COUNT, 139 } FEATURE_PWR_DOMAIN_e; 140 141 142 // Debug Overrides Bitmask 143 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 144 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 145 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 146 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 147 #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 148 #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 149 #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 150 #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 151 #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 152 #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 153 #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 154 #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 155 #define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000 156 157 // VR Mapping Bit Defines 158 #define VR_MAPPING_VR_SELECT_MASK 0x01 159 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 160 161 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 162 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 163 164 // PSI Bit Defines 165 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 166 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 167 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 168 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 169 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 170 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 171 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 172 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 173 174 typedef enum { 175 SVI_PSI_0, // Full phase count (default) 176 SVI_PSI_1, // Phase count 1st level 177 SVI_PSI_2, // Phase count 2nd level 178 SVI_PSI_3, // Single phase operation + active diode emulation 179 SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 180 SVI_PSI_5, // Reserved 181 SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 182 SVI_PSI_7, // Automated phase shedding and diode emulation 183 } SVI_PSI_e; 184 185 // Throttler Control/Status Bits 186 #define THROTTLER_TEMP_EDGE_BIT 0 187 #define THROTTLER_TEMP_HOTSPOT_BIT 1 188 #define THROTTLER_TEMP_HOTSPOT_G_BIT 2 189 #define THROTTLER_TEMP_HOTSPOT_M_BIT 3 190 #define THROTTLER_TEMP_MEM_BIT 4 191 #define THROTTLER_TEMP_VR_GFX_BIT 5 192 #define THROTTLER_TEMP_VR_MEM0_BIT 6 193 #define THROTTLER_TEMP_VR_MEM1_BIT 7 194 #define THROTTLER_TEMP_VR_SOC_BIT 8 195 #define THROTTLER_TEMP_VR_U_BIT 9 196 #define THROTTLER_TEMP_LIQUID0_BIT 10 197 #define THROTTLER_TEMP_LIQUID1_BIT 11 198 #define THROTTLER_TEMP_PLX_BIT 12 199 #define THROTTLER_TDC_GFX_BIT 13 200 #define THROTTLER_TDC_SOC_BIT 14 201 #define THROTTLER_TDC_U_BIT 15 202 #define THROTTLER_PPT0_BIT 16 203 #define THROTTLER_PPT1_BIT 17 204 #define THROTTLER_PPT2_BIT 18 205 #define THROTTLER_PPT3_BIT 19 206 #define THROTTLER_FIT_BIT 20 207 #define THROTTLER_GFX_APCC_PLUS_BIT 21 208 #define THROTTLER_COUNT 22 209 210 // FW DState Features Control Bits 211 #define FW_DSTATE_SOC_ULV_BIT 0 212 #define FW_DSTATE_G6_HSR_BIT 1 213 #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 214 #define FW_DSTATE_SMN_DS_BIT 3 215 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 216 #define FW_DSTATE_SOC_LIV_MIN_BIT 5 217 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 218 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 219 #define FW_DSTATE_MALL_ALLOC_BIT 8 220 #define FW_DSTATE_MEM_PSI_BIT 9 221 #define FW_DSTATE_HSR_NON_STROBE_BIT 10 222 #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 223 #define FW_DSTATE_U_ULV_BIT 12 224 #define FW_DSTATE_MALL_FLUSH_BIT 13 225 #define FW_DSTATE_SOC_PSI_BIT 14 226 #define FW_DSTATE_U_PSI_BIT 15 227 #define FW_DSTATE_UCP_DS_BIT 16 228 #define FW_DSTATE_CSRCLK_DS_BIT 17 229 #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 230 #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 231 #define FW_DSTATE_CLDO_PRG_BIT 20 232 #define FW_DSTATE_DF_PLL_PWRDN_BIT 21 233 #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 234 #define FW_DSTATE_GFX_PSI6_BIT 23 235 #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 236 237 //LED Display Mask & Control Bits 238 #define LED_DISPLAY_GFX_DPM_BIT 0 239 #define LED_DISPLAY_PCIE_BIT 1 240 #define LED_DISPLAY_ERROR_BIT 2 241 242 243 #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 244 #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 245 #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 246 247 typedef enum { 248 SMARTSHIFT_VERSION_1, 249 SMARTSHIFT_VERSION_2, 250 SMARTSHIFT_VERSION_3, 251 } SMARTSHIFT_VERSION_e; 252 253 typedef enum { 254 FOPT_CALC_AC_CALC_DC, 255 FOPT_PPTABLE_AC_CALC_DC, 256 FOPT_CALC_AC_PPTABLE_DC, 257 FOPT_PPTABLE_AC_PPTABLE_DC, 258 } FOPT_CALC_e; 259 260 typedef enum { 261 DRAM_BIT_WIDTH_DISABLED = 0, 262 DRAM_BIT_WIDTH_X_8 = 8, 263 DRAM_BIT_WIDTH_X_16 = 16, 264 DRAM_BIT_WIDTH_X_32 = 32, 265 DRAM_BIT_WIDTH_X_64 = 64, 266 DRAM_BIT_WIDTH_X_128 = 128, 267 DRAM_BIT_WIDTH_COUNT, 268 } DRAM_BIT_WIDTH_TYPE_e; 269 270 //I2C Interface 271 #define NUM_I2C_CONTROLLERS 8 272 273 #define I2C_CONTROLLER_ENABLED 1 274 #define I2C_CONTROLLER_DISABLED 0 275 276 #define MAX_SW_I2C_COMMANDS 24 277 278 typedef enum { 279 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 280 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 281 I2C_CONTROLLER_PORT_COUNT, 282 } I2cControllerPort_e; 283 284 typedef enum { 285 I2C_CONTROLLER_NAME_VR_GFX = 0, 286 I2C_CONTROLLER_NAME_VR_SOC, 287 I2C_CONTROLLER_NAME_VR_VMEMP, 288 I2C_CONTROLLER_NAME_VR_VDDIO, 289 I2C_CONTROLLER_NAME_LIQUID0, 290 I2C_CONTROLLER_NAME_LIQUID1, 291 I2C_CONTROLLER_NAME_PLX, 292 I2C_CONTROLLER_NAME_OTHER, 293 I2C_CONTROLLER_NAME_COUNT, 294 } I2cControllerName_e; 295 296 typedef enum { 297 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 298 I2C_CONTROLLER_THROTTLER_VR_GFX, 299 I2C_CONTROLLER_THROTTLER_VR_SOC, 300 I2C_CONTROLLER_THROTTLER_VR_VMEMP, 301 I2C_CONTROLLER_THROTTLER_VR_VDDIO, 302 I2C_CONTROLLER_THROTTLER_LIQUID0, 303 I2C_CONTROLLER_THROTTLER_LIQUID1, 304 I2C_CONTROLLER_THROTTLER_PLX, 305 I2C_CONTROLLER_THROTTLER_INA3221, 306 I2C_CONTROLLER_THROTTLER_COUNT, 307 } I2cControllerThrottler_e; 308 309 typedef enum { 310 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 311 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 312 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 313 I2C_CONTROLLER_PROTOCOL_INA3221, 314 I2C_CONTROLLER_PROTOCOL_COUNT, 315 } I2cControllerProtocol_e; 316 317 typedef struct { 318 uint8_t Enabled; 319 uint8_t Speed; 320 uint8_t SlaveAddress; 321 uint8_t ControllerPort; 322 uint8_t ControllerName; 323 uint8_t ThermalThrotter; 324 uint8_t I2cProtocol; 325 uint8_t PaddingConfig; 326 } I2cControllerConfig_t; 327 328 typedef enum { 329 I2C_PORT_SVD_SCL = 0, 330 I2C_PORT_GPIO, 331 } I2cPort_e; 332 333 typedef enum { 334 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 335 I2C_SPEED_FAST_100K, //100 Kbits/s 336 I2C_SPEED_FAST_400K, //400 Kbits/s 337 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 338 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 339 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 340 I2C_SPEED_COUNT, 341 } I2cSpeed_e; 342 343 typedef enum { 344 I2C_CMD_READ = 0, 345 I2C_CMD_WRITE, 346 I2C_CMD_COUNT, 347 } I2cCmdType_e; 348 349 #define CMDCONFIG_STOP_BIT 0 350 #define CMDCONFIG_RESTART_BIT 1 351 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 352 353 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 354 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 355 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 356 357 typedef struct { 358 uint8_t ReadWriteData; //Return data for read. Data to send for write 359 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 360 } SwI2cCmd_t; //SW I2C Command Table 361 362 typedef struct { 363 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 364 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 365 uint8_t SlaveAddress; //Slave address of device 366 uint8_t NumCmds; //Number of commands 367 368 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 369 } SwI2cRequest_t; // SW I2C Request Table 370 371 typedef struct { 372 SwI2cRequest_t SwI2cRequest; 373 374 uint32_t Spare[8]; 375 uint32_t MmHubPadding[8]; // SMU internal use 376 } SwI2cRequestExternal_t; 377 378 typedef struct { 379 uint64_t mca_umc_status; 380 uint64_t mca_umc_addr; 381 382 uint16_t ce_count_lo_chip; 383 uint16_t ce_count_hi_chip; 384 385 uint32_t eccPadding; 386 } EccInfo_t; 387 388 typedef struct { 389 EccInfo_t EccInfo[24]; 390 } EccInfoTable_t; 391 392 //D3HOT sequences 393 typedef enum { 394 BACO_SEQUENCE, 395 MSR_SEQUENCE, 396 BAMACO_SEQUENCE, 397 ULPS_SEQUENCE, 398 D3HOT_SEQUENCE_COUNT, 399 } D3HOTSequence_e; 400 401 //This is aligned with RSMU PGFSM Register Mapping 402 typedef enum { 403 PG_DYNAMIC_MODE = 0, 404 PG_STATIC_MODE, 405 } PowerGatingMode_e; 406 407 //This is aligned with RSMU PGFSM Register Mapping 408 typedef enum { 409 PG_POWER_DOWN = 0, 410 PG_POWER_UP, 411 } PowerGatingSettings_e; 412 413 typedef struct { 414 uint32_t a; // store in IEEE float format in this variable 415 uint32_t b; // store in IEEE float format in this variable 416 uint32_t c; // store in IEEE float format in this variable 417 } QuadraticInt_t; 418 419 typedef struct { 420 uint32_t m; // store in IEEE float format in this variable 421 uint32_t b; // store in IEEE float format in this variable 422 } LinearInt_t; 423 424 typedef struct { 425 uint32_t a; // store in IEEE float format in this variable 426 uint32_t b; // store in IEEE float format in this variable 427 uint32_t c; // store in IEEE float format in this variable 428 } DroopInt_t; 429 430 typedef enum { 431 DCS_ARCH_DISABLED, 432 DCS_ARCH_FADCS, 433 DCS_ARCH_ASYNC, 434 } DCS_ARCH_e; 435 436 //Only Clks that have DPM descriptors are listed here 437 typedef enum { 438 PPCLK_GFXCLK = 0, 439 PPCLK_SOCCLK, 440 PPCLK_UCLK, 441 PPCLK_FCLK, 442 PPCLK_DCLK_0, 443 PPCLK_VCLK_0, 444 PPCLK_DCLK_1, 445 PPCLK_VCLK_1, 446 PPCLK_DISPCLK, 447 PPCLK_DPPCLK, 448 PPCLK_DPREFCLK, 449 PPCLK_DCFCLK, 450 PPCLK_DTBCLK, 451 PPCLK_COUNT, 452 } PPCLK_e; 453 454 typedef enum { 455 VOLTAGE_MODE_PPTABLE = 0, 456 VOLTAGE_MODE_FUSES, 457 VOLTAGE_MODE_COUNT, 458 } VOLTAGE_MODE_e; 459 460 461 typedef enum { 462 AVFS_VOLTAGE_GFX = 0, 463 AVFS_VOLTAGE_SOC, 464 AVFS_VOLTAGE_COUNT, 465 } AVFS_VOLTAGE_TYPE_e; 466 467 typedef enum { 468 AVFS_TEMP_COLD = 0, 469 AVFS_TEMP_HOT, 470 AVFS_TEMP_COUNT, 471 } AVFS_TEMP_e; 472 473 typedef enum { 474 AVFS_D_G, 475 AVFS_D_M_B, 476 AVFS_D_M_S, 477 AVFS_D_COUNT, 478 } AVFS_D_e; 479 480 typedef enum { 481 UCLK_DIV_BY_1 = 0, 482 UCLK_DIV_BY_2, 483 UCLK_DIV_BY_4, 484 UCLK_DIV_BY_8, 485 } UCLK_DIV_e; 486 487 typedef enum { 488 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 489 GPIO_INT_POLARITY_ACTIVE_HIGH, 490 } GpioIntPolarity_e; 491 492 typedef enum { 493 PWR_CONFIG_TDP = 0, 494 PWR_CONFIG_TGP, 495 PWR_CONFIG_TCP_ESTIMATED, 496 PWR_CONFIG_TCP_MEASURED, 497 } PwrConfig_e; 498 499 typedef struct { 500 uint8_t Padding; 501 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 502 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 503 uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 504 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 505 uint32_t Padding3[3]; 506 uint16_t Padding4; 507 uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 508 uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 509 uint16_t Padding2; 510 } DpmDescriptor_t; 511 512 typedef enum { 513 PPT_THROTTLER_PPT0, 514 PPT_THROTTLER_PPT1, 515 PPT_THROTTLER_PPT2, 516 PPT_THROTTLER_PPT3, 517 PPT_THROTTLER_COUNT 518 } PPT_THROTTLER_e; 519 520 typedef enum { 521 TEMP_EDGE, 522 TEMP_HOTSPOT, 523 TEMP_HOTSPOT_G, 524 TEMP_HOTSPOT_M, 525 TEMP_MEM, 526 TEMP_VR_GFX, 527 TEMP_VR_MEM0, 528 TEMP_VR_MEM1, 529 TEMP_VR_SOC, 530 TEMP_VR_U, 531 TEMP_LIQUID0, 532 TEMP_LIQUID1, 533 TEMP_PLX, 534 TEMP_COUNT, 535 } TEMP_e; 536 537 typedef enum { 538 TDC_THROTTLER_GFX, 539 TDC_THROTTLER_SOC, 540 TDC_THROTTLER_U, 541 TDC_THROTTLER_COUNT 542 } TDC_THROTTLER_e; 543 544 typedef enum { 545 SVI_PLANE_GFX, 546 SVI_PLANE_SOC, 547 SVI_PLANE_VMEMP, 548 SVI_PLANE_VDDIO_MEM, 549 SVI_PLANE_U, 550 SVI_PLANE_COUNT, 551 } SVI_PLANE_e; 552 553 typedef enum { 554 PMFW_VOLT_PLANE_GFX, 555 PMFW_VOLT_PLANE_SOC, 556 PMFW_VOLT_PLANE_COUNT 557 } PMFW_VOLT_PLANE_e; 558 559 typedef enum { 560 CUSTOMER_VARIANT_ROW, 561 CUSTOMER_VARIANT_FALCON, 562 CUSTOMER_VARIANT_COUNT, 563 } CUSTOMER_VARIANT_e; 564 565 typedef enum { 566 POWER_SOURCE_AC, 567 POWER_SOURCE_DC, 568 POWER_SOURCE_COUNT, 569 } POWER_SOURCE_e; 570 571 typedef enum { 572 MEM_VENDOR_SAMSUNG, 573 MEM_VENDOR_INFINEON, 574 MEM_VENDOR_ELPIDA, 575 MEM_VENDOR_ETRON, 576 MEM_VENDOR_NANYA, 577 MEM_VENDOR_HYNIX, 578 MEM_VENDOR_MOSEL, 579 MEM_VENDOR_WINBOND, 580 MEM_VENDOR_ESMT, 581 MEM_VENDOR_PLACEHOLDER0, 582 MEM_VENDOR_PLACEHOLDER1, 583 MEM_VENDOR_PLACEHOLDER2, 584 MEM_VENDOR_PLACEHOLDER3, 585 MEM_VENDOR_PLACEHOLDER4, 586 MEM_VENDOR_PLACEHOLDER5, 587 MEM_VENDOR_MICRON, 588 MEM_VENDOR_COUNT, 589 } MEM_VENDOR_e; 590 591 typedef enum { 592 PP_GRTAVFS_HW_CPO_CTL_ZONE0, 593 PP_GRTAVFS_HW_CPO_CTL_ZONE1, 594 PP_GRTAVFS_HW_CPO_CTL_ZONE2, 595 PP_GRTAVFS_HW_CPO_CTL_ZONE3, 596 PP_GRTAVFS_HW_CPO_CTL_ZONE4, 597 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 598 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 599 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 600 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 601 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 602 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 603 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 604 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 605 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 606 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 607 PP_GRTAVFS_HW_ZONE0_VF, 608 PP_GRTAVFS_HW_ZONE1_VF1, 609 PP_GRTAVFS_HW_ZONE2_VF2, 610 PP_GRTAVFS_HW_ZONE3_VF3, 611 PP_GRTAVFS_HW_VOLTAGE_GB, 612 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 613 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 614 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 615 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 616 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 617 PP_GRTAVFS_HW_RESERVED_0, 618 PP_GRTAVFS_HW_RESERVED_1, 619 PP_GRTAVFS_HW_RESERVED_2, 620 PP_GRTAVFS_HW_RESERVED_3, 621 PP_GRTAVFS_HW_RESERVED_4, 622 PP_GRTAVFS_HW_RESERVED_5, 623 PP_GRTAVFS_HW_RESERVED_6, 624 PP_GRTAVFS_HW_FUSE_COUNT, 625 } PP_GRTAVFS_HW_FUSE_e; 626 627 typedef enum { 628 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 629 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 630 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 631 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 632 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 633 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 634 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 635 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 636 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 637 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 638 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 639 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 640 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 641 PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 642 } PP_GRTAVFS_FW_COMMON_FUSE_e; 643 644 typedef enum { 645 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 646 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 647 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 648 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 649 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 650 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 651 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 652 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 653 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 654 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 655 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 656 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 657 PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 658 PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 659 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 660 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 661 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 662 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 663 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 664 PP_GRTAVFS_FW_SEP_FUSE_COUNT, 665 } PP_GRTAVFS_FW_SEP_FUSE_e; 666 667 #define PP_NUM_RTAVFS_PWL_ZONES 5 668 669 670 671 // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 672 // Slope Q1.7, Offset Q1.2 673 typedef struct { 674 int8_t Offset; // in Amps 675 uint8_t Padding; 676 uint16_t MaxCurrent; // in Amps 677 } SviTelemetryScale_t; 678 679 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 680 681 682 #define PP_OD_FEATURE_GFX_VF_CURVE_BIT 0 683 #define PP_OD_FEATURE_VMAX_BIT 1 684 #define PP_OD_FEATURE_PPT_BIT 2 685 #define PP_OD_FEATURE_FAN_CURVE_BIT 3 686 #define PP_OD_FEATURE_FREQ_DETER_BIT 4 687 #define PP_OD_FEATURE_FULL_CTRL_BIT 5 688 #define PP_OD_FEATURE_TDC_BIT 6 689 #define PP_OD_FEATURE_GFXCLK_BIT 7 690 #define PP_OD_FEATURE_UCLK_BIT 8 691 #define PP_OD_FEATURE_ZERO_FAN_BIT 9 692 #define PP_OD_FEATURE_TEMPERATURE_BIT 10 693 694 typedef enum { 695 PP_OD_POWER_FEATURE_ALWAYS_ENABLED, 696 PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING, 697 PP_OD_POWER_FEATURE_ALWAYS_DISABLED, 698 } PP_OD_POWER_FEATURE_e; 699 700 typedef struct { 701 uint32_t FeatureCtrlMask; 702 703 //Voltage control 704 int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 705 uint16_t VddGfxVmax; // in mV 706 707 uint8_t IdlePwrSavingFeaturesCtrl; 708 uint8_t RuntimePwrSavingFeaturesCtrl; 709 710 //Frequency changes 711 int16_t GfxclkFmin; // MHz 712 int16_t GfxclkFmax; // MHz 713 uint16_t UclkFmin; // MHz 714 uint16_t UclkFmax; // MHz 715 716 //PPT 717 int16_t Ppt; // % 718 int16_t Tdc; 719 720 //Fan control 721 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 722 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 723 uint16_t FanMinimumPwm; 724 uint16_t AcousticTargetRpmThreshold; 725 uint16_t AcousticLimitRpmThreshold; 726 uint16_t FanTargetTemperature; // Degree Celcius 727 uint8_t FanZeroRpmEnable; 728 uint8_t FanZeroRpmStopTemp; 729 uint8_t FanMode; 730 uint8_t MaxOpTemp; 731 uint8_t Padding[4]; 732 733 uint32_t Spare[12]; 734 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 735 } OverDriveTable_t; 736 737 typedef struct { 738 OverDriveTable_t OverDriveTable; 739 740 } OverDriveTableExternal_t; 741 742 typedef struct { 743 uint32_t FeatureCtrlMask; 744 745 int16_t VoltageOffsetPerZoneBoundary; 746 uint16_t VddGfxVmax; // in mV 747 748 uint8_t IdlePwrSavingFeaturesCtrl; 749 uint8_t RuntimePwrSavingFeaturesCtrl; 750 751 uint16_t GfxclkFmin; // MHz 752 uint16_t GfxclkFmax; // MHz 753 uint16_t UclkFmin; // MHz 754 uint16_t UclkFmax; // MHz 755 756 //PPT 757 int16_t Ppt; // % 758 int16_t Tdc; 759 760 uint8_t FanLinearPwmPoints; 761 uint8_t FanLinearTempPoints; 762 uint16_t FanMinimumPwm; 763 uint16_t AcousticTargetRpmThreshold; 764 uint16_t AcousticLimitRpmThreshold; 765 uint16_t FanTargetTemperature; // Degree Celcius 766 uint8_t FanZeroRpmEnable; 767 uint8_t FanZeroRpmStopTemp; 768 uint8_t FanMode; 769 uint8_t MaxOpTemp; 770 uint8_t Padding[4]; 771 772 uint32_t Spare[12]; 773 774 } OverDriveLimits_t; 775 776 777 typedef enum { 778 BOARD_GPIO_SMUIO_0, 779 BOARD_GPIO_SMUIO_1, 780 BOARD_GPIO_SMUIO_2, 781 BOARD_GPIO_SMUIO_3, 782 BOARD_GPIO_SMUIO_4, 783 BOARD_GPIO_SMUIO_5, 784 BOARD_GPIO_SMUIO_6, 785 BOARD_GPIO_SMUIO_7, 786 BOARD_GPIO_SMUIO_8, 787 BOARD_GPIO_SMUIO_9, 788 BOARD_GPIO_SMUIO_10, 789 BOARD_GPIO_SMUIO_11, 790 BOARD_GPIO_SMUIO_12, 791 BOARD_GPIO_SMUIO_13, 792 BOARD_GPIO_SMUIO_14, 793 BOARD_GPIO_SMUIO_15, 794 BOARD_GPIO_SMUIO_16, 795 BOARD_GPIO_SMUIO_17, 796 BOARD_GPIO_SMUIO_18, 797 BOARD_GPIO_SMUIO_19, 798 BOARD_GPIO_SMUIO_20, 799 BOARD_GPIO_SMUIO_21, 800 BOARD_GPIO_SMUIO_22, 801 BOARD_GPIO_SMUIO_23, 802 BOARD_GPIO_SMUIO_24, 803 BOARD_GPIO_SMUIO_25, 804 BOARD_GPIO_SMUIO_26, 805 BOARD_GPIO_SMUIO_27, 806 BOARD_GPIO_SMUIO_28, 807 BOARD_GPIO_SMUIO_29, 808 BOARD_GPIO_SMUIO_30, 809 BOARD_GPIO_SMUIO_31, 810 MAX_BOARD_GPIO_SMUIO_NUM, 811 BOARD_GPIO_DC_GEN_A, 812 BOARD_GPIO_DC_GEN_B, 813 BOARD_GPIO_DC_GEN_C, 814 BOARD_GPIO_DC_GEN_D, 815 BOARD_GPIO_DC_GEN_E, 816 BOARD_GPIO_DC_GEN_F, 817 BOARD_GPIO_DC_GEN_G, 818 BOARD_GPIO_DC_GENLK_CLK, 819 BOARD_GPIO_DC_GENLK_VSYNC, 820 BOARD_GPIO_DC_SWAPLOCK_A, 821 BOARD_GPIO_DC_SWAPLOCK_B, 822 } BOARD_GPIO_TYPE_e; 823 824 #define INVALID_BOARD_GPIO 0xFF 825 826 827 typedef struct { 828 //PLL 0 829 uint16_t InitGfxclk_bypass; 830 uint16_t InitSocclk; 831 uint16_t InitMp0clk; 832 uint16_t InitMpioclk; 833 uint16_t InitSmnclk; 834 uint16_t InitUcpclk; 835 uint16_t InitCsrclk; 836 //PLL 1 837 838 uint16_t InitDprefclk; 839 uint16_t InitDcfclk; 840 uint16_t InitDtbclk; 841 //PLL 2 842 uint16_t InitDclk; //assume same DCLK/VCLK for both instances 843 uint16_t InitVclk; 844 // PLL 3 845 uint16_t InitUsbdfsclk; 846 uint16_t InitMp1clk; 847 uint16_t InitLclk; 848 uint16_t InitBaco400clk_bypass; 849 uint16_t InitBaco1200clk_bypass; 850 uint16_t InitBaco700clk_bypass; 851 // PLL 4 852 uint16_t InitFclk; 853 // PLL 5 854 uint16_t InitGfxclk_clkb; 855 856 //PLL 6 857 uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 858 859 uint8_t Padding[3]; 860 861 uint32_t InitVcoFreqPll0; 862 uint32_t InitVcoFreqPll1; 863 uint32_t InitVcoFreqPll2; 864 uint32_t InitVcoFreqPll3; 865 uint32_t InitVcoFreqPll4; 866 uint32_t InitVcoFreqPll5; 867 uint32_t InitVcoFreqPll6; 868 869 //encoding will change depending on SVI2/SVI3 870 uint16_t InitGfx; // In mV(Q2) , should be 0? 871 uint16_t InitSoc; // In mV(Q2) 872 uint16_t InitU; // In Mv(Q2) not applicable 873 874 uint16_t Padding2; 875 876 uint32_t Spare[8]; 877 878 } BootValues_t; 879 880 881 typedef struct { 882 uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 883 uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 884 885 uint16_t Temperature[TEMP_COUNT]; // Celsius 886 887 uint8_t PwmLimitMin; 888 uint8_t PwmLimitMax; 889 uint8_t FanTargetTemperature; 890 uint8_t Spare1[1]; 891 892 uint16_t AcousticTargetRpmThresholdMin; 893 uint16_t AcousticTargetRpmThresholdMax; 894 895 uint16_t AcousticLimitRpmThresholdMin; 896 uint16_t AcousticLimitRpmThresholdMax; 897 898 uint16_t PccLimitMin; 899 uint16_t PccLimitMax; 900 901 uint16_t FanStopTempMin; 902 uint16_t FanStopTempMax; 903 uint16_t FanStartTempMin; 904 uint16_t FanStartTempMax; 905 906 uint32_t Spare[12]; 907 908 } MsgLimits_t; 909 910 typedef struct { 911 uint16_t BaseClockAc; 912 uint16_t GameClockAc; 913 uint16_t BoostClockAc; 914 uint16_t BaseClockDc; 915 uint16_t GameClockDc; 916 uint16_t BoostClockDc; 917 918 uint32_t Reserved[4]; 919 } DriverReportedClocks_t; 920 921 typedef struct { 922 uint8_t DcBtcEnabled; 923 uint8_t Padding[3]; 924 925 uint16_t DcTol; // mV Q2 926 uint16_t DcBtcGb; // mV Q2 927 928 uint16_t DcBtcMin; // mV Q2 929 uint16_t DcBtcMax; // mV Q2 930 931 LinearInt_t DcBtcGbScalar; 932 933 } AvfsDcBtcParams_t; 934 935 typedef struct { 936 uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 937 uint16_t VftFMin; // in MHz 938 uint16_t VInversion; // in mV Q2 939 QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 940 QuadraticInt_t qAvfsGb; 941 QuadraticInt_t qAvfsGb2; 942 } AvfsFuseOverride_t; 943 944 typedef struct { 945 // SECTION: Version 946 947 uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 948 949 // SECTION: Feature Control 950 uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 951 952 // SECTION: Miscellaneous Configuration 953 uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 954 uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 955 uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 956 uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 957 958 // SECTION: Infrastructure Limits 959 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 960 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 961 962 uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 963 964 //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 965 //relative index 0 966 uint8_t EnableLegacyPptLimit; 967 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 968 uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 969 970 uint8_t PaddingPpt[1]; 971 972 uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 973 974 uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 975 976 uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 977 978 uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 979 980 uint16_t PaddingInfra; 981 982 // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 983 uint32_t FitControllerFailureRateLimit; //in IEEE float 984 //Expected GFX Duty Cycle at Vmax. 985 uint32_t FitControllerGfxDutyCycle; // in IEEE float 986 //Expected SOC Duty Cycle at Vmax. 987 uint32_t FitControllerSocDutyCycle; // in IEEE float 988 989 //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 990 uint32_t FitControllerSocOffset; //in IEEE float 991 992 uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 993 994 // SECTION: Throttler settings 995 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 996 997 // SECTION: FW DSTATE Settings 998 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 999 1000 // SECTION: Voltage Control Parameters 1001 uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 1002 1003 uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 1004 uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 1005 1006 // Voltage Limits 1007 uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 1008 uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 1009 1010 //Vmin Optimizations 1011 int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 1012 int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 1013 uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 1014 uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 1015 uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 1016 uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 1017 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 1018 uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 1019 uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 1020 1021 //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 1022 uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 1023 //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 1024 uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 1025 //Scalar coefficient of the PSM aging degradation function 1026 uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 1027 //Exponential coefficient of the PSM aging degradation function 1028 uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 1029 //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1030 uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 1031 //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1032 uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 1033 1034 uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 1035 uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 1036 1037 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1038 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1039 1040 QuadraticInt_t Vmin_droop; 1041 uint32_t SpareVmin[9]; 1042 1043 1044 //SECTION: DPM Configuration 1 1045 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1046 1047 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1048 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1049 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1050 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1051 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1052 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1053 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1054 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1055 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1056 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1057 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1058 1059 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1060 1061 // SECTION: DPM Configuration 2 1062 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1063 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1064 1065 uint8_t GfxclkSpare[2]; 1066 uint16_t GfxclkFreqCap; 1067 1068 //GFX Idle Power Settings 1069 uint16_t GfxclkFgfxoffEntry; // in Mhz 1070 uint16_t GfxclkFgfxoffExitImu; // in Mhz 1071 uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1072 uint16_t GfxclkThrottleClock; //Used primarily in DCS 1073 uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1074 uint8_t GfxIdlePadding; 1075 1076 uint8_t SmsRepairWRCKClkDivEn; 1077 uint8_t SmsRepairWRCKClkDivVal; 1078 uint8_t GfxOffEntryEarlyMGCGEn; 1079 uint8_t GfxOffEntryForceCGCGEn; 1080 uint8_t GfxOffEntryForceCGCGDelayEn; 1081 uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1082 1083 uint16_t GfxclkFreqGfxUlv; // in MHz 1084 uint8_t GfxIdlePadding2[2]; 1085 uint32_t GfxOffEntryHysteresis; //For RLC to count after it enters CGCG, and before triggers GFXOFF entry 1086 uint32_t GfxoffSpare[15]; 1087 1088 // GFX GPO 1089 float DfllBtcMasterScalerM; 1090 int32_t DfllBtcMasterScalerB; 1091 float DfllBtcSlaveScalerM; 1092 int32_t DfllBtcSlaveScalerB; 1093 uint32_t GfxGpoSpare[12]; 1094 1095 // GFX DCS 1096 1097 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1098 uint16_t PaddingDcs; 1099 1100 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1101 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1102 1103 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1104 1105 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1106 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1107 1108 1109 uint32_t DcsSpare[16]; 1110 1111 // UCLK section 1112 uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1113 uint8_t PaddingMem[3]; 1114 1115 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1116 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1117 1118 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1119 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1120 1121 //FCLK Section 1122 1123 uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1124 uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1125 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1126 uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1127 uint16_t PaddingFclk; 1128 1129 // Link DPM Settings 1130 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1131 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1132 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1133 1134 // SECTION: Fan Control 1135 uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1136 uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1137 1138 uint16_t FanGain[TEMP_COUNT]; 1139 uint16_t FanGainPadding; 1140 1141 uint16_t FanPwmMin; 1142 uint16_t AcousticTargetRpmThreshold; 1143 uint16_t AcousticLimitRpmThreshold; 1144 uint16_t FanMaximumRpm; 1145 uint16_t MGpuAcousticLimitRpmThreshold; 1146 uint16_t FanTargetGfxclk; 1147 uint32_t TempInputSelectMask; 1148 uint8_t FanZeroRpmEnable; 1149 uint8_t FanTachEdgePerRev; 1150 uint16_t FanTargetTemperature[TEMP_COUNT]; 1151 1152 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1153 int16_t FuzzyFan_ErrorSetDelta; 1154 int16_t FuzzyFan_ErrorRateSetDelta; 1155 int16_t FuzzyFan_PwmSetDelta; 1156 uint16_t FuzzyFan_Reserved; 1157 1158 uint16_t FwCtfLimit[TEMP_COUNT]; 1159 1160 uint16_t IntakeTempEnableRPM; 1161 int16_t IntakeTempOffsetTemp; 1162 uint16_t IntakeTempReleaseTemp; 1163 uint16_t IntakeTempHighIntakeAcousticLimit; 1164 uint16_t IntakeTempAcouticLimitReleaseRate; 1165 1166 uint16_t FanStalledTempLimitOffset; 1167 uint16_t FanStalledTriggerRpm; 1168 uint16_t FanAbnormalTriggerRpm; 1169 uint16_t FanPadding; 1170 1171 uint32_t FanSpare[14]; 1172 1173 // SECTION: VDD_GFX AVFS 1174 1175 uint8_t OverrideGfxAvfsFuses; 1176 uint8_t GfxAvfsPadding[3]; 1177 1178 uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1179 uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1180 1181 uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1182 1183 uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1184 uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1185 1186 uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1187 uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1188 uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1189 uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1190 1191 uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1192 1193 uint32_t dGbV_dT_vmin; 1194 uint32_t dGbV_dT_vmax; 1195 1196 //Unused: PMFW-9370 1197 uint32_t V2F_vmin_range_low; 1198 uint32_t V2F_vmin_range_high; 1199 uint32_t V2F_vmax_range_low; 1200 uint32_t V2F_vmax_range_high; 1201 1202 AvfsDcBtcParams_t DcBtcGfxParams; 1203 1204 uint32_t GfxAvfsSpare[32]; 1205 1206 //SECTION: VDD_SOC AVFS 1207 1208 uint8_t OverrideSocAvfsFuses; 1209 uint8_t MinSocAvfsRevision; 1210 uint8_t SocAvfsPadding[2]; 1211 1212 AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1213 1214 DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1215 1216 LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1217 1218 QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1219 1220 AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1221 1222 uint32_t SocAvfsSpare[32]; 1223 1224 //SECTION: Boot clock and voltage values 1225 BootValues_t BootValues; 1226 1227 //SECTION: Driver Reported Clocks 1228 DriverReportedClocks_t DriverReportedClocks; 1229 1230 //SECTION: Message Limits 1231 MsgLimits_t MsgLimits; 1232 1233 //SECTION: OverDrive Limits 1234 OverDriveLimits_t OverDriveLimitsMin; 1235 OverDriveLimits_t OverDriveLimitsBasicMax; 1236 OverDriveLimits_t OverDriveLimitsAdvancedMax; 1237 1238 // SECTION: Advanced Options 1239 uint32_t DebugOverrides; 1240 1241 // SECTION: Sku Reserved 1242 uint32_t Spare[64]; 1243 1244 // Padding for MMHUB - do not modify this 1245 uint32_t MmHubPadding[8]; 1246 1247 } SkuTable_t; 1248 1249 typedef struct { 1250 // SECTION: Version 1251 uint32_t Version; //should be unique to each board type 1252 1253 1254 // SECTION: I2C Control 1255 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1256 1257 // SECTION: SVI2 Board Parameters 1258 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1259 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1260 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1261 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1262 1263 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1264 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1265 uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1266 uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1267 1268 //SECTION SVI3 Board Parameters 1269 uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1270 uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1271 1272 uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1273 uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1274 1275 // SECTION: Voltage Regulator Settings 1276 SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1277 uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1278 1279 uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1280 1281 // SECTION: GPIO Settings 1282 1283 uint8_t LedOffGpio; 1284 uint8_t FanOffGpio; 1285 uint8_t GfxVrPowerStageOffGpio; 1286 1287 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1288 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1289 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1290 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1291 1292 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1293 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1294 1295 // LED Display Settings 1296 uint8_t LedPin0; // GPIO number for LedPin[0] 1297 uint8_t LedPin1; // GPIO number for LedPin[1] 1298 uint8_t LedPin2; // GPIO number for LedPin[2] 1299 uint8_t LedEnableMask; 1300 1301 uint8_t LedPcie; // GPIO number for PCIE results 1302 uint8_t LedError; // GPIO number for Error Cases 1303 1304 // SECTION: Clock Spread Spectrum 1305 1306 // UCLK Spread Spectrum 1307 uint16_t UclkSpreadPadding; 1308 uint16_t UclkSpreadFreq; // kHz 1309 1310 // UCLK Spread Spectrum 1311 uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1312 1313 // FCLK Spread Spectrum 1314 uint8_t FclkSpreadPadding; 1315 uint8_t FclkSpreadPercent; // Q4.4 1316 uint16_t FclkSpreadFreq; // kHz 1317 1318 // Section: Memory Config 1319 uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1320 uint8_t PaddingMem1[3]; 1321 1322 // Section: Total Board Power 1323 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 1324 uint16_t BoardPowerPadding; 1325 1326 // SECTION: UMC feature flags 1327 uint8_t HsrEnabled; 1328 uint8_t VddqOffEnabled; 1329 uint8_t PaddingUmcFlags[2]; 1330 1331 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1332 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1333 1334 uint8_t FuseWritePowerMuxPresent; 1335 uint8_t FuseWritePadding[3]; 1336 1337 // SECTION: Board Reserved 1338 uint32_t BoardSpare[63]; 1339 1340 // SECTION: Structure Padding 1341 1342 // Padding for MMHUB - do not modify this 1343 uint32_t MmHubPadding[8]; 1344 } BoardTable_t; 1345 1346 typedef struct { 1347 SkuTable_t SkuTable; 1348 BoardTable_t BoardTable; 1349 } PPTable_t; 1350 1351 typedef struct { 1352 // Time constant parameters for clock averages in ms 1353 uint16_t GfxclkAverageLpfTau; 1354 uint16_t FclkAverageLpfTau; 1355 uint16_t UclkAverageLpfTau; 1356 uint16_t GfxActivityLpfTau; 1357 uint16_t UclkActivityLpfTau; 1358 uint16_t SocketPowerLpfTau; 1359 uint16_t VcnClkAverageLpfTau; 1360 uint16_t VcnUsageAverageLpfTau; 1361 } DriverSmuConfig_t; 1362 1363 typedef struct { 1364 DriverSmuConfig_t DriverSmuConfig; 1365 1366 uint32_t Spare[8]; 1367 // Padding - ignore 1368 uint32_t MmHubPadding[8]; // SMU internal use 1369 } DriverSmuConfigExternal_t; 1370 1371 1372 typedef struct { 1373 1374 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1375 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1376 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1377 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1378 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1379 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1380 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1381 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1382 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1383 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1384 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1385 1386 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1387 1388 uint16_t Padding; 1389 1390 uint32_t Spare[32]; 1391 1392 // Padding - ignore 1393 uint32_t MmHubPadding[8]; // SMU internal use 1394 1395 } DriverInfoTable_t; 1396 1397 typedef struct { 1398 uint32_t CurrClock[PPCLK_COUNT]; 1399 1400 uint16_t AverageGfxclkFrequencyTarget; 1401 uint16_t AverageGfxclkFrequencyPreDs; 1402 uint16_t AverageGfxclkFrequencyPostDs; 1403 uint16_t AverageFclkFrequencyPreDs; 1404 uint16_t AverageFclkFrequencyPostDs; 1405 uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1406 uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1407 uint16_t AverageVclk0Frequency ; 1408 uint16_t AverageDclk0Frequency ; 1409 uint16_t AverageVclk1Frequency ; 1410 uint16_t AverageDclk1Frequency ; 1411 uint16_t PCIeBusy ; 1412 uint16_t dGPU_W_MAX ; 1413 uint16_t padding ; 1414 1415 uint32_t MetricsCounter ; 1416 1417 uint16_t AvgVoltage[SVI_PLANE_COUNT]; 1418 uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1419 1420 uint16_t AverageGfxActivity ; 1421 uint16_t AverageUclkActivity ; 1422 uint16_t Vcn0ActivityPercentage ; 1423 uint16_t Vcn1ActivityPercentage ; 1424 1425 uint32_t EnergyAccumulator; 1426 uint16_t AverageSocketPower ; 1427 uint16_t AvgTemperature[TEMP_COUNT]; 1428 1429 uint8_t PcieRate ; 1430 uint8_t PcieWidth ; 1431 1432 uint8_t AvgFanPwm; 1433 uint8_t Padding[1]; 1434 uint16_t AvgFanRpm; 1435 1436 1437 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1438 1439 //metrics for D3hot entry/exit and driver ARM msgs 1440 uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1441 uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1442 uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1443 1444 uint16_t ApuSTAPMSmartShiftLimit; 1445 uint16_t ApuSTAPMLimit; 1446 uint16_t AvgApuSocketPower; 1447 1448 uint16_t AverageUclkActivity_MAX; 1449 1450 uint32_t PublicSerialNumberLower; 1451 uint32_t PublicSerialNumberUpper; 1452 } SmuMetrics_t; 1453 1454 typedef struct { 1455 SmuMetrics_t SmuMetrics; 1456 uint32_t Spare[30]; 1457 1458 // Padding - ignore 1459 uint32_t MmHubPadding[8]; // SMU internal use 1460 } SmuMetricsExternal_t; 1461 1462 typedef struct { 1463 uint8_t WmSetting; 1464 uint8_t Flags; 1465 uint8_t Padding[2]; 1466 1467 } WatermarkRowGeneric_t; 1468 1469 #define NUM_WM_RANGES 4 1470 1471 typedef enum { 1472 WATERMARKS_CLOCK_RANGE = 0, 1473 WATERMARKS_DUMMY_PSTATE, 1474 WATERMARKS_MALL, 1475 WATERMARKS_COUNT, 1476 } WATERMARKS_FLAGS_e; 1477 1478 typedef struct { 1479 // Watermarks 1480 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1481 } Watermarks_t; 1482 1483 typedef struct { 1484 Watermarks_t Watermarks; 1485 uint32_t Spare[16]; 1486 1487 uint32_t MmHubPadding[8]; // SMU internal use 1488 } WatermarksExternal_t; 1489 1490 typedef struct { 1491 uint16_t avgPsmCount[36]; 1492 uint16_t minPsmCount[36]; 1493 float avgPsmVoltage[36]; 1494 float minPsmVoltage[36]; 1495 } AvfsDebugTable_t; 1496 1497 typedef struct { 1498 AvfsDebugTable_t AvfsDebugTable; 1499 1500 uint32_t MmHubPadding[8]; // SMU internal use 1501 } AvfsDebugTableExternal_t; 1502 1503 1504 typedef struct { 1505 uint8_t Gfx_ActiveHystLimit; 1506 uint8_t Gfx_IdleHystLimit; 1507 uint8_t Gfx_FPS; 1508 uint8_t Gfx_MinActiveFreqType; 1509 uint8_t Gfx_BoosterFreqType; 1510 uint8_t PaddingGfx; 1511 uint16_t Gfx_MinActiveFreq; // MHz 1512 uint16_t Gfx_BoosterFreq; // MHz 1513 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1514 uint32_t Gfx_PD_Data_limit_a; // Q16 1515 uint32_t Gfx_PD_Data_limit_b; // Q16 1516 uint32_t Gfx_PD_Data_limit_c; // Q16 1517 uint32_t Gfx_PD_Data_error_coeff; // Q16 1518 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1519 1520 uint8_t Fclk_ActiveHystLimit; 1521 uint8_t Fclk_IdleHystLimit; 1522 uint8_t Fclk_FPS; 1523 uint8_t Fclk_MinActiveFreqType; 1524 uint8_t Fclk_BoosterFreqType; 1525 uint8_t PaddingFclk; 1526 uint16_t Fclk_MinActiveFreq; // MHz 1527 uint16_t Fclk_BoosterFreq; // MHz 1528 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1529 uint32_t Fclk_PD_Data_limit_a; // Q16 1530 uint32_t Fclk_PD_Data_limit_b; // Q16 1531 uint32_t Fclk_PD_Data_limit_c; // Q16 1532 uint32_t Fclk_PD_Data_error_coeff; // Q16 1533 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1534 1535 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1536 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1537 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1538 uint16_t Mem_Fps; 1539 uint8_t padding[2]; 1540 1541 } DpmActivityMonitorCoeffInt_t; 1542 1543 1544 typedef struct { 1545 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1546 uint32_t MmHubPadding[8]; // SMU internal use 1547 } DpmActivityMonitorCoeffIntExternal_t; 1548 1549 1550 1551 // Workload bits 1552 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1553 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1554 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1555 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1556 #define WORKLOAD_PPLIB_VR_BIT 4 1557 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1558 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1559 #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1560 #define WORKLOAD_PPLIB_COUNT 8 1561 1562 1563 // These defines are used with the following messages: 1564 // SMC_MSG_TransferTableDram2Smu 1565 // SMC_MSG_TransferTableSmu2Dram 1566 1567 // Table transfer status 1568 #define TABLE_TRANSFER_OK 0x0 1569 #define TABLE_TRANSFER_FAILED 0xFF 1570 #define TABLE_TRANSFER_PENDING 0xAB 1571 1572 // Table types 1573 #define TABLE_PPTABLE 0 1574 #define TABLE_COMBO_PPTABLE 1 1575 #define TABLE_WATERMARKS 2 1576 #define TABLE_AVFS_PSM_DEBUG 3 1577 #define TABLE_PMSTATUSLOG 4 1578 #define TABLE_SMU_METRICS 5 1579 #define TABLE_DRIVER_SMU_CONFIG 6 1580 #define TABLE_ACTIVITY_MONITOR_COEFF 7 1581 #define TABLE_OVERDRIVE 8 1582 #define TABLE_I2C_COMMANDS 9 1583 #define TABLE_DRIVER_INFO 10 1584 #define TABLE_ECCINFO 11 1585 #define TABLE_COUNT 12 1586 1587 //IH Interupt ID 1588 #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1589 #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1590 #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1591 #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1592 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1593 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1594 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1595 1596 #endif 1597