1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SMU13_DRIVER_IF_SMU_13_0_7_H 24 #define SMU13_DRIVER_IF_SMU_13_0_7_H 25 26 // *** IMPORTANT *** 27 // PMFW TEAM: Always increment the interface version on any change to this file 28 #define SMU13_DRIVER_IF_VERSION 0x35 29 30 //Increment this version if SkuTable_t or BoardTable_t change 31 #define PPTABLE_VERSION 0x27 32 33 #define NUM_GFXCLK_DPM_LEVELS 16 34 #define NUM_SOCCLK_DPM_LEVELS 8 35 #define NUM_MP0CLK_DPM_LEVELS 2 36 #define NUM_DCLK_DPM_LEVELS 8 37 #define NUM_VCLK_DPM_LEVELS 8 38 #define NUM_DISPCLK_DPM_LEVELS 8 39 #define NUM_DPPCLK_DPM_LEVELS 8 40 #define NUM_DPREFCLK_DPM_LEVELS 8 41 #define NUM_DCFCLK_DPM_LEVELS 8 42 #define NUM_DTBCLK_DPM_LEVELS 8 43 #define NUM_UCLK_DPM_LEVELS 4 44 #define NUM_LINK_LEVELS 3 45 #define NUM_FCLK_DPM_LEVELS 8 46 #define NUM_OD_FAN_MAX_POINTS 6 47 48 // Feature Control Defines 49 #define FEATURE_FW_DATA_READ_BIT 0 50 #define FEATURE_DPM_GFXCLK_BIT 1 51 #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 52 #define FEATURE_DPM_UCLK_BIT 3 53 #define FEATURE_DPM_FCLK_BIT 4 54 #define FEATURE_DPM_SOCCLK_BIT 5 55 #define FEATURE_DPM_MP0CLK_BIT 6 56 #define FEATURE_DPM_LINK_BIT 7 57 #define FEATURE_DPM_DCN_BIT 8 58 #define FEATURE_VMEMP_SCALING_BIT 9 59 #define FEATURE_VDDIO_MEM_SCALING_BIT 10 60 #define FEATURE_DS_GFXCLK_BIT 11 61 #define FEATURE_DS_SOCCLK_BIT 12 62 #define FEATURE_DS_FCLK_BIT 13 63 #define FEATURE_DS_LCLK_BIT 14 64 #define FEATURE_DS_DCFCLK_BIT 15 65 #define FEATURE_DS_UCLK_BIT 16 66 #define FEATURE_GFX_ULV_BIT 17 67 #define FEATURE_FW_DSTATE_BIT 18 68 #define FEATURE_GFXOFF_BIT 19 69 #define FEATURE_BACO_BIT 20 70 #define FEATURE_MM_DPM_BIT 21 71 #define FEATURE_SOC_MPCLK_DS_BIT 22 72 #define FEATURE_BACO_MPCLK_DS_BIT 23 73 #define FEATURE_THROTTLERS_BIT 24 74 #define FEATURE_SMARTSHIFT_BIT 25 75 #define FEATURE_GTHR_BIT 26 76 #define FEATURE_ACDC_BIT 27 77 #define FEATURE_VR0HOT_BIT 28 78 #define FEATURE_FW_CTF_BIT 29 79 #define FEATURE_FAN_CONTROL_BIT 30 80 #define FEATURE_GFX_DCS_BIT 31 81 #define FEATURE_GFX_READ_MARGIN_BIT 32 82 #define FEATURE_LED_DISPLAY_BIT 33 83 #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 84 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 85 #define FEATURE_OPTIMIZED_VMIN_BIT 36 86 #define FEATURE_GFX_IMU_BIT 37 87 #define FEATURE_BOOT_TIME_CAL_BIT 38 88 #define FEATURE_GFX_PCC_DFLL_BIT 39 89 #define FEATURE_SOC_CG_BIT 40 90 #define FEATURE_DF_CSTATE_BIT 41 91 #define FEATURE_GFX_EDC_BIT 42 92 #define FEATURE_BOOT_POWER_OPT_BIT 43 93 #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 94 #define FEATURE_DS_VCN_BIT 45 95 #define FEATURE_BACO_CG_BIT 46 96 #define FEATURE_MEM_TEMP_READ_BIT 47 97 #define FEATURE_ATHUB_MMHUB_PG_BIT 48 98 #define FEATURE_SOC_PCC_BIT 49 99 #define FEATURE_EDC_PWRBRK_BIT 50 100 #define FEATURE_SPARE_51_BIT 51 101 #define FEATURE_SPARE_52_BIT 52 102 #define FEATURE_SPARE_53_BIT 53 103 #define FEATURE_SPARE_54_BIT 54 104 #define FEATURE_SPARE_55_BIT 55 105 #define FEATURE_SPARE_56_BIT 56 106 #define FEATURE_SPARE_57_BIT 57 107 #define FEATURE_SPARE_58_BIT 58 108 #define FEATURE_SPARE_59_BIT 59 109 #define FEATURE_SPARE_60_BIT 60 110 #define FEATURE_SPARE_61_BIT 61 111 #define FEATURE_SPARE_62_BIT 62 112 #define FEATURE_SPARE_63_BIT 63 113 #define NUM_FEATURES 64 114 115 #define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL 116 #define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \ 117 (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 118 (1 << FEATURE_DPM_UCLK_BIT) | \ 119 (1 << FEATURE_DPM_FCLK_BIT) | \ 120 (1 << FEATURE_DPM_SOCCLK_BIT) | \ 121 (1 << FEATURE_DPM_MP0CLK_BIT) | \ 122 (1 << FEATURE_DPM_LINK_BIT) | \ 123 (1 << FEATURE_DPM_DCN_BIT) | \ 124 (1 << FEATURE_DS_GFXCLK_BIT) | \ 125 (1 << FEATURE_DS_SOCCLK_BIT) | \ 126 (1 << FEATURE_DS_FCLK_BIT) | \ 127 (1 << FEATURE_DS_LCLK_BIT) | \ 128 (1 << FEATURE_DS_DCFCLK_BIT) | \ 129 (1 << FEATURE_DS_UCLK_BIT) | \ 130 (1ULL << FEATURE_DS_VCN_BIT)) 131 132 //For use with feature control messages 133 typedef enum { 134 FEATURE_PWR_ALL, 135 FEATURE_PWR_S5, 136 FEATURE_PWR_BACO, 137 FEATURE_PWR_SOC, 138 FEATURE_PWR_GFX, 139 FEATURE_PWR_DOMAIN_COUNT, 140 } FEATURE_PWR_DOMAIN_e; 141 142 143 // Debug Overrides Bitmask 144 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 145 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 146 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 147 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 148 #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 149 #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 150 #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 151 #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 152 #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 153 #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 154 #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 155 #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 156 #define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000 157 158 // VR Mapping Bit Defines 159 #define VR_MAPPING_VR_SELECT_MASK 0x01 160 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 161 162 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 163 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 164 165 // PSI Bit Defines 166 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 167 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 168 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 169 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 170 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 171 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 172 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 173 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 174 175 typedef enum { 176 SVI_PSI_0, // Full phase count (default) 177 SVI_PSI_1, // Phase count 1st level 178 SVI_PSI_2, // Phase count 2nd level 179 SVI_PSI_3, // Single phase operation + active diode emulation 180 SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 181 SVI_PSI_5, // Reserved 182 SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 183 SVI_PSI_7, // Automated phase shedding and diode emulation 184 } SVI_PSI_e; 185 186 // Throttler Control/Status Bits 187 #define THROTTLER_TEMP_EDGE_BIT 0 188 #define THROTTLER_TEMP_HOTSPOT_BIT 1 189 #define THROTTLER_TEMP_HOTSPOT_G_BIT 2 190 #define THROTTLER_TEMP_HOTSPOT_M_BIT 3 191 #define THROTTLER_TEMP_MEM_BIT 4 192 #define THROTTLER_TEMP_VR_GFX_BIT 5 193 #define THROTTLER_TEMP_VR_MEM0_BIT 6 194 #define THROTTLER_TEMP_VR_MEM1_BIT 7 195 #define THROTTLER_TEMP_VR_SOC_BIT 8 196 #define THROTTLER_TEMP_VR_U_BIT 9 197 #define THROTTLER_TEMP_LIQUID0_BIT 10 198 #define THROTTLER_TEMP_LIQUID1_BIT 11 199 #define THROTTLER_TEMP_PLX_BIT 12 200 #define THROTTLER_TDC_GFX_BIT 13 201 #define THROTTLER_TDC_SOC_BIT 14 202 #define THROTTLER_TDC_U_BIT 15 203 #define THROTTLER_PPT0_BIT 16 204 #define THROTTLER_PPT1_BIT 17 205 #define THROTTLER_PPT2_BIT 18 206 #define THROTTLER_PPT3_BIT 19 207 #define THROTTLER_FIT_BIT 20 208 #define THROTTLER_GFX_APCC_PLUS_BIT 21 209 #define THROTTLER_COUNT 22 210 211 // FW DState Features Control Bits 212 #define FW_DSTATE_SOC_ULV_BIT 0 213 #define FW_DSTATE_G6_HSR_BIT 1 214 #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 215 #define FW_DSTATE_SMN_DS_BIT 3 216 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 217 #define FW_DSTATE_SOC_LIV_MIN_BIT 5 218 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 219 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 220 #define FW_DSTATE_MALL_ALLOC_BIT 8 221 #define FW_DSTATE_MEM_PSI_BIT 9 222 #define FW_DSTATE_HSR_NON_STROBE_BIT 10 223 #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 224 #define FW_DSTATE_U_ULV_BIT 12 225 #define FW_DSTATE_MALL_FLUSH_BIT 13 226 #define FW_DSTATE_SOC_PSI_BIT 14 227 #define FW_DSTATE_U_PSI_BIT 15 228 #define FW_DSTATE_UCP_DS_BIT 16 229 #define FW_DSTATE_CSRCLK_DS_BIT 17 230 #define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 231 #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 232 #define FW_DSTATE_CLDO_PRG_BIT 20 233 #define FW_DSTATE_DF_PLL_PWRDN_BIT 21 234 #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 235 #define FW_DSTATE_GFX_PSI6_BIT 23 236 #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 237 238 //LED Display Mask & Control Bits 239 #define LED_DISPLAY_GFX_DPM_BIT 0 240 #define LED_DISPLAY_PCIE_BIT 1 241 #define LED_DISPLAY_ERROR_BIT 2 242 243 244 #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 245 #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 246 #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 247 248 typedef enum { 249 SMARTSHIFT_VERSION_1, 250 SMARTSHIFT_VERSION_2, 251 SMARTSHIFT_VERSION_3, 252 } SMARTSHIFT_VERSION_e; 253 254 typedef enum { 255 FOPT_CALC_AC_CALC_DC, 256 FOPT_PPTABLE_AC_CALC_DC, 257 FOPT_CALC_AC_PPTABLE_DC, 258 FOPT_PPTABLE_AC_PPTABLE_DC, 259 } FOPT_CALC_e; 260 261 typedef enum { 262 DRAM_BIT_WIDTH_DISABLED = 0, 263 DRAM_BIT_WIDTH_X_8 = 8, 264 DRAM_BIT_WIDTH_X_16 = 16, 265 DRAM_BIT_WIDTH_X_32 = 32, 266 DRAM_BIT_WIDTH_X_64 = 64, 267 DRAM_BIT_WIDTH_X_128 = 128, 268 DRAM_BIT_WIDTH_COUNT, 269 } DRAM_BIT_WIDTH_TYPE_e; 270 271 //I2C Interface 272 #define NUM_I2C_CONTROLLERS 8 273 274 #define I2C_CONTROLLER_ENABLED 1 275 #define I2C_CONTROLLER_DISABLED 0 276 277 #define MAX_SW_I2C_COMMANDS 24 278 279 typedef enum { 280 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 281 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 282 I2C_CONTROLLER_PORT_COUNT, 283 } I2cControllerPort_e; 284 285 typedef enum { 286 I2C_CONTROLLER_NAME_VR_GFX = 0, 287 I2C_CONTROLLER_NAME_VR_SOC, 288 I2C_CONTROLLER_NAME_VR_VMEMP, 289 I2C_CONTROLLER_NAME_VR_VDDIO, 290 I2C_CONTROLLER_NAME_LIQUID0, 291 I2C_CONTROLLER_NAME_LIQUID1, 292 I2C_CONTROLLER_NAME_PLX, 293 I2C_CONTROLLER_NAME_FAN_INTAKE, 294 I2C_CONTROLLER_NAME_COUNT, 295 } I2cControllerName_e; 296 297 typedef enum { 298 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 299 I2C_CONTROLLER_THROTTLER_VR_GFX, 300 I2C_CONTROLLER_THROTTLER_VR_SOC, 301 I2C_CONTROLLER_THROTTLER_VR_VMEMP, 302 I2C_CONTROLLER_THROTTLER_VR_VDDIO, 303 I2C_CONTROLLER_THROTTLER_LIQUID0, 304 I2C_CONTROLLER_THROTTLER_LIQUID1, 305 I2C_CONTROLLER_THROTTLER_PLX, 306 I2C_CONTROLLER_THROTTLER_FAN_INTAKE, 307 I2C_CONTROLLER_THROTTLER_INA3221, 308 I2C_CONTROLLER_THROTTLER_COUNT, 309 } I2cControllerThrottler_e; 310 311 typedef enum { 312 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 313 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 314 I2C_CONTROLLER_PROTOCOL_TMP_MAX31875, 315 I2C_CONTROLLER_PROTOCOL_INA3221, 316 I2C_CONTROLLER_PROTOCOL_TMP_MAX6604, 317 I2C_CONTROLLER_PROTOCOL_COUNT, 318 } I2cControllerProtocol_e; 319 320 typedef struct { 321 uint8_t Enabled; 322 uint8_t Speed; 323 uint8_t SlaveAddress; 324 uint8_t ControllerPort; 325 uint8_t ControllerName; 326 uint8_t ThermalThrotter; 327 uint8_t I2cProtocol; 328 uint8_t PaddingConfig; 329 } I2cControllerConfig_t; 330 331 typedef enum { 332 I2C_PORT_SVD_SCL = 0, 333 I2C_PORT_GPIO, 334 } I2cPort_e; 335 336 typedef enum { 337 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 338 I2C_SPEED_FAST_100K, //100 Kbits/s 339 I2C_SPEED_FAST_400K, //400 Kbits/s 340 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 341 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 342 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 343 I2C_SPEED_COUNT, 344 } I2cSpeed_e; 345 346 typedef enum { 347 I2C_CMD_READ = 0, 348 I2C_CMD_WRITE, 349 I2C_CMD_COUNT, 350 } I2cCmdType_e; 351 352 #define CMDCONFIG_STOP_BIT 0 353 #define CMDCONFIG_RESTART_BIT 1 354 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 355 356 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 357 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 358 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 359 360 typedef struct { 361 uint8_t ReadWriteData; //Return data for read. Data to send for write 362 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 363 } SwI2cCmd_t; //SW I2C Command Table 364 365 typedef struct { 366 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 367 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 368 uint8_t SlaveAddress; //Slave address of device 369 uint8_t NumCmds; //Number of commands 370 371 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 372 } SwI2cRequest_t; // SW I2C Request Table 373 374 typedef struct { 375 SwI2cRequest_t SwI2cRequest; 376 377 uint32_t Spare[8]; 378 uint32_t MmHubPadding[8]; // SMU internal use 379 } SwI2cRequestExternal_t; 380 381 typedef struct { 382 uint64_t mca_umc_status; 383 uint64_t mca_umc_addr; 384 385 uint16_t ce_count_lo_chip; 386 uint16_t ce_count_hi_chip; 387 388 uint32_t eccPadding; 389 } EccInfo_t; 390 391 typedef struct { 392 EccInfo_t EccInfo[24]; 393 } EccInfoTable_t; 394 395 //D3HOT sequences 396 typedef enum { 397 BACO_SEQUENCE, 398 MSR_SEQUENCE, 399 BAMACO_SEQUENCE, 400 ULPS_SEQUENCE, 401 D3HOT_SEQUENCE_COUNT, 402 } D3HOTSequence_e; 403 404 //This is aligned with RSMU PGFSM Register Mapping 405 typedef enum { 406 PG_DYNAMIC_MODE = 0, 407 PG_STATIC_MODE, 408 } PowerGatingMode_e; 409 410 //This is aligned with RSMU PGFSM Register Mapping 411 typedef enum { 412 PG_POWER_DOWN = 0, 413 PG_POWER_UP, 414 } PowerGatingSettings_e; 415 416 typedef struct { 417 uint32_t a; // store in IEEE float format in this variable 418 uint32_t b; // store in IEEE float format in this variable 419 uint32_t c; // store in IEEE float format in this variable 420 } QuadraticInt_t; 421 422 typedef struct { 423 uint32_t m; // store in IEEE float format in this variable 424 uint32_t b; // store in IEEE float format in this variable 425 } LinearInt_t; 426 427 typedef struct { 428 uint32_t a; // store in IEEE float format in this variable 429 uint32_t b; // store in IEEE float format in this variable 430 uint32_t c; // store in IEEE float format in this variable 431 } DroopInt_t; 432 433 typedef enum { 434 DCS_ARCH_DISABLED, 435 DCS_ARCH_FADCS, 436 DCS_ARCH_ASYNC, 437 } DCS_ARCH_e; 438 439 //Only Clks that have DPM descriptors are listed here 440 typedef enum { 441 PPCLK_GFXCLK = 0, 442 PPCLK_SOCCLK, 443 PPCLK_UCLK, 444 PPCLK_FCLK, 445 PPCLK_DCLK_0, 446 PPCLK_VCLK_0, 447 PPCLK_DCLK_1, 448 PPCLK_VCLK_1, 449 PPCLK_DISPCLK, 450 PPCLK_DPPCLK, 451 PPCLK_DPREFCLK, 452 PPCLK_DCFCLK, 453 PPCLK_DTBCLK, 454 PPCLK_COUNT, 455 } PPCLK_e; 456 457 typedef enum { 458 VOLTAGE_MODE_PPTABLE = 0, 459 VOLTAGE_MODE_FUSES, 460 VOLTAGE_MODE_COUNT, 461 } VOLTAGE_MODE_e; 462 463 464 typedef enum { 465 AVFS_VOLTAGE_GFX = 0, 466 AVFS_VOLTAGE_SOC, 467 AVFS_VOLTAGE_COUNT, 468 } AVFS_VOLTAGE_TYPE_e; 469 470 typedef enum { 471 AVFS_TEMP_COLD = 0, 472 AVFS_TEMP_HOT, 473 AVFS_TEMP_COUNT, 474 } AVFS_TEMP_e; 475 476 typedef enum { 477 AVFS_D_G, 478 AVFS_D_M_B, 479 AVFS_D_M_S, 480 AVFS_D_COUNT, 481 } AVFS_D_e; 482 483 typedef enum { 484 UCLK_DIV_BY_1 = 0, 485 UCLK_DIV_BY_2, 486 UCLK_DIV_BY_4, 487 UCLK_DIV_BY_8, 488 } UCLK_DIV_e; 489 490 typedef enum { 491 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 492 GPIO_INT_POLARITY_ACTIVE_HIGH, 493 } GpioIntPolarity_e; 494 495 typedef enum { 496 PWR_CONFIG_TDP = 0, 497 PWR_CONFIG_TGP, 498 PWR_CONFIG_TCP_ESTIMATED, 499 PWR_CONFIG_TCP_MEASURED, 500 } PwrConfig_e; 501 502 typedef struct { 503 uint8_t Padding; 504 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 505 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 506 uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 507 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 508 uint32_t Padding3[3]; 509 uint16_t Padding4; 510 uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 511 uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 512 uint16_t Padding2; 513 } DpmDescriptor_t; 514 515 typedef enum { 516 PPT_THROTTLER_PPT0, 517 PPT_THROTTLER_PPT1, 518 PPT_THROTTLER_PPT2, 519 PPT_THROTTLER_PPT3, 520 PPT_THROTTLER_COUNT 521 } PPT_THROTTLER_e; 522 523 typedef enum { 524 TEMP_EDGE, 525 TEMP_HOTSPOT, 526 TEMP_HOTSPOT_G, 527 TEMP_HOTSPOT_M, 528 TEMP_MEM, 529 TEMP_VR_GFX, 530 TEMP_VR_MEM0, 531 TEMP_VR_MEM1, 532 TEMP_VR_SOC, 533 TEMP_VR_U, 534 TEMP_LIQUID0, 535 TEMP_LIQUID1, 536 TEMP_PLX, 537 TEMP_COUNT, 538 } TEMP_e; 539 540 typedef enum { 541 TDC_THROTTLER_GFX, 542 TDC_THROTTLER_SOC, 543 TDC_THROTTLER_U, 544 TDC_THROTTLER_COUNT 545 } TDC_THROTTLER_e; 546 547 typedef enum { 548 SVI_PLANE_GFX, 549 SVI_PLANE_SOC, 550 SVI_PLANE_VMEMP, 551 SVI_PLANE_VDDIO_MEM, 552 SVI_PLANE_U, 553 SVI_PLANE_COUNT, 554 } SVI_PLANE_e; 555 556 typedef enum { 557 PMFW_VOLT_PLANE_GFX, 558 PMFW_VOLT_PLANE_SOC, 559 PMFW_VOLT_PLANE_COUNT 560 } PMFW_VOLT_PLANE_e; 561 562 typedef enum { 563 CUSTOMER_VARIANT_ROW, 564 CUSTOMER_VARIANT_FALCON, 565 CUSTOMER_VARIANT_COUNT, 566 } CUSTOMER_VARIANT_e; 567 568 typedef enum { 569 POWER_SOURCE_AC, 570 POWER_SOURCE_DC, 571 POWER_SOURCE_COUNT, 572 } POWER_SOURCE_e; 573 574 typedef enum { 575 MEM_VENDOR_SAMSUNG, 576 MEM_VENDOR_INFINEON, 577 MEM_VENDOR_ELPIDA, 578 MEM_VENDOR_ETRON, 579 MEM_VENDOR_NANYA, 580 MEM_VENDOR_HYNIX, 581 MEM_VENDOR_MOSEL, 582 MEM_VENDOR_WINBOND, 583 MEM_VENDOR_ESMT, 584 MEM_VENDOR_PLACEHOLDER0, 585 MEM_VENDOR_PLACEHOLDER1, 586 MEM_VENDOR_PLACEHOLDER2, 587 MEM_VENDOR_PLACEHOLDER3, 588 MEM_VENDOR_PLACEHOLDER4, 589 MEM_VENDOR_PLACEHOLDER5, 590 MEM_VENDOR_MICRON, 591 MEM_VENDOR_COUNT, 592 } MEM_VENDOR_e; 593 594 typedef enum { 595 PP_GRTAVFS_HW_CPO_CTL_ZONE0, 596 PP_GRTAVFS_HW_CPO_CTL_ZONE1, 597 PP_GRTAVFS_HW_CPO_CTL_ZONE2, 598 PP_GRTAVFS_HW_CPO_CTL_ZONE3, 599 PP_GRTAVFS_HW_CPO_CTL_ZONE4, 600 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 601 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 602 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 603 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 604 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 605 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 606 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 607 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 608 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 609 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 610 PP_GRTAVFS_HW_ZONE0_VF, 611 PP_GRTAVFS_HW_ZONE1_VF1, 612 PP_GRTAVFS_HW_ZONE2_VF2, 613 PP_GRTAVFS_HW_ZONE3_VF3, 614 PP_GRTAVFS_HW_VOLTAGE_GB, 615 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 616 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 617 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 618 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 619 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 620 PP_GRTAVFS_HW_RESERVED_0, 621 PP_GRTAVFS_HW_RESERVED_1, 622 PP_GRTAVFS_HW_RESERVED_2, 623 PP_GRTAVFS_HW_RESERVED_3, 624 PP_GRTAVFS_HW_RESERVED_4, 625 PP_GRTAVFS_HW_RESERVED_5, 626 PP_GRTAVFS_HW_RESERVED_6, 627 PP_GRTAVFS_HW_FUSE_COUNT, 628 } PP_GRTAVFS_HW_FUSE_e; 629 630 typedef enum { 631 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 632 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 633 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 634 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 635 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 636 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 637 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 638 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 639 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 640 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 641 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 642 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 643 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 644 PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 645 } PP_GRTAVFS_FW_COMMON_FUSE_e; 646 647 typedef enum { 648 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 649 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 650 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 651 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 652 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 653 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 654 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 655 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 656 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 657 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 658 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 659 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 660 PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 661 PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 662 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 663 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 664 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 665 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 666 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 667 PP_GRTAVFS_FW_SEP_FUSE_COUNT, 668 } PP_GRTAVFS_FW_SEP_FUSE_e; 669 670 #define PP_NUM_RTAVFS_PWL_ZONES 5 671 672 673 674 // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 675 // Slope Q1.7, Offset Q1.2 676 typedef struct { 677 int8_t Offset; // in Amps 678 uint8_t Padding; 679 uint16_t MaxCurrent; // in Amps 680 } SviTelemetryScale_t; 681 682 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 683 684 685 #define PP_OD_FEATURE_GFX_VF_CURVE_BIT 0 686 #define PP_OD_FEATURE_VMAX_BIT 1 687 #define PP_OD_FEATURE_PPT_BIT 2 688 #define PP_OD_FEATURE_FAN_CURVE_BIT 3 689 #define PP_OD_FEATURE_FREQ_DETER_BIT 4 690 #define PP_OD_FEATURE_FULL_CTRL_BIT 5 691 #define PP_OD_FEATURE_TDC_BIT 6 692 #define PP_OD_FEATURE_GFXCLK_BIT 7 693 #define PP_OD_FEATURE_UCLK_BIT 8 694 #define PP_OD_FEATURE_ZERO_FAN_BIT 9 695 #define PP_OD_FEATURE_TEMPERATURE_BIT 10 696 #define PP_OD_FEATURE_POWER_FEATURE_CTRL_BIT 11 697 #define PP_OD_FEATURE_ASIC_TDC_BIT 12 698 #define PP_OD_FEATURE_COUNT 13 699 700 typedef enum { 701 PP_OD_POWER_FEATURE_ALWAYS_ENABLED, 702 PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING, 703 PP_OD_POWER_FEATURE_ALWAYS_DISABLED, 704 } PP_OD_POWER_FEATURE_e; 705 706 typedef enum { 707 FAN_MODE_AUTO = 0, 708 FAN_MODE_MANUAL_LINEAR, 709 } FanMode_e; 710 711 typedef struct { 712 uint32_t FeatureCtrlMask; 713 714 //Voltage control 715 int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 716 uint16_t VddGfxVmax; // in mV 717 718 uint8_t IdlePwrSavingFeaturesCtrl; 719 uint8_t RuntimePwrSavingFeaturesCtrl; 720 721 //Frequency changes 722 int16_t GfxclkFmin; // MHz 723 int16_t GfxclkFmax; // MHz 724 uint16_t UclkFmin; // MHz 725 uint16_t UclkFmax; // MHz 726 727 //PPT 728 int16_t Ppt; // % 729 int16_t Tdc; 730 731 //Fan control 732 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 733 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 734 uint16_t FanMinimumPwm; 735 uint16_t AcousticTargetRpmThreshold; 736 uint16_t AcousticLimitRpmThreshold; 737 uint16_t FanTargetTemperature; // Degree Celcius 738 uint8_t FanZeroRpmEnable; 739 uint8_t FanZeroRpmStopTemp; 740 uint8_t FanMode; 741 uint8_t MaxOpTemp; 742 uint8_t Padding[4]; 743 744 uint16_t GfxVoltageFullCtrlMode; 745 uint16_t GfxclkFullCtrlMode; 746 uint16_t UclkFullCtrlMode; 747 int16_t AsicTdc; 748 749 uint32_t Spare[10]; 750 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 751 } OverDriveTable_t; 752 753 typedef struct { 754 OverDriveTable_t OverDriveTable; 755 756 } OverDriveTableExternal_t; 757 758 typedef struct { 759 uint32_t FeatureCtrlMask; 760 761 int16_t VoltageOffsetPerZoneBoundary; 762 uint16_t VddGfxVmax; // in mV 763 764 uint8_t IdlePwrSavingFeaturesCtrl; 765 uint8_t RuntimePwrSavingFeaturesCtrl; 766 767 int16_t GfxclkFmin; // MHz 768 int16_t GfxclkFmax; // MHz 769 uint16_t UclkFmin; // MHz 770 uint16_t UclkFmax; // MHz 771 772 //PPT 773 int16_t Ppt; // % 774 int16_t Tdc; 775 776 uint8_t FanLinearPwmPoints; 777 uint8_t FanLinearTempPoints; 778 uint16_t FanMinimumPwm; 779 uint16_t AcousticTargetRpmThreshold; 780 uint16_t AcousticLimitRpmThreshold; 781 uint16_t FanTargetTemperature; // Degree Celcius 782 uint8_t FanZeroRpmEnable; 783 uint8_t FanZeroRpmStopTemp; 784 uint8_t FanMode; 785 uint8_t MaxOpTemp; 786 uint8_t Padding[4]; 787 788 uint16_t GfxVoltageFullCtrlMode; 789 uint16_t GfxclkFullCtrlMode; 790 uint16_t UclkFullCtrlMode; 791 int16_t AsicTdc; 792 793 uint32_t Spare[10]; 794 795 } OverDriveLimits_t; 796 797 798 typedef enum { 799 BOARD_GPIO_SMUIO_0, 800 BOARD_GPIO_SMUIO_1, 801 BOARD_GPIO_SMUIO_2, 802 BOARD_GPIO_SMUIO_3, 803 BOARD_GPIO_SMUIO_4, 804 BOARD_GPIO_SMUIO_5, 805 BOARD_GPIO_SMUIO_6, 806 BOARD_GPIO_SMUIO_7, 807 BOARD_GPIO_SMUIO_8, 808 BOARD_GPIO_SMUIO_9, 809 BOARD_GPIO_SMUIO_10, 810 BOARD_GPIO_SMUIO_11, 811 BOARD_GPIO_SMUIO_12, 812 BOARD_GPIO_SMUIO_13, 813 BOARD_GPIO_SMUIO_14, 814 BOARD_GPIO_SMUIO_15, 815 BOARD_GPIO_SMUIO_16, 816 BOARD_GPIO_SMUIO_17, 817 BOARD_GPIO_SMUIO_18, 818 BOARD_GPIO_SMUIO_19, 819 BOARD_GPIO_SMUIO_20, 820 BOARD_GPIO_SMUIO_21, 821 BOARD_GPIO_SMUIO_22, 822 BOARD_GPIO_SMUIO_23, 823 BOARD_GPIO_SMUIO_24, 824 BOARD_GPIO_SMUIO_25, 825 BOARD_GPIO_SMUIO_26, 826 BOARD_GPIO_SMUIO_27, 827 BOARD_GPIO_SMUIO_28, 828 BOARD_GPIO_SMUIO_29, 829 BOARD_GPIO_SMUIO_30, 830 BOARD_GPIO_SMUIO_31, 831 MAX_BOARD_GPIO_SMUIO_NUM, 832 BOARD_GPIO_DC_GEN_A, 833 BOARD_GPIO_DC_GEN_B, 834 BOARD_GPIO_DC_GEN_C, 835 BOARD_GPIO_DC_GEN_D, 836 BOARD_GPIO_DC_GEN_E, 837 BOARD_GPIO_DC_GEN_F, 838 BOARD_GPIO_DC_GEN_G, 839 BOARD_GPIO_DC_GENLK_CLK, 840 BOARD_GPIO_DC_GENLK_VSYNC, 841 BOARD_GPIO_DC_SWAPLOCK_A, 842 BOARD_GPIO_DC_SWAPLOCK_B, 843 } BOARD_GPIO_TYPE_e; 844 845 #define INVALID_BOARD_GPIO 0xFF 846 847 848 typedef struct { 849 //PLL 0 850 uint16_t InitGfxclk_bypass; 851 uint16_t InitSocclk; 852 uint16_t InitMp0clk; 853 uint16_t InitMpioclk; 854 uint16_t InitSmnclk; 855 uint16_t InitUcpclk; 856 uint16_t InitCsrclk; 857 //PLL 1 858 859 uint16_t InitDprefclk; 860 uint16_t InitDcfclk; 861 uint16_t InitDtbclk; 862 //PLL 2 863 uint16_t InitDclk; //assume same DCLK/VCLK for both instances 864 uint16_t InitVclk; 865 // PLL 3 866 uint16_t InitUsbdfsclk; 867 uint16_t InitMp1clk; 868 uint16_t InitLclk; 869 uint16_t InitBaco400clk_bypass; 870 uint16_t InitBaco1200clk_bypass; 871 uint16_t InitBaco700clk_bypass; 872 // PLL 4 873 uint16_t InitFclk; 874 // PLL 5 875 uint16_t InitGfxclk_clkb; 876 877 //PLL 6 878 uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 879 880 uint8_t Padding[3]; 881 882 uint32_t InitVcoFreqPll0; 883 uint32_t InitVcoFreqPll1; 884 uint32_t InitVcoFreqPll2; 885 uint32_t InitVcoFreqPll3; 886 uint32_t InitVcoFreqPll4; 887 uint32_t InitVcoFreqPll5; 888 uint32_t InitVcoFreqPll6; 889 890 //encoding will change depending on SVI2/SVI3 891 uint16_t InitGfx; // In mV(Q2) , should be 0? 892 uint16_t InitSoc; // In mV(Q2) 893 uint16_t InitU; // In Mv(Q2) not applicable 894 895 uint16_t Padding2; 896 897 uint32_t Spare[8]; 898 899 } BootValues_t; 900 901 902 typedef struct { 903 uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 904 uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 905 906 uint16_t Temperature[TEMP_COUNT]; // Celsius 907 908 uint8_t PwmLimitMin; 909 uint8_t PwmLimitMax; 910 uint8_t FanTargetTemperature; 911 uint8_t Spare1[1]; 912 913 uint16_t AcousticTargetRpmThresholdMin; 914 uint16_t AcousticTargetRpmThresholdMax; 915 916 uint16_t AcousticLimitRpmThresholdMin; 917 uint16_t AcousticLimitRpmThresholdMax; 918 919 uint16_t PccLimitMin; 920 uint16_t PccLimitMax; 921 922 uint16_t FanStopTempMin; 923 uint16_t FanStopTempMax; 924 uint16_t FanStartTempMin; 925 uint16_t FanStartTempMax; 926 927 uint16_t PowerMinPpt0[POWER_SOURCE_COUNT]; 928 uint32_t Spare[11]; 929 930 } MsgLimits_t; 931 932 typedef struct { 933 uint16_t BaseClockAc; 934 uint16_t GameClockAc; 935 uint16_t BoostClockAc; 936 uint16_t BaseClockDc; 937 uint16_t GameClockDc; 938 uint16_t BoostClockDc; 939 940 uint32_t Reserved[4]; 941 } DriverReportedClocks_t; 942 943 typedef struct { 944 uint8_t DcBtcEnabled; 945 uint8_t Padding[3]; 946 947 uint16_t DcTol; // mV Q2 948 uint16_t DcBtcGb; // mV Q2 949 950 uint16_t DcBtcMin; // mV Q2 951 uint16_t DcBtcMax; // mV Q2 952 953 LinearInt_t DcBtcGbScalar; 954 955 } AvfsDcBtcParams_t; 956 957 typedef struct { 958 uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 959 uint16_t VftFMin; // in MHz 960 uint16_t VInversion; // in mV Q2 961 QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 962 QuadraticInt_t qAvfsGb; 963 QuadraticInt_t qAvfsGb2; 964 } AvfsFuseOverride_t; 965 966 typedef struct { 967 // SECTION: Version 968 969 uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 970 971 // SECTION: Feature Control 972 uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 973 974 // SECTION: Miscellaneous Configuration 975 uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 976 uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 977 uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 978 uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 979 980 // SECTION: Infrastructure Limits 981 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 982 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 983 984 uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 985 986 //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 987 //relative index 0 988 uint8_t EnableLegacyPptLimit; 989 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 990 uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 991 992 uint8_t PaddingPpt[1]; 993 994 uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 995 996 uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 997 998 uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 999 1000 uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 1001 1002 uint16_t PaddingInfra; 1003 1004 // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 1005 uint32_t FitControllerFailureRateLimit; //in IEEE float 1006 //Expected GFX Duty Cycle at Vmax. 1007 uint32_t FitControllerGfxDutyCycle; // in IEEE float 1008 //Expected SOC Duty Cycle at Vmax. 1009 uint32_t FitControllerSocDutyCycle; // in IEEE float 1010 1011 //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 1012 uint32_t FitControllerSocOffset; //in IEEE float 1013 1014 uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 1015 1016 // SECTION: Throttler settings 1017 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 1018 1019 // SECTION: FW DSTATE Settings 1020 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 1021 1022 // SECTION: Voltage Control Parameters 1023 uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 1024 1025 uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 1026 uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 1027 1028 // Voltage Limits 1029 uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 1030 uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 1031 1032 //Vmin Optimizations 1033 int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 1034 int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 1035 uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 1036 uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 1037 uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 1038 uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 1039 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 1040 uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 1041 uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 1042 1043 //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 1044 uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 1045 //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 1046 uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 1047 //Scalar coefficient of the PSM aging degradation function 1048 uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 1049 //Exponential coefficient of the PSM aging degradation function 1050 uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 1051 //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1052 uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 1053 //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1054 uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 1055 1056 uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 1057 uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 1058 1059 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1060 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1061 1062 QuadraticInt_t Vmin_droop; 1063 uint32_t SpareVmin[9]; 1064 1065 1066 //SECTION: DPM Configuration 1 1067 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1068 1069 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1070 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1071 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1072 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1073 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1074 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1075 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1076 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1077 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1078 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1079 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1080 1081 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1082 1083 // SECTION: DPM Configuration 2 1084 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1085 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1086 1087 uint8_t GfxclkSpare[2]; 1088 uint16_t GfxclkFreqCap; 1089 1090 //GFX Idle Power Settings 1091 uint16_t GfxclkFgfxoffEntry; // in Mhz 1092 uint16_t GfxclkFgfxoffExitImu; // in Mhz 1093 uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1094 uint16_t GfxclkThrottleClock; //Used primarily in DCS 1095 uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1096 uint8_t GfxIdlePadding; 1097 1098 uint8_t SmsRepairWRCKClkDivEn; 1099 uint8_t SmsRepairWRCKClkDivVal; 1100 uint8_t GfxOffEntryEarlyMGCGEn; 1101 uint8_t GfxOffEntryForceCGCGEn; 1102 uint8_t GfxOffEntryForceCGCGDelayEn; 1103 uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1104 1105 uint16_t GfxclkFreqGfxUlv; // in MHz 1106 uint8_t GfxIdlePadding2[2]; 1107 uint32_t GfxOffEntryHysteresis; //For RLC to count after it enters CGCG, and before triggers GFXOFF entry 1108 uint32_t GfxoffSpare[15]; 1109 1110 // GFX GPO 1111 uint32_t DfllBtcMasterScalerM; 1112 int32_t DfllBtcMasterScalerB; 1113 uint32_t DfllBtcSlaveScalerM; 1114 int32_t DfllBtcSlaveScalerB; 1115 uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg 1116 uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg 1117 uint32_t GfxGpoSpare[10]; 1118 1119 // GFX DCS 1120 1121 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1122 uint16_t PaddingDcs; 1123 1124 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1125 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1126 1127 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1128 1129 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1130 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1131 1132 1133 uint32_t DcsSpare[14]; 1134 1135 // UCLK section 1136 uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz 1137 1138 // UCLK section 1139 uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1140 uint8_t PaddingMem[3]; 1141 1142 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1143 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1144 1145 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1146 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1147 1148 //FCLK Section 1149 1150 uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1151 uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1152 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1153 uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1154 uint16_t PaddingFclk; 1155 1156 // Link DPM Settings 1157 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1158 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1159 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1160 1161 // SECTION: Fan Control 1162 uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1163 uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1164 1165 uint16_t FanGain[TEMP_COUNT]; 1166 uint16_t FanGainPadding; 1167 1168 uint16_t FanPwmMin; 1169 uint16_t AcousticTargetRpmThreshold; 1170 uint16_t AcousticLimitRpmThreshold; 1171 uint16_t FanMaximumRpm; 1172 uint16_t MGpuAcousticLimitRpmThreshold; 1173 uint16_t FanTargetGfxclk; 1174 uint32_t TempInputSelectMask; 1175 uint8_t FanZeroRpmEnable; 1176 uint8_t FanTachEdgePerRev; 1177 uint16_t FanTargetTemperature[TEMP_COUNT]; 1178 1179 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1180 int16_t FuzzyFan_ErrorSetDelta; 1181 int16_t FuzzyFan_ErrorRateSetDelta; 1182 int16_t FuzzyFan_PwmSetDelta; 1183 uint16_t FuzzyFan_Reserved; 1184 1185 uint16_t FwCtfLimit[TEMP_COUNT]; 1186 1187 uint16_t IntakeTempEnableRPM; 1188 int16_t IntakeTempOffsetTemp; 1189 uint16_t IntakeTempReleaseTemp; 1190 uint16_t IntakeTempHighIntakeAcousticLimit; 1191 uint16_t IntakeTempAcouticLimitReleaseRate; 1192 1193 int16_t FanAbnormalTempLimitOffset; 1194 uint16_t FanStalledTriggerRpm; 1195 uint16_t FanAbnormalTriggerRpmCoeff; 1196 uint16_t FanAbnormalDetectionEnable; 1197 1198 uint8_t FanIntakeSensorSupport; 1199 uint8_t FanIntakePadding[3]; 1200 uint32_t FanSpare[13]; 1201 // SECTION: VDD_GFX AVFS 1202 1203 uint8_t OverrideGfxAvfsFuses; 1204 uint8_t GfxAvfsPadding[3]; 1205 1206 uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1207 uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1208 1209 uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1210 1211 uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1212 uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1213 1214 uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1215 uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1216 uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1217 uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1218 1219 uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1220 1221 uint32_t dGbV_dT_vmin; 1222 uint32_t dGbV_dT_vmax; 1223 1224 uint32_t V2F_vmin_range_low; 1225 uint32_t V2F_vmin_range_high; 1226 uint32_t V2F_vmax_range_low; 1227 uint32_t V2F_vmax_range_high; 1228 1229 AvfsDcBtcParams_t DcBtcGfxParams; 1230 1231 uint32_t GfxAvfsSpare[32]; 1232 1233 //SECTION: VDD_SOC AVFS 1234 1235 uint8_t OverrideSocAvfsFuses; 1236 uint8_t MinSocAvfsRevision; 1237 uint8_t SocAvfsPadding[2]; 1238 1239 AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1240 1241 DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1242 1243 LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1244 1245 QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1246 1247 AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1248 1249 uint32_t SocAvfsSpare[32]; 1250 1251 //SECTION: Boot clock and voltage values 1252 BootValues_t BootValues; 1253 1254 //SECTION: Driver Reported Clocks 1255 DriverReportedClocks_t DriverReportedClocks; 1256 1257 //SECTION: Message Limits 1258 MsgLimits_t MsgLimits; 1259 1260 //SECTION: OverDrive Limits 1261 OverDriveLimits_t OverDriveLimitsMin; 1262 OverDriveLimits_t OverDriveLimitsBasicMax; 1263 OverDriveLimits_t OverDriveLimitsAdvancedMax; 1264 1265 // SECTION: Advanced Options 1266 uint32_t DebugOverrides; 1267 1268 // Section: Total Board Power idle vs active coefficients 1269 uint8_t TotalBoardPowerSupport; 1270 uint8_t TotalBoardPowerPadding[3]; 1271 1272 int16_t TotalIdleBoardPowerM; 1273 int16_t TotalIdleBoardPowerB; 1274 int16_t TotalBoardPowerM; 1275 int16_t TotalBoardPowerB; 1276 1277 QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT]; 1278 QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT]; 1279 QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT]; 1280 1281 // SECTION: Sku Reserved 1282 uint32_t Spare[43]; 1283 1284 // Padding for MMHUB - do not modify this 1285 uint32_t MmHubPadding[8]; 1286 1287 } SkuTable_t; 1288 1289 typedef struct { 1290 // SECTION: Version 1291 uint32_t Version; //should be unique to each board type 1292 1293 1294 // SECTION: I2C Control 1295 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1296 1297 // SECTION: SVI2 Board Parameters 1298 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1299 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1300 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1301 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1302 1303 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1304 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1305 uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1306 uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1307 1308 //SECTION SVI3 Board Parameters 1309 uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1310 uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1311 1312 uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1313 uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1314 1315 // SECTION: Voltage Regulator Settings 1316 SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1317 uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1318 1319 uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1320 1321 // SECTION: GPIO Settings 1322 1323 uint8_t LedOffGpio; 1324 uint8_t FanOffGpio; 1325 uint8_t GfxVrPowerStageOffGpio; 1326 1327 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1328 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1329 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1330 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1331 1332 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1333 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1334 1335 // LED Display Settings 1336 uint8_t LedPin0; // GPIO number for LedPin[0] 1337 uint8_t LedPin1; // GPIO number for LedPin[1] 1338 uint8_t LedPin2; // GPIO number for LedPin[2] 1339 uint8_t LedEnableMask; 1340 1341 uint8_t LedPcie; // GPIO number for PCIE results 1342 uint8_t LedError; // GPIO number for Error Cases 1343 1344 // SECTION: Clock Spread Spectrum 1345 1346 // UCLK Spread Spectrum 1347 uint8_t UclkTrainingModeSpreadPercent; // Q4.4 1348 uint8_t UclkSpreadPadding; 1349 uint16_t UclkSpreadFreq; // kHz 1350 1351 // UCLK Spread Spectrum 1352 uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1353 1354 // FCLK Spread Spectrum 1355 uint8_t FclkSpreadPadding; 1356 uint8_t FclkSpreadPercent; // Q4.4 1357 uint16_t FclkSpreadFreq; // kHz 1358 1359 // Section: Memory Config 1360 uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1361 uint8_t PaddingMem1[7]; 1362 1363 // SECTION: UMC feature flags 1364 uint8_t HsrEnabled; 1365 uint8_t VddqOffEnabled; 1366 uint8_t PaddingUmcFlags[2]; 1367 1368 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1369 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1370 1371 uint8_t FuseWritePowerMuxPresent; 1372 uint8_t FuseWritePadding[3]; 1373 1374 // SECTION: Board Reserved 1375 uint32_t BoardSpare[63]; 1376 1377 // SECTION: Structure Padding 1378 1379 // Padding for MMHUB - do not modify this 1380 uint32_t MmHubPadding[8]; 1381 } BoardTable_t; 1382 1383 #pragma pack(push, 1) 1384 typedef struct { 1385 SkuTable_t SkuTable; 1386 BoardTable_t BoardTable; 1387 } PPTable_t; 1388 #pragma pack(pop) 1389 1390 typedef struct { 1391 // Time constant parameters for clock averages in ms 1392 uint16_t GfxclkAverageLpfTau; 1393 uint16_t FclkAverageLpfTau; 1394 uint16_t UclkAverageLpfTau; 1395 uint16_t GfxActivityLpfTau; 1396 uint16_t UclkActivityLpfTau; 1397 uint16_t SocketPowerLpfTau; 1398 uint16_t VcnClkAverageLpfTau; 1399 uint16_t VcnUsageAverageLpfTau; 1400 } DriverSmuConfig_t; 1401 1402 typedef struct { 1403 DriverSmuConfig_t DriverSmuConfig; 1404 1405 uint32_t Spare[8]; 1406 // Padding - ignore 1407 uint32_t MmHubPadding[8]; // SMU internal use 1408 } DriverSmuConfigExternal_t; 1409 1410 1411 typedef struct { 1412 1413 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1414 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1415 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1416 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1417 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1418 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1419 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1420 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1421 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1422 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1423 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1424 1425 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1426 1427 uint16_t Padding; 1428 1429 uint32_t Spare[32]; 1430 1431 // Padding - ignore 1432 uint32_t MmHubPadding[8]; // SMU internal use 1433 1434 } DriverInfoTable_t; 1435 1436 typedef struct { 1437 uint32_t CurrClock[PPCLK_COUNT]; 1438 1439 uint16_t AverageGfxclkFrequencyTarget; 1440 uint16_t AverageGfxclkFrequencyPreDs; 1441 uint16_t AverageGfxclkFrequencyPostDs; 1442 uint16_t AverageFclkFrequencyPreDs; 1443 uint16_t AverageFclkFrequencyPostDs; 1444 uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1445 uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1446 uint16_t AverageVclk0Frequency ; 1447 uint16_t AverageDclk0Frequency ; 1448 uint16_t AverageVclk1Frequency ; 1449 uint16_t AverageDclk1Frequency ; 1450 uint16_t PCIeBusy ; 1451 uint16_t dGPU_W_MAX ; 1452 uint16_t padding ; 1453 1454 uint32_t MetricsCounter ; 1455 1456 uint16_t AvgVoltage[SVI_PLANE_COUNT]; 1457 uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1458 1459 uint16_t AverageGfxActivity ; 1460 uint16_t AverageUclkActivity ; 1461 uint16_t Vcn0ActivityPercentage ; 1462 uint16_t Vcn1ActivityPercentage ; 1463 1464 uint32_t EnergyAccumulator; 1465 uint16_t AverageSocketPower; 1466 uint16_t AverageTotalBoardPower; 1467 1468 uint16_t AvgTemperature[TEMP_COUNT]; 1469 uint16_t AvgTemperatureFanIntake; 1470 1471 uint8_t PcieRate ; 1472 uint8_t PcieWidth ; 1473 1474 uint8_t AvgFanPwm; 1475 uint8_t Padding[1]; 1476 uint16_t AvgFanRpm; 1477 1478 1479 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1480 1481 //metrics for D3hot entry/exit and driver ARM msgs 1482 uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1483 uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1484 uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1485 1486 uint16_t ApuSTAPMSmartShiftLimit; 1487 uint16_t ApuSTAPMLimit; 1488 uint16_t AvgApuSocketPower; 1489 1490 uint16_t AverageUclkActivity_MAX; 1491 1492 uint32_t PublicSerialNumberLower; 1493 uint32_t PublicSerialNumberUpper; 1494 } SmuMetrics_t; 1495 1496 typedef struct { 1497 SmuMetrics_t SmuMetrics; 1498 uint32_t Spare[30]; 1499 1500 // Padding - ignore 1501 uint32_t MmHubPadding[8]; // SMU internal use 1502 } SmuMetricsExternal_t; 1503 1504 typedef struct { 1505 uint8_t WmSetting; 1506 uint8_t Flags; 1507 uint8_t Padding[2]; 1508 1509 } WatermarkRowGeneric_t; 1510 1511 #define NUM_WM_RANGES 4 1512 1513 typedef enum { 1514 WATERMARKS_CLOCK_RANGE = 0, 1515 WATERMARKS_DUMMY_PSTATE, 1516 WATERMARKS_MALL, 1517 WATERMARKS_COUNT, 1518 } WATERMARKS_FLAGS_e; 1519 1520 typedef struct { 1521 // Watermarks 1522 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1523 } Watermarks_t; 1524 1525 typedef struct { 1526 Watermarks_t Watermarks; 1527 uint32_t Spare[16]; 1528 1529 uint32_t MmHubPadding[8]; // SMU internal use 1530 } WatermarksExternal_t; 1531 1532 typedef struct { 1533 uint16_t avgPsmCount[36]; 1534 uint16_t minPsmCount[36]; 1535 float avgPsmVoltage[36]; 1536 float minPsmVoltage[36]; 1537 } AvfsDebugTable_t; 1538 1539 typedef struct { 1540 AvfsDebugTable_t AvfsDebugTable; 1541 1542 uint32_t MmHubPadding[8]; // SMU internal use 1543 } AvfsDebugTableExternal_t; 1544 1545 1546 typedef struct { 1547 uint8_t Gfx_ActiveHystLimit; 1548 uint8_t Gfx_IdleHystLimit; 1549 uint8_t Gfx_FPS; 1550 uint8_t Gfx_MinActiveFreqType; 1551 uint8_t Gfx_BoosterFreqType; 1552 uint8_t PaddingGfx; 1553 uint16_t Gfx_MinActiveFreq; // MHz 1554 uint16_t Gfx_BoosterFreq; // MHz 1555 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1556 uint32_t Gfx_PD_Data_limit_a; // Q16 1557 uint32_t Gfx_PD_Data_limit_b; // Q16 1558 uint32_t Gfx_PD_Data_limit_c; // Q16 1559 uint32_t Gfx_PD_Data_error_coeff; // Q16 1560 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1561 1562 uint8_t Fclk_ActiveHystLimit; 1563 uint8_t Fclk_IdleHystLimit; 1564 uint8_t Fclk_FPS; 1565 uint8_t Fclk_MinActiveFreqType; 1566 uint8_t Fclk_BoosterFreqType; 1567 uint8_t PaddingFclk; 1568 uint16_t Fclk_MinActiveFreq; // MHz 1569 uint16_t Fclk_BoosterFreq; // MHz 1570 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1571 uint32_t Fclk_PD_Data_limit_a; // Q16 1572 uint32_t Fclk_PD_Data_limit_b; // Q16 1573 uint32_t Fclk_PD_Data_limit_c; // Q16 1574 uint32_t Fclk_PD_Data_error_coeff; // Q16 1575 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1576 1577 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1578 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1579 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1580 uint16_t Mem_Fps; 1581 uint8_t padding[2]; 1582 1583 } DpmActivityMonitorCoeffInt_t; 1584 1585 1586 typedef struct { 1587 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1588 uint32_t MmHubPadding[8]; // SMU internal use 1589 } DpmActivityMonitorCoeffIntExternal_t; 1590 1591 1592 1593 // Workload bits 1594 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1595 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1596 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1597 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1598 #define WORKLOAD_PPLIB_VR_BIT 4 1599 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1600 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1601 #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1602 #define WORKLOAD_PPLIB_COUNT 8 1603 1604 1605 // These defines are used with the following messages: 1606 // SMC_MSG_TransferTableDram2Smu 1607 // SMC_MSG_TransferTableSmu2Dram 1608 1609 // Table transfer status 1610 #define TABLE_TRANSFER_OK 0x0 1611 #define TABLE_TRANSFER_FAILED 0xFF 1612 #define TABLE_TRANSFER_PENDING 0xAB 1613 1614 // Table types 1615 #define TABLE_PPTABLE 0 1616 #define TABLE_COMBO_PPTABLE 1 1617 #define TABLE_WATERMARKS 2 1618 #define TABLE_AVFS_PSM_DEBUG 3 1619 #define TABLE_PMSTATUSLOG 4 1620 #define TABLE_SMU_METRICS 5 1621 #define TABLE_DRIVER_SMU_CONFIG 6 1622 #define TABLE_ACTIVITY_MONITOR_COEFF 7 1623 #define TABLE_OVERDRIVE 8 1624 #define TABLE_I2C_COMMANDS 9 1625 #define TABLE_DRIVER_INFO 10 1626 #define TABLE_ECCINFO 11 1627 #define TABLE_COUNT 12 1628 1629 //IH Interupt ID 1630 #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1631 #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1632 #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1633 #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1634 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1635 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1636 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1637 #define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 1638 #define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 1639 1640 #endif 1641