1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __SMU_V14_0_H__ 24 #define __SMU_V14_0_H__ 25 26 #include "amdgpu_smu.h" 27 28 #define SMU14_DRIVER_IF_VERSION_INV 0xFFFFFFFF 29 #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x7 30 #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_1 0x6 31 #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x1 32 33 #define FEATURE_MASK(feature) (1ULL << feature) 34 35 /* MP Apertures */ 36 #define MP0_Public 0x03800000 37 #define MP0_SRAM 0x03900000 38 #define MP1_Public 0x03b00000 39 #define MP1_SRAM 0x03c00004 40 41 /* address block */ 42 #define smnMP1_FIRMWARE_FLAGS 0x3010028 43 #define smnMP1_PUB_CTRL 0x3010d10 44 45 #define MAX_DPM_LEVELS 16 46 #define MAX_PCIE_CONF 3 47 48 struct smu_14_0_max_sustainable_clocks { 49 uint32_t display_clock; 50 uint32_t phy_clock; 51 uint32_t pixel_clock; 52 uint32_t uclock; 53 uint32_t dcef_clock; 54 uint32_t soc_clock; 55 }; 56 57 struct smu_14_0_dpm_clk_level { 58 bool enabled; 59 uint32_t value; 60 }; 61 62 struct smu_14_0_dpm_table { 63 uint32_t min; /* MHz */ 64 uint32_t max; /* MHz */ 65 uint32_t count; 66 bool is_fine_grained; 67 struct smu_14_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; 68 }; 69 70 struct smu_14_0_pcie_table { 71 uint8_t pcie_gen[MAX_PCIE_CONF]; 72 uint8_t pcie_lane[MAX_PCIE_CONF]; 73 uint16_t clk_freq[MAX_PCIE_CONF]; 74 uint32_t num_of_link_levels; 75 }; 76 77 struct smu_14_0_dpm_tables { 78 struct smu_14_0_dpm_table soc_table; 79 struct smu_14_0_dpm_table gfx_table; 80 struct smu_14_0_dpm_table uclk_table; 81 struct smu_14_0_dpm_table eclk_table; 82 struct smu_14_0_dpm_table vclk_table; 83 struct smu_14_0_dpm_table dclk_table; 84 struct smu_14_0_dpm_table dcef_table; 85 struct smu_14_0_dpm_table pixel_table; 86 struct smu_14_0_dpm_table display_table; 87 struct smu_14_0_dpm_table phy_table; 88 struct smu_14_0_dpm_table fclk_table; 89 struct smu_14_0_pcie_table pcie_table; 90 }; 91 92 struct smu_14_0_dpm_context { 93 struct smu_14_0_dpm_tables dpm_tables; 94 uint32_t workload_policy_mask; 95 uint32_t dcef_min_ds_clk; 96 }; 97 98 enum smu_14_0_power_state { 99 SMU_14_0_POWER_STATE__D0 = 0, 100 SMU_14_0_POWER_STATE__D1, 101 SMU_14_0_POWER_STATE__D3, /* Sleep*/ 102 SMU_14_0_POWER_STATE__D4, /* Hibernate*/ 103 SMU_14_0_POWER_STATE__D5, /* Power off*/ 104 }; 105 106 struct smu_14_0_power_context { 107 uint32_t power_source; 108 uint8_t in_power_limit_boost_mode; 109 enum smu_14_0_power_state power_state; 110 }; 111 112 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) 113 114 int smu_v14_0_init_microcode(struct smu_context *smu); 115 116 void smu_v14_0_fini_microcode(struct smu_context *smu); 117 118 int smu_v14_0_load_microcode(struct smu_context *smu); 119 120 int smu_v14_0_init_smc_tables(struct smu_context *smu); 121 122 int smu_v14_0_fini_smc_tables(struct smu_context *smu); 123 124 int smu_v14_0_init_power(struct smu_context *smu); 125 126 int smu_v14_0_fini_power(struct smu_context *smu); 127 128 int smu_v14_0_check_fw_status(struct smu_context *smu); 129 130 int smu_v14_0_setup_pptable(struct smu_context *smu); 131 132 int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu); 133 134 int smu_v14_0_check_fw_version(struct smu_context *smu); 135 136 int smu_v14_0_set_driver_table_location(struct smu_context *smu); 137 138 int smu_v14_0_set_tool_table_location(struct smu_context *smu); 139 140 int smu_v14_0_notify_memory_pool_location(struct smu_context *smu); 141 142 int smu_v14_0_system_features_control(struct smu_context *smu, 143 bool en); 144 145 int smu_v14_0_set_allowed_mask(struct smu_context *smu); 146 147 int smu_v14_0_notify_display_change(struct smu_context *smu); 148 149 int smu_v14_0_get_current_power_limit(struct smu_context *smu, 150 uint32_t *power_limit); 151 152 int smu_v14_0_set_power_limit(struct smu_context *smu, 153 enum smu_ppt_limit_type limit_type, 154 uint32_t limit); 155 156 int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable); 157 158 int smu_v14_0_register_irq_handler(struct smu_context *smu); 159 160 int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu, 161 enum smu_baco_seq baco_seq); 162 163 bool smu_v14_0_baco_is_support(struct smu_context *smu); 164 165 enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu); 166 167 int smu_v14_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state); 168 169 int smu_v14_0_baco_enter(struct smu_context *smu); 170 int smu_v14_0_baco_exit(struct smu_context *smu); 171 172 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 173 uint32_t *min, uint32_t *max); 174 175 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 176 uint32_t min, uint32_t max); 177 178 int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu, 179 enum smu_clk_type clk_type, 180 uint32_t min, 181 uint32_t max); 182 183 int smu_v14_0_set_performance_level(struct smu_context *smu, 184 enum amd_dpm_forced_level level); 185 186 int smu_v14_0_set_power_source(struct smu_context *smu, 187 enum smu_power_src_type power_src); 188 189 int smu_v14_0_set_single_dpm_table(struct smu_context *smu, 190 enum smu_clk_type clk_type, 191 struct smu_14_0_dpm_table *single_dpm_table); 192 193 int smu_v14_0_gfx_ulv_control(struct smu_context *smu, 194 bool enablement); 195 196 int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 197 uint64_t event_arg); 198 199 int smu_v14_0_set_vcn_enable(struct smu_context *smu, 200 bool enable); 201 202 int smu_v14_0_set_jpeg_enable(struct smu_context *smu, 203 bool enable); 204 205 int smu_v14_0_init_pptable_microcode(struct smu_context *smu); 206 207 int smu_v14_0_run_btc(struct smu_context *smu); 208 209 int smu_v14_0_gpo_control(struct smu_context *smu, 210 bool enablement); 211 212 int smu_v14_0_deep_sleep_control(struct smu_context *smu, 213 bool enablement); 214 215 int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu); 216 217 int smu_v14_0_set_default_dpm_tables(struct smu_context *smu); 218 219 int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu, 220 void **table, 221 uint32_t *size, 222 uint32_t pptable_id); 223 224 int smu_v14_0_od_edit_dpm_table(struct smu_context *smu, 225 enum PP_OD_DPM_TABLE_COMMAND type, 226 long input[], uint32_t size); 227 228 void smu_v14_0_set_smu_mailbox_registers(struct smu_context *smu); 229 230 #endif 231 #endif 232