1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "atomfirmware.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_atombios.h" 34 #include "smu_v13_0.h" 35 #include "smu13_driver_if_v13_0_0.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "smu_v13_0_0_ppt.h" 39 #include "smu_v13_0_0_pptable.h" 40 #include "smu_v13_0_0_ppsmc.h" 41 #include "nbio/nbio_4_3_0_offset.h" 42 #include "nbio/nbio_4_3_0_sh_mask.h" 43 #include "mp/mp_13_0_0_offset.h" 44 #include "mp/mp_13_0_0_sh_mask.h" 45 46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h" 47 #include "smu_cmn.h" 48 #include "amdgpu_ras.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define FEATURE_MASK(feature) (1ULL << feature) 63 #define SMC_DPM_FEATURE ( \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 70 71 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 72 73 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = { 74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 77 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 78 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 79 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 80 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 81 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 82 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 83 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 84 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 85 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 86 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 87 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 88 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 89 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 90 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 91 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 92 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 93 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 94 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 95 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 96 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 97 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 98 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 99 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 100 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 101 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 102 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 103 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 104 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 105 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 106 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 107 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 108 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 109 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 110 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 112 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 113 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 114 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 115 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 116 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 117 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 118 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 119 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 120 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 121 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 122 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0), 123 }; 124 125 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = { 126 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 127 CLK_MAP(SCLK, PPCLK_GFXCLK), 128 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 129 CLK_MAP(FCLK, PPCLK_FCLK), 130 CLK_MAP(UCLK, PPCLK_UCLK), 131 CLK_MAP(MCLK, PPCLK_UCLK), 132 CLK_MAP(VCLK, PPCLK_VCLK_0), 133 CLK_MAP(VCLK1, PPCLK_VCLK_1), 134 CLK_MAP(DCLK, PPCLK_DCLK_0), 135 CLK_MAP(DCLK1, PPCLK_DCLK_1), 136 }; 137 138 static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = { 139 FEA_MAP(FW_DATA_READ), 140 FEA_MAP(DPM_GFXCLK), 141 FEA_MAP(DPM_GFX_POWER_OPTIMIZER), 142 FEA_MAP(DPM_UCLK), 143 FEA_MAP(DPM_FCLK), 144 FEA_MAP(DPM_SOCCLK), 145 FEA_MAP(DPM_MP0CLK), 146 FEA_MAP(DPM_LINK), 147 FEA_MAP(DPM_DCN), 148 FEA_MAP(VMEMP_SCALING), 149 FEA_MAP(VDDIO_MEM_SCALING), 150 FEA_MAP(DS_GFXCLK), 151 FEA_MAP(DS_SOCCLK), 152 FEA_MAP(DS_FCLK), 153 FEA_MAP(DS_LCLK), 154 FEA_MAP(DS_DCFCLK), 155 FEA_MAP(DS_UCLK), 156 FEA_MAP(GFX_ULV), 157 FEA_MAP(FW_DSTATE), 158 FEA_MAP(GFXOFF), 159 FEA_MAP(BACO), 160 FEA_MAP(MM_DPM), 161 FEA_MAP(SOC_MPCLK_DS), 162 FEA_MAP(BACO_MPCLK_DS), 163 FEA_MAP(THROTTLERS), 164 FEA_MAP(SMARTSHIFT), 165 FEA_MAP(GTHR), 166 FEA_MAP(ACDC), 167 FEA_MAP(VR0HOT), 168 FEA_MAP(FW_CTF), 169 FEA_MAP(FAN_CONTROL), 170 FEA_MAP(GFX_DCS), 171 FEA_MAP(GFX_READ_MARGIN), 172 FEA_MAP(LED_DISPLAY), 173 FEA_MAP(GFXCLK_SPREAD_SPECTRUM), 174 FEA_MAP(OUT_OF_BAND_MONITOR), 175 FEA_MAP(OPTIMIZED_VMIN), 176 FEA_MAP(GFX_IMU), 177 FEA_MAP(BOOT_TIME_CAL), 178 FEA_MAP(GFX_PCC_DFLL), 179 FEA_MAP(SOC_CG), 180 FEA_MAP(DF_CSTATE), 181 FEA_MAP(GFX_EDC), 182 FEA_MAP(BOOT_POWER_OPT), 183 FEA_MAP(CLOCK_POWER_DOWN_BYPASS), 184 FEA_MAP(DS_VCN), 185 FEA_MAP(BACO_CG), 186 FEA_MAP(MEM_TEMP_READ), 187 FEA_MAP(ATHUB_MMHUB_PG), 188 FEA_MAP(SOC_PCC), 189 }; 190 191 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = { 192 TAB_MAP(PPTABLE), 193 TAB_MAP(WATERMARKS), 194 TAB_MAP(AVFS_PSM_DEBUG), 195 TAB_MAP(PMSTATUSLOG), 196 TAB_MAP(SMU_METRICS), 197 TAB_MAP(DRIVER_SMU_CONFIG), 198 TAB_MAP(ACTIVITY_MONITOR_COEFF), 199 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE}, 200 TAB_MAP(I2C_COMMANDS), 201 }; 202 203 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 204 PWR_MAP(AC), 205 PWR_MAP(DC), 206 }; 207 208 static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 211 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 212 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 213 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 214 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 215 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 216 }; 217 218 static const uint8_t smu_v13_0_0_throttler_map[] = { 219 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 220 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 221 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 222 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 223 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 224 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 225 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 226 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 227 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 228 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 229 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 230 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 231 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 232 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 233 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 234 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT), 235 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 236 }; 237 238 static int 239 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, 240 uint32_t *feature_mask, uint32_t num) 241 { 242 struct amdgpu_device *adev = smu->adev; 243 u32 smu_version; 244 245 if (num > 2) 246 return -EINVAL; 247 248 memset(feature_mask, 0xff, sizeof(uint32_t) * num); 249 250 if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) { 251 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 252 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); 253 } 254 255 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) || 256 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) 257 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 258 259 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) 260 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 261 262 /* PMFW 78.58 contains a critical fix for gfxoff feature */ 263 smu_cmn_get_smc_version(smu, NULL, &smu_version); 264 if ((smu_version < 0x004e3a00) || 265 !(adev->pm.pp_feature & PP_GFXOFF_MASK)) 266 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); 267 268 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { 269 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 270 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 271 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 272 } 273 274 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) 275 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 276 277 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { 278 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); 279 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); 280 } 281 282 if (!(adev->pm.pp_feature & PP_ULV_MASK)) 283 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT); 284 285 return 0; 286 } 287 288 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu) 289 { 290 struct smu_table_context *table_context = &smu->smu_table; 291 struct smu_13_0_0_powerplay_table *powerplay_table = 292 table_context->power_play_table; 293 struct smu_baco_context *smu_baco = &smu->smu_baco; 294 295 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC) 296 smu->dc_controlled_by_gpio = true; 297 298 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO || 299 powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) 300 smu_baco->platform_support = true; 301 302 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO) 303 smu_baco->maco_support = true; 304 305 table_context->thermal_controller_type = 306 powerplay_table->thermal_controller_type; 307 308 /* 309 * Instead of having its own buffer space and get overdrive_table copied, 310 * smu->od_settings just points to the actual overdrive_table 311 */ 312 smu->od_settings = &powerplay_table->overdrive_table; 313 314 return 0; 315 } 316 317 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu) 318 { 319 struct smu_table_context *table_context = &smu->smu_table; 320 struct smu_13_0_0_powerplay_table *powerplay_table = 321 table_context->power_play_table; 322 323 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 324 sizeof(PPTable_t)); 325 326 return 0; 327 } 328 329 #ifndef atom_smc_dpm_info_table_13_0_0 330 struct atom_smc_dpm_info_table_13_0_0 { 331 struct atom_common_table_header table_header; 332 BoardTable_t BoardTable; 333 }; 334 #endif 335 336 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu) 337 { 338 struct smu_table_context *table_context = &smu->smu_table; 339 PPTable_t *smc_pptable = table_context->driver_pptable; 340 struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table; 341 BoardTable_t *BoardTable = &smc_pptable->BoardTable; 342 int index, ret; 343 344 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 345 smc_dpm_info); 346 347 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 348 (uint8_t **)&smc_dpm_table); 349 if (ret) 350 return ret; 351 352 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t)); 353 354 return 0; 355 } 356 357 static int smu_v13_0_0_get_pptable_from_pmfw(struct smu_context *smu, 358 void **table, 359 uint32_t *size) 360 { 361 struct smu_table_context *smu_table = &smu->smu_table; 362 void *combo_pptable = smu_table->combo_pptable; 363 int ret = 0; 364 365 ret = smu_cmn_get_combo_pptable(smu); 366 if (ret) 367 return ret; 368 369 *table = combo_pptable; 370 *size = sizeof(struct smu_13_0_0_powerplay_table); 371 372 return 0; 373 } 374 375 static int smu_v13_0_0_setup_pptable(struct smu_context *smu) 376 { 377 struct smu_table_context *smu_table = &smu->smu_table; 378 struct amdgpu_device *adev = smu->adev; 379 int ret = 0; 380 381 ret = smu_v13_0_0_get_pptable_from_pmfw(smu, 382 &smu_table->power_play_table, 383 &smu_table->power_play_table_size); 384 if (ret) 385 return ret; 386 387 ret = smu_v13_0_0_store_powerplay_table(smu); 388 if (ret) 389 return ret; 390 391 /* 392 * With SCPM enabled, the operation below will be handled 393 * by PSP. Driver involvment is unnecessary and useless. 394 */ 395 if (!adev->scpm_enabled) { 396 ret = smu_v13_0_0_append_powerplay_table(smu); 397 if (ret) 398 return ret; 399 } 400 401 ret = smu_v13_0_0_check_powerplay_table(smu); 402 if (ret) 403 return ret; 404 405 return ret; 406 } 407 408 static int smu_v13_0_0_tables_init(struct smu_context *smu) 409 { 410 struct smu_table_context *smu_table = &smu->smu_table; 411 struct smu_table *tables = smu_table->tables; 412 413 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 414 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 415 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 416 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 417 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 418 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 419 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 420 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 421 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 422 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 423 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 424 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 425 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 426 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 427 AMDGPU_GEM_DOMAIN_VRAM); 428 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE, 429 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 430 431 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 432 if (!smu_table->metrics_table) 433 goto err0_out; 434 smu_table->metrics_time = 0; 435 436 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 437 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 438 if (!smu_table->gpu_metrics_table) 439 goto err1_out; 440 441 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 442 if (!smu_table->watermarks_table) 443 goto err2_out; 444 445 return 0; 446 447 err2_out: 448 kfree(smu_table->gpu_metrics_table); 449 err1_out: 450 kfree(smu_table->metrics_table); 451 err0_out: 452 return -ENOMEM; 453 } 454 455 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu) 456 { 457 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 458 459 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 460 GFP_KERNEL); 461 if (!smu_dpm->dpm_context) 462 return -ENOMEM; 463 464 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 465 466 return 0; 467 } 468 469 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu) 470 { 471 int ret = 0; 472 473 ret = smu_v13_0_0_tables_init(smu); 474 if (ret) 475 return ret; 476 477 ret = smu_v13_0_0_allocate_dpm_context(smu); 478 if (ret) 479 return ret; 480 481 return smu_v13_0_init_smc_tables(smu); 482 } 483 484 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) 485 { 486 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 487 struct smu_table_context *table_context = &smu->smu_table; 488 PPTable_t *pptable = table_context->driver_pptable; 489 SkuTable_t *skutable = &pptable->SkuTable; 490 struct smu_13_0_dpm_table *dpm_table; 491 struct smu_13_0_pcie_table *pcie_table; 492 uint32_t link_level; 493 int ret = 0; 494 495 /* socclk dpm table setup */ 496 dpm_table = &dpm_context->dpm_tables.soc_table; 497 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 498 ret = smu_v13_0_set_single_dpm_table(smu, 499 SMU_SOCCLK, 500 dpm_table); 501 if (ret) 502 return ret; 503 } else { 504 dpm_table->count = 1; 505 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 506 dpm_table->dpm_levels[0].enabled = true; 507 dpm_table->min = dpm_table->dpm_levels[0].value; 508 dpm_table->max = dpm_table->dpm_levels[0].value; 509 } 510 511 /* gfxclk dpm table setup */ 512 dpm_table = &dpm_context->dpm_tables.gfx_table; 513 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 514 ret = smu_v13_0_set_single_dpm_table(smu, 515 SMU_GFXCLK, 516 dpm_table); 517 if (ret) 518 return ret; 519 } else { 520 dpm_table->count = 1; 521 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 522 dpm_table->dpm_levels[0].enabled = true; 523 dpm_table->min = dpm_table->dpm_levels[0].value; 524 dpm_table->max = dpm_table->dpm_levels[0].value; 525 } 526 527 /* uclk dpm table setup */ 528 dpm_table = &dpm_context->dpm_tables.uclk_table; 529 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 530 ret = smu_v13_0_set_single_dpm_table(smu, 531 SMU_UCLK, 532 dpm_table); 533 if (ret) 534 return ret; 535 } else { 536 dpm_table->count = 1; 537 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 538 dpm_table->dpm_levels[0].enabled = true; 539 dpm_table->min = dpm_table->dpm_levels[0].value; 540 dpm_table->max = dpm_table->dpm_levels[0].value; 541 } 542 543 /* fclk dpm table setup */ 544 dpm_table = &dpm_context->dpm_tables.fclk_table; 545 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 546 ret = smu_v13_0_set_single_dpm_table(smu, 547 SMU_FCLK, 548 dpm_table); 549 if (ret) 550 return ret; 551 } else { 552 dpm_table->count = 1; 553 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 554 dpm_table->dpm_levels[0].enabled = true; 555 dpm_table->min = dpm_table->dpm_levels[0].value; 556 dpm_table->max = dpm_table->dpm_levels[0].value; 557 } 558 559 /* vclk dpm table setup */ 560 dpm_table = &dpm_context->dpm_tables.vclk_table; 561 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { 562 ret = smu_v13_0_set_single_dpm_table(smu, 563 SMU_VCLK, 564 dpm_table); 565 if (ret) 566 return ret; 567 } else { 568 dpm_table->count = 1; 569 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 570 dpm_table->dpm_levels[0].enabled = true; 571 dpm_table->min = dpm_table->dpm_levels[0].value; 572 dpm_table->max = dpm_table->dpm_levels[0].value; 573 } 574 575 /* dclk dpm table setup */ 576 dpm_table = &dpm_context->dpm_tables.dclk_table; 577 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { 578 ret = smu_v13_0_set_single_dpm_table(smu, 579 SMU_DCLK, 580 dpm_table); 581 if (ret) 582 return ret; 583 } else { 584 dpm_table->count = 1; 585 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 586 dpm_table->dpm_levels[0].enabled = true; 587 dpm_table->min = dpm_table->dpm_levels[0].value; 588 dpm_table->max = dpm_table->dpm_levels[0].value; 589 } 590 591 /* lclk dpm table setup */ 592 pcie_table = &dpm_context->dpm_tables.pcie_table; 593 pcie_table->num_of_link_levels = 0; 594 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { 595 if (!skutable->PcieGenSpeed[link_level] && 596 !skutable->PcieLaneCount[link_level] && 597 !skutable->LclkFreq[link_level]) 598 continue; 599 600 pcie_table->pcie_gen[pcie_table->num_of_link_levels] = 601 skutable->PcieGenSpeed[link_level]; 602 pcie_table->pcie_lane[pcie_table->num_of_link_levels] = 603 skutable->PcieLaneCount[link_level]; 604 pcie_table->clk_freq[pcie_table->num_of_link_levels] = 605 skutable->LclkFreq[link_level]; 606 pcie_table->num_of_link_levels++; 607 } 608 609 return 0; 610 } 611 612 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu) 613 { 614 int ret = 0; 615 uint64_t feature_enabled; 616 617 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 618 if (ret) 619 return false; 620 621 return !!(feature_enabled & SMC_DPM_FEATURE); 622 } 623 624 static void smu_v13_0_0_dump_pptable(struct smu_context *smu) 625 { 626 struct smu_table_context *table_context = &smu->smu_table; 627 PPTable_t *pptable = table_context->driver_pptable; 628 SkuTable_t *skutable = &pptable->SkuTable; 629 630 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 631 632 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version); 633 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]); 634 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]); 635 } 636 637 static int smu_v13_0_0_system_features_control(struct smu_context *smu, 638 bool en) 639 { 640 return smu_v13_0_system_features_control(smu, en); 641 } 642 643 static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics) 644 { 645 uint32_t throttler_status = 0; 646 int i; 647 648 for (i = 0; i < THROTTLER_COUNT; i++) 649 throttler_status |= 650 (metrics->ThrottlingPercentage[i] ? 1U << i : 0); 651 652 return throttler_status; 653 } 654 655 #define SMU_13_0_0_BUSY_THRESHOLD 15 656 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu, 657 MetricsMember_t member, 658 uint32_t *value) 659 { 660 struct smu_table_context *smu_table = &smu->smu_table; 661 SmuMetrics_t *metrics = 662 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 663 int ret = 0; 664 665 ret = smu_cmn_get_metrics_table(smu, 666 NULL, 667 false); 668 if (ret) 669 return ret; 670 671 switch (member) { 672 case METRICS_CURR_GFXCLK: 673 *value = metrics->CurrClock[PPCLK_GFXCLK]; 674 break; 675 case METRICS_CURR_SOCCLK: 676 *value = metrics->CurrClock[PPCLK_SOCCLK]; 677 break; 678 case METRICS_CURR_UCLK: 679 *value = metrics->CurrClock[PPCLK_UCLK]; 680 break; 681 case METRICS_CURR_VCLK: 682 *value = metrics->CurrClock[PPCLK_VCLK_0]; 683 break; 684 case METRICS_CURR_VCLK1: 685 *value = metrics->CurrClock[PPCLK_VCLK_1]; 686 break; 687 case METRICS_CURR_DCLK: 688 *value = metrics->CurrClock[PPCLK_DCLK_0]; 689 break; 690 case METRICS_CURR_DCLK1: 691 *value = metrics->CurrClock[PPCLK_DCLK_1]; 692 break; 693 case METRICS_CURR_FCLK: 694 *value = metrics->CurrClock[PPCLK_FCLK]; 695 break; 696 case METRICS_AVERAGE_GFXCLK: 697 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) 698 *value = metrics->AverageGfxclkFrequencyPostDs; 699 else 700 *value = metrics->AverageGfxclkFrequencyPreDs; 701 break; 702 case METRICS_AVERAGE_FCLK: 703 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 704 *value = metrics->AverageFclkFrequencyPostDs; 705 else 706 *value = metrics->AverageFclkFrequencyPreDs; 707 break; 708 case METRICS_AVERAGE_UCLK: 709 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 710 *value = metrics->AverageMemclkFrequencyPostDs; 711 else 712 *value = metrics->AverageMemclkFrequencyPreDs; 713 break; 714 case METRICS_AVERAGE_VCLK: 715 *value = metrics->AverageVclk0Frequency; 716 break; 717 case METRICS_AVERAGE_DCLK: 718 *value = metrics->AverageDclk0Frequency; 719 break; 720 case METRICS_AVERAGE_VCLK1: 721 *value = metrics->AverageVclk1Frequency; 722 break; 723 case METRICS_AVERAGE_DCLK1: 724 *value = metrics->AverageDclk1Frequency; 725 break; 726 case METRICS_AVERAGE_GFXACTIVITY: 727 *value = metrics->AverageGfxActivity; 728 break; 729 case METRICS_AVERAGE_MEMACTIVITY: 730 *value = metrics->AverageUclkActivity; 731 break; 732 case METRICS_AVERAGE_SOCKETPOWER: 733 *value = metrics->AverageSocketPower << 8; 734 break; 735 case METRICS_TEMPERATURE_EDGE: 736 *value = metrics->AvgTemperature[TEMP_EDGE] * 737 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 738 break; 739 case METRICS_TEMPERATURE_HOTSPOT: 740 *value = metrics->AvgTemperature[TEMP_HOTSPOT] * 741 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 742 break; 743 case METRICS_TEMPERATURE_MEM: 744 *value = metrics->AvgTemperature[TEMP_MEM] * 745 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 746 break; 747 case METRICS_TEMPERATURE_VRGFX: 748 *value = metrics->AvgTemperature[TEMP_VR_GFX] * 749 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 750 break; 751 case METRICS_TEMPERATURE_VRSOC: 752 *value = metrics->AvgTemperature[TEMP_VR_SOC] * 753 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 754 break; 755 case METRICS_THROTTLER_STATUS: 756 *value = smu_v13_0_get_throttler_status(metrics); 757 break; 758 case METRICS_CURR_FANSPEED: 759 *value = metrics->AvgFanRpm; 760 break; 761 case METRICS_CURR_FANPWM: 762 *value = metrics->AvgFanPwm; 763 break; 764 case METRICS_VOLTAGE_VDDGFX: 765 *value = metrics->AvgVoltage[SVI_PLANE_GFX]; 766 break; 767 case METRICS_PCIE_RATE: 768 *value = metrics->PcieRate; 769 break; 770 case METRICS_PCIE_WIDTH: 771 *value = metrics->PcieWidth; 772 break; 773 default: 774 *value = UINT_MAX; 775 break; 776 } 777 778 return ret; 779 } 780 781 static int smu_v13_0_0_read_sensor(struct smu_context *smu, 782 enum amd_pp_sensors sensor, 783 void *data, 784 uint32_t *size) 785 { 786 struct smu_table_context *table_context = &smu->smu_table; 787 PPTable_t *smc_pptable = table_context->driver_pptable; 788 int ret = 0; 789 790 switch (sensor) { 791 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 792 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm; 793 *size = 4; 794 break; 795 case AMDGPU_PP_SENSOR_MEM_LOAD: 796 ret = smu_v13_0_0_get_smu_metrics_data(smu, 797 METRICS_AVERAGE_MEMACTIVITY, 798 (uint32_t *)data); 799 *size = 4; 800 break; 801 case AMDGPU_PP_SENSOR_GPU_LOAD: 802 ret = smu_v13_0_0_get_smu_metrics_data(smu, 803 METRICS_AVERAGE_GFXACTIVITY, 804 (uint32_t *)data); 805 *size = 4; 806 break; 807 case AMDGPU_PP_SENSOR_GPU_POWER: 808 ret = smu_v13_0_0_get_smu_metrics_data(smu, 809 METRICS_AVERAGE_SOCKETPOWER, 810 (uint32_t *)data); 811 *size = 4; 812 break; 813 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 814 ret = smu_v13_0_0_get_smu_metrics_data(smu, 815 METRICS_TEMPERATURE_HOTSPOT, 816 (uint32_t *)data); 817 *size = 4; 818 break; 819 case AMDGPU_PP_SENSOR_EDGE_TEMP: 820 ret = smu_v13_0_0_get_smu_metrics_data(smu, 821 METRICS_TEMPERATURE_EDGE, 822 (uint32_t *)data); 823 *size = 4; 824 break; 825 case AMDGPU_PP_SENSOR_MEM_TEMP: 826 ret = smu_v13_0_0_get_smu_metrics_data(smu, 827 METRICS_TEMPERATURE_MEM, 828 (uint32_t *)data); 829 *size = 4; 830 break; 831 case AMDGPU_PP_SENSOR_GFX_MCLK: 832 ret = smu_v13_0_0_get_smu_metrics_data(smu, 833 METRICS_CURR_UCLK, 834 (uint32_t *)data); 835 *(uint32_t *)data *= 100; 836 *size = 4; 837 break; 838 case AMDGPU_PP_SENSOR_GFX_SCLK: 839 ret = smu_v13_0_0_get_smu_metrics_data(smu, 840 METRICS_AVERAGE_GFXCLK, 841 (uint32_t *)data); 842 *(uint32_t *)data *= 100; 843 *size = 4; 844 break; 845 case AMDGPU_PP_SENSOR_VDDGFX: 846 ret = smu_v13_0_0_get_smu_metrics_data(smu, 847 METRICS_VOLTAGE_VDDGFX, 848 (uint32_t *)data); 849 *size = 4; 850 break; 851 default: 852 ret = -EOPNOTSUPP; 853 break; 854 } 855 856 return ret; 857 } 858 859 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu, 860 enum smu_clk_type clk_type, 861 uint32_t *value) 862 { 863 MetricsMember_t member_type; 864 int clk_id = 0; 865 866 clk_id = smu_cmn_to_asic_specific_index(smu, 867 CMN2ASIC_MAPPING_CLK, 868 clk_type); 869 if (clk_id < 0) 870 return -EINVAL; 871 872 switch (clk_id) { 873 case PPCLK_GFXCLK: 874 member_type = METRICS_AVERAGE_GFXCLK; 875 break; 876 case PPCLK_UCLK: 877 member_type = METRICS_CURR_UCLK; 878 break; 879 case PPCLK_FCLK: 880 member_type = METRICS_CURR_FCLK; 881 break; 882 case PPCLK_SOCCLK: 883 member_type = METRICS_CURR_SOCCLK; 884 break; 885 case PPCLK_VCLK_0: 886 member_type = METRICS_AVERAGE_VCLK; 887 break; 888 case PPCLK_DCLK_0: 889 member_type = METRICS_AVERAGE_DCLK; 890 break; 891 case PPCLK_VCLK_1: 892 member_type = METRICS_AVERAGE_VCLK1; 893 break; 894 case PPCLK_DCLK_1: 895 member_type = METRICS_AVERAGE_DCLK1; 896 break; 897 default: 898 return -EINVAL; 899 } 900 901 return smu_v13_0_0_get_smu_metrics_data(smu, 902 member_type, 903 value); 904 } 905 906 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, 907 enum smu_clk_type clk_type, 908 char *buf) 909 { 910 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 911 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 912 struct smu_13_0_dpm_table *single_dpm_table; 913 struct smu_13_0_pcie_table *pcie_table; 914 const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 915 uint32_t gen_speed, lane_width; 916 int i, curr_freq, size = 0; 917 int ret = 0; 918 919 smu_cmn_get_sysfs_buf(&buf, &size); 920 921 if (amdgpu_ras_intr_triggered()) { 922 size += sysfs_emit_at(buf, size, "unavailable\n"); 923 return size; 924 } 925 926 switch (clk_type) { 927 case SMU_SCLK: 928 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 929 break; 930 case SMU_MCLK: 931 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 932 break; 933 case SMU_SOCCLK: 934 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 935 break; 936 case SMU_FCLK: 937 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 938 break; 939 case SMU_VCLK: 940 case SMU_VCLK1: 941 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 942 break; 943 case SMU_DCLK: 944 case SMU_DCLK1: 945 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 946 break; 947 default: 948 break; 949 } 950 951 switch (clk_type) { 952 case SMU_SCLK: 953 case SMU_MCLK: 954 case SMU_SOCCLK: 955 case SMU_FCLK: 956 case SMU_VCLK: 957 case SMU_VCLK1: 958 case SMU_DCLK: 959 case SMU_DCLK1: 960 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); 961 if (ret) { 962 dev_err(smu->adev->dev, "Failed to get current clock freq!"); 963 return ret; 964 } 965 966 if (single_dpm_table->is_fine_grained) { 967 /* 968 * For fine grained dpms, there are only two dpm levels: 969 * - level 0 -> min clock freq 970 * - level 1 -> max clock freq 971 * And the current clock frequency can be any value between them. 972 * So, if the current clock frequency is not at level 0 or level 1, 973 * we will fake it as three dpm levels: 974 * - level 0 -> min clock freq 975 * - level 1 -> current actual clock freq 976 * - level 2 -> max clock freq 977 */ 978 if ((single_dpm_table->dpm_levels[0].value != curr_freq) && 979 (single_dpm_table->dpm_levels[1].value != curr_freq)) { 980 size += sysfs_emit_at(buf, size, "0: %uMhz\n", 981 single_dpm_table->dpm_levels[0].value); 982 size += sysfs_emit_at(buf, size, "1: %uMhz *\n", 983 curr_freq); 984 size += sysfs_emit_at(buf, size, "2: %uMhz\n", 985 single_dpm_table->dpm_levels[1].value); 986 } else { 987 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", 988 single_dpm_table->dpm_levels[0].value, 989 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); 990 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 991 single_dpm_table->dpm_levels[1].value, 992 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); 993 } 994 } else { 995 for (i = 0; i < single_dpm_table->count; i++) 996 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 997 i, single_dpm_table->dpm_levels[i].value, 998 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); 999 } 1000 break; 1001 case SMU_PCIE: 1002 ret = smu_v13_0_0_get_smu_metrics_data(smu, 1003 METRICS_PCIE_RATE, 1004 &gen_speed); 1005 if (ret) 1006 return ret; 1007 1008 ret = smu_v13_0_0_get_smu_metrics_data(smu, 1009 METRICS_PCIE_WIDTH, 1010 &lane_width); 1011 if (ret) 1012 return ret; 1013 1014 pcie_table = &(dpm_context->dpm_tables.pcie_table); 1015 for (i = 0; i < pcie_table->num_of_link_levels; i++) 1016 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1017 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : 1018 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : 1019 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : 1020 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", 1021 (pcie_table->pcie_lane[i] == 1) ? "x1" : 1022 (pcie_table->pcie_lane[i] == 2) ? "x2" : 1023 (pcie_table->pcie_lane[i] == 3) ? "x4" : 1024 (pcie_table->pcie_lane[i] == 4) ? "x8" : 1025 (pcie_table->pcie_lane[i] == 5) ? "x12" : 1026 (pcie_table->pcie_lane[i] == 6) ? "x16" : "", 1027 pcie_table->clk_freq[i], 1028 ((gen_speed - 1) == pcie_table->pcie_gen[i]) && 1029 (lane_width == link_width[pcie_table->pcie_lane[i]]) ? 1030 "*" : ""); 1031 break; 1032 1033 default: 1034 break; 1035 } 1036 1037 return size; 1038 } 1039 1040 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu, 1041 enum smu_clk_type clk_type, 1042 uint32_t mask) 1043 { 1044 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1045 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1046 struct smu_13_0_dpm_table *single_dpm_table; 1047 uint32_t soft_min_level, soft_max_level; 1048 uint32_t min_freq, max_freq; 1049 int ret = 0; 1050 1051 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1052 soft_max_level = mask ? (fls(mask) - 1) : 0; 1053 1054 switch (clk_type) { 1055 case SMU_GFXCLK: 1056 case SMU_SCLK: 1057 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1058 break; 1059 case SMU_MCLK: 1060 case SMU_UCLK: 1061 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1062 break; 1063 case SMU_SOCCLK: 1064 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1065 break; 1066 case SMU_FCLK: 1067 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1068 break; 1069 case SMU_VCLK: 1070 case SMU_VCLK1: 1071 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1072 break; 1073 case SMU_DCLK: 1074 case SMU_DCLK1: 1075 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1076 break; 1077 default: 1078 break; 1079 } 1080 1081 switch (clk_type) { 1082 case SMU_GFXCLK: 1083 case SMU_SCLK: 1084 case SMU_MCLK: 1085 case SMU_UCLK: 1086 case SMU_SOCCLK: 1087 case SMU_FCLK: 1088 case SMU_VCLK: 1089 case SMU_VCLK1: 1090 case SMU_DCLK: 1091 case SMU_DCLK1: 1092 if (single_dpm_table->is_fine_grained) { 1093 /* There is only 2 levels for fine grained DPM */ 1094 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1095 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1096 } else { 1097 if ((soft_max_level >= single_dpm_table->count) || 1098 (soft_min_level >= single_dpm_table->count)) 1099 return -EINVAL; 1100 } 1101 1102 min_freq = single_dpm_table->dpm_levels[soft_min_level].value; 1103 max_freq = single_dpm_table->dpm_levels[soft_max_level].value; 1104 1105 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1106 clk_type, 1107 min_freq, 1108 max_freq); 1109 break; 1110 case SMU_DCEFCLK: 1111 case SMU_PCIE: 1112 default: 1113 break; 1114 } 1115 1116 return ret; 1117 } 1118 1119 static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu, 1120 uint32_t pcie_gen_cap, 1121 uint32_t pcie_width_cap) 1122 { 1123 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1124 struct smu_13_0_pcie_table *pcie_table = 1125 &dpm_context->dpm_tables.pcie_table; 1126 uint32_t smu_pcie_arg; 1127 int ret, i; 1128 1129 for (i = 0; i < pcie_table->num_of_link_levels; i++) { 1130 if (pcie_table->pcie_gen[i] > pcie_gen_cap) 1131 pcie_table->pcie_gen[i] = pcie_gen_cap; 1132 if (pcie_table->pcie_lane[i] > pcie_width_cap) 1133 pcie_table->pcie_lane[i] = pcie_width_cap; 1134 1135 smu_pcie_arg = i << 16; 1136 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8; 1137 smu_pcie_arg |= pcie_table->pcie_lane[i]; 1138 1139 ret = smu_cmn_send_smc_msg_with_param(smu, 1140 SMU_MSG_OverridePcieParameters, 1141 smu_pcie_arg, 1142 NULL); 1143 if (ret) 1144 return ret; 1145 } 1146 1147 return 0; 1148 } 1149 1150 static const struct smu_temperature_range smu13_thermal_policy[] = { 1151 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 1152 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 1153 }; 1154 1155 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu, 1156 struct smu_temperature_range *range) 1157 { 1158 struct smu_table_context *table_context = &smu->smu_table; 1159 struct smu_13_0_0_powerplay_table *powerplay_table = 1160 table_context->power_play_table; 1161 PPTable_t *pptable = smu->smu_table.driver_pptable; 1162 1163 if (!range) 1164 return -EINVAL; 1165 1166 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1167 1168 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] * 1169 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1170 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * 1171 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1172 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] * 1173 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1174 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * 1175 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1176 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] * 1177 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1178 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* 1179 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1180 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1181 1182 return 0; 1183 } 1184 1185 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 1186 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu, 1187 void **table) 1188 { 1189 struct smu_table_context *smu_table = &smu->smu_table; 1190 struct gpu_metrics_v1_3 *gpu_metrics = 1191 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1192 SmuMetricsExternal_t metrics_ext; 1193 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; 1194 int ret = 0; 1195 1196 ret = smu_cmn_get_metrics_table(smu, 1197 &metrics_ext, 1198 true); 1199 if (ret) 1200 return ret; 1201 1202 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1203 1204 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE]; 1205 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT]; 1206 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM]; 1207 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX]; 1208 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC]; 1209 gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0], 1210 metrics->AvgTemperature[TEMP_VR_MEM1]); 1211 1212 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 1213 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 1214 gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage, 1215 metrics->Vcn1ActivityPercentage); 1216 1217 gpu_metrics->average_socket_power = metrics->AverageSocketPower; 1218 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 1219 1220 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) 1221 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; 1222 else 1223 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 1224 1225 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 1226 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs; 1227 else 1228 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs; 1229 1230 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency; 1231 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency; 1232 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency; 1233 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; 1234 1235 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK]; 1236 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK]; 1237 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK]; 1238 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; 1239 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0]; 1240 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1]; 1241 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1]; 1242 1243 gpu_metrics->throttle_status = 1244 smu_v13_0_get_throttler_status(metrics); 1245 gpu_metrics->indep_throttle_status = 1246 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 1247 smu_v13_0_0_throttler_map); 1248 1249 gpu_metrics->current_fan_speed = metrics->AvgFanRpm; 1250 1251 gpu_metrics->pcie_link_width = metrics->PcieWidth; 1252 gpu_metrics->pcie_link_speed = metrics->PcieRate; 1253 1254 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1255 1256 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX]; 1257 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC]; 1258 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP]; 1259 1260 *table = (void *)gpu_metrics; 1261 1262 return sizeof(struct gpu_metrics_v1_3); 1263 } 1264 1265 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu) 1266 { 1267 struct smu_13_0_dpm_context *dpm_context = 1268 smu->smu_dpm.dpm_context; 1269 struct smu_13_0_dpm_table *gfx_table = 1270 &dpm_context->dpm_tables.gfx_table; 1271 struct smu_13_0_dpm_table *mem_table = 1272 &dpm_context->dpm_tables.uclk_table; 1273 struct smu_13_0_dpm_table *soc_table = 1274 &dpm_context->dpm_tables.soc_table; 1275 struct smu_13_0_dpm_table *vclk_table = 1276 &dpm_context->dpm_tables.vclk_table; 1277 struct smu_13_0_dpm_table *dclk_table = 1278 &dpm_context->dpm_tables.dclk_table; 1279 struct smu_13_0_dpm_table *fclk_table = 1280 &dpm_context->dpm_tables.fclk_table; 1281 struct smu_umd_pstate_table *pstate_table = 1282 &smu->pstate_table; 1283 1284 pstate_table->gfxclk_pstate.min = gfx_table->min; 1285 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1286 1287 pstate_table->uclk_pstate.min = mem_table->min; 1288 pstate_table->uclk_pstate.peak = mem_table->max; 1289 1290 pstate_table->socclk_pstate.min = soc_table->min; 1291 pstate_table->socclk_pstate.peak = soc_table->max; 1292 1293 pstate_table->vclk_pstate.min = vclk_table->min; 1294 pstate_table->vclk_pstate.peak = vclk_table->max; 1295 1296 pstate_table->dclk_pstate.min = dclk_table->min; 1297 pstate_table->dclk_pstate.peak = dclk_table->max; 1298 1299 pstate_table->fclk_pstate.min = fclk_table->min; 1300 pstate_table->fclk_pstate.peak = fclk_table->max; 1301 1302 /* 1303 * For now, just use the mininum clock frequency. 1304 * TODO: update them when the real pstate settings available 1305 */ 1306 pstate_table->gfxclk_pstate.standard = gfx_table->min; 1307 pstate_table->uclk_pstate.standard = mem_table->min; 1308 pstate_table->socclk_pstate.standard = soc_table->min; 1309 pstate_table->vclk_pstate.standard = vclk_table->min; 1310 pstate_table->dclk_pstate.standard = dclk_table->min; 1311 pstate_table->fclk_pstate.standard = fclk_table->min; 1312 1313 return 0; 1314 } 1315 1316 static void smu_v13_0_0_get_unique_id(struct smu_context *smu) 1317 { 1318 struct smu_table_context *smu_table = &smu->smu_table; 1319 SmuMetrics_t *metrics = 1320 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 1321 struct amdgpu_device *adev = smu->adev; 1322 uint32_t upper32 = 0, lower32 = 0; 1323 int ret; 1324 1325 ret = smu_cmn_get_metrics_table(smu, NULL, false); 1326 if (ret) 1327 goto out; 1328 1329 upper32 = metrics->PublicSerialNumberUpper; 1330 lower32 = metrics->PublicSerialNumberLower; 1331 1332 out: 1333 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 1334 if (adev->serial[0] == '\0') 1335 sprintf(adev->serial, "%016llx", adev->unique_id); 1336 } 1337 1338 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu, 1339 uint32_t *speed) 1340 { 1341 if (!speed) 1342 return -EINVAL; 1343 1344 return smu_v13_0_0_get_smu_metrics_data(smu, 1345 METRICS_CURR_FANPWM, 1346 speed); 1347 } 1348 1349 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu, 1350 uint32_t *speed) 1351 { 1352 if (!speed) 1353 return -EINVAL; 1354 1355 return smu_v13_0_0_get_smu_metrics_data(smu, 1356 METRICS_CURR_FANSPEED, 1357 speed); 1358 } 1359 1360 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu) 1361 { 1362 struct smu_table_context *table_context = &smu->smu_table; 1363 PPTable_t *pptable = table_context->driver_pptable; 1364 SkuTable_t *skutable = &pptable->SkuTable; 1365 1366 /* 1367 * Skip the MGpuFanBoost setting for those ASICs 1368 * which do not support it 1369 */ 1370 if (skutable->MGpuAcousticLimitRpmThreshold == 0) 1371 return 0; 1372 1373 return smu_cmn_send_smc_msg_with_param(smu, 1374 SMU_MSG_SetMGpuFanBoostLimitRpm, 1375 0, 1376 NULL); 1377 } 1378 1379 static int smu_v13_0_0_get_power_limit(struct smu_context *smu, 1380 uint32_t *current_power_limit, 1381 uint32_t *default_power_limit, 1382 uint32_t *max_power_limit) 1383 { 1384 struct smu_table_context *table_context = &smu->smu_table; 1385 struct smu_13_0_0_powerplay_table *powerplay_table = 1386 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table; 1387 PPTable_t *pptable = table_context->driver_pptable; 1388 SkuTable_t *skutable = &pptable->SkuTable; 1389 uint32_t power_limit, od_percent; 1390 1391 if (smu_v13_0_get_current_power_limit(smu, &power_limit)) 1392 power_limit = smu->adev->pm.ac_power ? 1393 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] : 1394 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0]; 1395 1396 if (current_power_limit) 1397 *current_power_limit = power_limit; 1398 if (default_power_limit) 1399 *default_power_limit = power_limit; 1400 1401 if (max_power_limit) { 1402 if (smu->od_enabled) { 1403 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]); 1404 1405 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1406 1407 power_limit *= (100 + od_percent); 1408 power_limit /= 100; 1409 } 1410 *max_power_limit = power_limit; 1411 } 1412 1413 return 0; 1414 } 1415 1416 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu, 1417 char *buf) 1418 { 1419 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1420 DpmActivityMonitorCoeffInt_t *activity_monitor = 1421 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1422 static const char *title[] = { 1423 "PROFILE_INDEX(NAME)", 1424 "CLOCK_TYPE(NAME)", 1425 "FPS", 1426 "MinActiveFreqType", 1427 "MinActiveFreq", 1428 "BoosterFreqType", 1429 "BoosterFreq", 1430 "PD_Data_limit_c", 1431 "PD_Data_error_coeff", 1432 "PD_Data_error_rate_coeff"}; 1433 int16_t workload_type = 0; 1434 uint32_t i, size = 0; 1435 int result = 0; 1436 1437 if (!buf) 1438 return -EINVAL; 1439 1440 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n", 1441 title[0], title[1], title[2], title[3], title[4], title[5], 1442 title[6], title[7], title[8], title[9]); 1443 1444 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1445 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1446 workload_type = smu_cmn_to_asic_specific_index(smu, 1447 CMN2ASIC_MAPPING_WORKLOAD, 1448 i); 1449 if (workload_type < 0) 1450 return -EINVAL; 1451 1452 result = smu_cmn_update_table(smu, 1453 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1454 workload_type, 1455 (void *)(&activity_monitor_external), 1456 false); 1457 if (result) { 1458 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1459 return result; 1460 } 1461 1462 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1463 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1464 1465 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n", 1466 " ", 1467 0, 1468 "GFXCLK", 1469 activity_monitor->Gfx_FPS, 1470 activity_monitor->Gfx_MinActiveFreqType, 1471 activity_monitor->Gfx_MinActiveFreq, 1472 activity_monitor->Gfx_BoosterFreqType, 1473 activity_monitor->Gfx_BoosterFreq, 1474 activity_monitor->Gfx_PD_Data_limit_c, 1475 activity_monitor->Gfx_PD_Data_error_coeff, 1476 activity_monitor->Gfx_PD_Data_error_rate_coeff); 1477 1478 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n", 1479 " ", 1480 1, 1481 "FCLK", 1482 activity_monitor->Fclk_FPS, 1483 activity_monitor->Fclk_MinActiveFreqType, 1484 activity_monitor->Fclk_MinActiveFreq, 1485 activity_monitor->Fclk_BoosterFreqType, 1486 activity_monitor->Fclk_BoosterFreq, 1487 activity_monitor->Fclk_PD_Data_limit_c, 1488 activity_monitor->Fclk_PD_Data_error_coeff, 1489 activity_monitor->Fclk_PD_Data_error_rate_coeff); 1490 } 1491 1492 return size; 1493 } 1494 1495 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, 1496 long *input, 1497 uint32_t size) 1498 { 1499 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1500 DpmActivityMonitorCoeffInt_t *activity_monitor = 1501 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1502 int workload_type, ret = 0; 1503 1504 smu->power_profile_mode = input[size]; 1505 1506 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1507 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1508 return -EINVAL; 1509 } 1510 1511 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1512 ret = smu_cmn_update_table(smu, 1513 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1514 WORKLOAD_PPLIB_CUSTOM_BIT, 1515 (void *)(&activity_monitor_external), 1516 false); 1517 if (ret) { 1518 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1519 return ret; 1520 } 1521 1522 switch (input[0]) { 1523 case 0: /* Gfxclk */ 1524 activity_monitor->Gfx_FPS = input[1]; 1525 activity_monitor->Gfx_MinActiveFreqType = input[2]; 1526 activity_monitor->Gfx_MinActiveFreq = input[3]; 1527 activity_monitor->Gfx_BoosterFreqType = input[4]; 1528 activity_monitor->Gfx_BoosterFreq = input[5]; 1529 activity_monitor->Gfx_PD_Data_limit_c = input[6]; 1530 activity_monitor->Gfx_PD_Data_error_coeff = input[7]; 1531 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[8]; 1532 break; 1533 case 1: /* Fclk */ 1534 activity_monitor->Fclk_FPS = input[1]; 1535 activity_monitor->Fclk_MinActiveFreqType = input[2]; 1536 activity_monitor->Fclk_MinActiveFreq = input[3]; 1537 activity_monitor->Fclk_BoosterFreqType = input[4]; 1538 activity_monitor->Fclk_BoosterFreq = input[5]; 1539 activity_monitor->Fclk_PD_Data_limit_c = input[6]; 1540 activity_monitor->Fclk_PD_Data_error_coeff = input[7]; 1541 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8]; 1542 break; 1543 } 1544 1545 ret = smu_cmn_update_table(smu, 1546 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1547 WORKLOAD_PPLIB_CUSTOM_BIT, 1548 (void *)(&activity_monitor_external), 1549 true); 1550 if (ret) { 1551 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1552 return ret; 1553 } 1554 } 1555 1556 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1557 workload_type = smu_cmn_to_asic_specific_index(smu, 1558 CMN2ASIC_MAPPING_WORKLOAD, 1559 smu->power_profile_mode); 1560 if (workload_type < 0) 1561 return -EINVAL; 1562 1563 return smu_cmn_send_smc_msg_with_param(smu, 1564 SMU_MSG_SetWorkloadMask, 1565 1 << workload_type, 1566 NULL); 1567 } 1568 1569 static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu) 1570 { 1571 struct amdgpu_device *adev = smu->adev; 1572 u32 smu_version; 1573 1574 /* SRIOV does not support SMU mode1 reset */ 1575 if (amdgpu_sriov_vf(adev)) 1576 return false; 1577 1578 /* PMFW support is available since 78.41 */ 1579 smu_cmn_get_smc_version(smu, NULL, &smu_version); 1580 if (smu_version < 0x004e2900) 1581 return false; 1582 1583 return true; 1584 } 1585 1586 static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap, 1587 struct i2c_msg *msg, int num_msgs) 1588 { 1589 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 1590 struct amdgpu_device *adev = smu_i2c->adev; 1591 struct smu_context *smu = adev->powerplay.pp_handle; 1592 struct smu_table_context *smu_table = &smu->smu_table; 1593 struct smu_table *table = &smu_table->driver_table; 1594 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 1595 int i, j, r, c; 1596 u16 dir; 1597 1598 if (!adev->pm.dpm_enabled) 1599 return -EBUSY; 1600 1601 req = kzalloc(sizeof(*req), GFP_KERNEL); 1602 if (!req) 1603 return -ENOMEM; 1604 1605 req->I2CcontrollerPort = smu_i2c->port; 1606 req->I2CSpeed = I2C_SPEED_FAST_400K; 1607 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 1608 dir = msg[0].flags & I2C_M_RD; 1609 1610 for (c = i = 0; i < num_msgs; i++) { 1611 for (j = 0; j < msg[i].len; j++, c++) { 1612 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 1613 1614 if (!(msg[i].flags & I2C_M_RD)) { 1615 /* write */ 1616 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 1617 cmd->ReadWriteData = msg[i].buf[j]; 1618 } 1619 1620 if ((dir ^ msg[i].flags) & I2C_M_RD) { 1621 /* The direction changes. 1622 */ 1623 dir = msg[i].flags & I2C_M_RD; 1624 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 1625 } 1626 1627 req->NumCmds++; 1628 1629 /* 1630 * Insert STOP if we are at the last byte of either last 1631 * message for the transaction or the client explicitly 1632 * requires a STOP at this particular message. 1633 */ 1634 if ((j == msg[i].len - 1) && 1635 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 1636 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 1637 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 1638 } 1639 } 1640 } 1641 mutex_lock(&adev->pm.mutex); 1642 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 1643 mutex_unlock(&adev->pm.mutex); 1644 if (r) 1645 goto fail; 1646 1647 for (c = i = 0; i < num_msgs; i++) { 1648 if (!(msg[i].flags & I2C_M_RD)) { 1649 c += msg[i].len; 1650 continue; 1651 } 1652 for (j = 0; j < msg[i].len; j++, c++) { 1653 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 1654 1655 msg[i].buf[j] = cmd->ReadWriteData; 1656 } 1657 } 1658 r = num_msgs; 1659 fail: 1660 kfree(req); 1661 return r; 1662 } 1663 1664 static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap) 1665 { 1666 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1667 } 1668 1669 static const struct i2c_algorithm smu_v13_0_0_i2c_algo = { 1670 .master_xfer = smu_v13_0_0_i2c_xfer, 1671 .functionality = smu_v13_0_0_i2c_func, 1672 }; 1673 1674 static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = { 1675 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 1676 .max_read_len = MAX_SW_I2C_COMMANDS, 1677 .max_write_len = MAX_SW_I2C_COMMANDS, 1678 .max_comb_1st_msg_len = 2, 1679 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 1680 }; 1681 1682 static int smu_v13_0_0_i2c_control_init(struct smu_context *smu) 1683 { 1684 struct amdgpu_device *adev = smu->adev; 1685 int res, i; 1686 1687 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 1688 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1689 struct i2c_adapter *control = &smu_i2c->adapter; 1690 1691 smu_i2c->adev = adev; 1692 smu_i2c->port = i; 1693 mutex_init(&smu_i2c->mutex); 1694 control->owner = THIS_MODULE; 1695 control->class = I2C_CLASS_SPD; 1696 control->dev.parent = &adev->pdev->dev; 1697 control->algo = &smu_v13_0_0_i2c_algo; 1698 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 1699 control->quirks = &smu_v13_0_0_i2c_control_quirks; 1700 i2c_set_adapdata(control, smu_i2c); 1701 1702 res = i2c_add_adapter(control); 1703 if (res) { 1704 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 1705 goto Out_err; 1706 } 1707 } 1708 1709 /* assign the buses used for the FRU EEPROM and RAS EEPROM */ 1710 /* XXX ideally this would be something in a vbios data table */ 1711 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 1712 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 1713 1714 return 0; 1715 Out_err: 1716 for ( ; i >= 0; i--) { 1717 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1718 struct i2c_adapter *control = &smu_i2c->adapter; 1719 1720 i2c_del_adapter(control); 1721 } 1722 return res; 1723 } 1724 1725 static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu) 1726 { 1727 struct amdgpu_device *adev = smu->adev; 1728 int i; 1729 1730 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 1731 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 1732 struct i2c_adapter *control = &smu_i2c->adapter; 1733 1734 i2c_del_adapter(control); 1735 } 1736 adev->pm.ras_eeprom_i2c_bus = NULL; 1737 adev->pm.fru_eeprom_i2c_bus = NULL; 1738 } 1739 1740 static int smu_v13_0_0_set_mp1_state(struct smu_context *smu, 1741 enum pp_mp1_state mp1_state) 1742 { 1743 int ret; 1744 1745 switch (mp1_state) { 1746 case PP_MP1_STATE_UNLOAD: 1747 ret = smu_cmn_set_mp1_state(smu, mp1_state); 1748 break; 1749 default: 1750 /* Ignore others */ 1751 ret = 0; 1752 } 1753 1754 return ret; 1755 } 1756 1757 static int smu_v13_0_0_set_df_cstate(struct smu_context *smu, 1758 enum pp_df_cstate state) 1759 { 1760 return smu_cmn_send_smc_msg_with_param(smu, 1761 SMU_MSG_DFCstateControl, 1762 state, 1763 NULL); 1764 } 1765 1766 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { 1767 .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask, 1768 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table, 1769 .i2c_init = smu_v13_0_0_i2c_control_init, 1770 .i2c_fini = smu_v13_0_0_i2c_control_fini, 1771 .is_dpm_running = smu_v13_0_0_is_dpm_running, 1772 .dump_pptable = smu_v13_0_0_dump_pptable, 1773 .init_microcode = smu_v13_0_init_microcode, 1774 .load_microcode = smu_v13_0_load_microcode, 1775 .fini_microcode = smu_v13_0_fini_microcode, 1776 .init_smc_tables = smu_v13_0_0_init_smc_tables, 1777 .fini_smc_tables = smu_v13_0_fini_smc_tables, 1778 .init_power = smu_v13_0_init_power, 1779 .fini_power = smu_v13_0_fini_power, 1780 .check_fw_status = smu_v13_0_check_fw_status, 1781 .setup_pptable = smu_v13_0_0_setup_pptable, 1782 .check_fw_version = smu_v13_0_check_fw_version, 1783 .write_pptable = smu_cmn_write_pptable, 1784 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1785 .system_features_control = smu_v13_0_0_system_features_control, 1786 .set_allowed_mask = smu_v13_0_set_allowed_mask, 1787 .get_enabled_mask = smu_cmn_get_enabled_mask, 1788 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, 1789 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, 1790 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 1791 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1792 .read_sensor = smu_v13_0_0_read_sensor, 1793 .feature_is_enabled = smu_cmn_feature_is_enabled, 1794 .print_clk_levels = smu_v13_0_0_print_clk_levels, 1795 .force_clk_levels = smu_v13_0_0_force_clk_levels, 1796 .update_pcie_parameters = smu_v13_0_0_update_pcie_parameters, 1797 .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range, 1798 .register_irq_handler = smu_v13_0_register_irq_handler, 1799 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 1800 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 1801 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 1802 .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics, 1803 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range, 1804 .init_pptable_microcode = smu_v13_0_init_pptable_microcode, 1805 .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk, 1806 .set_performance_level = smu_v13_0_set_performance_level, 1807 .gfx_off_control = smu_v13_0_gfx_off_control, 1808 .get_unique_id = smu_v13_0_0_get_unique_id, 1809 .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm, 1810 .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm, 1811 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm, 1812 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm, 1813 .get_fan_control_mode = smu_v13_0_get_fan_control_mode, 1814 .set_fan_control_mode = smu_v13_0_set_fan_control_mode, 1815 .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost, 1816 .get_power_limit = smu_v13_0_0_get_power_limit, 1817 .set_power_limit = smu_v13_0_set_power_limit, 1818 .set_power_source = smu_v13_0_set_power_source, 1819 .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode, 1820 .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode, 1821 .run_btc = smu_v13_0_run_btc, 1822 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1823 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1824 .set_tool_table_location = smu_v13_0_set_tool_table_location, 1825 .deep_sleep_control = smu_v13_0_deep_sleep_control, 1826 .gfx_ulv_control = smu_v13_0_gfx_ulv_control, 1827 .baco_is_support = smu_v13_0_baco_is_support, 1828 .baco_get_state = smu_v13_0_baco_get_state, 1829 .baco_set_state = smu_v13_0_baco_set_state, 1830 .baco_enter = smu_v13_0_baco_enter, 1831 .baco_exit = smu_v13_0_baco_exit, 1832 .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported, 1833 .mode1_reset = smu_v13_0_mode1_reset, 1834 .set_mp1_state = smu_v13_0_0_set_mp1_state, 1835 .set_df_cstate = smu_v13_0_0_set_df_cstate, 1836 }; 1837 1838 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) 1839 { 1840 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs; 1841 smu->message_map = smu_v13_0_0_message_map; 1842 smu->clock_map = smu_v13_0_0_clk_map; 1843 smu->feature_map = smu_v13_0_0_feature_mask_map; 1844 smu->table_map = smu_v13_0_0_table_map; 1845 smu->pwr_src_map = smu_v13_0_0_pwr_src_map; 1846 smu->workload_map = smu_v13_0_0_workload_map; 1847 smu_v13_0_set_smu_mailbox_registers(smu); 1848 } 1849