1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "smu_types.h" 25 #define SWSMU_CODE_LAYER_L2 26 27 #include "amdgpu.h" 28 #include "amdgpu_smu.h" 29 #include "smu_v13_0.h" 30 #include "smu13_driver_if_v13_0_4.h" 31 #include "smu_v13_0_4_ppt.h" 32 #include "smu_v13_0_4_ppsmc.h" 33 #include "smu_v13_0_4_pmfw.h" 34 #include "smu_cmn.h" 35 36 /* 37 * DO NOT use these for err/warn/info/debug messages. 38 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 39 * They are more MGPU friendly. 40 */ 41 #undef pr_err 42 #undef pr_warn 43 #undef pr_info 44 #undef pr_debug 45 46 #define FEATURE_MASK(feature) (1ULL << feature) 47 48 #define SMC_DPM_FEATURE ( \ 49 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 50 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 51 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 52 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 53 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 54 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 55 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 56 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \ 57 FEATURE_MASK(FEATURE_ISP_DPM_BIT) | \ 58 FEATURE_MASK(FEATURE_IPU_DPM_BIT) | \ 59 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 60 61 static struct cmn2asic_msg_mapping smu_v13_0_4_message_map[SMU_MSG_MAX_COUNT] = { 62 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 63 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetPmfwVersion, 1), 64 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 65 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 1), 66 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1), 67 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1), 68 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 69 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 70 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 71 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 72 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 73 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 74 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 75 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), 76 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 77 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1), 78 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), 79 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 80 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 81 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1), 82 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 83 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 84 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), 85 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), 86 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 87 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1), 88 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 89 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 90 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), 91 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1), 92 MSG_MAP(EnableGfxImu, PPSMC_MSG_EnableGfxImu, 1), 93 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1), 94 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1), 95 }; 96 97 static struct cmn2asic_mapping smu_v13_0_4_feature_mask_map[SMU_FEATURE_COUNT] = { 98 FEA_MAP(CCLK_DPM), 99 FEA_MAP(FAN_CONTROLLER), 100 FEA_MAP(PPT), 101 FEA_MAP(TDC), 102 FEA_MAP(THERMAL), 103 FEA_MAP(VCN_DPM), 104 FEA_MAP_REVERSE(FCLK), 105 FEA_MAP_REVERSE(SOCCLK), 106 FEA_MAP(LCLK_DPM), 107 FEA_MAP(SHUBCLK_DPM), 108 FEA_MAP(DCFCLK_DPM), 109 FEA_MAP_HALF_REVERSE(GFX), 110 FEA_MAP(DS_GFXCLK), 111 FEA_MAP(DS_SOCCLK), 112 FEA_MAP(DS_LCLK), 113 FEA_MAP(DS_DCFCLK), 114 FEA_MAP(DS_FCLK), 115 FEA_MAP(DS_MP1CLK), 116 FEA_MAP(DS_MP0CLK), 117 FEA_MAP(GFX_DEM), 118 FEA_MAP(PSI), 119 FEA_MAP(PROCHOT), 120 FEA_MAP(CPUOFF), 121 FEA_MAP(STAPM), 122 FEA_MAP(S0I3), 123 FEA_MAP(PERF_LIMIT), 124 FEA_MAP(CORE_DLDO), 125 FEA_MAP(DS_VCN), 126 FEA_MAP(CPPC), 127 FEA_MAP(DF_CSTATES), 128 FEA_MAP(ATHUB_PG), 129 }; 130 131 static struct cmn2asic_mapping smu_v13_0_4_table_map[SMU_TABLE_COUNT] = { 132 TAB_MAP_VALID(WATERMARKS), 133 TAB_MAP_VALID(SMU_METRICS), 134 TAB_MAP_VALID(CUSTOM_DPM), 135 TAB_MAP_VALID(DPMCLOCKS), 136 }; 137 138 static int smu_v13_0_4_init_smc_tables(struct smu_context *smu) 139 { 140 struct smu_table_context *smu_table = &smu->smu_table; 141 struct smu_table *tables = smu_table->tables; 142 143 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 144 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 145 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 146 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 147 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 148 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 149 150 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 151 if (!smu_table->clocks_table) 152 goto err0_out; 153 154 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 155 if (!smu_table->metrics_table) 156 goto err1_out; 157 smu_table->metrics_time = 0; 158 159 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 160 if (!smu_table->watermarks_table) 161 goto err2_out; 162 163 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); 164 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 165 if (!smu_table->gpu_metrics_table) 166 goto err3_out; 167 168 return 0; 169 170 err3_out: 171 kfree(smu_table->watermarks_table); 172 err2_out: 173 kfree(smu_table->metrics_table); 174 err1_out: 175 kfree(smu_table->clocks_table); 176 err0_out: 177 return -ENOMEM; 178 } 179 180 static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu) 181 { 182 struct smu_table_context *smu_table = &smu->smu_table; 183 184 kfree(smu_table->clocks_table); 185 smu_table->clocks_table = NULL; 186 187 kfree(smu_table->metrics_table); 188 smu_table->metrics_table = NULL; 189 190 kfree(smu_table->watermarks_table); 191 smu_table->watermarks_table = NULL; 192 193 return 0; 194 } 195 196 static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu) 197 { 198 int ret = 0; 199 uint64_t feature_enabled; 200 201 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 202 203 if (ret) 204 return false; 205 206 return !!(feature_enabled & SMC_DPM_FEATURE); 207 } 208 209 static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en) 210 { 211 struct amdgpu_device *adev = smu->adev; 212 int ret = 0; 213 /* SMU fw need this message to trigger IMU to complete the initialization */ 214 if (en) 215 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxImu, NULL); 216 else { 217 if (!adev->in_s0ix) 218 ret = smu_cmn_send_smc_msg(smu, 219 SMU_MSG_PrepareMp1ForUnload, 220 NULL); 221 } 222 return ret; 223 } 224 225 static int smu_v13_0_4_post_smu_init(struct smu_context *smu) 226 { 227 struct amdgpu_device *adev = smu->adev; 228 int ret = 0; 229 230 /* allow message will be sent after enable message */ 231 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL); 232 if (ret) 233 dev_err(adev->dev, "Failed to Enable GfxOff!\n"); 234 return ret; 235 } 236 237 static ssize_t smu_v13_0_4_get_gpu_metrics(struct smu_context *smu, 238 void **table) 239 { 240 struct smu_table_context *smu_table = &smu->smu_table; 241 struct gpu_metrics_v2_1 *gpu_metrics = 242 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; 243 SmuMetrics_t metrics; 244 int ret = 0; 245 246 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 247 if (ret) 248 return ret; 249 250 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); 251 252 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 253 gpu_metrics->temperature_soc = metrics.SocTemperature; 254 memcpy(&gpu_metrics->temperature_core[0], 255 &metrics.CoreTemperature[0], 256 sizeof(uint16_t) * 8); 257 gpu_metrics->temperature_l3[0] = metrics.L3Temperature; 258 259 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 260 gpu_metrics->average_mm_activity = metrics.UvdActivity; 261 262 gpu_metrics->average_socket_power = metrics.CurrentSocketPower; 263 gpu_metrics->average_gfx_power = metrics.Power[0]; 264 gpu_metrics->average_soc_power = metrics.Power[1]; 265 memcpy(&gpu_metrics->average_core_power[0], 266 &metrics.CorePower[0], 267 sizeof(uint16_t) * 8); 268 269 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 270 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 271 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 272 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 273 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 274 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 275 276 memcpy(&gpu_metrics->current_coreclk[0], 277 &metrics.CoreFrequency[0], 278 sizeof(uint16_t) * 8); 279 gpu_metrics->current_l3clk[0] = metrics.L3Frequency; 280 281 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 282 283 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 284 285 *table = (void *)gpu_metrics; 286 287 return sizeof(struct gpu_metrics_v2_1); 288 } 289 290 static int smu_v13_0_4_get_smu_metrics_data(struct smu_context *smu, 291 MetricsMember_t member, 292 uint32_t *value) 293 { 294 struct smu_table_context *smu_table = &smu->smu_table; 295 296 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 297 int ret = 0; 298 299 ret = smu_cmn_get_metrics_table(smu, NULL, false); 300 if (ret) 301 return ret; 302 303 switch (member) { 304 case METRICS_AVERAGE_GFXCLK: 305 *value = metrics->GfxclkFrequency; 306 break; 307 case METRICS_AVERAGE_SOCCLK: 308 *value = metrics->SocclkFrequency; 309 break; 310 case METRICS_AVERAGE_VCLK: 311 *value = metrics->VclkFrequency; 312 break; 313 case METRICS_AVERAGE_DCLK: 314 *value = metrics->DclkFrequency; 315 break; 316 case METRICS_AVERAGE_UCLK: 317 *value = metrics->MemclkFrequency; 318 break; 319 case METRICS_AVERAGE_GFXACTIVITY: 320 *value = metrics->GfxActivity / 100; 321 break; 322 case METRICS_AVERAGE_VCNACTIVITY: 323 *value = metrics->UvdActivity; 324 break; 325 case METRICS_AVERAGE_SOCKETPOWER: 326 *value = (metrics->CurrentSocketPower << 8) / 1000; 327 break; 328 case METRICS_TEMPERATURE_EDGE: 329 *value = metrics->GfxTemperature / 100 * 330 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 331 break; 332 case METRICS_TEMPERATURE_HOTSPOT: 333 *value = metrics->SocTemperature / 100 * 334 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 335 break; 336 case METRICS_THROTTLER_STATUS: 337 *value = metrics->ThrottlerStatus; 338 break; 339 case METRICS_VOLTAGE_VDDGFX: 340 *value = metrics->Voltage[0]; 341 break; 342 case METRICS_VOLTAGE_VDDSOC: 343 *value = metrics->Voltage[1]; 344 break; 345 case METRICS_SS_APU_SHARE: 346 /* return the percentage of APU power with respect to APU's power limit. 347 * percentage is reported, this isn't boost value. Smartshift power 348 * boost/shift is only when the percentage is more than 100. 349 */ 350 if (metrics->StapmOpnLimit > 0) 351 *value = (metrics->ApuPower * 100) / metrics->StapmOpnLimit; 352 else 353 *value = 0; 354 break; 355 case METRICS_SS_DGPU_SHARE: 356 /* return the percentage of dGPU power with respect to dGPU's power limit. 357 * percentage is reported, this isn't boost value. Smartshift power 358 * boost/shift is only when the percentage is more than 100. 359 */ 360 if ((metrics->dGpuPower > 0) && 361 (metrics->StapmCurrentLimit > metrics->StapmOpnLimit)) 362 *value = (metrics->dGpuPower * 100) / 363 (metrics->StapmCurrentLimit - metrics->StapmOpnLimit); 364 else 365 *value = 0; 366 break; 367 default: 368 *value = UINT_MAX; 369 break; 370 } 371 372 return ret; 373 } 374 375 static int smu_v13_0_4_get_current_clk_freq(struct smu_context *smu, 376 enum smu_clk_type clk_type, 377 uint32_t *value) 378 { 379 MetricsMember_t member_type; 380 381 switch (clk_type) { 382 case SMU_SOCCLK: 383 member_type = METRICS_AVERAGE_SOCCLK; 384 break; 385 case SMU_VCLK: 386 member_type = METRICS_AVERAGE_VCLK; 387 break; 388 case SMU_DCLK: 389 member_type = METRICS_AVERAGE_DCLK; 390 break; 391 case SMU_MCLK: 392 member_type = METRICS_AVERAGE_UCLK; 393 break; 394 case SMU_FCLK: 395 return smu_cmn_send_smc_msg_with_param(smu, 396 SMU_MSG_GetFclkFrequency, 397 0, value); 398 case SMU_GFXCLK: 399 case SMU_SCLK: 400 return smu_cmn_send_smc_msg_with_param(smu, 401 SMU_MSG_GetGfxclkFrequency, 402 0, value); 403 break; 404 default: 405 return -EINVAL; 406 } 407 408 return smu_v13_0_4_get_smu_metrics_data(smu, member_type, value); 409 } 410 411 static int smu_v13_0_4_get_dpm_freq_by_index(struct smu_context *smu, 412 enum smu_clk_type clk_type, 413 uint32_t dpm_level, 414 uint32_t *freq) 415 { 416 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 417 418 if (!clk_table || clk_type >= SMU_CLK_COUNT) 419 return -EINVAL; 420 421 switch (clk_type) { 422 case SMU_SOCCLK: 423 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 424 return -EINVAL; 425 *freq = clk_table->SocClocks[dpm_level]; 426 break; 427 case SMU_VCLK: 428 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 429 return -EINVAL; 430 *freq = clk_table->VClocks[dpm_level]; 431 break; 432 case SMU_DCLK: 433 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 434 return -EINVAL; 435 *freq = clk_table->DClocks[dpm_level]; 436 break; 437 case SMU_UCLK: 438 case SMU_MCLK: 439 if (dpm_level >= clk_table->NumDfPstatesEnabled) 440 return -EINVAL; 441 *freq = clk_table->DfPstateTable[dpm_level].MemClk; 442 break; 443 case SMU_FCLK: 444 if (dpm_level >= clk_table->NumDfPstatesEnabled) 445 return -EINVAL; 446 *freq = clk_table->DfPstateTable[dpm_level].FClk; 447 break; 448 default: 449 return -EINVAL; 450 } 451 452 return 0; 453 } 454 455 static int smu_v13_0_4_get_dpm_level_count(struct smu_context *smu, 456 enum smu_clk_type clk_type, 457 uint32_t *count) 458 { 459 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 460 461 switch (clk_type) { 462 case SMU_SOCCLK: 463 *count = clk_table->NumSocClkLevelsEnabled; 464 break; 465 case SMU_VCLK: 466 *count = clk_table->VcnClkLevelsEnabled; 467 break; 468 case SMU_DCLK: 469 *count = clk_table->VcnClkLevelsEnabled; 470 break; 471 case SMU_MCLK: 472 *count = clk_table->NumDfPstatesEnabled; 473 break; 474 case SMU_FCLK: 475 *count = clk_table->NumDfPstatesEnabled; 476 break; 477 default: 478 break; 479 } 480 481 return 0; 482 } 483 484 static int smu_v13_0_4_print_clk_levels(struct smu_context *smu, 485 enum smu_clk_type clk_type, char *buf) 486 { 487 int i, size = 0, ret = 0; 488 uint32_t cur_value = 0, value = 0, count = 0; 489 uint32_t min, max; 490 491 smu_cmn_get_sysfs_buf(&buf, &size); 492 493 switch (clk_type) { 494 case SMU_OD_SCLK: 495 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 496 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 497 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 498 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 499 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 500 break; 501 case SMU_OD_RANGE: 502 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 503 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 504 smu->gfx_default_hard_min_freq, 505 smu->gfx_default_soft_max_freq); 506 break; 507 case SMU_SOCCLK: 508 case SMU_VCLK: 509 case SMU_DCLK: 510 case SMU_MCLK: 511 case SMU_FCLK: 512 ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value); 513 if (ret) 514 break; 515 516 ret = smu_v13_0_4_get_dpm_level_count(smu, clk_type, &count); 517 if (ret) 518 break; 519 520 for (i = 0; i < count; i++) { 521 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, i, &value); 522 if (ret) 523 break; 524 525 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 526 cur_value == value ? "*" : ""); 527 } 528 break; 529 case SMU_GFXCLK: 530 case SMU_SCLK: 531 ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value); 532 if (ret) 533 break; 534 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 535 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 536 if (cur_value == max) 537 i = 2; 538 else if (cur_value == min) 539 i = 0; 540 else 541 i = 1; 542 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, 543 i == 0 ? "*" : ""); 544 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 545 i == 1 ? cur_value : 1100, /* UMD PSTATE GFXCLK 1100 */ 546 i == 1 ? "*" : ""); 547 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, 548 i == 2 ? "*" : ""); 549 break; 550 default: 551 break; 552 } 553 554 return size; 555 } 556 557 static int smu_v13_0_4_read_sensor(struct smu_context *smu, 558 enum amd_pp_sensors sensor, 559 void *data, uint32_t *size) 560 { 561 int ret = 0; 562 563 if (!data || !size) 564 return -EINVAL; 565 566 switch (sensor) { 567 case AMDGPU_PP_SENSOR_GPU_LOAD: 568 ret = smu_v13_0_4_get_smu_metrics_data(smu, 569 METRICS_AVERAGE_GFXACTIVITY, 570 (uint32_t *)data); 571 *size = 4; 572 break; 573 case AMDGPU_PP_SENSOR_GPU_POWER: 574 ret = smu_v13_0_4_get_smu_metrics_data(smu, 575 METRICS_AVERAGE_SOCKETPOWER, 576 (uint32_t *)data); 577 *size = 4; 578 break; 579 case AMDGPU_PP_SENSOR_EDGE_TEMP: 580 ret = smu_v13_0_4_get_smu_metrics_data(smu, 581 METRICS_TEMPERATURE_EDGE, 582 (uint32_t *)data); 583 *size = 4; 584 break; 585 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 586 ret = smu_v13_0_4_get_smu_metrics_data(smu, 587 METRICS_TEMPERATURE_HOTSPOT, 588 (uint32_t *)data); 589 *size = 4; 590 break; 591 case AMDGPU_PP_SENSOR_GFX_MCLK: 592 ret = smu_v13_0_4_get_smu_metrics_data(smu, 593 METRICS_AVERAGE_UCLK, 594 (uint32_t *)data); 595 *(uint32_t *)data *= 100; 596 *size = 4; 597 break; 598 case AMDGPU_PP_SENSOR_GFX_SCLK: 599 ret = smu_v13_0_4_get_smu_metrics_data(smu, 600 METRICS_AVERAGE_GFXCLK, 601 (uint32_t *)data); 602 *(uint32_t *)data *= 100; 603 *size = 4; 604 break; 605 case AMDGPU_PP_SENSOR_VDDGFX: 606 ret = smu_v13_0_4_get_smu_metrics_data(smu, 607 METRICS_VOLTAGE_VDDGFX, 608 (uint32_t *)data); 609 *size = 4; 610 break; 611 case AMDGPU_PP_SENSOR_VDDNB: 612 ret = smu_v13_0_4_get_smu_metrics_data(smu, 613 METRICS_VOLTAGE_VDDSOC, 614 (uint32_t *)data); 615 *size = 4; 616 break; 617 case AMDGPU_PP_SENSOR_SS_APU_SHARE: 618 ret = smu_v13_0_4_get_smu_metrics_data(smu, 619 METRICS_SS_APU_SHARE, 620 (uint32_t *)data); 621 *size = 4; 622 break; 623 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: 624 ret = smu_v13_0_4_get_smu_metrics_data(smu, 625 METRICS_SS_DGPU_SHARE, 626 (uint32_t *)data); 627 *size = 4; 628 break; 629 default: 630 ret = -EOPNOTSUPP; 631 break; 632 } 633 634 return ret; 635 } 636 637 static int smu_v13_0_4_set_watermarks_table(struct smu_context *smu, 638 struct pp_smu_wm_range_sets *clock_ranges) 639 { 640 int i; 641 int ret = 0; 642 Watermarks_t *table = smu->smu_table.watermarks_table; 643 644 if (!table || !clock_ranges) 645 return -EINVAL; 646 647 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 648 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 649 return -EINVAL; 650 651 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 652 table->WatermarkRow[WM_DCFCLK][i].MinClock = 653 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 654 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 655 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 656 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 657 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 658 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 659 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 660 661 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 662 clock_ranges->reader_wm_sets[i].wm_inst; 663 } 664 665 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 666 table->WatermarkRow[WM_SOCCLK][i].MinClock = 667 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 668 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 669 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 670 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 671 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 672 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 673 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 674 675 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 676 clock_ranges->writer_wm_sets[i].wm_inst; 677 } 678 679 smu->watermarks_bitmap |= WATERMARKS_EXIST; 680 681 /* pass data to smu controller */ 682 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 683 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 684 ret = smu_cmn_write_watermarks_table(smu); 685 if (ret) { 686 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 687 return ret; 688 } 689 smu->watermarks_bitmap |= WATERMARKS_LOADED; 690 } 691 692 return 0; 693 } 694 695 static bool smu_v13_0_4_clk_dpm_is_enabled(struct smu_context *smu, 696 enum smu_clk_type clk_type) 697 { 698 enum smu_feature_mask feature_id = 0; 699 700 switch (clk_type) { 701 case SMU_MCLK: 702 case SMU_UCLK: 703 case SMU_FCLK: 704 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 705 break; 706 case SMU_GFXCLK: 707 case SMU_SCLK: 708 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 709 break; 710 case SMU_SOCCLK: 711 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 712 break; 713 case SMU_VCLK: 714 case SMU_DCLK: 715 feature_id = SMU_FEATURE_VCN_DPM_BIT; 716 break; 717 default: 718 return true; 719 } 720 721 return smu_cmn_feature_is_enabled(smu, feature_id); 722 } 723 724 static int smu_v13_0_4_get_dpm_ultimate_freq(struct smu_context *smu, 725 enum smu_clk_type clk_type, 726 uint32_t *min, 727 uint32_t *max) 728 { 729 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 730 uint32_t clock_limit; 731 uint32_t max_dpm_level, min_dpm_level; 732 int ret = 0; 733 734 if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type)) { 735 switch (clk_type) { 736 case SMU_MCLK: 737 case SMU_UCLK: 738 clock_limit = smu->smu_table.boot_values.uclk; 739 break; 740 case SMU_FCLK: 741 clock_limit = smu->smu_table.boot_values.fclk; 742 break; 743 case SMU_GFXCLK: 744 case SMU_SCLK: 745 clock_limit = smu->smu_table.boot_values.gfxclk; 746 break; 747 case SMU_SOCCLK: 748 clock_limit = smu->smu_table.boot_values.socclk; 749 break; 750 case SMU_VCLK: 751 clock_limit = smu->smu_table.boot_values.vclk; 752 break; 753 case SMU_DCLK: 754 clock_limit = smu->smu_table.boot_values.dclk; 755 break; 756 default: 757 clock_limit = 0; 758 break; 759 } 760 761 /* clock in Mhz unit */ 762 if (min) 763 *min = clock_limit / 100; 764 if (max) 765 *max = clock_limit / 100; 766 767 return 0; 768 } 769 770 if (max) { 771 switch (clk_type) { 772 case SMU_GFXCLK: 773 case SMU_SCLK: 774 *max = clk_table->MaxGfxClk; 775 break; 776 case SMU_MCLK: 777 case SMU_UCLK: 778 case SMU_FCLK: 779 max_dpm_level = 0; 780 break; 781 case SMU_SOCCLK: 782 max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1; 783 break; 784 case SMU_VCLK: 785 case SMU_DCLK: 786 max_dpm_level = clk_table->VcnClkLevelsEnabled - 1; 787 break; 788 default: 789 return -EINVAL; 790 } 791 792 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { 793 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, 794 max_dpm_level, 795 max); 796 if (ret) 797 return ret; 798 } 799 } 800 801 if (min) { 802 switch (clk_type) { 803 case SMU_GFXCLK: 804 case SMU_SCLK: 805 *min = clk_table->MinGfxClk; 806 break; 807 case SMU_MCLK: 808 case SMU_UCLK: 809 case SMU_FCLK: 810 min_dpm_level = clk_table->NumDfPstatesEnabled - 1; 811 break; 812 case SMU_SOCCLK: 813 min_dpm_level = 0; 814 break; 815 case SMU_VCLK: 816 case SMU_DCLK: 817 min_dpm_level = 0; 818 break; 819 default: 820 return -EINVAL; 821 } 822 823 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { 824 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, 825 min_dpm_level, 826 min); 827 } 828 } 829 830 return ret; 831 } 832 833 static int smu_v13_0_4_set_soft_freq_limited_range(struct smu_context *smu, 834 enum smu_clk_type clk_type, 835 uint32_t min, 836 uint32_t max) 837 { 838 enum smu_message_type msg_set_min, msg_set_max; 839 int ret = 0; 840 841 if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type)) 842 return -EINVAL; 843 844 switch (clk_type) { 845 case SMU_GFXCLK: 846 case SMU_SCLK: 847 msg_set_min = SMU_MSG_SetHardMinGfxClk; 848 msg_set_max = SMU_MSG_SetSoftMaxGfxClk; 849 break; 850 case SMU_FCLK: 851 msg_set_min = SMU_MSG_SetHardMinFclkByFreq; 852 msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq; 853 break; 854 case SMU_SOCCLK: 855 msg_set_min = SMU_MSG_SetHardMinSocclkByFreq; 856 msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq; 857 break; 858 case SMU_VCLK: 859 case SMU_DCLK: 860 msg_set_min = SMU_MSG_SetHardMinVcn; 861 msg_set_max = SMU_MSG_SetSoftMaxVcn; 862 break; 863 default: 864 return -EINVAL; 865 } 866 867 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL); 868 if (ret) 869 return ret; 870 871 return smu_cmn_send_smc_msg_with_param(smu, msg_set_max, 872 max, NULL); 873 } 874 875 static int smu_v13_0_4_force_clk_levels(struct smu_context *smu, 876 enum smu_clk_type clk_type, 877 uint32_t mask) 878 { 879 uint32_t soft_min_level = 0, soft_max_level = 0; 880 uint32_t min_freq = 0, max_freq = 0; 881 int ret = 0; 882 883 soft_min_level = mask ? (ffs(mask) - 1) : 0; 884 soft_max_level = mask ? (fls(mask) - 1) : 0; 885 886 switch (clk_type) { 887 case SMU_SOCCLK: 888 case SMU_FCLK: 889 case SMU_VCLK: 890 case SMU_DCLK: 891 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 892 if (ret) 893 break; 894 895 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 896 if (ret) 897 break; 898 899 ret = smu_v13_0_4_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 900 break; 901 default: 902 ret = -EINVAL; 903 break; 904 } 905 906 return ret; 907 } 908 909 static int smu_v13_0_4_set_performance_level(struct smu_context *smu, 910 enum amd_dpm_forced_level level) 911 { 912 struct amdgpu_device *adev = smu->adev; 913 uint32_t sclk_min = 0, sclk_max = 0; 914 uint32_t fclk_min = 0, fclk_max = 0; 915 uint32_t socclk_min = 0, socclk_max = 0; 916 int ret = 0; 917 918 switch (level) { 919 case AMD_DPM_FORCED_LEVEL_HIGH: 920 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max); 921 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max); 922 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max); 923 sclk_min = sclk_max; 924 fclk_min = fclk_max; 925 socclk_min = socclk_max; 926 break; 927 case AMD_DPM_FORCED_LEVEL_LOW: 928 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL); 929 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL); 930 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL); 931 sclk_max = sclk_min; 932 fclk_max = fclk_min; 933 socclk_max = socclk_min; 934 break; 935 case AMD_DPM_FORCED_LEVEL_AUTO: 936 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max); 937 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max); 938 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max); 939 break; 940 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 941 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 942 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 943 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 944 /* Temporarily do nothing since the optimal clocks haven't been provided yet */ 945 break; 946 case AMD_DPM_FORCED_LEVEL_MANUAL: 947 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 948 return 0; 949 default: 950 dev_err(adev->dev, "Invalid performance level %d\n", level); 951 return -EINVAL; 952 } 953 954 if (sclk_min && sclk_max) { 955 ret = smu_v13_0_4_set_soft_freq_limited_range(smu, 956 SMU_SCLK, 957 sclk_min, 958 sclk_max); 959 if (ret) 960 return ret; 961 962 smu->gfx_actual_hard_min_freq = sclk_min; 963 smu->gfx_actual_soft_max_freq = sclk_max; 964 } 965 966 if (fclk_min && fclk_max) { 967 ret = smu_v13_0_4_set_soft_freq_limited_range(smu, 968 SMU_FCLK, 969 fclk_min, 970 fclk_max); 971 if (ret) 972 return ret; 973 } 974 975 if (socclk_min && socclk_max) { 976 ret = smu_v13_0_4_set_soft_freq_limited_range(smu, 977 SMU_SOCCLK, 978 socclk_min, 979 socclk_max); 980 if (ret) 981 return ret; 982 } 983 984 return ret; 985 } 986 987 static int smu_v13_0_4_mode2_reset(struct smu_context *smu) 988 { 989 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, 990 SMU_RESET_MODE_2, NULL); 991 } 992 993 static int smu_v13_0_4_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 994 { 995 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 996 997 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 998 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 999 smu->gfx_actual_hard_min_freq = 0; 1000 smu->gfx_actual_soft_max_freq = 0; 1001 1002 return 0; 1003 } 1004 1005 static const struct pptable_funcs smu_v13_0_4_ppt_funcs = { 1006 .check_fw_status = smu_v13_0_check_fw_status, 1007 .check_fw_version = smu_v13_0_check_fw_version, 1008 .init_smc_tables = smu_v13_0_4_init_smc_tables, 1009 .fini_smc_tables = smu_v13_0_4_fini_smc_tables, 1010 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1011 .system_features_control = smu_v13_0_4_system_features_control, 1012 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1013 .send_smc_msg = smu_cmn_send_smc_msg, 1014 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, 1015 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, 1016 .set_default_dpm_table = smu_v13_0_set_default_dpm_tables, 1017 .read_sensor = smu_v13_0_4_read_sensor, 1018 .is_dpm_running = smu_v13_0_4_is_dpm_running, 1019 .set_watermarks_table = smu_v13_0_4_set_watermarks_table, 1020 .get_gpu_metrics = smu_v13_0_4_get_gpu_metrics, 1021 .get_enabled_mask = smu_cmn_get_enabled_mask, 1022 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1023 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1024 .gfx_off_control = smu_v13_0_gfx_off_control, 1025 .post_init = smu_v13_0_4_post_smu_init, 1026 .mode2_reset = smu_v13_0_4_mode2_reset, 1027 .get_dpm_ultimate_freq = smu_v13_0_4_get_dpm_ultimate_freq, 1028 .od_edit_dpm_table = smu_v13_0_od_edit_dpm_table, 1029 .print_clk_levels = smu_v13_0_4_print_clk_levels, 1030 .force_clk_levels = smu_v13_0_4_force_clk_levels, 1031 .set_performance_level = smu_v13_0_4_set_performance_level, 1032 .set_fine_grain_gfx_freq_parameters = smu_v13_0_4_set_fine_grain_gfx_freq_parameters, 1033 }; 1034 1035 void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu) 1036 { 1037 smu->ppt_funcs = &smu_v13_0_4_ppt_funcs; 1038 smu->message_map = smu_v13_0_4_message_map; 1039 smu->feature_map = smu_v13_0_4_feature_mask_map; 1040 smu->table_map = smu_v13_0_4_table_map; 1041 smu->is_apu = true; 1042 } 1043