1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_smu.h" 31 #include "atomfirmware.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_atombios.h" 34 #include "smu_v13_0.h" 35 #include "smu13_driver_if_v13_0_7.h" 36 #include "soc15_common.h" 37 #include "atom.h" 38 #include "smu_v13_0_7_ppt.h" 39 #include "smu_v13_0_7_pptable.h" 40 #include "smu_v13_0_7_ppsmc.h" 41 #include "nbio/nbio_4_3_0_offset.h" 42 #include "nbio/nbio_4_3_0_sh_mask.h" 43 #include "mp/mp_13_0_0_offset.h" 44 #include "mp/mp_13_0_0_sh_mask.h" 45 46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h" 47 #include "smu_cmn.h" 48 #include "amdgpu_ras.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define FEATURE_MASK(feature) (1ULL << feature) 63 #define SMC_DPM_FEATURE ( \ 64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 70 71 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028 72 73 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 74 75 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = { 76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 77 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 78 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 79 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 80 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 81 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 82 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 83 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 84 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 85 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 86 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 87 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 88 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 89 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 90 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 91 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 92 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 93 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 94 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 95 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 96 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 97 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 98 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 100 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 101 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 102 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 103 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 104 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 105 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 106 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 107 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 108 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 109 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 110 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 111 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 112 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 113 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 114 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 115 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 116 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 117 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 118 }; 119 120 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = { 121 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 122 CLK_MAP(SCLK, PPCLK_GFXCLK), 123 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 124 CLK_MAP(FCLK, PPCLK_FCLK), 125 CLK_MAP(UCLK, PPCLK_UCLK), 126 CLK_MAP(MCLK, PPCLK_UCLK), 127 CLK_MAP(VCLK, PPCLK_VCLK_0), 128 CLK_MAP(VCLK1, PPCLK_VCLK_1), 129 CLK_MAP(DCLK, PPCLK_DCLK_0), 130 CLK_MAP(DCLK1, PPCLK_DCLK_1), 131 }; 132 133 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = { 134 FEA_MAP(FW_DATA_READ), 135 FEA_MAP(DPM_GFXCLK), 136 FEA_MAP(DPM_GFX_POWER_OPTIMIZER), 137 FEA_MAP(DPM_UCLK), 138 FEA_MAP(DPM_FCLK), 139 FEA_MAP(DPM_SOCCLK), 140 FEA_MAP(DPM_MP0CLK), 141 FEA_MAP(DPM_LINK), 142 FEA_MAP(DPM_DCN), 143 FEA_MAP(VMEMP_SCALING), 144 FEA_MAP(VDDIO_MEM_SCALING), 145 FEA_MAP(DS_GFXCLK), 146 FEA_MAP(DS_SOCCLK), 147 FEA_MAP(DS_FCLK), 148 FEA_MAP(DS_LCLK), 149 FEA_MAP(DS_DCFCLK), 150 FEA_MAP(DS_UCLK), 151 FEA_MAP(GFX_ULV), 152 FEA_MAP(FW_DSTATE), 153 FEA_MAP(GFXOFF), 154 FEA_MAP(BACO), 155 FEA_MAP(MM_DPM), 156 FEA_MAP(SOC_MPCLK_DS), 157 FEA_MAP(BACO_MPCLK_DS), 158 FEA_MAP(THROTTLERS), 159 FEA_MAP(SMARTSHIFT), 160 FEA_MAP(GTHR), 161 FEA_MAP(ACDC), 162 FEA_MAP(VR0HOT), 163 FEA_MAP(FW_CTF), 164 FEA_MAP(FAN_CONTROL), 165 FEA_MAP(GFX_DCS), 166 FEA_MAP(GFX_READ_MARGIN), 167 FEA_MAP(LED_DISPLAY), 168 FEA_MAP(GFXCLK_SPREAD_SPECTRUM), 169 FEA_MAP(OUT_OF_BAND_MONITOR), 170 FEA_MAP(OPTIMIZED_VMIN), 171 FEA_MAP(GFX_IMU), 172 FEA_MAP(BOOT_TIME_CAL), 173 FEA_MAP(GFX_PCC_DFLL), 174 FEA_MAP(SOC_CG), 175 FEA_MAP(DF_CSTATE), 176 FEA_MAP(GFX_EDC), 177 FEA_MAP(BOOT_POWER_OPT), 178 FEA_MAP(CLOCK_POWER_DOWN_BYPASS), 179 FEA_MAP(DS_VCN), 180 FEA_MAP(BACO_CG), 181 FEA_MAP(MEM_TEMP_READ), 182 FEA_MAP(ATHUB_MMHUB_PG), 183 FEA_MAP(SOC_PCC), 184 }; 185 186 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = { 187 TAB_MAP(PPTABLE), 188 TAB_MAP(WATERMARKS), 189 TAB_MAP(AVFS_PSM_DEBUG), 190 TAB_MAP(PMSTATUSLOG), 191 TAB_MAP(SMU_METRICS), 192 TAB_MAP(DRIVER_SMU_CONFIG), 193 TAB_MAP(ACTIVITY_MONITOR_COEFF), 194 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE}, 195 }; 196 197 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 198 PWR_MAP(AC), 199 PWR_MAP(DC), 200 }; 201 202 static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT), 211 }; 212 213 static const uint8_t smu_v13_0_7_throttler_map[] = { 214 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 215 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 216 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 217 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 218 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 219 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 220 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 221 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 222 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 223 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 224 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 225 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 226 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 227 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 228 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 229 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT), 230 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 231 }; 232 233 static int 234 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, 235 uint32_t *feature_mask, uint32_t num) 236 { 237 struct amdgpu_device *adev = smu->adev; 238 239 if (num > 2) 240 return -EINVAL; 241 242 memset(feature_mask, 0, sizeof(uint32_t) * num); 243 244 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); 245 246 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 247 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 248 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); 249 } 250 251 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { 252 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 253 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); 254 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 255 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); 256 } 257 258 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 259 260 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 261 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 262 263 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 264 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 265 266 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT); 268 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT); 269 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT); 270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT); 271 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT); 272 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT); 273 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT); 274 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT); 275 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT); 276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); 277 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT); 278 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT); 279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT); 280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT); 281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT); 282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT); 283 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); 284 285 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 286 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT); 287 288 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) && 289 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) 290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 291 292 return 0; 293 } 294 295 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu) 296 { 297 struct smu_table_context *table_context = &smu->smu_table; 298 struct smu_13_0_7_powerplay_table *powerplay_table = 299 table_context->power_play_table; 300 struct smu_baco_context *smu_baco = &smu->smu_baco; 301 302 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC) 303 smu->dc_controlled_by_gpio = true; 304 305 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO || 306 powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO) 307 smu_baco->platform_support = true; 308 309 table_context->thermal_controller_type = 310 powerplay_table->thermal_controller_type; 311 312 /* 313 * Instead of having its own buffer space and get overdrive_table copied, 314 * smu->od_settings just points to the actual overdrive_table 315 */ 316 smu->od_settings = &powerplay_table->overdrive_table; 317 318 return 0; 319 } 320 321 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu) 322 { 323 struct smu_table_context *table_context = &smu->smu_table; 324 struct smu_13_0_7_powerplay_table *powerplay_table = 325 table_context->power_play_table; 326 struct amdgpu_device *adev = smu->adev; 327 328 if (adev->pdev->device == 0x51) 329 powerplay_table->smc_pptable.SkuTable.DebugOverrides |= 0x00000080; 330 331 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 332 sizeof(PPTable_t)); 333 334 return 0; 335 } 336 337 static int smu_v13_0_7_check_fw_status(struct smu_context *smu) 338 { 339 struct amdgpu_device *adev = smu->adev; 340 uint32_t mp1_fw_flags; 341 342 mp1_fw_flags = RREG32_PCIE(MP1_Public | 343 (smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 & 0xffffffff)); 344 345 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 346 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 347 return 0; 348 349 return -EIO; 350 } 351 352 #ifndef atom_smc_dpm_info_table_13_0_7 353 struct atom_smc_dpm_info_table_13_0_7 354 { 355 struct atom_common_table_header table_header; 356 BoardTable_t BoardTable; 357 }; 358 #endif 359 360 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu) 361 { 362 struct smu_table_context *table_context = &smu->smu_table; 363 364 PPTable_t *smc_pptable = table_context->driver_pptable; 365 366 struct atom_smc_dpm_info_table_13_0_7 *smc_dpm_table; 367 368 BoardTable_t *BoardTable = &smc_pptable->BoardTable; 369 370 int index, ret; 371 372 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 373 smc_dpm_info); 374 375 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 376 (uint8_t **)&smc_dpm_table); 377 if (ret) 378 return ret; 379 380 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t)); 381 382 return 0; 383 } 384 385 386 static int smu_v13_0_7_setup_pptable(struct smu_context *smu) 387 { 388 struct smu_table_context *smu_table = &smu->smu_table; 389 void *combo_pptable = smu_table->combo_pptable; 390 struct amdgpu_device *adev = smu->adev; 391 int ret = 0; 392 393 /* 394 * With SCPM enabled, the pptable used will be signed. It cannot 395 * be used directly by driver. To get the raw pptable, we need to 396 * rely on the combo pptable(and its revelant SMU message). 397 */ 398 if (adev->scpm_enabled) { 399 ret = smu_cmn_get_combo_pptable(smu); 400 if (ret) 401 return ret; 402 403 smu->smu_table.power_play_table = combo_pptable; 404 smu->smu_table.power_play_table_size = sizeof(struct smu_13_0_7_powerplay_table); 405 } else { 406 ret = smu_v13_0_setup_pptable(smu); 407 if (ret) 408 return ret; 409 } 410 411 ret = smu_v13_0_7_store_powerplay_table(smu); 412 if (ret) 413 return ret; 414 415 /* 416 * With SCPM enabled, the operation below will be handled 417 * by PSP. Driver involvment is unnecessary and useless. 418 */ 419 if (!adev->scpm_enabled) { 420 ret = smu_v13_0_7_append_powerplay_table(smu); 421 if (ret) 422 return ret; 423 } 424 425 ret = smu_v13_0_7_check_powerplay_table(smu); 426 if (ret) 427 return ret; 428 429 return ret; 430 } 431 432 static int smu_v13_0_7_tables_init(struct smu_context *smu) 433 { 434 struct smu_table_context *smu_table = &smu->smu_table; 435 struct smu_table *tables = smu_table->tables; 436 437 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 438 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 439 440 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 441 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 442 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 443 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 444 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 445 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 446 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 447 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 448 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, 449 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 450 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 451 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 452 AMDGPU_GEM_DOMAIN_VRAM); 453 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE, 454 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 455 456 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 457 if (!smu_table->metrics_table) 458 goto err0_out; 459 smu_table->metrics_time = 0; 460 461 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 462 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 463 if (!smu_table->gpu_metrics_table) 464 goto err1_out; 465 466 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 467 if (!smu_table->watermarks_table) 468 goto err2_out; 469 470 return 0; 471 472 err2_out: 473 kfree(smu_table->gpu_metrics_table); 474 err1_out: 475 kfree(smu_table->metrics_table); 476 err0_out: 477 return -ENOMEM; 478 } 479 480 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu) 481 { 482 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 483 484 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context), 485 GFP_KERNEL); 486 if (!smu_dpm->dpm_context) 487 return -ENOMEM; 488 489 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context); 490 491 return 0; 492 } 493 494 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu) 495 { 496 int ret = 0; 497 498 ret = smu_v13_0_7_tables_init(smu); 499 if (ret) 500 return ret; 501 502 ret = smu_v13_0_7_allocate_dpm_context(smu); 503 if (ret) 504 return ret; 505 506 return smu_v13_0_init_smc_tables(smu); 507 } 508 509 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) 510 { 511 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 512 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 513 SkuTable_t *skutable = &driver_ppt->SkuTable; 514 struct smu_13_0_dpm_table *dpm_table; 515 struct smu_13_0_pcie_table *pcie_table; 516 uint32_t link_level; 517 int ret = 0; 518 519 /* socclk dpm table setup */ 520 dpm_table = &dpm_context->dpm_tables.soc_table; 521 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 522 ret = smu_v13_0_set_single_dpm_table(smu, 523 SMU_SOCCLK, 524 dpm_table); 525 if (ret) 526 return ret; 527 } else { 528 dpm_table->count = 1; 529 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 530 dpm_table->dpm_levels[0].enabled = true; 531 dpm_table->min = dpm_table->dpm_levels[0].value; 532 dpm_table->max = dpm_table->dpm_levels[0].value; 533 } 534 535 /* gfxclk dpm table setup */ 536 dpm_table = &dpm_context->dpm_tables.gfx_table; 537 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 538 ret = smu_v13_0_set_single_dpm_table(smu, 539 SMU_GFXCLK, 540 dpm_table); 541 if (ret) 542 return ret; 543 } else { 544 dpm_table->count = 1; 545 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 546 dpm_table->dpm_levels[0].enabled = true; 547 dpm_table->min = dpm_table->dpm_levels[0].value; 548 dpm_table->max = dpm_table->dpm_levels[0].value; 549 } 550 551 /* uclk dpm table setup */ 552 dpm_table = &dpm_context->dpm_tables.uclk_table; 553 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 554 ret = smu_v13_0_set_single_dpm_table(smu, 555 SMU_UCLK, 556 dpm_table); 557 if (ret) 558 return ret; 559 } else { 560 dpm_table->count = 1; 561 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 562 dpm_table->dpm_levels[0].enabled = true; 563 dpm_table->min = dpm_table->dpm_levels[0].value; 564 dpm_table->max = dpm_table->dpm_levels[0].value; 565 } 566 567 /* fclk dpm table setup */ 568 dpm_table = &dpm_context->dpm_tables.fclk_table; 569 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 570 ret = smu_v13_0_set_single_dpm_table(smu, 571 SMU_FCLK, 572 dpm_table); 573 if (ret) 574 return ret; 575 } else { 576 dpm_table->count = 1; 577 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 578 dpm_table->dpm_levels[0].enabled = true; 579 dpm_table->min = dpm_table->dpm_levels[0].value; 580 dpm_table->max = dpm_table->dpm_levels[0].value; 581 } 582 583 /* vclk dpm table setup */ 584 dpm_table = &dpm_context->dpm_tables.vclk_table; 585 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { 586 ret = smu_v13_0_set_single_dpm_table(smu, 587 SMU_VCLK, 588 dpm_table); 589 if (ret) 590 return ret; 591 } else { 592 dpm_table->count = 1; 593 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 594 dpm_table->dpm_levels[0].enabled = true; 595 dpm_table->min = dpm_table->dpm_levels[0].value; 596 dpm_table->max = dpm_table->dpm_levels[0].value; 597 } 598 599 /* dclk dpm table setup */ 600 dpm_table = &dpm_context->dpm_tables.dclk_table; 601 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { 602 ret = smu_v13_0_set_single_dpm_table(smu, 603 SMU_DCLK, 604 dpm_table); 605 if (ret) 606 return ret; 607 } else { 608 dpm_table->count = 1; 609 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 610 dpm_table->dpm_levels[0].enabled = true; 611 dpm_table->min = dpm_table->dpm_levels[0].value; 612 dpm_table->max = dpm_table->dpm_levels[0].value; 613 } 614 615 /* lclk dpm table setup */ 616 pcie_table = &dpm_context->dpm_tables.pcie_table; 617 pcie_table->num_of_link_levels = 0; 618 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { 619 if (!skutable->PcieGenSpeed[link_level] && 620 !skutable->PcieLaneCount[link_level] && 621 !skutable->LclkFreq[link_level]) 622 continue; 623 624 pcie_table->pcie_gen[pcie_table->num_of_link_levels] = 625 skutable->PcieGenSpeed[link_level]; 626 pcie_table->pcie_lane[pcie_table->num_of_link_levels] = 627 skutable->PcieLaneCount[link_level]; 628 pcie_table->clk_freq[pcie_table->num_of_link_levels] = 629 skutable->LclkFreq[link_level]; 630 pcie_table->num_of_link_levels++; 631 } 632 633 return 0; 634 } 635 636 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu) 637 { 638 int ret = 0; 639 uint64_t feature_enabled; 640 641 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 642 if (ret) 643 return false; 644 645 return !!(feature_enabled & SMC_DPM_FEATURE); 646 } 647 648 static void smu_v13_0_7_dump_pptable(struct smu_context *smu) 649 { 650 struct smu_table_context *table_context = &smu->smu_table; 651 PPTable_t *pptable = table_context->driver_pptable; 652 SkuTable_t *skutable = &pptable->SkuTable; 653 654 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 655 656 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version); 657 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]); 658 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]); 659 } 660 661 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics) 662 { 663 uint32_t throttler_status = 0; 664 int i; 665 666 for (i = 0; i < THROTTLER_COUNT; i++) 667 throttler_status |= 668 (metrics->ThrottlingPercentage[i] ? 1U << i : 0); 669 670 return throttler_status; 671 } 672 673 #define SMU_13_0_7_BUSY_THRESHOLD 15 674 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu, 675 MetricsMember_t member, 676 uint32_t *value) 677 { 678 struct smu_table_context *smu_table= &smu->smu_table; 679 SmuMetrics_t *metrics = 680 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 681 int ret = 0; 682 683 ret = smu_cmn_get_metrics_table(smu, 684 NULL, 685 false); 686 if (ret) 687 return ret; 688 689 switch (member) { 690 case METRICS_CURR_GFXCLK: 691 *value = metrics->CurrClock[PPCLK_GFXCLK]; 692 break; 693 case METRICS_CURR_SOCCLK: 694 *value = metrics->CurrClock[PPCLK_SOCCLK]; 695 break; 696 case METRICS_CURR_UCLK: 697 *value = metrics->CurrClock[PPCLK_UCLK]; 698 break; 699 case METRICS_CURR_VCLK: 700 *value = metrics->CurrClock[PPCLK_VCLK_0]; 701 break; 702 case METRICS_CURR_VCLK1: 703 *value = metrics->CurrClock[PPCLK_VCLK_1]; 704 break; 705 case METRICS_CURR_DCLK: 706 *value = metrics->CurrClock[PPCLK_DCLK_0]; 707 break; 708 case METRICS_CURR_DCLK1: 709 *value = metrics->CurrClock[PPCLK_DCLK_1]; 710 break; 711 case METRICS_CURR_FCLK: 712 *value = metrics->CurrClock[PPCLK_FCLK]; 713 break; 714 case METRICS_AVERAGE_GFXCLK: 715 *value = metrics->AverageGfxclkFrequencyPreDs; 716 break; 717 case METRICS_AVERAGE_FCLK: 718 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 719 *value = metrics->AverageFclkFrequencyPostDs; 720 else 721 *value = metrics->AverageFclkFrequencyPreDs; 722 break; 723 case METRICS_AVERAGE_UCLK: 724 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 725 *value = metrics->AverageMemclkFrequencyPostDs; 726 else 727 *value = metrics->AverageMemclkFrequencyPreDs; 728 break; 729 case METRICS_AVERAGE_VCLK: 730 *value = metrics->AverageVclk0Frequency; 731 break; 732 case METRICS_AVERAGE_DCLK: 733 *value = metrics->AverageDclk0Frequency; 734 break; 735 case METRICS_AVERAGE_VCLK1: 736 *value = metrics->AverageVclk1Frequency; 737 break; 738 case METRICS_AVERAGE_DCLK1: 739 *value = metrics->AverageDclk1Frequency; 740 break; 741 case METRICS_AVERAGE_GFXACTIVITY: 742 *value = metrics->AverageGfxActivity; 743 break; 744 case METRICS_AVERAGE_MEMACTIVITY: 745 *value = metrics->AverageUclkActivity; 746 break; 747 case METRICS_AVERAGE_SOCKETPOWER: 748 *value = metrics->AverageSocketPower << 8; 749 break; 750 case METRICS_TEMPERATURE_EDGE: 751 *value = metrics->AvgTemperature[TEMP_EDGE] * 752 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 753 break; 754 case METRICS_TEMPERATURE_HOTSPOT: 755 *value = metrics->AvgTemperature[TEMP_HOTSPOT] * 756 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 757 break; 758 case METRICS_TEMPERATURE_MEM: 759 *value = metrics->AvgTemperature[TEMP_MEM] * 760 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 761 break; 762 case METRICS_TEMPERATURE_VRGFX: 763 *value = metrics->AvgTemperature[TEMP_VR_GFX] * 764 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 765 break; 766 case METRICS_TEMPERATURE_VRSOC: 767 *value = metrics->AvgTemperature[TEMP_VR_SOC] * 768 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 769 break; 770 case METRICS_THROTTLER_STATUS: 771 *value = smu_v13_0_7_get_throttler_status(metrics); 772 break; 773 case METRICS_CURR_FANSPEED: 774 *value = metrics->AvgFanRpm; 775 break; 776 case METRICS_CURR_FANPWM: 777 *value = metrics->AvgFanPwm; 778 break; 779 case METRICS_VOLTAGE_VDDGFX: 780 *value = metrics->AvgVoltage[SVI_PLANE_GFX]; 781 break; 782 case METRICS_PCIE_RATE: 783 *value = metrics->PcieRate; 784 break; 785 case METRICS_PCIE_WIDTH: 786 *value = metrics->PcieWidth; 787 break; 788 default: 789 *value = UINT_MAX; 790 break; 791 } 792 793 return ret; 794 } 795 796 static int smu_v13_0_7_read_sensor(struct smu_context *smu, 797 enum amd_pp_sensors sensor, 798 void *data, 799 uint32_t *size) 800 { 801 struct smu_table_context *table_context = &smu->smu_table; 802 PPTable_t *smc_pptable = table_context->driver_pptable; 803 int ret = 0; 804 805 switch (sensor) { 806 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 807 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm; 808 *size = 4; 809 break; 810 case AMDGPU_PP_SENSOR_MEM_LOAD: 811 ret = smu_v13_0_7_get_smu_metrics_data(smu, 812 METRICS_AVERAGE_MEMACTIVITY, 813 (uint32_t *)data); 814 *size = 4; 815 break; 816 case AMDGPU_PP_SENSOR_GPU_LOAD: 817 ret = smu_v13_0_7_get_smu_metrics_data(smu, 818 METRICS_AVERAGE_GFXACTIVITY, 819 (uint32_t *)data); 820 *size = 4; 821 break; 822 case AMDGPU_PP_SENSOR_GPU_POWER: 823 ret = smu_v13_0_7_get_smu_metrics_data(smu, 824 METRICS_AVERAGE_SOCKETPOWER, 825 (uint32_t *)data); 826 *size = 4; 827 break; 828 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 829 ret = smu_v13_0_7_get_smu_metrics_data(smu, 830 METRICS_TEMPERATURE_HOTSPOT, 831 (uint32_t *)data); 832 *size = 4; 833 break; 834 case AMDGPU_PP_SENSOR_EDGE_TEMP: 835 ret = smu_v13_0_7_get_smu_metrics_data(smu, 836 METRICS_TEMPERATURE_EDGE, 837 (uint32_t *)data); 838 *size = 4; 839 break; 840 case AMDGPU_PP_SENSOR_MEM_TEMP: 841 ret = smu_v13_0_7_get_smu_metrics_data(smu, 842 METRICS_TEMPERATURE_MEM, 843 (uint32_t *)data); 844 *size = 4; 845 break; 846 case AMDGPU_PP_SENSOR_GFX_MCLK: 847 ret = smu_v13_0_7_get_smu_metrics_data(smu, 848 METRICS_AVERAGE_UCLK, 849 (uint32_t *)data); 850 *(uint32_t *)data *= 100; 851 *size = 4; 852 break; 853 case AMDGPU_PP_SENSOR_GFX_SCLK: 854 ret = smu_v13_0_7_get_smu_metrics_data(smu, 855 METRICS_AVERAGE_GFXCLK, 856 (uint32_t *)data); 857 *(uint32_t *)data *= 100; 858 *size = 4; 859 break; 860 case AMDGPU_PP_SENSOR_VDDGFX: 861 ret = smu_v13_0_7_get_smu_metrics_data(smu, 862 METRICS_VOLTAGE_VDDGFX, 863 (uint32_t *)data); 864 *size = 4; 865 break; 866 default: 867 ret = -EOPNOTSUPP; 868 break; 869 } 870 871 return ret; 872 } 873 874 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu, 875 enum smu_clk_type clk_type, 876 uint32_t *value) 877 { 878 MetricsMember_t member_type; 879 int clk_id = 0; 880 881 clk_id = smu_cmn_to_asic_specific_index(smu, 882 CMN2ASIC_MAPPING_CLK, 883 clk_type); 884 if (clk_id < 0) 885 return -EINVAL; 886 887 switch (clk_id) { 888 case PPCLK_GFXCLK: 889 member_type = METRICS_AVERAGE_GFXCLK; 890 break; 891 case PPCLK_UCLK: 892 member_type = METRICS_CURR_UCLK; 893 break; 894 case PPCLK_FCLK: 895 member_type = METRICS_CURR_FCLK; 896 break; 897 case PPCLK_SOCCLK: 898 member_type = METRICS_CURR_SOCCLK; 899 break; 900 case PPCLK_VCLK_0: 901 member_type = METRICS_CURR_VCLK; 902 break; 903 case PPCLK_DCLK_0: 904 member_type = METRICS_CURR_DCLK; 905 break; 906 case PPCLK_VCLK_1: 907 member_type = METRICS_CURR_VCLK1; 908 break; 909 case PPCLK_DCLK_1: 910 member_type = METRICS_CURR_DCLK1; 911 break; 912 default: 913 return -EINVAL; 914 } 915 916 return smu_v13_0_7_get_smu_metrics_data(smu, 917 member_type, 918 value); 919 } 920 921 static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, 922 enum smu_clk_type clk_type, 923 char *buf) 924 { 925 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 926 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 927 struct smu_13_0_dpm_table *single_dpm_table; 928 struct smu_13_0_pcie_table *pcie_table; 929 uint32_t gen_speed, lane_width; 930 int i, curr_freq, size = 0; 931 int ret = 0; 932 933 smu_cmn_get_sysfs_buf(&buf, &size); 934 935 if (amdgpu_ras_intr_triggered()) { 936 size += sysfs_emit_at(buf, size, "unavailable\n"); 937 return size; 938 } 939 940 switch (clk_type) { 941 case SMU_SCLK: 942 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 943 break; 944 case SMU_MCLK: 945 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 946 break; 947 case SMU_SOCCLK: 948 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 949 break; 950 case SMU_FCLK: 951 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 952 break; 953 case SMU_VCLK: 954 case SMU_VCLK1: 955 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 956 break; 957 case SMU_DCLK: 958 case SMU_DCLK1: 959 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 960 break; 961 default: 962 break; 963 } 964 965 switch (clk_type) { 966 case SMU_SCLK: 967 case SMU_MCLK: 968 case SMU_SOCCLK: 969 case SMU_FCLK: 970 case SMU_VCLK: 971 case SMU_VCLK1: 972 case SMU_DCLK: 973 case SMU_DCLK1: 974 ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); 975 if (ret) { 976 dev_err(smu->adev->dev, "Failed to get current clock freq!"); 977 return ret; 978 } 979 980 if (single_dpm_table->is_fine_grained) { 981 /* 982 * For fine grained dpms, there are only two dpm levels: 983 * - level 0 -> min clock freq 984 * - level 1 -> max clock freq 985 * And the current clock frequency can be any value between them. 986 * So, if the current clock frequency is not at level 0 or level 1, 987 * we will fake it as three dpm levels: 988 * - level 0 -> min clock freq 989 * - level 1 -> current actual clock freq 990 * - level 2 -> max clock freq 991 */ 992 if ((single_dpm_table->dpm_levels[0].value != curr_freq) && 993 (single_dpm_table->dpm_levels[1].value != curr_freq)) { 994 size += sysfs_emit_at(buf, size, "0: %uMhz\n", 995 single_dpm_table->dpm_levels[0].value); 996 size += sysfs_emit_at(buf, size, "1: %uMhz *\n", 997 curr_freq); 998 size += sysfs_emit_at(buf, size, "2: %uMhz\n", 999 single_dpm_table->dpm_levels[1].value); 1000 } else { 1001 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", 1002 single_dpm_table->dpm_levels[0].value, 1003 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); 1004 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 1005 single_dpm_table->dpm_levels[1].value, 1006 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); 1007 } 1008 } else { 1009 for (i = 0; i < single_dpm_table->count; i++) 1010 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 1011 i, single_dpm_table->dpm_levels[i].value, 1012 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); 1013 } 1014 break; 1015 case SMU_PCIE: 1016 ret = smu_v13_0_7_get_smu_metrics_data(smu, 1017 METRICS_PCIE_RATE, 1018 &gen_speed); 1019 if (ret) 1020 return ret; 1021 1022 ret = smu_v13_0_7_get_smu_metrics_data(smu, 1023 METRICS_PCIE_WIDTH, 1024 &lane_width); 1025 if (ret) 1026 return ret; 1027 1028 pcie_table = &(dpm_context->dpm_tables.pcie_table); 1029 for (i = 0; i < pcie_table->num_of_link_levels; i++) 1030 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1031 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : 1032 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : 1033 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : 1034 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", 1035 (pcie_table->pcie_lane[i] == 1) ? "x1" : 1036 (pcie_table->pcie_lane[i] == 2) ? "x2" : 1037 (pcie_table->pcie_lane[i] == 3) ? "x4" : 1038 (pcie_table->pcie_lane[i] == 4) ? "x8" : 1039 (pcie_table->pcie_lane[i] == 5) ? "x12" : 1040 (pcie_table->pcie_lane[i] == 6) ? "x16" : "", 1041 pcie_table->clk_freq[i], 1042 (gen_speed == pcie_table->pcie_gen[i]) && 1043 (lane_width == pcie_table->pcie_lane[i]) ? 1044 "*" : ""); 1045 break; 1046 1047 default: 1048 break; 1049 } 1050 1051 return size; 1052 } 1053 1054 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu, 1055 enum smu_clk_type clk_type, 1056 uint32_t mask) 1057 { 1058 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1059 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1060 struct smu_13_0_dpm_table *single_dpm_table; 1061 uint32_t soft_min_level, soft_max_level; 1062 uint32_t min_freq, max_freq; 1063 int ret = 0; 1064 1065 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1066 soft_max_level = mask ? (fls(mask) - 1) : 0; 1067 1068 switch (clk_type) { 1069 case SMU_GFXCLK: 1070 case SMU_SCLK: 1071 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1072 break; 1073 case SMU_MCLK: 1074 case SMU_UCLK: 1075 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 1076 break; 1077 case SMU_SOCCLK: 1078 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 1079 break; 1080 case SMU_FCLK: 1081 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 1082 break; 1083 case SMU_VCLK: 1084 case SMU_VCLK1: 1085 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 1086 break; 1087 case SMU_DCLK: 1088 case SMU_DCLK1: 1089 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 1090 break; 1091 default: 1092 break; 1093 } 1094 1095 switch (clk_type) { 1096 case SMU_GFXCLK: 1097 case SMU_SCLK: 1098 case SMU_MCLK: 1099 case SMU_UCLK: 1100 case SMU_SOCCLK: 1101 case SMU_FCLK: 1102 case SMU_VCLK: 1103 case SMU_VCLK1: 1104 case SMU_DCLK: 1105 case SMU_DCLK1: 1106 if (single_dpm_table->is_fine_grained) { 1107 /* There is only 2 levels for fine grained DPM */ 1108 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1109 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1110 } else { 1111 if ((soft_max_level >= single_dpm_table->count) || 1112 (soft_min_level >= single_dpm_table->count)) 1113 return -EINVAL; 1114 } 1115 1116 min_freq = single_dpm_table->dpm_levels[soft_min_level].value; 1117 max_freq = single_dpm_table->dpm_levels[soft_max_level].value; 1118 1119 ret = smu_v13_0_set_soft_freq_limited_range(smu, 1120 clk_type, 1121 min_freq, 1122 max_freq); 1123 break; 1124 case SMU_DCEFCLK: 1125 case SMU_PCIE: 1126 default: 1127 break; 1128 } 1129 1130 return ret; 1131 } 1132 1133 static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu, 1134 uint32_t pcie_gen_cap, 1135 uint32_t pcie_width_cap) 1136 { 1137 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1138 struct smu_13_0_pcie_table *pcie_table = 1139 &dpm_context->dpm_tables.pcie_table; 1140 uint32_t smu_pcie_arg; 1141 int ret, i; 1142 1143 for (i = 0; i < pcie_table->num_of_link_levels; i++) { 1144 if (pcie_table->pcie_gen[i] > pcie_gen_cap) 1145 pcie_table->pcie_gen[i] = pcie_gen_cap; 1146 if (pcie_table->pcie_lane[i] > pcie_width_cap) 1147 pcie_table->pcie_lane[i] = pcie_width_cap; 1148 1149 smu_pcie_arg = i << 16; 1150 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8; 1151 smu_pcie_arg |= pcie_table->pcie_lane[i]; 1152 1153 ret = smu_cmn_send_smc_msg_with_param(smu, 1154 SMU_MSG_OverridePcieParameters, 1155 smu_pcie_arg, 1156 NULL); 1157 if (ret) 1158 return ret; 1159 } 1160 1161 return 0; 1162 } 1163 1164 static const struct smu_temperature_range smu13_thermal_policy[] = 1165 { 1166 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, 1167 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, 1168 }; 1169 1170 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu, 1171 struct smu_temperature_range *range) 1172 { 1173 struct smu_table_context *table_context = &smu->smu_table; 1174 struct smu_13_0_7_powerplay_table *powerplay_table = 1175 table_context->power_play_table; 1176 PPTable_t *pptable = smu->smu_table.driver_pptable; 1177 1178 if (!range) 1179 return -EINVAL; 1180 1181 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range)); 1182 1183 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] * 1184 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1185 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * 1186 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1187 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] * 1188 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1189 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * 1190 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1191 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] * 1192 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1193 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* 1194 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1195 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1196 1197 return 0; 1198 } 1199 1200 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 1201 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu, 1202 void **table) 1203 { 1204 struct smu_table_context *smu_table = &smu->smu_table; 1205 struct gpu_metrics_v1_3 *gpu_metrics = 1206 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 1207 SmuMetricsExternal_t metrics_ext; 1208 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; 1209 int ret = 0; 1210 1211 ret = smu_cmn_get_metrics_table(smu, 1212 &metrics_ext, 1213 true); 1214 if (ret) 1215 return ret; 1216 1217 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 1218 1219 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE]; 1220 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT]; 1221 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM]; 1222 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX]; 1223 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC]; 1224 gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0], 1225 metrics->AvgTemperature[TEMP_VR_MEM1]); 1226 1227 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 1228 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 1229 gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage, 1230 metrics->Vcn1ActivityPercentage); 1231 1232 gpu_metrics->average_socket_power = metrics->AverageSocketPower; 1233 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; 1234 1235 if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD) 1236 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; 1237 else 1238 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 1239 1240 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 1241 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs; 1242 else 1243 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs; 1244 1245 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency; 1246 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency; 1247 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency; 1248 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; 1249 1250 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK]; 1251 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; 1252 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0]; 1253 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1]; 1254 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1]; 1255 1256 gpu_metrics->throttle_status = 1257 smu_v13_0_7_get_throttler_status(metrics); 1258 gpu_metrics->indep_throttle_status = 1259 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 1260 smu_v13_0_7_throttler_map); 1261 1262 gpu_metrics->current_fan_speed = metrics->AvgFanRpm; 1263 1264 gpu_metrics->pcie_link_width = metrics->PcieWidth; 1265 gpu_metrics->pcie_link_speed = metrics->PcieRate; 1266 1267 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 1268 1269 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX]; 1270 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC]; 1271 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP]; 1272 1273 *table = (void *)gpu_metrics; 1274 1275 return sizeof(struct gpu_metrics_v1_3); 1276 } 1277 1278 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu) 1279 { 1280 struct smu_13_0_dpm_context *dpm_context = 1281 smu->smu_dpm.dpm_context; 1282 struct smu_13_0_dpm_table *gfx_table = 1283 &dpm_context->dpm_tables.gfx_table; 1284 struct smu_13_0_dpm_table *mem_table = 1285 &dpm_context->dpm_tables.uclk_table; 1286 struct smu_13_0_dpm_table *soc_table = 1287 &dpm_context->dpm_tables.soc_table; 1288 struct smu_13_0_dpm_table *vclk_table = 1289 &dpm_context->dpm_tables.vclk_table; 1290 struct smu_13_0_dpm_table *dclk_table = 1291 &dpm_context->dpm_tables.dclk_table; 1292 struct smu_13_0_dpm_table *fclk_table = 1293 &dpm_context->dpm_tables.fclk_table; 1294 struct smu_umd_pstate_table *pstate_table = 1295 &smu->pstate_table; 1296 1297 pstate_table->gfxclk_pstate.min = gfx_table->min; 1298 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1299 1300 pstate_table->uclk_pstate.min = mem_table->min; 1301 pstate_table->uclk_pstate.peak = mem_table->max; 1302 1303 pstate_table->socclk_pstate.min = soc_table->min; 1304 pstate_table->socclk_pstate.peak = soc_table->max; 1305 1306 pstate_table->vclk_pstate.min = vclk_table->min; 1307 pstate_table->vclk_pstate.peak = vclk_table->max; 1308 1309 pstate_table->dclk_pstate.min = dclk_table->min; 1310 pstate_table->dclk_pstate.peak = dclk_table->max; 1311 1312 pstate_table->fclk_pstate.min = fclk_table->min; 1313 pstate_table->fclk_pstate.peak = fclk_table->max; 1314 1315 /* 1316 * For now, just use the mininum clock frequency. 1317 * TODO: update them when the real pstate settings available 1318 */ 1319 pstate_table->gfxclk_pstate.standard = gfx_table->min; 1320 pstate_table->uclk_pstate.standard = mem_table->min; 1321 pstate_table->socclk_pstate.standard = soc_table->min; 1322 pstate_table->vclk_pstate.standard = vclk_table->min; 1323 pstate_table->dclk_pstate.standard = dclk_table->min; 1324 pstate_table->fclk_pstate.standard = fclk_table->min; 1325 1326 return 0; 1327 } 1328 1329 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu, 1330 uint32_t *speed) 1331 { 1332 if (!speed) 1333 return -EINVAL; 1334 1335 return smu_v13_0_7_get_smu_metrics_data(smu, 1336 METRICS_CURR_FANPWM, 1337 speed); 1338 } 1339 1340 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu, 1341 uint32_t *speed) 1342 { 1343 if (!speed) 1344 return -EINVAL; 1345 1346 return smu_v13_0_7_get_smu_metrics_data(smu, 1347 METRICS_CURR_FANSPEED, 1348 speed); 1349 } 1350 1351 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu) 1352 { 1353 struct smu_table_context *table_context = &smu->smu_table; 1354 PPTable_t *pptable = table_context->driver_pptable; 1355 SkuTable_t *skutable = &pptable->SkuTable; 1356 1357 /* 1358 * Skip the MGpuFanBoost setting for those ASICs 1359 * which do not support it 1360 */ 1361 if (skutable->MGpuAcousticLimitRpmThreshold == 0) 1362 return 0; 1363 1364 return smu_cmn_send_smc_msg_with_param(smu, 1365 SMU_MSG_SetMGpuFanBoostLimitRpm, 1366 0, 1367 NULL); 1368 } 1369 1370 static int smu_v13_0_7_get_power_limit(struct smu_context *smu, 1371 uint32_t *current_power_limit, 1372 uint32_t *default_power_limit, 1373 uint32_t *max_power_limit) 1374 { 1375 struct smu_table_context *table_context = &smu->smu_table; 1376 struct smu_13_0_7_powerplay_table *powerplay_table = 1377 (struct smu_13_0_7_powerplay_table *)table_context->power_play_table; 1378 PPTable_t *pptable = table_context->driver_pptable; 1379 SkuTable_t *skutable = &pptable->SkuTable; 1380 uint32_t power_limit, od_percent; 1381 1382 if (smu_v13_0_get_current_power_limit(smu, &power_limit)) 1383 power_limit = smu->adev->pm.ac_power ? 1384 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] : 1385 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0]; 1386 1387 if (current_power_limit) 1388 *current_power_limit = power_limit; 1389 if (default_power_limit) 1390 *default_power_limit = power_limit; 1391 1392 if (max_power_limit) { 1393 if (smu->od_enabled) { 1394 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]); 1395 1396 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1397 1398 power_limit *= (100 + od_percent); 1399 power_limit /= 100; 1400 } 1401 *max_power_limit = power_limit; 1402 } 1403 1404 return 0; 1405 } 1406 1407 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf) 1408 { 1409 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external[PP_SMC_POWER_PROFILE_COUNT]; 1410 uint32_t i, j, size = 0; 1411 int16_t workload_type = 0; 1412 int result = 0; 1413 1414 if (!buf) 1415 return -EINVAL; 1416 1417 size += sysfs_emit_at(buf, size, " "); 1418 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) 1419 size += sysfs_emit_at(buf, size, "%-14s%s", amdgpu_pp_profile_name[i], 1420 (i == smu->power_profile_mode) ? "* " : " "); 1421 1422 size += sysfs_emit_at(buf, size, "\n"); 1423 1424 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) { 1425 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1426 workload_type = smu_cmn_to_asic_specific_index(smu, 1427 CMN2ASIC_MAPPING_WORKLOAD, 1428 i); 1429 if (workload_type < 0) 1430 return -EINVAL; 1431 1432 result = smu_cmn_update_table(smu, 1433 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1434 (void *)(&activity_monitor_external[i]), false); 1435 if (result) { 1436 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1437 return result; 1438 } 1439 } 1440 1441 #define PRINT_DPM_MONITOR(field) \ 1442 do { \ 1443 size += sysfs_emit_at(buf, size, "%-30s", #field); \ 1444 for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++) \ 1445 size += sysfs_emit_at(buf, size, "%-16d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \ 1446 size += sysfs_emit_at(buf, size, "\n"); \ 1447 } while (0) 1448 1449 PRINT_DPM_MONITOR(Gfx_ActiveHystLimit); 1450 PRINT_DPM_MONITOR(Gfx_IdleHystLimit); 1451 PRINT_DPM_MONITOR(Gfx_FPS); 1452 PRINT_DPM_MONITOR(Gfx_MinActiveFreqType); 1453 PRINT_DPM_MONITOR(Gfx_BoosterFreqType); 1454 PRINT_DPM_MONITOR(Gfx_MinActiveFreq); 1455 PRINT_DPM_MONITOR(Gfx_BoosterFreq); 1456 PRINT_DPM_MONITOR(Fclk_ActiveHystLimit); 1457 PRINT_DPM_MONITOR(Fclk_IdleHystLimit); 1458 PRINT_DPM_MONITOR(Fclk_FPS); 1459 PRINT_DPM_MONITOR(Fclk_MinActiveFreqType); 1460 PRINT_DPM_MONITOR(Fclk_BoosterFreqType); 1461 PRINT_DPM_MONITOR(Fclk_MinActiveFreq); 1462 PRINT_DPM_MONITOR(Fclk_BoosterFreq); 1463 #undef PRINT_DPM_MONITOR 1464 1465 return size; 1466 } 1467 1468 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1469 { 1470 1471 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1472 DpmActivityMonitorCoeffInt_t *activity_monitor = 1473 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1474 int workload_type, ret = 0; 1475 1476 smu->power_profile_mode = input[size]; 1477 1478 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_WINDOW3D) { 1479 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1480 return -EINVAL; 1481 } 1482 1483 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1484 1485 ret = smu_cmn_update_table(smu, 1486 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1487 (void *)(&activity_monitor_external), false); 1488 if (ret) { 1489 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1490 return ret; 1491 } 1492 1493 switch (input[0]) { 1494 case 0: /* Gfxclk */ 1495 activity_monitor->Gfx_ActiveHystLimit = input[1]; 1496 activity_monitor->Gfx_IdleHystLimit = input[2]; 1497 activity_monitor->Gfx_FPS = input[3]; 1498 activity_monitor->Gfx_MinActiveFreqType = input[4]; 1499 activity_monitor->Gfx_BoosterFreqType = input[5]; 1500 activity_monitor->Gfx_MinActiveFreq = input[6]; 1501 activity_monitor->Gfx_BoosterFreq = input[7]; 1502 break; 1503 case 1: /* Fclk */ 1504 activity_monitor->Fclk_ActiveHystLimit = input[1]; 1505 activity_monitor->Fclk_IdleHystLimit = input[2]; 1506 activity_monitor->Fclk_FPS = input[3]; 1507 activity_monitor->Fclk_MinActiveFreqType = input[4]; 1508 activity_monitor->Fclk_BoosterFreqType = input[5]; 1509 activity_monitor->Fclk_MinActiveFreq = input[6]; 1510 activity_monitor->Fclk_BoosterFreq = input[7]; 1511 break; 1512 } 1513 1514 ret = smu_cmn_update_table(smu, 1515 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1516 (void *)(&activity_monitor_external), true); 1517 if (ret) { 1518 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1519 return ret; 1520 } 1521 } 1522 1523 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1524 workload_type = smu_cmn_to_asic_specific_index(smu, 1525 CMN2ASIC_MAPPING_WORKLOAD, 1526 smu->power_profile_mode); 1527 if (workload_type < 0) 1528 return -EINVAL; 1529 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1530 1 << workload_type, NULL); 1531 1532 return ret; 1533 } 1534 1535 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { 1536 .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask, 1537 .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table, 1538 .is_dpm_running = smu_v13_0_7_is_dpm_running, 1539 .dump_pptable = smu_v13_0_7_dump_pptable, 1540 .init_microcode = smu_v13_0_init_microcode, 1541 .load_microcode = smu_v13_0_load_microcode, 1542 .init_smc_tables = smu_v13_0_7_init_smc_tables, 1543 .init_power = smu_v13_0_init_power, 1544 .check_fw_status = smu_v13_0_7_check_fw_status, 1545 .setup_pptable = smu_v13_0_7_setup_pptable, 1546 .check_fw_version = smu_v13_0_check_fw_version, 1547 .write_pptable = smu_cmn_write_pptable, 1548 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1549 .system_features_control = smu_v13_0_system_features_control, 1550 .set_allowed_mask = smu_v13_0_set_allowed_mask, 1551 .get_enabled_mask = smu_cmn_get_enabled_mask, 1552 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, 1553 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, 1554 .init_pptable_microcode = smu_v13_0_init_pptable_microcode, 1555 .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk, 1556 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, 1557 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1558 .read_sensor = smu_v13_0_7_read_sensor, 1559 .feature_is_enabled = smu_cmn_feature_is_enabled, 1560 .print_clk_levels = smu_v13_0_7_print_clk_levels, 1561 .force_clk_levels = smu_v13_0_7_force_clk_levels, 1562 .update_pcie_parameters = smu_v13_0_7_update_pcie_parameters, 1563 .get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range, 1564 .register_irq_handler = smu_v13_0_register_irq_handler, 1565 .enable_thermal_alert = smu_v13_0_enable_thermal_alert, 1566 .disable_thermal_alert = smu_v13_0_disable_thermal_alert, 1567 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 1568 .get_gpu_metrics = smu_v13_0_7_get_gpu_metrics, 1569 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range, 1570 .set_performance_level = smu_v13_0_set_performance_level, 1571 .gfx_off_control = smu_v13_0_gfx_off_control, 1572 .get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm, 1573 .get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm, 1574 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm, 1575 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm, 1576 .get_fan_control_mode = smu_v13_0_get_fan_control_mode, 1577 .set_fan_control_mode = smu_v13_0_set_fan_control_mode, 1578 .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost, 1579 .get_power_limit = smu_v13_0_7_get_power_limit, 1580 .set_power_limit = smu_v13_0_set_power_limit, 1581 .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode, 1582 .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode, 1583 .set_tool_table_location = smu_v13_0_set_tool_table_location, 1584 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1585 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 1586 }; 1587 1588 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu) 1589 { 1590 smu->ppt_funcs = &smu_v13_0_7_ppt_funcs; 1591 smu->message_map = smu_v13_0_7_message_map; 1592 smu->clock_map = smu_v13_0_7_clk_map; 1593 smu->feature_map = smu_v13_0_7_feature_mask_map; 1594 smu->table_map = smu_v13_0_7_table_map; 1595 smu->pwr_src_map = smu_v13_0_7_pwr_src_map; 1596 smu->workload_map = smu_v13_0_7_workload_map; 1597 } 1598