1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __SMU_CMN_H__ 24 #define __SMU_CMN_H__ 25 26 #include "amdgpu_smu.h" 27 28 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4) 29 30 #define FDO_PWM_MODE_STATIC 1 31 #define FDO_PWM_MODE_STATIC_RPM 5 32 33 #define SMU_IH_INTERRUPT_ID_TO_DRIVER 0xFE 34 #define SMU_IH_INTERRUPT_CONTEXT_ID_BACO 0x2 35 #define SMU_IH_INTERRUPT_CONTEXT_ID_AC 0x3 36 #define SMU_IH_INTERRUPT_CONTEXT_ID_DC 0x4 37 #define SMU_IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 38 #define SMU_IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 39 #define SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 40 #define SMU_IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 41 #define SMU_IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 42 43 extern const int link_speed[]; 44 45 /* Helper to Convert from PCIE Gen 1/2/3/4/5/6 to 0.1 GT/s speed units */ 46 static inline int pcie_gen_to_speed(uint32_t gen) 47 { 48 return ((gen == 0) ? link_speed[0] : link_speed[gen - 1]); 49 } 50 51 int smu_cmn_send_msg_without_waiting(struct smu_context *smu, 52 uint16_t msg_index, 53 uint32_t param); 54 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, 55 enum smu_message_type msg, 56 uint32_t param, 57 uint32_t *read_arg); 58 59 int smu_cmn_send_smc_msg(struct smu_context *smu, 60 enum smu_message_type msg, 61 uint32_t *read_arg); 62 63 int smu_cmn_send_debug_smc_msg(struct smu_context *smu, 64 uint32_t msg); 65 66 int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu, 67 uint32_t msg, uint32_t param); 68 69 int smu_cmn_wait_for_response(struct smu_context *smu); 70 71 int smu_cmn_to_asic_specific_index(struct smu_context *smu, 72 enum smu_cmn2asic_mapping_type type, 73 uint32_t index); 74 75 int smu_cmn_feature_is_supported(struct smu_context *smu, 76 enum smu_feature_mask mask); 77 78 int smu_cmn_feature_is_enabled(struct smu_context *smu, 79 enum smu_feature_mask mask); 80 81 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu, 82 enum smu_clk_type clk_type); 83 84 int smu_cmn_get_enabled_mask(struct smu_context *smu, 85 uint64_t *feature_mask); 86 87 uint64_t smu_cmn_get_indep_throttler_status( 88 const unsigned long dep_status, 89 const uint8_t *throttler_map); 90 91 int smu_cmn_feature_update_enable_state(struct smu_context *smu, 92 uint64_t feature_mask, 93 bool enabled); 94 95 int smu_cmn_feature_set_enabled(struct smu_context *smu, 96 enum smu_feature_mask mask, 97 bool enable); 98 99 size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, 100 char *buf); 101 102 int smu_cmn_set_pp_feature_mask(struct smu_context *smu, 103 uint64_t new_mask); 104 105 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu, 106 enum smu_feature_mask mask); 107 108 int smu_cmn_get_smc_version(struct smu_context *smu, 109 uint32_t *if_version, 110 uint32_t *smu_version); 111 112 int smu_cmn_update_table(struct smu_context *smu, 113 enum smu_table_id table_index, 114 int argument, 115 void *table_data, 116 bool drv2smu); 117 118 int smu_cmn_write_watermarks_table(struct smu_context *smu); 119 120 int smu_cmn_write_pptable(struct smu_context *smu); 121 122 int smu_cmn_get_metrics_table(struct smu_context *smu, 123 void *metrics_table, 124 bool bypass_cache); 125 126 int smu_cmn_get_combo_pptable(struct smu_context *smu); 127 128 void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev); 129 130 int smu_cmn_set_mp1_state(struct smu_context *smu, 131 enum pp_mp1_state mp1_state); 132 133 /* 134 * Helper function to make sysfs_emit_at() happy. Align buf to 135 * the current page boundary and record the offset. 136 */ 137 static inline void smu_cmn_get_sysfs_buf(char **buf, int *offset) 138 { 139 if (!*buf || !offset) 140 return; 141 142 *offset = offset_in_page(*buf); 143 *buf -= *offset; 144 } 145 146 bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev); 147 148 #endif 149 #endif 150