1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 BayLibre, SAS 4 * Author: Phong LE <ple@baylibre.com> 5 * Copyright (C) 2018-2019, Artem Mygaiev 6 * Copyright (C) 2017, Fresco Logic, Incorporated. 7 * 8 */ 9 10 #include <linux/media-bus-format.h> 11 #include <linux/module.h> 12 #include <linux/device.h> 13 #include <linux/interrupt.h> 14 #include <linux/i2c.h> 15 #include <linux/bitfield.h> 16 #include <linux/property.h> 17 #include <linux/regmap.h> 18 #include <linux/of_graph.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/regulator/consumer.h> 22 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_crtc_helper.h> 26 #include <drm/drm_edid.h> 27 #include <drm/drm_modes.h> 28 #include <drm/drm_print.h> 29 #include <drm/drm_probe_helper.h> 30 31 #include <sound/hdmi-codec.h> 32 33 #define IT66121_VENDOR_ID0_REG 0x00 34 #define IT66121_VENDOR_ID1_REG 0x01 35 #define IT66121_DEVICE_ID0_REG 0x02 36 #define IT66121_DEVICE_ID1_REG 0x03 37 38 #define IT66121_VENDOR_ID0 0x54 39 #define IT66121_VENDOR_ID1 0x49 40 #define IT66121_DEVICE_ID0 0x12 41 #define IT66121_DEVICE_ID1 0x06 42 #define IT66121_REVISION_MASK GENMASK(7, 4) 43 #define IT66121_DEVICE_ID1_MASK GENMASK(3, 0) 44 45 #define IT66121_MASTER_SEL_REG 0x10 46 #define IT66121_MASTER_SEL_HOST BIT(0) 47 48 #define IT66121_AFE_DRV_REG 0x61 49 #define IT66121_AFE_DRV_RST BIT(4) 50 #define IT66121_AFE_DRV_PWD BIT(5) 51 52 #define IT66121_INPUT_MODE_REG 0x70 53 #define IT66121_INPUT_MODE_RGB (0 << 6) 54 #define IT66121_INPUT_MODE_YUV422 BIT(6) 55 #define IT66121_INPUT_MODE_YUV444 (2 << 6) 56 #define IT66121_INPUT_MODE_CCIR656 BIT(4) 57 #define IT66121_INPUT_MODE_SYNCEMB BIT(3) 58 #define IT66121_INPUT_MODE_DDR BIT(2) 59 60 #define IT66121_INPUT_CSC_REG 0x72 61 #define IT66121_INPUT_CSC_ENDITHER BIT(7) 62 #define IT66121_INPUT_CSC_ENUDFILTER BIT(6) 63 #define IT66121_INPUT_CSC_DNFREE_GO BIT(5) 64 #define IT66121_INPUT_CSC_RGB_TO_YUV 0x02 65 #define IT66121_INPUT_CSC_YUV_TO_RGB 0x03 66 #define IT66121_INPUT_CSC_NO_CONV 0x00 67 68 #define IT66121_AFE_XP_REG 0x62 69 #define IT66121_AFE_XP_GAINBIT BIT(7) 70 #define IT66121_AFE_XP_PWDPLL BIT(6) 71 #define IT66121_AFE_XP_ENI BIT(5) 72 #define IT66121_AFE_XP_ENO BIT(4) 73 #define IT66121_AFE_XP_RESETB BIT(3) 74 #define IT66121_AFE_XP_PWDI BIT(2) 75 76 #define IT66121_AFE_IP_REG 0x64 77 #define IT66121_AFE_IP_GAINBIT BIT(7) 78 #define IT66121_AFE_IP_PWDPLL BIT(6) 79 #define IT66121_AFE_IP_CKSEL_05 (0 << 4) 80 #define IT66121_AFE_IP_CKSEL_1 BIT(4) 81 #define IT66121_AFE_IP_CKSEL_2 (2 << 4) 82 #define IT66121_AFE_IP_CKSEL_2OR4 (3 << 4) 83 #define IT66121_AFE_IP_ER0 BIT(3) 84 #define IT66121_AFE_IP_RESETB BIT(2) 85 #define IT66121_AFE_IP_ENC BIT(1) 86 #define IT66121_AFE_IP_EC1 BIT(0) 87 88 #define IT66121_AFE_XP_EC1_REG 0x68 89 #define IT66121_AFE_XP_EC1_LOWCLK BIT(4) 90 91 #define IT66121_SW_RST_REG 0x04 92 #define IT66121_SW_RST_REF BIT(5) 93 #define IT66121_SW_RST_AREF BIT(4) 94 #define IT66121_SW_RST_VID BIT(3) 95 #define IT66121_SW_RST_AUD BIT(2) 96 #define IT66121_SW_RST_HDCP BIT(0) 97 98 #define IT66121_DDC_COMMAND_REG 0x15 99 #define IT66121_DDC_COMMAND_BURST_READ 0x0 100 #define IT66121_DDC_COMMAND_EDID_READ 0x3 101 #define IT66121_DDC_COMMAND_FIFO_CLR 0x9 102 #define IT66121_DDC_COMMAND_SCL_PULSE 0xA 103 #define IT66121_DDC_COMMAND_ABORT 0xF 104 105 #define IT66121_HDCP_REG 0x20 106 #define IT66121_HDCP_CPDESIRED BIT(0) 107 #define IT66121_HDCP_EN1P1FEAT BIT(1) 108 109 #define IT66121_INT_STATUS1_REG 0x06 110 #define IT66121_INT_STATUS1_AUD_OVF BIT(7) 111 #define IT66121_INT_STATUS1_DDC_NOACK BIT(5) 112 #define IT66121_INT_STATUS1_DDC_FIFOERR BIT(4) 113 #define IT66121_INT_STATUS1_DDC_BUSHANG BIT(2) 114 #define IT66121_INT_STATUS1_RX_SENS_STATUS BIT(1) 115 #define IT66121_INT_STATUS1_HPD_STATUS BIT(0) 116 117 #define IT66121_DDC_HEADER_REG 0x11 118 #define IT66121_DDC_HEADER_HDCP 0x74 119 #define IT66121_DDC_HEADER_EDID 0xA0 120 121 #define IT66121_DDC_OFFSET_REG 0x12 122 #define IT66121_DDC_BYTE_REG 0x13 123 #define IT66121_DDC_SEGMENT_REG 0x14 124 #define IT66121_DDC_RD_FIFO_REG 0x17 125 126 #define IT66121_CLK_BANK_REG 0x0F 127 #define IT66121_CLK_BANK_PWROFF_RCLK BIT(6) 128 #define IT66121_CLK_BANK_PWROFF_ACLK BIT(5) 129 #define IT66121_CLK_BANK_PWROFF_TXCLK BIT(4) 130 #define IT66121_CLK_BANK_PWROFF_CRCLK BIT(3) 131 #define IT66121_CLK_BANK_0 0 132 #define IT66121_CLK_BANK_1 1 133 134 #define IT66121_INT_REG 0x05 135 #define IT66121_INT_ACTIVE_HIGH BIT(7) 136 #define IT66121_INT_OPEN_DRAIN BIT(6) 137 #define IT66121_INT_TX_CLK_OFF BIT(0) 138 139 #define IT66121_INT_MASK1_REG 0x09 140 #define IT66121_INT_MASK1_AUD_OVF BIT(7) 141 #define IT66121_INT_MASK1_DDC_NOACK BIT(5) 142 #define IT66121_INT_MASK1_DDC_FIFOERR BIT(4) 143 #define IT66121_INT_MASK1_DDC_BUSHANG BIT(2) 144 #define IT66121_INT_MASK1_RX_SENS BIT(1) 145 #define IT66121_INT_MASK1_HPD BIT(0) 146 147 #define IT66121_INT_CLR1_REG 0x0C 148 #define IT66121_INT_CLR1_PKTACP BIT(7) 149 #define IT66121_INT_CLR1_PKTNULL BIT(6) 150 #define IT66121_INT_CLR1_PKTGEN BIT(5) 151 #define IT66121_INT_CLR1_KSVLISTCHK BIT(4) 152 #define IT66121_INT_CLR1_AUTHDONE BIT(3) 153 #define IT66121_INT_CLR1_AUTHFAIL BIT(2) 154 #define IT66121_INT_CLR1_RX_SENS BIT(1) 155 #define IT66121_INT_CLR1_HPD BIT(0) 156 157 #define IT66121_AV_MUTE_REG 0xC1 158 #define IT66121_AV_MUTE_ON BIT(0) 159 #define IT66121_AV_MUTE_BLUESCR BIT(1) 160 161 #define IT66121_PKT_CTS_CTRL_REG 0xC5 162 #define IT66121_PKT_CTS_CTRL_SEL BIT(1) 163 164 #define IT66121_PKT_GEN_CTRL_REG 0xC6 165 #define IT66121_PKT_GEN_CTRL_ON BIT(0) 166 #define IT66121_PKT_GEN_CTRL_RPT BIT(1) 167 168 #define IT66121_AVIINFO_DB1_REG 0x158 169 #define IT66121_AVIINFO_DB2_REG 0x159 170 #define IT66121_AVIINFO_DB3_REG 0x15A 171 #define IT66121_AVIINFO_DB4_REG 0x15B 172 #define IT66121_AVIINFO_DB5_REG 0x15C 173 #define IT66121_AVIINFO_CSUM_REG 0x15D 174 #define IT66121_AVIINFO_DB6_REG 0x15E 175 #define IT66121_AVIINFO_DB7_REG 0x15F 176 #define IT66121_AVIINFO_DB8_REG 0x160 177 #define IT66121_AVIINFO_DB9_REG 0x161 178 #define IT66121_AVIINFO_DB10_REG 0x162 179 #define IT66121_AVIINFO_DB11_REG 0x163 180 #define IT66121_AVIINFO_DB12_REG 0x164 181 #define IT66121_AVIINFO_DB13_REG 0x165 182 183 #define IT66121_AVI_INFO_PKT_REG 0xCD 184 #define IT66121_AVI_INFO_PKT_ON BIT(0) 185 #define IT66121_AVI_INFO_PKT_RPT BIT(1) 186 187 #define IT66121_HDMI_MODE_REG 0xC0 188 #define IT66121_HDMI_MODE_HDMI BIT(0) 189 190 #define IT66121_SYS_STATUS_REG 0x0E 191 #define IT66121_SYS_STATUS_ACTIVE_IRQ BIT(7) 192 #define IT66121_SYS_STATUS_HPDETECT BIT(6) 193 #define IT66121_SYS_STATUS_SENDECTECT BIT(5) 194 #define IT66121_SYS_STATUS_VID_STABLE BIT(4) 195 #define IT66121_SYS_STATUS_AUD_CTS_CLR BIT(1) 196 #define IT66121_SYS_STATUS_CLEAR_IRQ BIT(0) 197 198 #define IT66121_DDC_STATUS_REG 0x16 199 #define IT66121_DDC_STATUS_TX_DONE BIT(7) 200 #define IT66121_DDC_STATUS_ACTIVE BIT(6) 201 #define IT66121_DDC_STATUS_NOACK BIT(5) 202 #define IT66121_DDC_STATUS_WAIT_BUS BIT(4) 203 #define IT66121_DDC_STATUS_ARBI_LOSE BIT(3) 204 #define IT66121_DDC_STATUS_FIFO_FULL BIT(2) 205 #define IT66121_DDC_STATUS_FIFO_EMPTY BIT(1) 206 #define IT66121_DDC_STATUS_FIFO_VALID BIT(0) 207 208 #define IT66121_EDID_SLEEP_US 20000 209 #define IT66121_EDID_TIMEOUT_US 200000 210 #define IT66121_EDID_FIFO_SIZE 32 211 212 #define IT66121_CLK_CTRL0_REG 0x58 213 #define IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING BIT(4) 214 #define IT66121_CLK_CTRL0_EXT_MCLK_MASK GENMASK(3, 2) 215 #define IT66121_CLK_CTRL0_EXT_MCLK_128FS (0 << 2) 216 #define IT66121_CLK_CTRL0_EXT_MCLK_256FS BIT(2) 217 #define IT66121_CLK_CTRL0_EXT_MCLK_512FS (2 << 2) 218 #define IT66121_CLK_CTRL0_EXT_MCLK_1024FS (3 << 2) 219 #define IT66121_CLK_CTRL0_AUTO_IPCLK BIT(0) 220 #define IT66121_CLK_STATUS1_REG 0x5E 221 #define IT66121_CLK_STATUS2_REG 0x5F 222 223 #define IT66121_AUD_CTRL0_REG 0xE0 224 #define IT66121_AUD_SWL (3 << 6) 225 #define IT66121_AUD_16BIT (0 << 6) 226 #define IT66121_AUD_18BIT BIT(6) 227 #define IT66121_AUD_20BIT (2 << 6) 228 #define IT66121_AUD_24BIT (3 << 6) 229 #define IT66121_AUD_SPDIFTC BIT(5) 230 #define IT66121_AUD_SPDIF BIT(4) 231 #define IT66121_AUD_I2S (0 << 4) 232 #define IT66121_AUD_EN_I2S3 BIT(3) 233 #define IT66121_AUD_EN_I2S2 BIT(2) 234 #define IT66121_AUD_EN_I2S1 BIT(1) 235 #define IT66121_AUD_EN_I2S0 BIT(0) 236 #define IT66121_AUD_CTRL0_AUD_SEL BIT(4) 237 238 #define IT66121_AUD_CTRL1_REG 0xE1 239 #define IT66121_AUD_FIFOMAP_REG 0xE2 240 #define IT66121_AUD_CTRL3_REG 0xE3 241 #define IT66121_AUD_SRCVALID_FLAT_REG 0xE4 242 #define IT66121_AUD_FLAT_SRC0 BIT(4) 243 #define IT66121_AUD_FLAT_SRC1 BIT(5) 244 #define IT66121_AUD_FLAT_SRC2 BIT(6) 245 #define IT66121_AUD_FLAT_SRC3 BIT(7) 246 #define IT66121_AUD_HDAUDIO_REG 0xE5 247 248 #define IT66121_AUD_PKT_CTS0_REG 0x130 249 #define IT66121_AUD_PKT_CTS1_REG 0x131 250 #define IT66121_AUD_PKT_CTS2_REG 0x132 251 #define IT66121_AUD_PKT_N0_REG 0x133 252 #define IT66121_AUD_PKT_N1_REG 0x134 253 #define IT66121_AUD_PKT_N2_REG 0x135 254 255 #define IT66121_AUD_CHST_MODE_REG 0x191 256 #define IT66121_AUD_CHST_CAT_REG 0x192 257 #define IT66121_AUD_CHST_SRCNUM_REG 0x193 258 #define IT66121_AUD_CHST_CHTNUM_REG 0x194 259 #define IT66121_AUD_CHST_CA_FS_REG 0x198 260 #define IT66121_AUD_CHST_OFS_WL_REG 0x199 261 262 #define IT66121_AUD_PKT_CTS_CNT0_REG 0x1A0 263 #define IT66121_AUD_PKT_CTS_CNT1_REG 0x1A1 264 #define IT66121_AUD_PKT_CTS_CNT2_REG 0x1A2 265 266 #define IT66121_AUD_FS_22P05K 0x4 267 #define IT66121_AUD_FS_44P1K 0x0 268 #define IT66121_AUD_FS_88P2K 0x8 269 #define IT66121_AUD_FS_176P4K 0xC 270 #define IT66121_AUD_FS_24K 0x6 271 #define IT66121_AUD_FS_48K 0x2 272 #define IT66121_AUD_FS_96K 0xA 273 #define IT66121_AUD_FS_192K 0xE 274 #define IT66121_AUD_FS_768K 0x9 275 #define IT66121_AUD_FS_32K 0x3 276 #define IT66121_AUD_FS_OTHER 0x1 277 278 #define IT66121_AUD_SWL_21BIT 0xD 279 #define IT66121_AUD_SWL_24BIT 0xB 280 #define IT66121_AUD_SWL_23BIT 0x9 281 #define IT66121_AUD_SWL_22BIT 0x5 282 #define IT66121_AUD_SWL_20BIT 0x3 283 #define IT66121_AUD_SWL_17BIT 0xC 284 #define IT66121_AUD_SWL_19BIT 0x8 285 #define IT66121_AUD_SWL_18BIT 0x4 286 #define IT66121_AUD_SWL_16BIT 0x2 287 #define IT66121_AUD_SWL_NOT_INDICATED 0x0 288 289 #define IT66121_VENDOR_ID0 0x54 290 #define IT66121_VENDOR_ID1 0x49 291 #define IT66121_DEVICE_ID0 0x12 292 #define IT66121_DEVICE_ID1 0x06 293 #define IT66121_DEVICE_MASK 0x0F 294 #define IT66121_AFE_CLK_HIGH 80000 /* Khz */ 295 296 struct it66121_ctx { 297 struct regmap *regmap; 298 struct drm_bridge bridge; 299 struct drm_bridge *next_bridge; 300 struct drm_connector *connector; 301 struct device *dev; 302 struct gpio_desc *gpio_reset; 303 struct i2c_client *client; 304 struct regulator_bulk_data supplies[3]; 305 u32 bus_width; 306 struct mutex lock; /* Protects fields below and device registers */ 307 struct hdmi_avi_infoframe hdmi_avi_infoframe; 308 struct { 309 struct platform_device *pdev; 310 u8 ch_enable; 311 u8 fs; 312 u8 swl; 313 bool auto_cts; 314 } audio; 315 }; 316 317 static const struct regmap_range_cfg it66121_regmap_banks[] = { 318 { 319 .name = "it66121", 320 .range_min = 0x00, 321 .range_max = 0x1FF, 322 .selector_reg = IT66121_CLK_BANK_REG, 323 .selector_mask = 0x1, 324 .selector_shift = 0, 325 .window_start = 0x00, 326 .window_len = 0x100, 327 }, 328 }; 329 330 static const struct regmap_config it66121_regmap_config = { 331 .val_bits = 8, 332 .reg_bits = 8, 333 .max_register = 0x1FF, 334 .ranges = it66121_regmap_banks, 335 .num_ranges = ARRAY_SIZE(it66121_regmap_banks), 336 }; 337 338 static void it66121_hw_reset(struct it66121_ctx *ctx) 339 { 340 gpiod_set_value(ctx->gpio_reset, 1); 341 msleep(20); 342 gpiod_set_value(ctx->gpio_reset, 0); 343 } 344 345 static inline int ite66121_power_on(struct it66121_ctx *ctx) 346 { 347 return regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 348 } 349 350 static inline int ite66121_power_off(struct it66121_ctx *ctx) 351 { 352 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 353 } 354 355 static inline int it66121_preamble_ddc(struct it66121_ctx *ctx) 356 { 357 return regmap_write(ctx->regmap, IT66121_MASTER_SEL_REG, IT66121_MASTER_SEL_HOST); 358 } 359 360 static inline int it66121_fire_afe(struct it66121_ctx *ctx) 361 { 362 return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0); 363 } 364 365 /* TOFIX: Handle YCbCr Input & Output */ 366 static int it66121_configure_input(struct it66121_ctx *ctx) 367 { 368 int ret; 369 u8 mode = IT66121_INPUT_MODE_RGB; 370 371 if (ctx->bus_width == 12) 372 mode |= IT66121_INPUT_MODE_DDR; 373 374 ret = regmap_write(ctx->regmap, IT66121_INPUT_MODE_REG, mode); 375 if (ret) 376 return ret; 377 378 return regmap_write(ctx->regmap, IT66121_INPUT_CSC_REG, IT66121_INPUT_CSC_NO_CONV); 379 } 380 381 /** 382 * it66121_configure_afe() - Configure the analog front end 383 * @ctx: it66121_ctx object 384 * @mode: mode to configure 385 * 386 * RETURNS: 387 * zero if success, a negative error code otherwise. 388 */ 389 static int it66121_configure_afe(struct it66121_ctx *ctx, 390 const struct drm_display_mode *mode) 391 { 392 int ret; 393 394 ret = regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 395 IT66121_AFE_DRV_RST); 396 if (ret) 397 return ret; 398 399 if (mode->clock > IT66121_AFE_CLK_HIGH) { 400 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 401 IT66121_AFE_XP_GAINBIT | 402 IT66121_AFE_XP_ENO, 403 IT66121_AFE_XP_GAINBIT); 404 if (ret) 405 return ret; 406 407 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 408 IT66121_AFE_IP_GAINBIT | 409 IT66121_AFE_IP_ER0 | 410 IT66121_AFE_IP_EC1, 411 IT66121_AFE_IP_GAINBIT); 412 if (ret) 413 return ret; 414 415 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG, 416 IT66121_AFE_XP_EC1_LOWCLK, 0x80); 417 if (ret) 418 return ret; 419 } else { 420 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 421 IT66121_AFE_XP_GAINBIT | 422 IT66121_AFE_XP_ENO, 423 IT66121_AFE_XP_ENO); 424 if (ret) 425 return ret; 426 427 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 428 IT66121_AFE_IP_GAINBIT | 429 IT66121_AFE_IP_ER0 | 430 IT66121_AFE_IP_EC1, IT66121_AFE_IP_ER0 | 431 IT66121_AFE_IP_EC1); 432 if (ret) 433 return ret; 434 435 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG, 436 IT66121_AFE_XP_EC1_LOWCLK, 437 IT66121_AFE_XP_EC1_LOWCLK); 438 if (ret) 439 return ret; 440 } 441 442 /* Clear reset flags */ 443 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 444 IT66121_SW_RST_REF | IT66121_SW_RST_VID, 0); 445 if (ret) 446 return ret; 447 448 return it66121_fire_afe(ctx); 449 } 450 451 static inline int it66121_wait_ddc_ready(struct it66121_ctx *ctx) 452 { 453 int ret, val; 454 u32 busy = IT66121_DDC_STATUS_NOACK | IT66121_DDC_STATUS_WAIT_BUS | 455 IT66121_DDC_STATUS_ARBI_LOSE; 456 457 ret = regmap_read_poll_timeout(ctx->regmap, IT66121_DDC_STATUS_REG, val, true, 458 IT66121_EDID_SLEEP_US, IT66121_EDID_TIMEOUT_US); 459 if (ret) 460 return ret; 461 462 if (val & busy) 463 return -EAGAIN; 464 465 return 0; 466 } 467 468 static int it66121_clear_ddc_fifo(struct it66121_ctx *ctx) 469 { 470 int ret; 471 472 ret = it66121_preamble_ddc(ctx); 473 if (ret) 474 return ret; 475 476 return regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 477 IT66121_DDC_COMMAND_FIFO_CLR); 478 } 479 480 static int it66121_abort_ddc_ops(struct it66121_ctx *ctx) 481 { 482 int ret; 483 unsigned int swreset, cpdesire; 484 485 ret = regmap_read(ctx->regmap, IT66121_SW_RST_REG, &swreset); 486 if (ret) 487 return ret; 488 489 ret = regmap_read(ctx->regmap, IT66121_HDCP_REG, &cpdesire); 490 if (ret) 491 return ret; 492 493 ret = regmap_write(ctx->regmap, IT66121_HDCP_REG, 494 cpdesire & (~IT66121_HDCP_CPDESIRED & 0xFF)); 495 if (ret) 496 return ret; 497 498 ret = regmap_write(ctx->regmap, IT66121_SW_RST_REG, 499 (swreset | IT66121_SW_RST_HDCP)); 500 if (ret) 501 return ret; 502 503 ret = it66121_preamble_ddc(ctx); 504 if (ret) 505 return ret; 506 507 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 508 IT66121_DDC_COMMAND_ABORT); 509 if (ret) 510 return ret; 511 512 return it66121_wait_ddc_ready(ctx); 513 } 514 515 static int it66121_get_edid_block(void *context, u8 *buf, 516 unsigned int block, size_t len) 517 { 518 struct it66121_ctx *ctx = context; 519 unsigned int val; 520 int remain = len; 521 int offset = 0; 522 int ret, cnt; 523 524 offset = (block % 2) * len; 525 block = block / 2; 526 527 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val); 528 if (ret) 529 return ret; 530 531 if (val & IT66121_INT_STATUS1_DDC_BUSHANG) { 532 ret = it66121_abort_ddc_ops(ctx); 533 if (ret) 534 return ret; 535 } 536 537 ret = it66121_clear_ddc_fifo(ctx); 538 if (ret) 539 return ret; 540 541 while (remain > 0) { 542 cnt = (remain > IT66121_EDID_FIFO_SIZE) ? 543 IT66121_EDID_FIFO_SIZE : remain; 544 ret = it66121_preamble_ddc(ctx); 545 if (ret) 546 return ret; 547 548 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 549 IT66121_DDC_COMMAND_FIFO_CLR); 550 if (ret) 551 return ret; 552 553 ret = it66121_wait_ddc_ready(ctx); 554 if (ret) 555 return ret; 556 557 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val); 558 if (ret) 559 return ret; 560 561 if (val & IT66121_INT_STATUS1_DDC_BUSHANG) { 562 ret = it66121_abort_ddc_ops(ctx); 563 if (ret) 564 return ret; 565 } 566 567 ret = it66121_preamble_ddc(ctx); 568 if (ret) 569 return ret; 570 571 ret = regmap_write(ctx->regmap, IT66121_DDC_HEADER_REG, 572 IT66121_DDC_HEADER_EDID); 573 if (ret) 574 return ret; 575 576 ret = regmap_write(ctx->regmap, IT66121_DDC_OFFSET_REG, offset); 577 if (ret) 578 return ret; 579 580 ret = regmap_write(ctx->regmap, IT66121_DDC_BYTE_REG, cnt); 581 if (ret) 582 return ret; 583 584 ret = regmap_write(ctx->regmap, IT66121_DDC_SEGMENT_REG, block); 585 if (ret) 586 return ret; 587 588 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 589 IT66121_DDC_COMMAND_EDID_READ); 590 if (ret) 591 return ret; 592 593 offset += cnt; 594 remain -= cnt; 595 596 /* Per programming manual, sleep here before emptying the FIFO */ 597 msleep(20); 598 599 ret = it66121_wait_ddc_ready(ctx); 600 if (ret) 601 return ret; 602 603 do { 604 ret = regmap_read(ctx->regmap, IT66121_DDC_RD_FIFO_REG, &val); 605 if (ret) 606 return ret; 607 *(buf++) = val; 608 cnt--; 609 } while (cnt > 0); 610 } 611 612 return 0; 613 } 614 615 static bool it66121_is_hpd_detect(struct it66121_ctx *ctx) 616 { 617 int val; 618 619 if (regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val)) 620 return false; 621 622 return val & IT66121_SYS_STATUS_HPDETECT; 623 } 624 625 static int it66121_bridge_attach(struct drm_bridge *bridge, 626 enum drm_bridge_attach_flags flags) 627 { 628 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 629 int ret; 630 631 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 632 return -EINVAL; 633 634 ret = drm_bridge_attach(bridge->encoder, ctx->next_bridge, bridge, flags); 635 if (ret) 636 return ret; 637 638 ret = regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 639 IT66121_CLK_BANK_PWROFF_RCLK, 0); 640 if (ret) 641 return ret; 642 643 ret = regmap_write_bits(ctx->regmap, IT66121_INT_REG, 644 IT66121_INT_TX_CLK_OFF, 0); 645 if (ret) 646 return ret; 647 648 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG, 649 IT66121_AFE_DRV_PWD, 0); 650 if (ret) 651 return ret; 652 653 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 654 IT66121_AFE_XP_PWDI | IT66121_AFE_XP_PWDPLL, 0); 655 if (ret) 656 return ret; 657 658 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 659 IT66121_AFE_IP_PWDPLL, 0); 660 if (ret) 661 return ret; 662 663 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG, 664 IT66121_AFE_DRV_RST, 0); 665 if (ret) 666 return ret; 667 668 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 669 IT66121_AFE_XP_RESETB, IT66121_AFE_XP_RESETB); 670 if (ret) 671 return ret; 672 673 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 674 IT66121_AFE_IP_RESETB, IT66121_AFE_IP_RESETB); 675 if (ret) 676 return ret; 677 678 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 679 IT66121_SW_RST_REF, 680 IT66121_SW_RST_REF); 681 if (ret) 682 return ret; 683 684 /* Per programming manual, sleep here for bridge to settle */ 685 msleep(50); 686 687 /* Start interrupts */ 688 return regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, 689 IT66121_INT_MASK1_DDC_NOACK | 690 IT66121_INT_MASK1_DDC_FIFOERR | 691 IT66121_INT_MASK1_DDC_BUSHANG, 0); 692 } 693 694 static int it66121_set_mute(struct it66121_ctx *ctx, bool mute) 695 { 696 int ret; 697 unsigned int val = 0; 698 699 if (mute) 700 val = IT66121_AV_MUTE_ON; 701 702 ret = regmap_write_bits(ctx->regmap, IT66121_AV_MUTE_REG, IT66121_AV_MUTE_ON, val); 703 if (ret) 704 return ret; 705 706 return regmap_write(ctx->regmap, IT66121_PKT_GEN_CTRL_REG, 707 IT66121_PKT_GEN_CTRL_ON | IT66121_PKT_GEN_CTRL_RPT); 708 } 709 710 #define MAX_OUTPUT_SEL_FORMATS 1 711 712 static u32 *it66121_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 713 struct drm_bridge_state *bridge_state, 714 struct drm_crtc_state *crtc_state, 715 struct drm_connector_state *conn_state, 716 unsigned int *num_output_fmts) 717 { 718 u32 *output_fmts; 719 720 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 721 GFP_KERNEL); 722 if (!output_fmts) 723 return NULL; 724 725 /* TOFIX handle more than MEDIA_BUS_FMT_RGB888_1X24 as output format */ 726 output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 727 *num_output_fmts = 1; 728 729 return output_fmts; 730 } 731 732 #define MAX_INPUT_SEL_FORMATS 1 733 734 static u32 *it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 735 struct drm_bridge_state *bridge_state, 736 struct drm_crtc_state *crtc_state, 737 struct drm_connector_state *conn_state, 738 u32 output_fmt, 739 unsigned int *num_input_fmts) 740 { 741 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 742 u32 *input_fmts; 743 744 *num_input_fmts = 0; 745 746 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 747 GFP_KERNEL); 748 if (!input_fmts) 749 return NULL; 750 751 if (ctx->bus_width == 12) 752 /* IT66121FN Datasheet specifies Little-Endian ordering */ 753 input_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE; 754 else 755 /* TOFIX support more input bus formats in 24bit width */ 756 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 757 *num_input_fmts = 1; 758 759 return input_fmts; 760 } 761 762 static void it66121_bridge_enable(struct drm_bridge *bridge, 763 struct drm_bridge_state *bridge_state) 764 { 765 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 766 struct drm_atomic_state *state = bridge_state->base.state; 767 768 ctx->connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 769 770 it66121_set_mute(ctx, false); 771 } 772 773 static void it66121_bridge_disable(struct drm_bridge *bridge, 774 struct drm_bridge_state *bridge_state) 775 { 776 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 777 778 it66121_set_mute(ctx, true); 779 780 ctx->connector = NULL; 781 } 782 783 static 784 void it66121_bridge_mode_set(struct drm_bridge *bridge, 785 const struct drm_display_mode *mode, 786 const struct drm_display_mode *adjusted_mode) 787 { 788 int ret, i; 789 u8 buf[HDMI_INFOFRAME_SIZE(AVI)]; 790 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 791 const u16 aviinfo_reg[HDMI_AVI_INFOFRAME_SIZE] = { 792 IT66121_AVIINFO_DB1_REG, 793 IT66121_AVIINFO_DB2_REG, 794 IT66121_AVIINFO_DB3_REG, 795 IT66121_AVIINFO_DB4_REG, 796 IT66121_AVIINFO_DB5_REG, 797 IT66121_AVIINFO_DB6_REG, 798 IT66121_AVIINFO_DB7_REG, 799 IT66121_AVIINFO_DB8_REG, 800 IT66121_AVIINFO_DB9_REG, 801 IT66121_AVIINFO_DB10_REG, 802 IT66121_AVIINFO_DB11_REG, 803 IT66121_AVIINFO_DB12_REG, 804 IT66121_AVIINFO_DB13_REG 805 }; 806 807 mutex_lock(&ctx->lock); 808 809 hdmi_avi_infoframe_init(&ctx->hdmi_avi_infoframe); 810 811 ret = drm_hdmi_avi_infoframe_from_display_mode(&ctx->hdmi_avi_infoframe, ctx->connector, 812 adjusted_mode); 813 if (ret) { 814 DRM_ERROR("Failed to setup AVI infoframe: %d\n", ret); 815 goto unlock; 816 } 817 818 ret = hdmi_avi_infoframe_pack(&ctx->hdmi_avi_infoframe, buf, sizeof(buf)); 819 if (ret < 0) { 820 DRM_ERROR("Failed to pack infoframe: %d\n", ret); 821 goto unlock; 822 } 823 824 /* Write new AVI infoframe packet */ 825 for (i = 0; i < HDMI_AVI_INFOFRAME_SIZE; i++) { 826 if (regmap_write(ctx->regmap, aviinfo_reg[i], buf[i + HDMI_INFOFRAME_HEADER_SIZE])) 827 goto unlock; 828 } 829 if (regmap_write(ctx->regmap, IT66121_AVIINFO_CSUM_REG, buf[3])) 830 goto unlock; 831 832 /* Enable AVI infoframe */ 833 if (regmap_write(ctx->regmap, IT66121_AVI_INFO_PKT_REG, 834 IT66121_AVI_INFO_PKT_ON | IT66121_AVI_INFO_PKT_RPT)) 835 goto unlock; 836 837 /* Set TX mode to HDMI */ 838 if (regmap_write(ctx->regmap, IT66121_HDMI_MODE_REG, IT66121_HDMI_MODE_HDMI)) 839 goto unlock; 840 841 if (regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 842 IT66121_CLK_BANK_PWROFF_TXCLK, IT66121_CLK_BANK_PWROFF_TXCLK)) 843 goto unlock; 844 845 if (it66121_configure_input(ctx)) 846 goto unlock; 847 848 if (it66121_configure_afe(ctx, adjusted_mode)) 849 goto unlock; 850 851 regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, IT66121_CLK_BANK_PWROFF_TXCLK, 0); 852 853 unlock: 854 mutex_unlock(&ctx->lock); 855 } 856 857 static enum drm_mode_status it66121_bridge_mode_valid(struct drm_bridge *bridge, 858 const struct drm_display_info *info, 859 const struct drm_display_mode *mode) 860 { 861 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 862 unsigned long max_clock; 863 864 max_clock = (ctx->bus_width == 12) ? 74250 : 148500; 865 866 if (mode->clock > max_clock) 867 return MODE_CLOCK_HIGH; 868 869 if (mode->clock < 25000) 870 return MODE_CLOCK_LOW; 871 872 return MODE_OK; 873 } 874 875 static enum drm_connector_status it66121_bridge_detect(struct drm_bridge *bridge) 876 { 877 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 878 879 return it66121_is_hpd_detect(ctx) ? connector_status_connected 880 : connector_status_disconnected; 881 } 882 883 static void it66121_bridge_hpd_enable(struct drm_bridge *bridge) 884 { 885 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 886 int ret; 887 888 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, IT66121_INT_MASK1_HPD, 0); 889 if (ret) 890 dev_err(ctx->dev, "failed to enable HPD IRQ\n"); 891 } 892 893 static void it66121_bridge_hpd_disable(struct drm_bridge *bridge) 894 { 895 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 896 int ret; 897 898 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, 899 IT66121_INT_MASK1_HPD, IT66121_INT_MASK1_HPD); 900 if (ret) 901 dev_err(ctx->dev, "failed to disable HPD IRQ\n"); 902 } 903 904 static struct edid *it66121_bridge_get_edid(struct drm_bridge *bridge, 905 struct drm_connector *connector) 906 { 907 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 908 struct edid *edid; 909 910 mutex_lock(&ctx->lock); 911 edid = drm_do_get_edid(connector, it66121_get_edid_block, ctx); 912 mutex_unlock(&ctx->lock); 913 914 return edid; 915 } 916 917 static const struct drm_bridge_funcs it66121_bridge_funcs = { 918 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 919 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 920 .atomic_reset = drm_atomic_helper_bridge_reset, 921 .attach = it66121_bridge_attach, 922 .atomic_get_output_bus_fmts = it66121_bridge_atomic_get_output_bus_fmts, 923 .atomic_get_input_bus_fmts = it66121_bridge_atomic_get_input_bus_fmts, 924 .atomic_enable = it66121_bridge_enable, 925 .atomic_disable = it66121_bridge_disable, 926 .mode_set = it66121_bridge_mode_set, 927 .mode_valid = it66121_bridge_mode_valid, 928 .detect = it66121_bridge_detect, 929 .get_edid = it66121_bridge_get_edid, 930 .hpd_enable = it66121_bridge_hpd_enable, 931 .hpd_disable = it66121_bridge_hpd_disable, 932 }; 933 934 static irqreturn_t it66121_irq_threaded_handler(int irq, void *dev_id) 935 { 936 int ret; 937 unsigned int val; 938 struct it66121_ctx *ctx = dev_id; 939 struct device *dev = ctx->dev; 940 enum drm_connector_status status; 941 bool event = false; 942 943 mutex_lock(&ctx->lock); 944 945 ret = regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val); 946 if (ret) 947 goto unlock; 948 949 if (!(val & IT66121_SYS_STATUS_ACTIVE_IRQ)) 950 goto unlock; 951 952 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val); 953 if (ret) { 954 dev_err(dev, "Cannot read STATUS1_REG %d\n", ret); 955 } else { 956 if (val & IT66121_INT_STATUS1_DDC_FIFOERR) 957 it66121_clear_ddc_fifo(ctx); 958 if (val & (IT66121_INT_STATUS1_DDC_BUSHANG | 959 IT66121_INT_STATUS1_DDC_NOACK)) 960 it66121_abort_ddc_ops(ctx); 961 if (val & IT66121_INT_STATUS1_HPD_STATUS) { 962 regmap_write_bits(ctx->regmap, IT66121_INT_CLR1_REG, 963 IT66121_INT_CLR1_HPD, IT66121_INT_CLR1_HPD); 964 965 status = it66121_is_hpd_detect(ctx) ? connector_status_connected 966 : connector_status_disconnected; 967 968 event = true; 969 } 970 } 971 972 regmap_write_bits(ctx->regmap, IT66121_SYS_STATUS_REG, 973 IT66121_SYS_STATUS_CLEAR_IRQ, 974 IT66121_SYS_STATUS_CLEAR_IRQ); 975 976 unlock: 977 mutex_unlock(&ctx->lock); 978 979 if (event) 980 drm_bridge_hpd_notify(&ctx->bridge, status); 981 982 return IRQ_HANDLED; 983 } 984 985 static int it661221_set_chstat(struct it66121_ctx *ctx, u8 iec60958_chstat[]) 986 { 987 int ret; 988 989 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_MODE_REG, iec60958_chstat[0] & 0x7C); 990 if (ret) 991 return ret; 992 993 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CAT_REG, iec60958_chstat[1]); 994 if (ret) 995 return ret; 996 997 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_SRCNUM_REG, iec60958_chstat[2] & 0x0F); 998 if (ret) 999 return ret; 1000 1001 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CHTNUM_REG, 1002 (iec60958_chstat[2] >> 4) & 0x0F); 1003 if (ret) 1004 return ret; 1005 1006 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CA_FS_REG, iec60958_chstat[3]); 1007 if (ret) 1008 return ret; 1009 1010 return regmap_write(ctx->regmap, IT66121_AUD_CHST_OFS_WL_REG, iec60958_chstat[4]); 1011 } 1012 1013 static int it661221_set_lpcm_audio(struct it66121_ctx *ctx, u8 audio_src_num, u8 audio_swl) 1014 { 1015 int ret; 1016 unsigned int audio_enable = 0; 1017 unsigned int audio_format = 0; 1018 1019 switch (audio_swl) { 1020 case 16: 1021 audio_enable |= IT66121_AUD_16BIT; 1022 break; 1023 case 18: 1024 audio_enable |= IT66121_AUD_18BIT; 1025 break; 1026 case 20: 1027 audio_enable |= IT66121_AUD_20BIT; 1028 break; 1029 case 24: 1030 default: 1031 audio_enable |= IT66121_AUD_24BIT; 1032 break; 1033 } 1034 1035 audio_format |= 0x40; 1036 switch (audio_src_num) { 1037 case 4: 1038 audio_enable |= IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1039 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0; 1040 break; 1041 case 3: 1042 audio_enable |= IT66121_AUD_EN_I2S2 | IT66121_AUD_EN_I2S1 | 1043 IT66121_AUD_EN_I2S0; 1044 break; 1045 case 2: 1046 audio_enable |= IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0; 1047 break; 1048 case 1: 1049 default: 1050 audio_format &= ~0x40; 1051 audio_enable |= IT66121_AUD_EN_I2S0; 1052 break; 1053 } 1054 1055 audio_format |= 0x01; 1056 ctx->audio.ch_enable = audio_enable; 1057 1058 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, audio_enable & 0xF0); 1059 if (ret) 1060 return ret; 1061 1062 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL1_REG, audio_format); 1063 if (ret) 1064 return ret; 1065 1066 ret = regmap_write(ctx->regmap, IT66121_AUD_FIFOMAP_REG, 0xE4); 1067 if (ret) 1068 return ret; 1069 1070 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL3_REG, 0x00); 1071 if (ret) 1072 return ret; 1073 1074 ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0x00); 1075 if (ret) 1076 return ret; 1077 1078 return regmap_write(ctx->regmap, IT66121_AUD_HDAUDIO_REG, 0x00); 1079 } 1080 1081 static int it661221_set_ncts(struct it66121_ctx *ctx, u8 fs) 1082 { 1083 int ret; 1084 unsigned int n; 1085 1086 switch (fs) { 1087 case IT66121_AUD_FS_32K: 1088 n = 4096; 1089 break; 1090 case IT66121_AUD_FS_44P1K: 1091 n = 6272; 1092 break; 1093 case IT66121_AUD_FS_48K: 1094 n = 6144; 1095 break; 1096 case IT66121_AUD_FS_88P2K: 1097 n = 12544; 1098 break; 1099 case IT66121_AUD_FS_96K: 1100 n = 12288; 1101 break; 1102 case IT66121_AUD_FS_176P4K: 1103 n = 25088; 1104 break; 1105 case IT66121_AUD_FS_192K: 1106 n = 24576; 1107 break; 1108 case IT66121_AUD_FS_768K: 1109 n = 24576; 1110 break; 1111 default: 1112 n = 6144; 1113 break; 1114 } 1115 1116 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N0_REG, (u8)((n) & 0xFF)); 1117 if (ret) 1118 return ret; 1119 1120 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N1_REG, (u8)((n >> 8) & 0xFF)); 1121 if (ret) 1122 return ret; 1123 1124 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N2_REG, (u8)((n >> 16) & 0xF)); 1125 if (ret) 1126 return ret; 1127 1128 if (ctx->audio.auto_cts) { 1129 u8 loop_cnt = 255; 1130 u8 cts_stable_cnt = 0; 1131 unsigned int sum_cts = 0; 1132 unsigned int cts = 0; 1133 unsigned int last_cts = 0; 1134 unsigned int diff; 1135 unsigned int val; 1136 1137 while (loop_cnt--) { 1138 msleep(30); 1139 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT2_REG, &val); 1140 cts = val << 12; 1141 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT1_REG, &val); 1142 cts |= val << 4; 1143 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT0_REG, &val); 1144 cts |= val >> 4; 1145 if (cts == 0) { 1146 continue; 1147 } else { 1148 if (last_cts > cts) 1149 diff = last_cts - cts; 1150 else 1151 diff = cts - last_cts; 1152 last_cts = cts; 1153 if (diff < 5) { 1154 cts_stable_cnt++; 1155 sum_cts += cts; 1156 } else { 1157 cts_stable_cnt = 0; 1158 sum_cts = 0; 1159 continue; 1160 } 1161 1162 if (cts_stable_cnt >= 32) { 1163 last_cts = (sum_cts >> 5); 1164 break; 1165 } 1166 } 1167 } 1168 1169 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS0_REG, (u8)((last_cts) & 0xFF)); 1170 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS1_REG, (u8)((last_cts >> 8) & 0xFF)); 1171 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS2_REG, (u8)((last_cts >> 16) & 0x0F)); 1172 } 1173 1174 ret = regmap_write(ctx->regmap, 0xF8, 0xC3); 1175 if (ret) 1176 return ret; 1177 1178 ret = regmap_write(ctx->regmap, 0xF8, 0xA5); 1179 if (ret) 1180 return ret; 1181 1182 if (ctx->audio.auto_cts) { 1183 ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG, 1184 IT66121_PKT_CTS_CTRL_SEL, 1185 1); 1186 } else { 1187 ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG, 1188 IT66121_PKT_CTS_CTRL_SEL, 1189 0); 1190 } 1191 1192 if (ret) 1193 return ret; 1194 1195 return regmap_write(ctx->regmap, 0xF8, 0xFF); 1196 } 1197 1198 static int it661221_audio_output_enable(struct it66121_ctx *ctx, bool enable) 1199 { 1200 int ret; 1201 1202 if (enable) { 1203 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 1204 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF, 1205 0); 1206 if (ret) 1207 return ret; 1208 1209 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1210 IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1211 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0, 1212 ctx->audio.ch_enable); 1213 } else { 1214 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1215 IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1216 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0, 1217 ctx->audio.ch_enable & 0xF0); 1218 if (ret) 1219 return ret; 1220 1221 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 1222 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF, 1223 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF); 1224 } 1225 1226 return ret; 1227 } 1228 1229 static int it661221_audio_ch_enable(struct it66121_ctx *ctx, bool enable) 1230 { 1231 int ret; 1232 1233 if (enable) { 1234 ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0); 1235 if (ret) 1236 return ret; 1237 1238 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable); 1239 } else { 1240 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable & 0xF0); 1241 } 1242 1243 return ret; 1244 } 1245 1246 static int it66121_audio_hw_params(struct device *dev, void *data, 1247 struct hdmi_codec_daifmt *daifmt, 1248 struct hdmi_codec_params *params) 1249 { 1250 u8 fs; 1251 u8 swl; 1252 int ret; 1253 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1254 static u8 iec60958_chstat[5]; 1255 unsigned int channels = params->channels; 1256 unsigned int sample_rate = params->sample_rate; 1257 unsigned int sample_width = params->sample_width; 1258 1259 mutex_lock(&ctx->lock); 1260 dev_dbg(dev, "%s: %u, %u, %u, %u\n", __func__, 1261 daifmt->fmt, sample_rate, sample_width, channels); 1262 1263 switch (daifmt->fmt) { 1264 case HDMI_I2S: 1265 dev_dbg(dev, "Using HDMI I2S\n"); 1266 break; 1267 default: 1268 dev_err(dev, "Invalid or unsupported DAI format %d\n", daifmt->fmt); 1269 ret = -EINVAL; 1270 goto out; 1271 } 1272 1273 // Set audio clock recovery (N/CTS) 1274 ret = regmap_write(ctx->regmap, IT66121_CLK_CTRL0_REG, 1275 IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING | 1276 IT66121_CLK_CTRL0_EXT_MCLK_256FS | 1277 IT66121_CLK_CTRL0_AUTO_IPCLK); 1278 if (ret) 1279 goto out; 1280 1281 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1282 IT66121_AUD_CTRL0_AUD_SEL, 0); // remove spdif selection 1283 if (ret) 1284 goto out; 1285 1286 switch (sample_rate) { 1287 case 44100L: 1288 fs = IT66121_AUD_FS_44P1K; 1289 break; 1290 case 88200L: 1291 fs = IT66121_AUD_FS_88P2K; 1292 break; 1293 case 176400L: 1294 fs = IT66121_AUD_FS_176P4K; 1295 break; 1296 case 32000L: 1297 fs = IT66121_AUD_FS_32K; 1298 break; 1299 case 48000L: 1300 fs = IT66121_AUD_FS_48K; 1301 break; 1302 case 96000L: 1303 fs = IT66121_AUD_FS_96K; 1304 break; 1305 case 192000L: 1306 fs = IT66121_AUD_FS_192K; 1307 break; 1308 case 768000L: 1309 fs = IT66121_AUD_FS_768K; 1310 break; 1311 default: 1312 fs = IT66121_AUD_FS_48K; 1313 break; 1314 } 1315 1316 ctx->audio.fs = fs; 1317 ret = it661221_set_ncts(ctx, fs); 1318 if (ret) { 1319 dev_err(dev, "Failed to set N/CTS: %d\n", ret); 1320 goto out; 1321 } 1322 1323 // Set audio format register (except audio channel enable) 1324 ret = it661221_set_lpcm_audio(ctx, (channels + 1) / 2, sample_width); 1325 if (ret) { 1326 dev_err(dev, "Failed to set LPCM audio: %d\n", ret); 1327 goto out; 1328 } 1329 1330 // Set audio channel status 1331 iec60958_chstat[0] = 0; 1332 if ((channels + 1) / 2 == 1) 1333 iec60958_chstat[0] |= 0x1; 1334 iec60958_chstat[0] &= ~(1 << 1); 1335 iec60958_chstat[1] = 0; 1336 iec60958_chstat[2] = (channels + 1) / 2; 1337 iec60958_chstat[2] |= (channels << 4) & 0xF0; 1338 iec60958_chstat[3] = fs; 1339 1340 switch (sample_width) { 1341 case 21L: 1342 swl = IT66121_AUD_SWL_21BIT; 1343 break; 1344 case 24L: 1345 swl = IT66121_AUD_SWL_24BIT; 1346 break; 1347 case 23L: 1348 swl = IT66121_AUD_SWL_23BIT; 1349 break; 1350 case 22L: 1351 swl = IT66121_AUD_SWL_22BIT; 1352 break; 1353 case 20L: 1354 swl = IT66121_AUD_SWL_20BIT; 1355 break; 1356 case 17L: 1357 swl = IT66121_AUD_SWL_17BIT; 1358 break; 1359 case 19L: 1360 swl = IT66121_AUD_SWL_19BIT; 1361 break; 1362 case 18L: 1363 swl = IT66121_AUD_SWL_18BIT; 1364 break; 1365 case 16L: 1366 swl = IT66121_AUD_SWL_16BIT; 1367 break; 1368 default: 1369 swl = IT66121_AUD_SWL_NOT_INDICATED; 1370 break; 1371 } 1372 1373 iec60958_chstat[4] = (((~fs) << 4) & 0xF0) | swl; 1374 ret = it661221_set_chstat(ctx, iec60958_chstat); 1375 if (ret) { 1376 dev_err(dev, "Failed to set channel status: %d\n", ret); 1377 goto out; 1378 } 1379 1380 // Enable audio channel enable while input clock stable (if SPDIF). 1381 ret = it661221_audio_ch_enable(ctx, true); 1382 if (ret) { 1383 dev_err(dev, "Failed to enable audio channel: %d\n", ret); 1384 goto out; 1385 } 1386 1387 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, 1388 IT66121_INT_MASK1_AUD_OVF, 1389 0); 1390 if (ret) 1391 goto out; 1392 1393 dev_dbg(dev, "HDMI audio enabled.\n"); 1394 out: 1395 mutex_unlock(&ctx->lock); 1396 1397 return ret; 1398 } 1399 1400 static int it66121_audio_startup(struct device *dev, void *data) 1401 { 1402 int ret; 1403 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1404 1405 dev_dbg(dev, "%s\n", __func__); 1406 1407 mutex_lock(&ctx->lock); 1408 ret = it661221_audio_output_enable(ctx, true); 1409 if (ret) 1410 dev_err(dev, "Failed to enable audio output: %d\n", ret); 1411 1412 mutex_unlock(&ctx->lock); 1413 1414 return ret; 1415 } 1416 1417 static void it66121_audio_shutdown(struct device *dev, void *data) 1418 { 1419 int ret; 1420 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1421 1422 dev_dbg(dev, "%s\n", __func__); 1423 1424 mutex_lock(&ctx->lock); 1425 ret = it661221_audio_output_enable(ctx, false); 1426 if (ret) 1427 dev_err(dev, "Failed to disable audio output: %d\n", ret); 1428 1429 mutex_unlock(&ctx->lock); 1430 } 1431 1432 static int it66121_audio_mute(struct device *dev, void *data, 1433 bool enable, int direction) 1434 { 1435 int ret; 1436 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1437 1438 dev_dbg(dev, "%s: enable=%s, direction=%d\n", 1439 __func__, enable ? "true" : "false", direction); 1440 1441 mutex_lock(&ctx->lock); 1442 1443 if (enable) { 1444 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 1445 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1446 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3, 1447 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1448 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3); 1449 } else { 1450 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 1451 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1452 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3, 1453 0); 1454 } 1455 1456 mutex_unlock(&ctx->lock); 1457 1458 return ret; 1459 } 1460 1461 static int it66121_audio_get_eld(struct device *dev, void *data, 1462 u8 *buf, size_t len) 1463 { 1464 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1465 1466 mutex_lock(&ctx->lock); 1467 1468 memcpy(buf, ctx->connector->eld, 1469 min(sizeof(ctx->connector->eld), len)); 1470 1471 mutex_unlock(&ctx->lock); 1472 1473 return 0; 1474 } 1475 1476 static const struct hdmi_codec_ops it66121_audio_codec_ops = { 1477 .hw_params = it66121_audio_hw_params, 1478 .audio_startup = it66121_audio_startup, 1479 .audio_shutdown = it66121_audio_shutdown, 1480 .mute_stream = it66121_audio_mute, 1481 .get_eld = it66121_audio_get_eld, 1482 .no_capture_mute = 1, 1483 }; 1484 1485 static int it66121_audio_codec_init(struct it66121_ctx *ctx, struct device *dev) 1486 { 1487 struct hdmi_codec_pdata codec_data = { 1488 .ops = &it66121_audio_codec_ops, 1489 .i2s = 1, /* Only i2s support for now */ 1490 .spdif = 0, 1491 .max_i2s_channels = 8, 1492 }; 1493 1494 dev_dbg(dev, "%s\n", __func__); 1495 1496 if (!of_property_read_bool(dev->of_node, "#sound-dai-cells")) { 1497 dev_info(dev, "No \"#sound-dai-cells\", no audio\n"); 1498 return 0; 1499 } 1500 1501 ctx->audio.pdev = platform_device_register_data(dev, 1502 HDMI_CODEC_DRV_NAME, 1503 PLATFORM_DEVID_AUTO, 1504 &codec_data, 1505 sizeof(codec_data)); 1506 1507 if (IS_ERR(ctx->audio.pdev)) { 1508 dev_err(dev, "Failed to initialize HDMI audio codec: %d\n", 1509 PTR_ERR_OR_ZERO(ctx->audio.pdev)); 1510 } 1511 1512 return PTR_ERR_OR_ZERO(ctx->audio.pdev); 1513 } 1514 1515 static int it66121_probe(struct i2c_client *client, 1516 const struct i2c_device_id *id) 1517 { 1518 u32 revision_id, vendor_ids[2] = { 0 }, device_ids[2] = { 0 }; 1519 struct device_node *ep; 1520 int ret; 1521 struct it66121_ctx *ctx; 1522 struct device *dev = &client->dev; 1523 1524 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1525 dev_err(dev, "I2C check functionality failed.\n"); 1526 return -ENXIO; 1527 } 1528 1529 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1530 if (!ctx) 1531 return -ENOMEM; 1532 1533 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 1534 if (!ep) 1535 return -EINVAL; 1536 1537 ctx->dev = dev; 1538 ctx->client = client; 1539 1540 of_property_read_u32(ep, "bus-width", &ctx->bus_width); 1541 of_node_put(ep); 1542 1543 if (ctx->bus_width != 12 && ctx->bus_width != 24) 1544 return -EINVAL; 1545 1546 ep = of_graph_get_remote_node(dev->of_node, 1, -1); 1547 if (!ep) { 1548 dev_err(ctx->dev, "The endpoint is unconnected\n"); 1549 return -EINVAL; 1550 } 1551 1552 if (!of_device_is_available(ep)) { 1553 of_node_put(ep); 1554 dev_err(ctx->dev, "The remote device is disabled\n"); 1555 return -ENODEV; 1556 } 1557 1558 ctx->next_bridge = of_drm_find_bridge(ep); 1559 of_node_put(ep); 1560 if (!ctx->next_bridge) { 1561 dev_dbg(ctx->dev, "Next bridge not found, deferring probe\n"); 1562 return -EPROBE_DEFER; 1563 } 1564 1565 i2c_set_clientdata(client, ctx); 1566 mutex_init(&ctx->lock); 1567 1568 ctx->supplies[0].supply = "vcn33"; 1569 ctx->supplies[1].supply = "vcn18"; 1570 ctx->supplies[2].supply = "vrf12"; 1571 ret = devm_regulator_bulk_get(ctx->dev, 3, ctx->supplies); 1572 if (ret) { 1573 dev_err(ctx->dev, "regulator_bulk failed\n"); 1574 return ret; 1575 } 1576 1577 ret = ite66121_power_on(ctx); 1578 if (ret) 1579 return ret; 1580 1581 it66121_hw_reset(ctx); 1582 1583 ctx->regmap = devm_regmap_init_i2c(client, &it66121_regmap_config); 1584 if (IS_ERR(ctx->regmap)) { 1585 ite66121_power_off(ctx); 1586 return PTR_ERR(ctx->regmap); 1587 } 1588 1589 regmap_read(ctx->regmap, IT66121_VENDOR_ID0_REG, &vendor_ids[0]); 1590 regmap_read(ctx->regmap, IT66121_VENDOR_ID1_REG, &vendor_ids[1]); 1591 regmap_read(ctx->regmap, IT66121_DEVICE_ID0_REG, &device_ids[0]); 1592 regmap_read(ctx->regmap, IT66121_DEVICE_ID1_REG, &device_ids[1]); 1593 1594 /* Revision is shared with DEVICE_ID1 */ 1595 revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]); 1596 device_ids[1] &= IT66121_DEVICE_ID1_MASK; 1597 1598 if (vendor_ids[0] != IT66121_VENDOR_ID0 || vendor_ids[1] != IT66121_VENDOR_ID1 || 1599 device_ids[0] != IT66121_DEVICE_ID0 || device_ids[1] != IT66121_DEVICE_ID1) { 1600 ite66121_power_off(ctx); 1601 return -ENODEV; 1602 } 1603 1604 ctx->bridge.funcs = &it66121_bridge_funcs; 1605 ctx->bridge.of_node = dev->of_node; 1606 ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 1607 ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; 1608 1609 ret = devm_request_threaded_irq(dev, client->irq, NULL, it66121_irq_threaded_handler, 1610 IRQF_ONESHOT, dev_name(dev), ctx); 1611 if (ret < 0) { 1612 dev_err(dev, "Failed to request irq %d:%d\n", client->irq, ret); 1613 ite66121_power_off(ctx); 1614 return ret; 1615 } 1616 1617 it66121_audio_codec_init(ctx, dev); 1618 1619 drm_bridge_add(&ctx->bridge); 1620 1621 dev_info(ctx->dev, "IT66121 revision %d probed\n", revision_id); 1622 1623 return 0; 1624 } 1625 1626 static void it66121_remove(struct i2c_client *client) 1627 { 1628 struct it66121_ctx *ctx = i2c_get_clientdata(client); 1629 1630 ite66121_power_off(ctx); 1631 drm_bridge_remove(&ctx->bridge); 1632 mutex_destroy(&ctx->lock); 1633 } 1634 1635 static const struct of_device_id it66121_dt_match[] = { 1636 { .compatible = "ite,it66121" }, 1637 { } 1638 }; 1639 MODULE_DEVICE_TABLE(of, it66121_dt_match); 1640 1641 static const struct i2c_device_id it66121_id[] = { 1642 { "it66121", 0 }, 1643 { } 1644 }; 1645 MODULE_DEVICE_TABLE(i2c, it66121_id); 1646 1647 static struct i2c_driver it66121_driver = { 1648 .driver = { 1649 .name = "it66121", 1650 .of_match_table = it66121_dt_match, 1651 }, 1652 .probe = it66121_probe, 1653 .remove = it66121_remove, 1654 .id_table = it66121_id, 1655 }; 1656 1657 module_i2c_driver(it66121_driver); 1658 1659 MODULE_AUTHOR("Phong LE"); 1660 MODULE_DESCRIPTION("IT66121 HDMI transmitter driver"); 1661 MODULE_LICENSE("GPL v2"); 1662