1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* exynos_drm_fimd.c 3 * 4 * Copyright (C) 2011 Samsung Electronics Co.Ltd 5 * Authors: 6 * Joonyoung Shim <jy0922.shim@samsung.com> 7 * Inki Dae <inki.dae@samsung.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/component.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 20 #include <video/of_display_timing.h> 21 #include <video/of_videomode.h> 22 #include <video/samsung_fimd.h> 23 24 #include <drm/drm_blend.h> 25 #include <drm/drm_fourcc.h> 26 #include <drm/drm_framebuffer.h> 27 #include <drm/drm_vblank.h> 28 #include <drm/exynos_drm.h> 29 30 #include "exynos_drm_crtc.h" 31 #include "exynos_drm_drv.h" 32 #include "exynos_drm_fb.h" 33 #include "exynos_drm_plane.h" 34 35 /* 36 * FIMD stands for Fully Interactive Mobile Display and 37 * as a display controller, it transfers contents drawn on memory 38 * to a LCD Panel through Display Interfaces such as RGB or 39 * CPU Interface. 40 */ 41 42 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 43 44 /* position control register for hardware window 0, 2 ~ 4.*/ 45 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 46 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 47 /* 48 * size control register for hardware windows 0 and alpha control register 49 * for hardware windows 1 ~ 4 50 */ 51 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) 52 /* size control register for hardware windows 1 ~ 2. */ 53 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 54 55 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) 56 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) 57 58 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 59 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8) 60 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 61 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 62 63 /* color key control register for hardware window 1 ~ 4. */ 64 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) 65 /* color key value register for hardware window 1 ~ 4. */ 66 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) 67 68 /* I80 trigger control register */ 69 #define TRIGCON 0x1A4 70 #define TRGMODE_ENABLE (1 << 0) 71 #define SWTRGCMD_ENABLE (1 << 1) 72 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */ 73 #define HWTRGEN_ENABLE (1 << 3) 74 #define HWTRGMASK_ENABLE (1 << 4) 75 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */ 76 #define HWTRIGEN_PER_ENABLE (1 << 31) 77 78 /* display mode change control register except exynos4 */ 79 #define VIDOUT_CON 0x000 80 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) 81 82 /* I80 interface control for main LDI register */ 83 #define I80IFCONFAx(x) (0x1B0 + (x) * 4) 84 #define I80IFCONFBx(x) (0x1B8 + (x) * 4) 85 #define LCD_CS_SETUP(x) ((x) << 16) 86 #define LCD_WR_SETUP(x) ((x) << 12) 87 #define LCD_WR_ACTIVE(x) ((x) << 8) 88 #define LCD_WR_HOLD(x) ((x) << 4) 89 #define I80IFEN_ENABLE (1 << 0) 90 91 /* FIMD has totally five hardware windows. */ 92 #define WINDOWS_NR 5 93 94 /* HW trigger flag on i80 panel. */ 95 #define I80_HW_TRG (1 << 1) 96 97 struct fimd_driver_data { 98 unsigned int timing_base; 99 unsigned int lcdblk_offset; 100 unsigned int lcdblk_vt_shift; 101 unsigned int lcdblk_bypass_shift; 102 unsigned int lcdblk_mic_bypass_shift; 103 unsigned int trg_type; 104 105 unsigned int has_shadowcon:1; 106 unsigned int has_clksel:1; 107 unsigned int has_limited_fmt:1; 108 unsigned int has_vidoutcon:1; 109 unsigned int has_vtsel:1; 110 unsigned int has_mic_bypass:1; 111 unsigned int has_dp_clk:1; 112 unsigned int has_hw_trigger:1; 113 unsigned int has_trigger_per_te:1; 114 unsigned int has_bgr_support:1; 115 }; 116 117 static struct fimd_driver_data s3c64xx_fimd_driver_data = { 118 .timing_base = 0x0, 119 .has_clksel = 1, 120 .has_limited_fmt = 1, 121 }; 122 123 static struct fimd_driver_data s5pv210_fimd_driver_data = { 124 .timing_base = 0x0, 125 .has_shadowcon = 1, 126 .has_clksel = 1, 127 }; 128 129 static struct fimd_driver_data exynos3_fimd_driver_data = { 130 .timing_base = 0x20000, 131 .lcdblk_offset = 0x210, 132 .lcdblk_bypass_shift = 1, 133 .has_shadowcon = 1, 134 .has_vidoutcon = 1, 135 }; 136 137 static struct fimd_driver_data exynos4_fimd_driver_data = { 138 .timing_base = 0x0, 139 .lcdblk_offset = 0x210, 140 .lcdblk_vt_shift = 10, 141 .lcdblk_bypass_shift = 1, 142 .has_shadowcon = 1, 143 .has_vtsel = 1, 144 .has_bgr_support = 1, 145 }; 146 147 static struct fimd_driver_data exynos5_fimd_driver_data = { 148 .timing_base = 0x20000, 149 .lcdblk_offset = 0x214, 150 .lcdblk_vt_shift = 24, 151 .lcdblk_bypass_shift = 15, 152 .has_shadowcon = 1, 153 .has_vidoutcon = 1, 154 .has_vtsel = 1, 155 .has_dp_clk = 1, 156 .has_bgr_support = 1, 157 }; 158 159 static struct fimd_driver_data exynos5420_fimd_driver_data = { 160 .timing_base = 0x20000, 161 .lcdblk_offset = 0x214, 162 .lcdblk_vt_shift = 24, 163 .lcdblk_bypass_shift = 15, 164 .lcdblk_mic_bypass_shift = 11, 165 .has_shadowcon = 1, 166 .has_vidoutcon = 1, 167 .has_vtsel = 1, 168 .has_mic_bypass = 1, 169 .has_dp_clk = 1, 170 .has_bgr_support = 1, 171 }; 172 173 struct fimd_context { 174 struct device *dev; 175 struct drm_device *drm_dev; 176 void *dma_priv; 177 struct exynos_drm_crtc *crtc; 178 struct exynos_drm_plane planes[WINDOWS_NR]; 179 struct exynos_drm_plane_config configs[WINDOWS_NR]; 180 struct clk *bus_clk; 181 struct clk *lcd_clk; 182 void __iomem *regs; 183 struct regmap *sysreg; 184 unsigned long irq_flags; 185 u32 vidcon0; 186 u32 vidcon1; 187 u32 vidout_con; 188 u32 i80ifcon; 189 bool i80_if; 190 bool suspended; 191 wait_queue_head_t wait_vsync_queue; 192 atomic_t wait_vsync_event; 193 atomic_t win_updated; 194 atomic_t triggering; 195 u32 clkdiv; 196 197 const struct fimd_driver_data *driver_data; 198 struct drm_encoder *encoder; 199 struct exynos_drm_clk dp_clk; 200 }; 201 202 static const struct of_device_id fimd_driver_dt_match[] = { 203 { .compatible = "samsung,s3c6400-fimd", 204 .data = &s3c64xx_fimd_driver_data }, 205 { .compatible = "samsung,s5pv210-fimd", 206 .data = &s5pv210_fimd_driver_data }, 207 { .compatible = "samsung,exynos3250-fimd", 208 .data = &exynos3_fimd_driver_data }, 209 { .compatible = "samsung,exynos4210-fimd", 210 .data = &exynos4_fimd_driver_data }, 211 { .compatible = "samsung,exynos5250-fimd", 212 .data = &exynos5_fimd_driver_data }, 213 { .compatible = "samsung,exynos5420-fimd", 214 .data = &exynos5420_fimd_driver_data }, 215 {}, 216 }; 217 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); 218 219 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = { 220 DRM_PLANE_TYPE_PRIMARY, 221 DRM_PLANE_TYPE_OVERLAY, 222 DRM_PLANE_TYPE_OVERLAY, 223 DRM_PLANE_TYPE_OVERLAY, 224 DRM_PLANE_TYPE_CURSOR, 225 }; 226 227 static const uint32_t fimd_formats[] = { 228 DRM_FORMAT_C8, 229 DRM_FORMAT_XRGB1555, 230 DRM_FORMAT_RGB565, 231 DRM_FORMAT_XRGB8888, 232 DRM_FORMAT_ARGB8888, 233 }; 234 235 static const uint32_t fimd_extended_formats[] = { 236 DRM_FORMAT_C8, 237 DRM_FORMAT_XRGB1555, 238 DRM_FORMAT_XBGR1555, 239 DRM_FORMAT_RGB565, 240 DRM_FORMAT_BGR565, 241 DRM_FORMAT_XRGB8888, 242 DRM_FORMAT_XBGR8888, 243 DRM_FORMAT_ARGB8888, 244 DRM_FORMAT_ABGR8888, 245 }; 246 247 static const unsigned int capabilities[WINDOWS_NR] = { 248 0, 249 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 250 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 251 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 252 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 253 }; 254 255 static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, 256 u32 val) 257 { 258 val = (val & mask) | (readl(ctx->regs + reg) & ~mask); 259 writel(val, ctx->regs + reg); 260 } 261 262 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) 263 { 264 struct fimd_context *ctx = crtc->ctx; 265 u32 val; 266 267 if (ctx->suspended) 268 return -EPERM; 269 270 if (!test_and_set_bit(0, &ctx->irq_flags)) { 271 val = readl(ctx->regs + VIDINTCON0); 272 273 val |= VIDINTCON0_INT_ENABLE; 274 275 if (ctx->i80_if) { 276 val |= VIDINTCON0_INT_I80IFDONE; 277 val |= VIDINTCON0_INT_SYSMAINCON; 278 val &= ~VIDINTCON0_INT_SYSSUBCON; 279 } else { 280 val |= VIDINTCON0_INT_FRAME; 281 282 val &= ~VIDINTCON0_FRAMESEL0_MASK; 283 val |= VIDINTCON0_FRAMESEL0_FRONTPORCH; 284 val &= ~VIDINTCON0_FRAMESEL1_MASK; 285 val |= VIDINTCON0_FRAMESEL1_NONE; 286 } 287 288 writel(val, ctx->regs + VIDINTCON0); 289 } 290 291 return 0; 292 } 293 294 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) 295 { 296 struct fimd_context *ctx = crtc->ctx; 297 u32 val; 298 299 if (ctx->suspended) 300 return; 301 302 if (test_and_clear_bit(0, &ctx->irq_flags)) { 303 val = readl(ctx->regs + VIDINTCON0); 304 305 val &= ~VIDINTCON0_INT_ENABLE; 306 307 if (ctx->i80_if) { 308 val &= ~VIDINTCON0_INT_I80IFDONE; 309 val &= ~VIDINTCON0_INT_SYSMAINCON; 310 val &= ~VIDINTCON0_INT_SYSSUBCON; 311 } else 312 val &= ~VIDINTCON0_INT_FRAME; 313 314 writel(val, ctx->regs + VIDINTCON0); 315 } 316 } 317 318 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) 319 { 320 struct fimd_context *ctx = crtc->ctx; 321 322 if (ctx->suspended) 323 return; 324 325 atomic_set(&ctx->wait_vsync_event, 1); 326 327 /* 328 * wait for FIMD to signal VSYNC interrupt or return after 329 * timeout which is set to 50ms (refresh rate of 20). 330 */ 331 if (!wait_event_timeout(ctx->wait_vsync_queue, 332 !atomic_read(&ctx->wait_vsync_event), 333 HZ/20)) 334 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); 335 } 336 337 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, 338 bool enable) 339 { 340 u32 val = readl(ctx->regs + WINCON(win)); 341 342 if (enable) 343 val |= WINCONx_ENWIN; 344 else 345 val &= ~WINCONx_ENWIN; 346 347 writel(val, ctx->regs + WINCON(win)); 348 } 349 350 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, 351 unsigned int win, 352 bool enable) 353 { 354 u32 val = readl(ctx->regs + SHADOWCON); 355 356 if (enable) 357 val |= SHADOWCON_CHx_ENABLE(win); 358 else 359 val &= ~SHADOWCON_CHx_ENABLE(win); 360 361 writel(val, ctx->regs + SHADOWCON); 362 } 363 364 static int fimd_clear_channels(struct exynos_drm_crtc *crtc) 365 { 366 struct fimd_context *ctx = crtc->ctx; 367 unsigned int win, ch_enabled = 0; 368 int ret; 369 370 /* Hardware is in unknown state, so ensure it gets enabled properly */ 371 ret = pm_runtime_resume_and_get(ctx->dev); 372 if (ret < 0) { 373 dev_err(ctx->dev, "failed to enable FIMD device.\n"); 374 return ret; 375 } 376 377 clk_prepare_enable(ctx->bus_clk); 378 clk_prepare_enable(ctx->lcd_clk); 379 380 /* Check if any channel is enabled. */ 381 for (win = 0; win < WINDOWS_NR; win++) { 382 u32 val = readl(ctx->regs + WINCON(win)); 383 384 if (val & WINCONx_ENWIN) { 385 fimd_enable_video_output(ctx, win, false); 386 387 if (ctx->driver_data->has_shadowcon) 388 fimd_enable_shadow_channel_path(ctx, win, 389 false); 390 391 ch_enabled = 1; 392 } 393 } 394 395 /* Wait for vsync, as disable channel takes effect at next vsync */ 396 if (ch_enabled) { 397 ctx->suspended = false; 398 399 fimd_enable_vblank(ctx->crtc); 400 fimd_wait_for_vblank(ctx->crtc); 401 fimd_disable_vblank(ctx->crtc); 402 403 ctx->suspended = true; 404 } 405 406 clk_disable_unprepare(ctx->lcd_clk); 407 clk_disable_unprepare(ctx->bus_clk); 408 409 pm_runtime_put(ctx->dev); 410 411 return 0; 412 } 413 414 415 static int fimd_atomic_check(struct exynos_drm_crtc *crtc, 416 struct drm_crtc_state *state) 417 { 418 struct drm_display_mode *mode = &state->adjusted_mode; 419 struct fimd_context *ctx = crtc->ctx; 420 unsigned long ideal_clk, lcd_rate; 421 u32 clkdiv; 422 423 if (mode->clock == 0) { 424 DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n"); 425 return -EINVAL; 426 } 427 428 ideal_clk = mode->clock * 1000; 429 430 if (ctx->i80_if) { 431 /* 432 * The frame done interrupt should be occurred prior to the 433 * next TE signal. 434 */ 435 ideal_clk *= 2; 436 } 437 438 lcd_rate = clk_get_rate(ctx->lcd_clk); 439 if (2 * lcd_rate < ideal_clk) { 440 DRM_DEV_ERROR(ctx->dev, 441 "sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n", 442 lcd_rate, ideal_clk); 443 return -EINVAL; 444 } 445 446 /* Find the clock divider value that gets us closest to ideal_clk */ 447 clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk); 448 if (clkdiv >= 0x200) { 449 DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n", 450 ideal_clk); 451 return -EINVAL; 452 } 453 454 ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff; 455 456 return 0; 457 } 458 459 static void fimd_setup_trigger(struct fimd_context *ctx) 460 { 461 void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base; 462 u32 trg_type = ctx->driver_data->trg_type; 463 u32 val = readl(timing_base + TRIGCON); 464 465 val &= ~(TRGMODE_ENABLE); 466 467 if (trg_type == I80_HW_TRG) { 468 if (ctx->driver_data->has_hw_trigger) 469 val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE; 470 if (ctx->driver_data->has_trigger_per_te) 471 val |= HWTRIGEN_PER_ENABLE; 472 } else { 473 val |= TRGMODE_ENABLE; 474 } 475 476 writel(val, timing_base + TRIGCON); 477 } 478 479 static void fimd_commit(struct exynos_drm_crtc *crtc) 480 { 481 struct fimd_context *ctx = crtc->ctx; 482 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 483 const struct fimd_driver_data *driver_data = ctx->driver_data; 484 void *timing_base = ctx->regs + driver_data->timing_base; 485 u32 val; 486 487 if (ctx->suspended) 488 return; 489 490 /* nothing to do if we haven't set the mode yet */ 491 if (mode->htotal == 0 || mode->vtotal == 0) 492 return; 493 494 if (ctx->i80_if) { 495 val = ctx->i80ifcon | I80IFEN_ENABLE; 496 writel(val, timing_base + I80IFCONFAx(0)); 497 498 /* disable auto frame rate */ 499 writel(0, timing_base + I80IFCONFBx(0)); 500 501 /* set video type selection to I80 interface */ 502 if (driver_data->has_vtsel && ctx->sysreg && 503 regmap_update_bits(ctx->sysreg, 504 driver_data->lcdblk_offset, 505 0x3 << driver_data->lcdblk_vt_shift, 506 0x1 << driver_data->lcdblk_vt_shift)) { 507 DRM_DEV_ERROR(ctx->dev, 508 "Failed to update sysreg for I80 i/f.\n"); 509 return; 510 } 511 } else { 512 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 513 u32 vidcon1; 514 515 /* setup polarity values */ 516 vidcon1 = ctx->vidcon1; 517 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 518 vidcon1 |= VIDCON1_INV_VSYNC; 519 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 520 vidcon1 |= VIDCON1_INV_HSYNC; 521 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); 522 523 /* setup vertical timing values. */ 524 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 525 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 526 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 527 528 val = VIDTCON0_VBPD(vbpd - 1) | 529 VIDTCON0_VFPD(vfpd - 1) | 530 VIDTCON0_VSPW(vsync_len - 1); 531 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); 532 533 /* setup horizontal timing values. */ 534 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 535 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 536 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 537 538 val = VIDTCON1_HBPD(hbpd - 1) | 539 VIDTCON1_HFPD(hfpd - 1) | 540 VIDTCON1_HSPW(hsync_len - 1); 541 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); 542 } 543 544 if (driver_data->has_vidoutcon) 545 writel(ctx->vidout_con, timing_base + VIDOUT_CON); 546 547 /* set bypass selection */ 548 if (ctx->sysreg && regmap_update_bits(ctx->sysreg, 549 driver_data->lcdblk_offset, 550 0x1 << driver_data->lcdblk_bypass_shift, 551 0x1 << driver_data->lcdblk_bypass_shift)) { 552 DRM_DEV_ERROR(ctx->dev, 553 "Failed to update sysreg for bypass setting.\n"); 554 return; 555 } 556 557 /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass 558 * bit should be cleared. 559 */ 560 if (driver_data->has_mic_bypass && ctx->sysreg && 561 regmap_update_bits(ctx->sysreg, 562 driver_data->lcdblk_offset, 563 0x1 << driver_data->lcdblk_mic_bypass_shift, 564 0x1 << driver_data->lcdblk_mic_bypass_shift)) { 565 DRM_DEV_ERROR(ctx->dev, 566 "Failed to update sysreg for bypass mic.\n"); 567 return; 568 } 569 570 /* setup horizontal and vertical display size. */ 571 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | 572 VIDTCON2_HOZVAL(mode->hdisplay - 1) | 573 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | 574 VIDTCON2_HOZVAL_E(mode->hdisplay - 1); 575 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); 576 577 fimd_setup_trigger(ctx); 578 579 /* 580 * fields of register with prefix '_F' would be updated 581 * at vsync(same as dma start) 582 */ 583 val = ctx->vidcon0; 584 val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 585 586 if (ctx->driver_data->has_clksel) 587 val |= VIDCON0_CLKSEL_LCD; 588 589 if (ctx->clkdiv > 1) 590 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; 591 592 writel(val, ctx->regs + VIDCON0); 593 } 594 595 static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win, 596 unsigned int alpha, unsigned int pixel_alpha) 597 { 598 u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf); 599 u32 val = 0; 600 601 switch (pixel_alpha) { 602 case DRM_MODE_BLEND_PIXEL_NONE: 603 case DRM_MODE_BLEND_COVERAGE: 604 val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A); 605 val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); 606 break; 607 case DRM_MODE_BLEND_PREMULTI: 608 default: 609 if (alpha != DRM_BLEND_ALPHA_OPAQUE) { 610 val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0); 611 val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); 612 } else { 613 val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE); 614 val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); 615 } 616 break; 617 } 618 fimd_set_bits(ctx, BLENDEQx(win), mask, val); 619 } 620 621 static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win, 622 unsigned int alpha, unsigned int pixel_alpha) 623 { 624 u32 win_alpha_l = (alpha >> 8) & 0xf; 625 u32 win_alpha_h = alpha >> 12; 626 u32 val = 0; 627 628 switch (pixel_alpha) { 629 case DRM_MODE_BLEND_PIXEL_NONE: 630 break; 631 case DRM_MODE_BLEND_COVERAGE: 632 case DRM_MODE_BLEND_PREMULTI: 633 default: 634 val |= WINCON1_ALPHA_SEL; 635 val |= WINCON1_BLD_PIX; 636 val |= WINCON1_ALPHA_MUL; 637 break; 638 } 639 fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val); 640 641 /* OSD alpha */ 642 val = VIDISD14C_ALPHA0_R(win_alpha_h) | 643 VIDISD14C_ALPHA0_G(win_alpha_h) | 644 VIDISD14C_ALPHA0_B(win_alpha_h) | 645 VIDISD14C_ALPHA1_R(0x0) | 646 VIDISD14C_ALPHA1_G(0x0) | 647 VIDISD14C_ALPHA1_B(0x0); 648 writel(val, ctx->regs + VIDOSD_C(win)); 649 650 val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) | 651 VIDW_ALPHA_B(win_alpha_l); 652 writel(val, ctx->regs + VIDWnALPHA0(win)); 653 654 val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) | 655 VIDW_ALPHA_B(0x0); 656 writel(val, ctx->regs + VIDWnALPHA1(win)); 657 658 fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK, 659 BLENDCON_NEW_8BIT_ALPHA_VALUE); 660 } 661 662 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, 663 struct drm_framebuffer *fb, int width) 664 { 665 struct exynos_drm_plane plane = ctx->planes[win]; 666 struct exynos_drm_plane_state *state = 667 to_exynos_plane_state(plane.base.state); 668 uint32_t pixel_format = fb->format->format; 669 unsigned int alpha = state->base.alpha; 670 u32 val = WINCONx_ENWIN; 671 unsigned int pixel_alpha; 672 673 if (fb->format->has_alpha) 674 pixel_alpha = state->base.pixel_blend_mode; 675 else 676 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; 677 678 /* 679 * In case of s3c64xx, window 0 doesn't support alpha channel. 680 * So the request format is ARGB8888 then change it to XRGB8888. 681 */ 682 if (ctx->driver_data->has_limited_fmt && !win) { 683 if (pixel_format == DRM_FORMAT_ARGB8888) 684 pixel_format = DRM_FORMAT_XRGB8888; 685 } 686 687 switch (pixel_format) { 688 case DRM_FORMAT_C8: 689 val |= WINCON0_BPPMODE_8BPP_PALETTE; 690 val |= WINCONx_BURSTLEN_8WORD; 691 val |= WINCONx_BYTSWP; 692 break; 693 case DRM_FORMAT_XRGB1555: 694 case DRM_FORMAT_XBGR1555: 695 val |= WINCON0_BPPMODE_16BPP_1555; 696 val |= WINCONx_HAWSWP; 697 val |= WINCONx_BURSTLEN_16WORD; 698 break; 699 case DRM_FORMAT_RGB565: 700 case DRM_FORMAT_BGR565: 701 val |= WINCON0_BPPMODE_16BPP_565; 702 val |= WINCONx_HAWSWP; 703 val |= WINCONx_BURSTLEN_16WORD; 704 break; 705 case DRM_FORMAT_XRGB8888: 706 case DRM_FORMAT_XBGR8888: 707 val |= WINCON0_BPPMODE_24BPP_888; 708 val |= WINCONx_WSWP; 709 val |= WINCONx_BURSTLEN_16WORD; 710 break; 711 case DRM_FORMAT_ARGB8888: 712 case DRM_FORMAT_ABGR8888: 713 default: 714 val |= WINCON1_BPPMODE_25BPP_A1888; 715 val |= WINCONx_WSWP; 716 val |= WINCONx_BURSTLEN_16WORD; 717 break; 718 } 719 720 switch (pixel_format) { 721 case DRM_FORMAT_XBGR1555: 722 case DRM_FORMAT_XBGR8888: 723 case DRM_FORMAT_ABGR8888: 724 case DRM_FORMAT_BGR565: 725 writel(WIN_RGB_ORDER_REVERSE, ctx->regs + WIN_RGB_ORDER(win)); 726 break; 727 default: 728 writel(WIN_RGB_ORDER_FORWARD, ctx->regs + WIN_RGB_ORDER(win)); 729 break; 730 } 731 732 /* 733 * Setting dma-burst to 16Word causes permanent tearing for very small 734 * buffers, e.g. cursor buffer. Burst Mode switching which based on 735 * plane size is not recommended as plane size varies alot towards the 736 * end of the screen and rapid movement causes unstable DMA, but it is 737 * still better to change dma-burst than displaying garbage. 738 */ 739 740 if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 741 val &= ~WINCONx_BURSTLEN_MASK; 742 val |= WINCONx_BURSTLEN_4WORD; 743 } 744 fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val); 745 746 /* hardware window 0 doesn't support alpha channel. */ 747 if (win != 0) { 748 fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha); 749 fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha); 750 } 751 } 752 753 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) 754 { 755 unsigned int keycon0 = 0, keycon1 = 0; 756 757 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 758 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 759 760 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 761 762 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 763 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 764 } 765 766 /** 767 * fimd_shadow_protect_win() - disable updating values from shadow registers at vsync 768 * 769 * @ctx: local driver data 770 * @win: window to protect registers for 771 * @protect: 1 to protect (disable updates) 772 */ 773 static void fimd_shadow_protect_win(struct fimd_context *ctx, 774 unsigned int win, bool protect) 775 { 776 u32 reg, bits, val; 777 778 /* 779 * SHADOWCON/PRTCON register is used for enabling timing. 780 * 781 * for example, once only width value of a register is set, 782 * if the dma is started then fimd hardware could malfunction so 783 * with protect window setting, the register fields with prefix '_F' 784 * wouldn't be updated at vsync also but updated once unprotect window 785 * is set. 786 */ 787 788 if (ctx->driver_data->has_shadowcon) { 789 reg = SHADOWCON; 790 bits = SHADOWCON_WINx_PROTECT(win); 791 } else { 792 reg = PRTCON; 793 bits = PRTCON_PROTECT; 794 } 795 796 val = readl(ctx->regs + reg); 797 if (protect) 798 val |= bits; 799 else 800 val &= ~bits; 801 writel(val, ctx->regs + reg); 802 } 803 804 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc) 805 { 806 struct fimd_context *ctx = crtc->ctx; 807 int i; 808 809 if (ctx->suspended) 810 return; 811 812 for (i = 0; i < WINDOWS_NR; i++) 813 fimd_shadow_protect_win(ctx, i, true); 814 } 815 816 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc) 817 { 818 struct fimd_context *ctx = crtc->ctx; 819 int i; 820 821 if (ctx->suspended) 822 return; 823 824 for (i = 0; i < WINDOWS_NR; i++) 825 fimd_shadow_protect_win(ctx, i, false); 826 827 exynos_crtc_handle_event(crtc); 828 } 829 830 static void fimd_update_plane(struct exynos_drm_crtc *crtc, 831 struct exynos_drm_plane *plane) 832 { 833 struct exynos_drm_plane_state *state = 834 to_exynos_plane_state(plane->base.state); 835 struct fimd_context *ctx = crtc->ctx; 836 struct drm_framebuffer *fb = state->base.fb; 837 dma_addr_t dma_addr; 838 unsigned long val, size, offset; 839 unsigned int last_x, last_y, buf_offsize, line_size; 840 unsigned int win = plane->index; 841 unsigned int cpp = fb->format->cpp[0]; 842 unsigned int pitch = fb->pitches[0]; 843 844 if (ctx->suspended) 845 return; 846 847 offset = state->src.x * cpp; 848 offset += state->src.y * pitch; 849 850 /* buffer start address */ 851 dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset; 852 val = (unsigned long)dma_addr; 853 writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 854 855 /* buffer end address */ 856 size = pitch * state->crtc.h; 857 val = (unsigned long)(dma_addr + size); 858 writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 859 860 DRM_DEV_DEBUG_KMS(ctx->dev, 861 "start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 862 (unsigned long)dma_addr, val, size); 863 DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n", 864 state->crtc.w, state->crtc.h); 865 866 /* buffer size */ 867 buf_offsize = pitch - (state->crtc.w * cpp); 868 line_size = state->crtc.w * cpp; 869 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | 870 VIDW_BUF_SIZE_PAGEWIDTH(line_size) | 871 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | 872 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); 873 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 874 875 /* OSD position */ 876 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | 877 VIDOSDxA_TOPLEFT_Y(state->crtc.y) | 878 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) | 879 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y); 880 writel(val, ctx->regs + VIDOSD_A(win)); 881 882 last_x = state->crtc.x + state->crtc.w; 883 if (last_x) 884 last_x--; 885 last_y = state->crtc.y + state->crtc.h; 886 if (last_y) 887 last_y--; 888 889 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | 890 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); 891 892 writel(val, ctx->regs + VIDOSD_B(win)); 893 894 DRM_DEV_DEBUG_KMS(ctx->dev, 895 "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 896 state->crtc.x, state->crtc.y, last_x, last_y); 897 898 /* OSD size */ 899 if (win != 3 && win != 4) { 900 u32 offset = VIDOSD_D(win); 901 if (win == 0) 902 offset = VIDOSD_C(win); 903 val = state->crtc.w * state->crtc.h; 904 writel(val, ctx->regs + offset); 905 906 DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n", 907 (unsigned int)val); 908 } 909 910 fimd_win_set_pixfmt(ctx, win, fb, state->src.w); 911 912 /* hardware window 0 doesn't support color key. */ 913 if (win != 0) 914 fimd_win_set_colkey(ctx, win); 915 916 fimd_enable_video_output(ctx, win, true); 917 918 if (ctx->driver_data->has_shadowcon) 919 fimd_enable_shadow_channel_path(ctx, win, true); 920 921 if (ctx->i80_if) 922 atomic_set(&ctx->win_updated, 1); 923 } 924 925 static void fimd_disable_plane(struct exynos_drm_crtc *crtc, 926 struct exynos_drm_plane *plane) 927 { 928 struct fimd_context *ctx = crtc->ctx; 929 unsigned int win = plane->index; 930 931 if (ctx->suspended) 932 return; 933 934 fimd_enable_video_output(ctx, win, false); 935 936 if (ctx->driver_data->has_shadowcon) 937 fimd_enable_shadow_channel_path(ctx, win, false); 938 } 939 940 static void fimd_atomic_enable(struct exynos_drm_crtc *crtc) 941 { 942 struct fimd_context *ctx = crtc->ctx; 943 944 if (!ctx->suspended) 945 return; 946 947 ctx->suspended = false; 948 949 if (pm_runtime_resume_and_get(ctx->dev) < 0) { 950 dev_warn(ctx->dev, "failed to enable FIMD device.\n"); 951 return; 952 } 953 954 /* if vblank was enabled status, enable it again. */ 955 if (test_and_clear_bit(0, &ctx->irq_flags)) 956 fimd_enable_vblank(ctx->crtc); 957 958 fimd_commit(ctx->crtc); 959 } 960 961 static void fimd_atomic_disable(struct exynos_drm_crtc *crtc) 962 { 963 struct fimd_context *ctx = crtc->ctx; 964 int i; 965 966 if (ctx->suspended) 967 return; 968 969 /* 970 * We need to make sure that all windows are disabled before we 971 * suspend that connector. Otherwise we might try to scan from 972 * a destroyed buffer later. 973 */ 974 for (i = 0; i < WINDOWS_NR; i++) 975 fimd_disable_plane(crtc, &ctx->planes[i]); 976 977 fimd_enable_vblank(crtc); 978 fimd_wait_for_vblank(crtc); 979 fimd_disable_vblank(crtc); 980 981 writel(0, ctx->regs + VIDCON0); 982 983 pm_runtime_put_sync(ctx->dev); 984 ctx->suspended = true; 985 } 986 987 static void fimd_trigger(struct device *dev) 988 { 989 struct fimd_context *ctx = dev_get_drvdata(dev); 990 const struct fimd_driver_data *driver_data = ctx->driver_data; 991 void *timing_base = ctx->regs + driver_data->timing_base; 992 u32 reg; 993 994 /* 995 * Skips triggering if in triggering state, because multiple triggering 996 * requests can cause panel reset. 997 */ 998 if (atomic_read(&ctx->triggering)) 999 return; 1000 1001 /* Enters triggering mode */ 1002 atomic_set(&ctx->triggering, 1); 1003 1004 reg = readl(timing_base + TRIGCON); 1005 reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE); 1006 writel(reg, timing_base + TRIGCON); 1007 1008 /* 1009 * Exits triggering mode if vblank is not enabled yet, because when the 1010 * VIDINTCON0 register is not set, it can not exit from triggering mode. 1011 */ 1012 if (!test_bit(0, &ctx->irq_flags)) 1013 atomic_set(&ctx->triggering, 0); 1014 } 1015 1016 static void fimd_te_handler(struct exynos_drm_crtc *crtc) 1017 { 1018 struct fimd_context *ctx = crtc->ctx; 1019 u32 trg_type = ctx->driver_data->trg_type; 1020 1021 /* Checks the crtc is detached already from encoder */ 1022 if (!ctx->drm_dev) 1023 return; 1024 1025 if (trg_type == I80_HW_TRG) 1026 goto out; 1027 1028 /* 1029 * If there is a page flip request, triggers and handles the page flip 1030 * event so that current fb can be updated into panel GRAM. 1031 */ 1032 if (atomic_add_unless(&ctx->win_updated, -1, 0)) 1033 fimd_trigger(ctx->dev); 1034 1035 out: 1036 /* Wakes up vsync event queue */ 1037 if (atomic_read(&ctx->wait_vsync_event)) { 1038 atomic_set(&ctx->wait_vsync_event, 0); 1039 wake_up(&ctx->wait_vsync_queue); 1040 } 1041 1042 if (test_bit(0, &ctx->irq_flags)) 1043 drm_crtc_handle_vblank(&ctx->crtc->base); 1044 } 1045 1046 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable) 1047 { 1048 struct fimd_context *ctx = container_of(clk, struct fimd_context, 1049 dp_clk); 1050 u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; 1051 writel(val, ctx->regs + DP_MIE_CLKCON); 1052 } 1053 1054 static const struct exynos_drm_crtc_ops fimd_crtc_ops = { 1055 .atomic_enable = fimd_atomic_enable, 1056 .atomic_disable = fimd_atomic_disable, 1057 .enable_vblank = fimd_enable_vblank, 1058 .disable_vblank = fimd_disable_vblank, 1059 .atomic_begin = fimd_atomic_begin, 1060 .update_plane = fimd_update_plane, 1061 .disable_plane = fimd_disable_plane, 1062 .atomic_flush = fimd_atomic_flush, 1063 .atomic_check = fimd_atomic_check, 1064 .te_handler = fimd_te_handler, 1065 }; 1066 1067 static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 1068 { 1069 struct fimd_context *ctx = (struct fimd_context *)dev_id; 1070 u32 val, clear_bit; 1071 1072 val = readl(ctx->regs + VIDINTCON1); 1073 1074 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 1075 if (val & clear_bit) 1076 writel(clear_bit, ctx->regs + VIDINTCON1); 1077 1078 /* check the crtc is detached already from encoder */ 1079 if (!ctx->drm_dev) 1080 goto out; 1081 1082 if (!ctx->i80_if) 1083 drm_crtc_handle_vblank(&ctx->crtc->base); 1084 1085 if (ctx->i80_if) { 1086 /* Exits triggering mode */ 1087 atomic_set(&ctx->triggering, 0); 1088 } else { 1089 /* set wait vsync event to zero and wake up queue. */ 1090 if (atomic_read(&ctx->wait_vsync_event)) { 1091 atomic_set(&ctx->wait_vsync_event, 0); 1092 wake_up(&ctx->wait_vsync_queue); 1093 } 1094 } 1095 1096 out: 1097 return IRQ_HANDLED; 1098 } 1099 1100 static int fimd_bind(struct device *dev, struct device *master, void *data) 1101 { 1102 struct fimd_context *ctx = dev_get_drvdata(dev); 1103 struct drm_device *drm_dev = data; 1104 struct exynos_drm_plane *exynos_plane; 1105 unsigned int i; 1106 int ret; 1107 1108 ctx->drm_dev = drm_dev; 1109 1110 for (i = 0; i < WINDOWS_NR; i++) { 1111 if (ctx->driver_data->has_bgr_support) { 1112 ctx->configs[i].pixel_formats = fimd_extended_formats; 1113 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_extended_formats); 1114 } else { 1115 ctx->configs[i].pixel_formats = fimd_formats; 1116 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); 1117 } 1118 1119 ctx->configs[i].zpos = i; 1120 ctx->configs[i].type = fimd_win_types[i]; 1121 ctx->configs[i].capabilities = capabilities[i]; 1122 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, 1123 &ctx->configs[i]); 1124 if (ret) 1125 return ret; 1126 } 1127 1128 exynos_plane = &ctx->planes[DEFAULT_WIN]; 1129 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 1130 EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx); 1131 if (IS_ERR(ctx->crtc)) 1132 return PTR_ERR(ctx->crtc); 1133 1134 if (ctx->driver_data->has_dp_clk) { 1135 ctx->dp_clk.enable = fimd_dp_clock_enable; 1136 ctx->crtc->pipe_clk = &ctx->dp_clk; 1137 } 1138 1139 if (ctx->encoder) 1140 exynos_dpi_bind(drm_dev, ctx->encoder); 1141 1142 if (is_drm_iommu_supported(drm_dev)) { 1143 int ret; 1144 1145 ret = fimd_clear_channels(ctx->crtc); 1146 if (ret < 0) 1147 return ret; 1148 } 1149 1150 return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv); 1151 } 1152 1153 static void fimd_unbind(struct device *dev, struct device *master, 1154 void *data) 1155 { 1156 struct fimd_context *ctx = dev_get_drvdata(dev); 1157 1158 fimd_atomic_disable(ctx->crtc); 1159 1160 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv); 1161 1162 if (ctx->encoder) 1163 exynos_dpi_remove(ctx->encoder); 1164 } 1165 1166 static const struct component_ops fimd_component_ops = { 1167 .bind = fimd_bind, 1168 .unbind = fimd_unbind, 1169 }; 1170 1171 static int fimd_probe(struct platform_device *pdev) 1172 { 1173 struct device *dev = &pdev->dev; 1174 struct fimd_context *ctx; 1175 struct device_node *i80_if_timings; 1176 int ret; 1177 1178 if (!dev->of_node) 1179 return -ENODEV; 1180 1181 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1182 if (!ctx) 1183 return -ENOMEM; 1184 1185 ctx->dev = dev; 1186 ctx->suspended = true; 1187 ctx->driver_data = of_device_get_match_data(dev); 1188 1189 if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) 1190 ctx->vidcon1 |= VIDCON1_INV_VDEN; 1191 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) 1192 ctx->vidcon1 |= VIDCON1_INV_VCLK; 1193 1194 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 1195 if (i80_if_timings) { 1196 u32 val; 1197 1198 ctx->i80_if = true; 1199 1200 if (ctx->driver_data->has_vidoutcon) 1201 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; 1202 else 1203 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; 1204 /* 1205 * The user manual describes that this "DSI_EN" bit is required 1206 * to enable I80 24-bit data interface. 1207 */ 1208 ctx->vidcon0 |= VIDCON0_DSI_EN; 1209 1210 if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) 1211 val = 0; 1212 ctx->i80ifcon = LCD_CS_SETUP(val); 1213 if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) 1214 val = 0; 1215 ctx->i80ifcon |= LCD_WR_SETUP(val); 1216 if (of_property_read_u32(i80_if_timings, "wr-active", &val)) 1217 val = 1; 1218 ctx->i80ifcon |= LCD_WR_ACTIVE(val); 1219 if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) 1220 val = 0; 1221 ctx->i80ifcon |= LCD_WR_HOLD(val); 1222 } 1223 of_node_put(i80_if_timings); 1224 1225 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 1226 "samsung,sysreg"); 1227 if (IS_ERR(ctx->sysreg)) { 1228 dev_warn(dev, "failed to get system register.\n"); 1229 ctx->sysreg = NULL; 1230 } 1231 1232 ctx->bus_clk = devm_clk_get(dev, "fimd"); 1233 if (IS_ERR(ctx->bus_clk)) { 1234 dev_err(dev, "failed to get bus clock\n"); 1235 return PTR_ERR(ctx->bus_clk); 1236 } 1237 1238 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); 1239 if (IS_ERR(ctx->lcd_clk)) { 1240 dev_err(dev, "failed to get lcd clock\n"); 1241 return PTR_ERR(ctx->lcd_clk); 1242 } 1243 1244 ctx->regs = devm_platform_ioremap_resource(pdev, 0); 1245 if (IS_ERR(ctx->regs)) 1246 return PTR_ERR(ctx->regs); 1247 1248 ret = platform_get_irq_byname(pdev, ctx->i80_if ? "lcd_sys" : "vsync"); 1249 if (ret < 0) 1250 return ret; 1251 1252 ret = devm_request_irq(dev, ret, fimd_irq_handler, 0, "drm_fimd", ctx); 1253 if (ret) { 1254 dev_err(dev, "irq request failed.\n"); 1255 return ret; 1256 } 1257 1258 init_waitqueue_head(&ctx->wait_vsync_queue); 1259 atomic_set(&ctx->wait_vsync_event, 0); 1260 1261 platform_set_drvdata(pdev, ctx); 1262 1263 ctx->encoder = exynos_dpi_probe(dev); 1264 if (IS_ERR(ctx->encoder)) 1265 return PTR_ERR(ctx->encoder); 1266 1267 pm_runtime_enable(dev); 1268 1269 ret = component_add(dev, &fimd_component_ops); 1270 if (ret) 1271 goto err_disable_pm_runtime; 1272 1273 return ret; 1274 1275 err_disable_pm_runtime: 1276 pm_runtime_disable(dev); 1277 1278 return ret; 1279 } 1280 1281 static int fimd_remove(struct platform_device *pdev) 1282 { 1283 pm_runtime_disable(&pdev->dev); 1284 1285 component_del(&pdev->dev, &fimd_component_ops); 1286 1287 return 0; 1288 } 1289 1290 #ifdef CONFIG_PM 1291 static int exynos_fimd_suspend(struct device *dev) 1292 { 1293 struct fimd_context *ctx = dev_get_drvdata(dev); 1294 1295 clk_disable_unprepare(ctx->lcd_clk); 1296 clk_disable_unprepare(ctx->bus_clk); 1297 1298 return 0; 1299 } 1300 1301 static int exynos_fimd_resume(struct device *dev) 1302 { 1303 struct fimd_context *ctx = dev_get_drvdata(dev); 1304 int ret; 1305 1306 ret = clk_prepare_enable(ctx->bus_clk); 1307 if (ret < 0) { 1308 DRM_DEV_ERROR(dev, 1309 "Failed to prepare_enable the bus clk [%d]\n", 1310 ret); 1311 return ret; 1312 } 1313 1314 ret = clk_prepare_enable(ctx->lcd_clk); 1315 if (ret < 0) { 1316 DRM_DEV_ERROR(dev, 1317 "Failed to prepare_enable the lcd clk [%d]\n", 1318 ret); 1319 return ret; 1320 } 1321 1322 return 0; 1323 } 1324 #endif 1325 1326 static const struct dev_pm_ops exynos_fimd_pm_ops = { 1327 SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL) 1328 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1329 pm_runtime_force_resume) 1330 }; 1331 1332 struct platform_driver fimd_driver = { 1333 .probe = fimd_probe, 1334 .remove = fimd_remove, 1335 .driver = { 1336 .name = "exynos4-fb", 1337 .owner = THIS_MODULE, 1338 .pm = &exynos_fimd_pm_ops, 1339 .of_match_table = fimd_driver_dt_match, 1340 }, 1341 }; 1342