1 /* 2 * Copyright © 2006 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28 #include <drm/dp/drm_dp_helper.h> 29 30 #include "display/intel_display.h" 31 #include "display/intel_display_types.h" 32 #include "display/intel_gmbus.h" 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 37 #define _INTEL_BIOS_PRIVATE 38 #include "intel_vbt_defs.h" 39 40 /** 41 * DOC: Video BIOS Table (VBT) 42 * 43 * The Video BIOS Table, or VBT, provides platform and board specific 44 * configuration information to the driver that is not discoverable or available 45 * through other means. The configuration is mostly related to display 46 * hardware. The VBT is available via the ACPI OpRegion or, on older systems, in 47 * the PCI ROM. 48 * 49 * The VBT consists of a VBT Header (defined as &struct vbt_header), a BDB 50 * Header (&struct bdb_header), and a number of BIOS Data Blocks (BDB) that 51 * contain the actual configuration information. The VBT Header, and thus the 52 * VBT, begins with "$VBT" signature. The VBT Header contains the offset of the 53 * BDB Header. The data blocks are concatenated after the BDB Header. The data 54 * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of 55 * data. (Block 53, the MIPI Sequence Block is an exception.) 56 * 57 * The driver parses the VBT during load. The relevant information is stored in 58 * driver private data for ease of use, and the actual VBT is not read after 59 * that. 60 */ 61 62 /* Wrapper for VBT child device config */ 63 struct intel_bios_encoder_data { 64 struct drm_i915_private *i915; 65 66 struct child_device_config child; 67 struct dsc_compression_parameters_entry *dsc; 68 struct list_head node; 69 }; 70 71 #define SLAVE_ADDR1 0x70 72 #define SLAVE_ADDR2 0x72 73 74 /* Get BDB block size given a pointer to Block ID. */ 75 static u32 _get_blocksize(const u8 *block_base) 76 { 77 /* The MIPI Sequence Block v3+ has a separate size field. */ 78 if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3) 79 return *((const u32 *)(block_base + 4)); 80 else 81 return *((const u16 *)(block_base + 1)); 82 } 83 84 /* Get BDB block size give a pointer to data after Block ID and Block Size. */ 85 static u32 get_blocksize(const void *block_data) 86 { 87 return _get_blocksize(block_data - 3); 88 } 89 90 static const void * 91 find_section(const void *_bdb, enum bdb_block_id section_id) 92 { 93 const struct bdb_header *bdb = _bdb; 94 const u8 *base = _bdb; 95 int index = 0; 96 u32 total, current_size; 97 enum bdb_block_id current_id; 98 99 /* skip to first section */ 100 index += bdb->header_size; 101 total = bdb->bdb_size; 102 103 /* walk the sections looking for section_id */ 104 while (index + 3 < total) { 105 current_id = *(base + index); 106 current_size = _get_blocksize(base + index); 107 index += 3; 108 109 if (index + current_size > total) 110 return NULL; 111 112 if (current_id == section_id) 113 return base + index; 114 115 index += current_size; 116 } 117 118 return NULL; 119 } 120 121 static void 122 fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode, 123 const struct lvds_dvo_timing *dvo_timing) 124 { 125 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) | 126 dvo_timing->hactive_lo; 127 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay + 128 ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo); 129 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start + 130 ((dvo_timing->hsync_pulse_width_hi << 8) | 131 dvo_timing->hsync_pulse_width_lo); 132 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay + 133 ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo); 134 135 panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) | 136 dvo_timing->vactive_lo; 137 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay + 138 ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo); 139 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start + 140 ((dvo_timing->vsync_pulse_width_hi << 4) | 141 dvo_timing->vsync_pulse_width_lo); 142 panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay + 143 ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo); 144 panel_fixed_mode->clock = dvo_timing->clock * 10; 145 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; 146 147 if (dvo_timing->hsync_positive) 148 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; 149 else 150 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; 151 152 if (dvo_timing->vsync_positive) 153 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; 154 else 155 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; 156 157 panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) | 158 dvo_timing->himage_lo; 159 panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) | 160 dvo_timing->vimage_lo; 161 162 /* Some VBTs have bogus h/vtotal values */ 163 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) 164 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1; 165 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) 166 panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1; 167 168 drm_mode_set_name(panel_fixed_mode); 169 } 170 171 static const struct lvds_dvo_timing * 172 get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data, 173 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs, 174 int index) 175 { 176 /* 177 * the size of fp_timing varies on the different platform. 178 * So calculate the DVO timing relative offset in LVDS data 179 * entry to get the DVO timing entry 180 */ 181 182 int lfp_data_size = 183 lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset - 184 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset; 185 int dvo_timing_offset = 186 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset - 187 lvds_lfp_data_ptrs->ptr[0].fp_timing_offset; 188 char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index; 189 190 return (struct lvds_dvo_timing *)(entry + dvo_timing_offset); 191 } 192 193 /* get lvds_fp_timing entry 194 * this function may return NULL if the corresponding entry is invalid 195 */ 196 static const struct lvds_fp_timing * 197 get_lvds_fp_timing(const struct bdb_header *bdb, 198 const struct bdb_lvds_lfp_data *data, 199 const struct bdb_lvds_lfp_data_ptrs *ptrs, 200 int index) 201 { 202 size_t data_ofs = (const u8 *)data - (const u8 *)bdb; 203 u16 data_size = ((const u16 *)data)[-1]; /* stored in header */ 204 size_t ofs; 205 206 if (index >= ARRAY_SIZE(ptrs->ptr)) 207 return NULL; 208 ofs = ptrs->ptr[index].fp_timing_offset; 209 if (ofs < data_ofs || 210 ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size) 211 return NULL; 212 return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs); 213 } 214 215 /* Parse general panel options */ 216 static void 217 parse_panel_options(struct drm_i915_private *i915, 218 const struct bdb_header *bdb) 219 { 220 const struct bdb_lvds_options *lvds_options; 221 int panel_type; 222 int drrs_mode; 223 int ret; 224 225 lvds_options = find_section(bdb, BDB_LVDS_OPTIONS); 226 if (!lvds_options) 227 return; 228 229 i915->vbt.lvds_dither = lvds_options->pixel_dither; 230 231 ret = intel_opregion_get_panel_type(i915); 232 if (ret >= 0) { 233 drm_WARN_ON(&i915->drm, ret > 0xf); 234 panel_type = ret; 235 drm_dbg_kms(&i915->drm, "Panel type: %d (OpRegion)\n", 236 panel_type); 237 } else { 238 if (lvds_options->panel_type > 0xf) { 239 drm_dbg_kms(&i915->drm, 240 "Invalid VBT panel type 0x%x\n", 241 lvds_options->panel_type); 242 return; 243 } 244 panel_type = lvds_options->panel_type; 245 drm_dbg_kms(&i915->drm, "Panel type: %d (VBT)\n", 246 panel_type); 247 } 248 249 i915->vbt.panel_type = panel_type; 250 251 drrs_mode = (lvds_options->dps_panel_type_bits 252 >> (panel_type * 2)) & MODE_MASK; 253 /* 254 * VBT has static DRRS = 0 and seamless DRRS = 2. 255 * The below piece of code is required to adjust vbt.drrs_type 256 * to match the enum drrs_support_type. 257 */ 258 switch (drrs_mode) { 259 case 0: 260 i915->vbt.drrs_type = STATIC_DRRS_SUPPORT; 261 drm_dbg_kms(&i915->drm, "DRRS supported mode is static\n"); 262 break; 263 case 2: 264 i915->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT; 265 drm_dbg_kms(&i915->drm, 266 "DRRS supported mode is seamless\n"); 267 break; 268 default: 269 i915->vbt.drrs_type = DRRS_NOT_SUPPORTED; 270 drm_dbg_kms(&i915->drm, 271 "DRRS not supported (VBT input)\n"); 272 break; 273 } 274 } 275 276 /* Try to find integrated panel timing data */ 277 static void 278 parse_lfp_panel_dtd(struct drm_i915_private *i915, 279 const struct bdb_header *bdb) 280 { 281 const struct bdb_lvds_lfp_data *lvds_lfp_data; 282 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs; 283 const struct lvds_dvo_timing *panel_dvo_timing; 284 const struct lvds_fp_timing *fp_timing; 285 struct drm_display_mode *panel_fixed_mode; 286 int panel_type = i915->vbt.panel_type; 287 288 lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA); 289 if (!lvds_lfp_data) 290 return; 291 292 lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS); 293 if (!lvds_lfp_data_ptrs) 294 return; 295 296 panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data, 297 lvds_lfp_data_ptrs, 298 panel_type); 299 300 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); 301 if (!panel_fixed_mode) 302 return; 303 304 fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing); 305 306 i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; 307 308 drm_dbg_kms(&i915->drm, 309 "Found panel mode in BIOS VBT legacy lfp table:\n"); 310 drm_mode_debug_printmodeline(panel_fixed_mode); 311 312 fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data, 313 lvds_lfp_data_ptrs, 314 panel_type); 315 if (fp_timing) { 316 /* check the resolution, just to be sure */ 317 if (fp_timing->x_res == panel_fixed_mode->hdisplay && 318 fp_timing->y_res == panel_fixed_mode->vdisplay) { 319 i915->vbt.bios_lvds_val = fp_timing->lvds_reg_val; 320 drm_dbg_kms(&i915->drm, 321 "VBT initial LVDS value %x\n", 322 i915->vbt.bios_lvds_val); 323 } 324 } 325 } 326 327 static void 328 parse_generic_dtd(struct drm_i915_private *i915, 329 const struct bdb_header *bdb) 330 { 331 const struct bdb_generic_dtd *generic_dtd; 332 const struct generic_dtd_entry *dtd; 333 struct drm_display_mode *panel_fixed_mode; 334 int num_dtd; 335 336 generic_dtd = find_section(bdb, BDB_GENERIC_DTD); 337 if (!generic_dtd) 338 return; 339 340 if (generic_dtd->gdtd_size < sizeof(struct generic_dtd_entry)) { 341 drm_err(&i915->drm, "GDTD size %u is too small.\n", 342 generic_dtd->gdtd_size); 343 return; 344 } else if (generic_dtd->gdtd_size != 345 sizeof(struct generic_dtd_entry)) { 346 drm_err(&i915->drm, "Unexpected GDTD size %u\n", 347 generic_dtd->gdtd_size); 348 /* DTD has unknown fields, but keep going */ 349 } 350 351 num_dtd = (get_blocksize(generic_dtd) - 352 sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size; 353 if (i915->vbt.panel_type >= num_dtd) { 354 drm_err(&i915->drm, 355 "Panel type %d not found in table of %d DTD's\n", 356 i915->vbt.panel_type, num_dtd); 357 return; 358 } 359 360 dtd = &generic_dtd->dtd[i915->vbt.panel_type]; 361 362 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); 363 if (!panel_fixed_mode) 364 return; 365 366 panel_fixed_mode->hdisplay = dtd->hactive; 367 panel_fixed_mode->hsync_start = 368 panel_fixed_mode->hdisplay + dtd->hfront_porch; 369 panel_fixed_mode->hsync_end = 370 panel_fixed_mode->hsync_start + dtd->hsync; 371 panel_fixed_mode->htotal = 372 panel_fixed_mode->hdisplay + dtd->hblank; 373 374 panel_fixed_mode->vdisplay = dtd->vactive; 375 panel_fixed_mode->vsync_start = 376 panel_fixed_mode->vdisplay + dtd->vfront_porch; 377 panel_fixed_mode->vsync_end = 378 panel_fixed_mode->vsync_start + dtd->vsync; 379 panel_fixed_mode->vtotal = 380 panel_fixed_mode->vdisplay + dtd->vblank; 381 382 panel_fixed_mode->clock = dtd->pixel_clock; 383 panel_fixed_mode->width_mm = dtd->width_mm; 384 panel_fixed_mode->height_mm = dtd->height_mm; 385 386 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; 387 drm_mode_set_name(panel_fixed_mode); 388 389 if (dtd->hsync_positive_polarity) 390 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; 391 else 392 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; 393 394 if (dtd->vsync_positive_polarity) 395 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; 396 else 397 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; 398 399 drm_dbg_kms(&i915->drm, 400 "Found panel mode in BIOS VBT generic dtd table:\n"); 401 drm_mode_debug_printmodeline(panel_fixed_mode); 402 403 i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; 404 } 405 406 static void 407 parse_panel_dtd(struct drm_i915_private *i915, 408 const struct bdb_header *bdb) 409 { 410 /* 411 * Older VBTs provided provided DTD information for internal displays 412 * through the "LFP panel DTD" block (42). As of VBT revision 229, 413 * that block is now deprecated and DTD information should be provided 414 * via a newer "generic DTD" block (58). Just to be safe, we'll 415 * try the new generic DTD block first on VBT >= 229, but still fall 416 * back to trying the old LFP block if that fails. 417 */ 418 if (bdb->version >= 229) 419 parse_generic_dtd(i915, bdb); 420 if (!i915->vbt.lfp_lvds_vbt_mode) 421 parse_lfp_panel_dtd(i915, bdb); 422 } 423 424 static void 425 parse_lfp_backlight(struct drm_i915_private *i915, 426 const struct bdb_header *bdb) 427 { 428 const struct bdb_lfp_backlight_data *backlight_data; 429 const struct lfp_backlight_data_entry *entry; 430 int panel_type = i915->vbt.panel_type; 431 u16 level; 432 433 backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT); 434 if (!backlight_data) 435 return; 436 437 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) { 438 drm_dbg_kms(&i915->drm, 439 "Unsupported backlight data entry size %u\n", 440 backlight_data->entry_size); 441 return; 442 } 443 444 entry = &backlight_data->data[panel_type]; 445 446 i915->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM; 447 if (!i915->vbt.backlight.present) { 448 drm_dbg_kms(&i915->drm, 449 "PWM backlight not present in VBT (type %u)\n", 450 entry->type); 451 return; 452 } 453 454 i915->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI; 455 if (bdb->version >= 191) { 456 size_t exp_size; 457 458 if (bdb->version >= 236) 459 exp_size = sizeof(struct bdb_lfp_backlight_data); 460 else if (bdb->version >= 234) 461 exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234; 462 else 463 exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191; 464 465 if (get_blocksize(backlight_data) >= exp_size) { 466 const struct lfp_backlight_control_method *method; 467 468 method = &backlight_data->backlight_control[panel_type]; 469 i915->vbt.backlight.type = method->type; 470 i915->vbt.backlight.controller = method->controller; 471 } 472 } 473 474 i915->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; 475 i915->vbt.backlight.active_low_pwm = entry->active_low_pwm; 476 477 if (bdb->version >= 234) { 478 u16 min_level; 479 bool scale; 480 481 level = backlight_data->brightness_level[panel_type].level; 482 min_level = backlight_data->brightness_min_level[panel_type].level; 483 484 if (bdb->version >= 236) 485 scale = backlight_data->brightness_precision_bits[panel_type] == 16; 486 else 487 scale = level > 255; 488 489 if (scale) 490 min_level = min_level / 255; 491 492 if (min_level > 255) { 493 drm_warn(&i915->drm, "Brightness min level > 255\n"); 494 level = 255; 495 } 496 i915->vbt.backlight.min_brightness = min_level; 497 498 i915->vbt.backlight.brightness_precision_bits = 499 backlight_data->brightness_precision_bits[panel_type]; 500 } else { 501 level = backlight_data->level[panel_type]; 502 i915->vbt.backlight.min_brightness = entry->min_brightness; 503 } 504 505 drm_dbg_kms(&i915->drm, 506 "VBT backlight PWM modulation frequency %u Hz, " 507 "active %s, min brightness %u, level %u, controller %u\n", 508 i915->vbt.backlight.pwm_freq_hz, 509 i915->vbt.backlight.active_low_pwm ? "low" : "high", 510 i915->vbt.backlight.min_brightness, 511 level, 512 i915->vbt.backlight.controller); 513 } 514 515 /* Try to find sdvo panel data */ 516 static void 517 parse_sdvo_panel_data(struct drm_i915_private *i915, 518 const struct bdb_header *bdb) 519 { 520 const struct bdb_sdvo_panel_dtds *dtds; 521 struct drm_display_mode *panel_fixed_mode; 522 int index; 523 524 index = i915->params.vbt_sdvo_panel_type; 525 if (index == -2) { 526 drm_dbg_kms(&i915->drm, 527 "Ignore SDVO panel mode from BIOS VBT tables.\n"); 528 return; 529 } 530 531 if (index == -1) { 532 const struct bdb_sdvo_lvds_options *sdvo_lvds_options; 533 534 sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS); 535 if (!sdvo_lvds_options) 536 return; 537 538 index = sdvo_lvds_options->panel_type; 539 } 540 541 dtds = find_section(bdb, BDB_SDVO_PANEL_DTDS); 542 if (!dtds) 543 return; 544 545 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); 546 if (!panel_fixed_mode) 547 return; 548 549 fill_detail_timing_data(panel_fixed_mode, &dtds->dtds[index]); 550 551 i915->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; 552 553 drm_dbg_kms(&i915->drm, 554 "Found SDVO panel mode in BIOS VBT tables:\n"); 555 drm_mode_debug_printmodeline(panel_fixed_mode); 556 } 557 558 static int intel_bios_ssc_frequency(struct drm_i915_private *i915, 559 bool alternate) 560 { 561 switch (DISPLAY_VER(i915)) { 562 case 2: 563 return alternate ? 66667 : 48000; 564 case 3: 565 case 4: 566 return alternate ? 100000 : 96000; 567 default: 568 return alternate ? 100000 : 120000; 569 } 570 } 571 572 static void 573 parse_general_features(struct drm_i915_private *i915, 574 const struct bdb_header *bdb) 575 { 576 const struct bdb_general_features *general; 577 578 general = find_section(bdb, BDB_GENERAL_FEATURES); 579 if (!general) 580 return; 581 582 i915->vbt.int_tv_support = general->int_tv_support; 583 /* int_crt_support can't be trusted on earlier platforms */ 584 if (bdb->version >= 155 && 585 (HAS_DDI(i915) || IS_VALLEYVIEW(i915))) 586 i915->vbt.int_crt_support = general->int_crt_support; 587 i915->vbt.lvds_use_ssc = general->enable_ssc; 588 i915->vbt.lvds_ssc_freq = 589 intel_bios_ssc_frequency(i915, general->ssc_freq); 590 i915->vbt.display_clock_mode = general->display_clock_mode; 591 i915->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; 592 if (bdb->version >= 181) { 593 i915->vbt.orientation = general->rotate_180 ? 594 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP : 595 DRM_MODE_PANEL_ORIENTATION_NORMAL; 596 } else { 597 i915->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 598 } 599 600 if (bdb->version >= 249 && general->afc_startup_config) { 601 i915->vbt.override_afc_startup = true; 602 i915->vbt.override_afc_startup_val = general->afc_startup_config == 0x1 ? 0x0 : 0x7; 603 } 604 605 drm_dbg_kms(&i915->drm, 606 "BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", 607 i915->vbt.int_tv_support, 608 i915->vbt.int_crt_support, 609 i915->vbt.lvds_use_ssc, 610 i915->vbt.lvds_ssc_freq, 611 i915->vbt.display_clock_mode, 612 i915->vbt.fdi_rx_polarity_inverted); 613 } 614 615 static const struct child_device_config * 616 child_device_ptr(const struct bdb_general_definitions *defs, int i) 617 { 618 return (const void *) &defs->devices[i * defs->child_dev_size]; 619 } 620 621 static void 622 parse_sdvo_device_mapping(struct drm_i915_private *i915) 623 { 624 struct sdvo_device_mapping *mapping; 625 const struct intel_bios_encoder_data *devdata; 626 const struct child_device_config *child; 627 int count = 0; 628 629 /* 630 * Only parse SDVO mappings on gens that could have SDVO. This isn't 631 * accurate and doesn't have to be, as long as it's not too strict. 632 */ 633 if (!IS_DISPLAY_VER(i915, 3, 7)) { 634 drm_dbg_kms(&i915->drm, "Skipping SDVO device mapping\n"); 635 return; 636 } 637 638 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 639 child = &devdata->child; 640 641 if (child->slave_addr != SLAVE_ADDR1 && 642 child->slave_addr != SLAVE_ADDR2) { 643 /* 644 * If the slave address is neither 0x70 nor 0x72, 645 * it is not a SDVO device. Skip it. 646 */ 647 continue; 648 } 649 if (child->dvo_port != DEVICE_PORT_DVOB && 650 child->dvo_port != DEVICE_PORT_DVOC) { 651 /* skip the incorrect SDVO port */ 652 drm_dbg_kms(&i915->drm, 653 "Incorrect SDVO port. Skip it\n"); 654 continue; 655 } 656 drm_dbg_kms(&i915->drm, 657 "the SDVO device with slave addr %2x is found on" 658 " %s port\n", 659 child->slave_addr, 660 (child->dvo_port == DEVICE_PORT_DVOB) ? 661 "SDVOB" : "SDVOC"); 662 mapping = &i915->vbt.sdvo_mappings[child->dvo_port - 1]; 663 if (!mapping->initialized) { 664 mapping->dvo_port = child->dvo_port; 665 mapping->slave_addr = child->slave_addr; 666 mapping->dvo_wiring = child->dvo_wiring; 667 mapping->ddc_pin = child->ddc_pin; 668 mapping->i2c_pin = child->i2c_pin; 669 mapping->initialized = 1; 670 drm_dbg_kms(&i915->drm, 671 "SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", 672 mapping->dvo_port, mapping->slave_addr, 673 mapping->dvo_wiring, mapping->ddc_pin, 674 mapping->i2c_pin); 675 } else { 676 drm_dbg_kms(&i915->drm, 677 "Maybe one SDVO port is shared by " 678 "two SDVO device.\n"); 679 } 680 if (child->slave2_addr) { 681 /* Maybe this is a SDVO device with multiple inputs */ 682 /* And the mapping info is not added */ 683 drm_dbg_kms(&i915->drm, 684 "there exists the slave2_addr. Maybe this" 685 " is a SDVO device with multiple inputs.\n"); 686 } 687 count++; 688 } 689 690 if (!count) { 691 /* No SDVO device info is found */ 692 drm_dbg_kms(&i915->drm, 693 "No SDVO device info is found in VBT\n"); 694 } 695 } 696 697 static void 698 parse_driver_features(struct drm_i915_private *i915, 699 const struct bdb_header *bdb) 700 { 701 const struct bdb_driver_features *driver; 702 703 driver = find_section(bdb, BDB_DRIVER_FEATURES); 704 if (!driver) 705 return; 706 707 if (DISPLAY_VER(i915) >= 5) { 708 /* 709 * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS 710 * to mean "eDP". The VBT spec doesn't agree with that 711 * interpretation, but real world VBTs seem to. 712 */ 713 if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS) 714 i915->vbt.int_lvds_support = 0; 715 } else { 716 /* 717 * FIXME it's not clear which BDB version has the LVDS config 718 * bits defined. Revision history in the VBT spec says: 719 * "0.92 | Add two definitions for VBT value of LVDS Active 720 * Config (00b and 11b values defined) | 06/13/2005" 721 * but does not the specify the BDB version. 722 * 723 * So far version 134 (on i945gm) is the oldest VBT observed 724 * in the wild with the bits correctly populated. Version 725 * 108 (on i85x) does not have the bits correctly populated. 726 */ 727 if (bdb->version >= 134 && 728 driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS && 729 driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS) 730 i915->vbt.int_lvds_support = 0; 731 } 732 733 if (bdb->version < 228) { 734 drm_dbg_kms(&i915->drm, "DRRS State Enabled:%d\n", 735 driver->drrs_enabled); 736 /* 737 * If DRRS is not supported, drrs_type has to be set to 0. 738 * This is because, VBT is configured in such a way that 739 * static DRRS is 0 and DRRS not supported is represented by 740 * driver->drrs_enabled=false 741 */ 742 if (!driver->drrs_enabled) 743 i915->vbt.drrs_type = DRRS_NOT_SUPPORTED; 744 745 i915->vbt.psr.enable = driver->psr_enabled; 746 } 747 } 748 749 static void 750 parse_power_conservation_features(struct drm_i915_private *i915, 751 const struct bdb_header *bdb) 752 { 753 const struct bdb_lfp_power *power; 754 u8 panel_type = i915->vbt.panel_type; 755 756 if (bdb->version < 228) 757 return; 758 759 power = find_section(bdb, BDB_LFP_POWER); 760 if (!power) 761 return; 762 763 i915->vbt.psr.enable = power->psr & BIT(panel_type); 764 765 /* 766 * If DRRS is not supported, drrs_type has to be set to 0. 767 * This is because, VBT is configured in such a way that 768 * static DRRS is 0 and DRRS not supported is represented by 769 * power->drrs & BIT(panel_type)=false 770 */ 771 if (!(power->drrs & BIT(panel_type))) 772 i915->vbt.drrs_type = DRRS_NOT_SUPPORTED; 773 774 if (bdb->version >= 232) 775 i915->vbt.edp.hobl = power->hobl & BIT(panel_type); 776 } 777 778 static void 779 parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb) 780 { 781 const struct bdb_edp *edp; 782 const struct edp_power_seq *edp_pps; 783 const struct edp_fast_link_params *edp_link_params; 784 int panel_type = i915->vbt.panel_type; 785 786 edp = find_section(bdb, BDB_EDP); 787 if (!edp) 788 return; 789 790 switch ((edp->color_depth >> (panel_type * 2)) & 3) { 791 case EDP_18BPP: 792 i915->vbt.edp.bpp = 18; 793 break; 794 case EDP_24BPP: 795 i915->vbt.edp.bpp = 24; 796 break; 797 case EDP_30BPP: 798 i915->vbt.edp.bpp = 30; 799 break; 800 } 801 802 /* Get the eDP sequencing and link info */ 803 edp_pps = &edp->power_seqs[panel_type]; 804 edp_link_params = &edp->fast_link_params[panel_type]; 805 806 i915->vbt.edp.pps = *edp_pps; 807 808 switch (edp_link_params->rate) { 809 case EDP_RATE_1_62: 810 i915->vbt.edp.rate = DP_LINK_BW_1_62; 811 break; 812 case EDP_RATE_2_7: 813 i915->vbt.edp.rate = DP_LINK_BW_2_7; 814 break; 815 default: 816 drm_dbg_kms(&i915->drm, 817 "VBT has unknown eDP link rate value %u\n", 818 edp_link_params->rate); 819 break; 820 } 821 822 switch (edp_link_params->lanes) { 823 case EDP_LANE_1: 824 i915->vbt.edp.lanes = 1; 825 break; 826 case EDP_LANE_2: 827 i915->vbt.edp.lanes = 2; 828 break; 829 case EDP_LANE_4: 830 i915->vbt.edp.lanes = 4; 831 break; 832 default: 833 drm_dbg_kms(&i915->drm, 834 "VBT has unknown eDP lane count value %u\n", 835 edp_link_params->lanes); 836 break; 837 } 838 839 switch (edp_link_params->preemphasis) { 840 case EDP_PREEMPHASIS_NONE: 841 i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0; 842 break; 843 case EDP_PREEMPHASIS_3_5dB: 844 i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1; 845 break; 846 case EDP_PREEMPHASIS_6dB: 847 i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2; 848 break; 849 case EDP_PREEMPHASIS_9_5dB: 850 i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; 851 break; 852 default: 853 drm_dbg_kms(&i915->drm, 854 "VBT has unknown eDP pre-emphasis value %u\n", 855 edp_link_params->preemphasis); 856 break; 857 } 858 859 switch (edp_link_params->vswing) { 860 case EDP_VSWING_0_4V: 861 i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 862 break; 863 case EDP_VSWING_0_6V: 864 i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 865 break; 866 case EDP_VSWING_0_8V: 867 i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 868 break; 869 case EDP_VSWING_1_2V: 870 i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 871 break; 872 default: 873 drm_dbg_kms(&i915->drm, 874 "VBT has unknown eDP voltage swing value %u\n", 875 edp_link_params->vswing); 876 break; 877 } 878 879 if (bdb->version >= 173) { 880 u8 vswing; 881 882 /* Don't read from VBT if module parameter has valid value*/ 883 if (i915->params.edp_vswing) { 884 i915->vbt.edp.low_vswing = 885 i915->params.edp_vswing == 1; 886 } else { 887 vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; 888 i915->vbt.edp.low_vswing = vswing == 0; 889 } 890 } 891 } 892 893 static void 894 parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb) 895 { 896 const struct bdb_psr *psr; 897 const struct psr_table *psr_table; 898 int panel_type = i915->vbt.panel_type; 899 900 psr = find_section(bdb, BDB_PSR); 901 if (!psr) { 902 drm_dbg_kms(&i915->drm, "No PSR BDB found.\n"); 903 return; 904 } 905 906 psr_table = &psr->psr_table[panel_type]; 907 908 i915->vbt.psr.full_link = psr_table->full_link; 909 i915->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; 910 911 /* Allowed VBT values goes from 0 to 15 */ 912 i915->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : 913 psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames; 914 915 /* 916 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us 917 * Old decimal value is wake up time in multiples of 100 us. 918 */ 919 if (bdb->version >= 205 && 920 (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) { 921 switch (psr_table->tp1_wakeup_time) { 922 case 0: 923 i915->vbt.psr.tp1_wakeup_time_us = 500; 924 break; 925 case 1: 926 i915->vbt.psr.tp1_wakeup_time_us = 100; 927 break; 928 case 3: 929 i915->vbt.psr.tp1_wakeup_time_us = 0; 930 break; 931 default: 932 drm_dbg_kms(&i915->drm, 933 "VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", 934 psr_table->tp1_wakeup_time); 935 fallthrough; 936 case 2: 937 i915->vbt.psr.tp1_wakeup_time_us = 2500; 938 break; 939 } 940 941 switch (psr_table->tp2_tp3_wakeup_time) { 942 case 0: 943 i915->vbt.psr.tp2_tp3_wakeup_time_us = 500; 944 break; 945 case 1: 946 i915->vbt.psr.tp2_tp3_wakeup_time_us = 100; 947 break; 948 case 3: 949 i915->vbt.psr.tp2_tp3_wakeup_time_us = 0; 950 break; 951 default: 952 drm_dbg_kms(&i915->drm, 953 "VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", 954 psr_table->tp2_tp3_wakeup_time); 955 fallthrough; 956 case 2: 957 i915->vbt.psr.tp2_tp3_wakeup_time_us = 2500; 958 break; 959 } 960 } else { 961 i915->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100; 962 i915->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100; 963 } 964 965 if (bdb->version >= 226) { 966 u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time; 967 968 wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3; 969 switch (wakeup_time) { 970 case 0: 971 wakeup_time = 500; 972 break; 973 case 1: 974 wakeup_time = 100; 975 break; 976 case 3: 977 wakeup_time = 50; 978 break; 979 default: 980 case 2: 981 wakeup_time = 2500; 982 break; 983 } 984 i915->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time; 985 } else { 986 /* Reusing PSR1 wakeup time for PSR2 in older VBTs */ 987 i915->vbt.psr.psr2_tp2_tp3_wakeup_time_us = i915->vbt.psr.tp2_tp3_wakeup_time_us; 988 } 989 } 990 991 static void parse_dsi_backlight_ports(struct drm_i915_private *i915, 992 u16 version, enum port port) 993 { 994 if (!i915->vbt.dsi.config->dual_link || version < 197) { 995 i915->vbt.dsi.bl_ports = BIT(port); 996 if (i915->vbt.dsi.config->cabc_supported) 997 i915->vbt.dsi.cabc_ports = BIT(port); 998 999 return; 1000 } 1001 1002 switch (i915->vbt.dsi.config->dl_dcs_backlight_ports) { 1003 case DL_DCS_PORT_A: 1004 i915->vbt.dsi.bl_ports = BIT(PORT_A); 1005 break; 1006 case DL_DCS_PORT_C: 1007 i915->vbt.dsi.bl_ports = BIT(PORT_C); 1008 break; 1009 default: 1010 case DL_DCS_PORT_A_AND_C: 1011 i915->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C); 1012 break; 1013 } 1014 1015 if (!i915->vbt.dsi.config->cabc_supported) 1016 return; 1017 1018 switch (i915->vbt.dsi.config->dl_dcs_cabc_ports) { 1019 case DL_DCS_PORT_A: 1020 i915->vbt.dsi.cabc_ports = BIT(PORT_A); 1021 break; 1022 case DL_DCS_PORT_C: 1023 i915->vbt.dsi.cabc_ports = BIT(PORT_C); 1024 break; 1025 default: 1026 case DL_DCS_PORT_A_AND_C: 1027 i915->vbt.dsi.cabc_ports = 1028 BIT(PORT_A) | BIT(PORT_C); 1029 break; 1030 } 1031 } 1032 1033 static void 1034 parse_mipi_config(struct drm_i915_private *i915, 1035 const struct bdb_header *bdb) 1036 { 1037 const struct bdb_mipi_config *start; 1038 const struct mipi_config *config; 1039 const struct mipi_pps_data *pps; 1040 int panel_type = i915->vbt.panel_type; 1041 enum port port; 1042 1043 /* parse MIPI blocks only if LFP type is MIPI */ 1044 if (!intel_bios_is_dsi_present(i915, &port)) 1045 return; 1046 1047 /* Initialize this to undefined indicating no generic MIPI support */ 1048 i915->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; 1049 1050 /* Block #40 is already parsed and panel_fixed_mode is 1051 * stored in i915->lfp_lvds_vbt_mode 1052 * resuse this when needed 1053 */ 1054 1055 /* Parse #52 for panel index used from panel_type already 1056 * parsed 1057 */ 1058 start = find_section(bdb, BDB_MIPI_CONFIG); 1059 if (!start) { 1060 drm_dbg_kms(&i915->drm, "No MIPI config BDB found"); 1061 return; 1062 } 1063 1064 drm_dbg(&i915->drm, "Found MIPI Config block, panel index = %d\n", 1065 panel_type); 1066 1067 /* 1068 * get hold of the correct configuration block and pps data as per 1069 * the panel_type as index 1070 */ 1071 config = &start->config[panel_type]; 1072 pps = &start->pps[panel_type]; 1073 1074 /* store as of now full data. Trim when we realise all is not needed */ 1075 i915->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL); 1076 if (!i915->vbt.dsi.config) 1077 return; 1078 1079 i915->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL); 1080 if (!i915->vbt.dsi.pps) { 1081 kfree(i915->vbt.dsi.config); 1082 return; 1083 } 1084 1085 parse_dsi_backlight_ports(i915, bdb->version, port); 1086 1087 /* FIXME is the 90 vs. 270 correct? */ 1088 switch (config->rotation) { 1089 case ENABLE_ROTATION_0: 1090 /* 1091 * Most (all?) VBTs claim 0 degrees despite having 1092 * an upside down panel, thus we do not trust this. 1093 */ 1094 i915->vbt.dsi.orientation = 1095 DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1096 break; 1097 case ENABLE_ROTATION_90: 1098 i915->vbt.dsi.orientation = 1099 DRM_MODE_PANEL_ORIENTATION_RIGHT_UP; 1100 break; 1101 case ENABLE_ROTATION_180: 1102 i915->vbt.dsi.orientation = 1103 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; 1104 break; 1105 case ENABLE_ROTATION_270: 1106 i915->vbt.dsi.orientation = 1107 DRM_MODE_PANEL_ORIENTATION_LEFT_UP; 1108 break; 1109 } 1110 1111 /* We have mandatory mipi config blocks. Initialize as generic panel */ 1112 i915->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID; 1113 } 1114 1115 /* Find the sequence block and size for the given panel. */ 1116 static const u8 * 1117 find_panel_sequence_block(const struct bdb_mipi_sequence *sequence, 1118 u16 panel_id, u32 *seq_size) 1119 { 1120 u32 total = get_blocksize(sequence); 1121 const u8 *data = &sequence->data[0]; 1122 u8 current_id; 1123 u32 current_size; 1124 int header_size = sequence->version >= 3 ? 5 : 3; 1125 int index = 0; 1126 int i; 1127 1128 /* skip new block size */ 1129 if (sequence->version >= 3) 1130 data += 4; 1131 1132 for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) { 1133 if (index + header_size > total) { 1134 DRM_ERROR("Invalid sequence block (header)\n"); 1135 return NULL; 1136 } 1137 1138 current_id = *(data + index); 1139 if (sequence->version >= 3) 1140 current_size = *((const u32 *)(data + index + 1)); 1141 else 1142 current_size = *((const u16 *)(data + index + 1)); 1143 1144 index += header_size; 1145 1146 if (index + current_size > total) { 1147 DRM_ERROR("Invalid sequence block\n"); 1148 return NULL; 1149 } 1150 1151 if (current_id == panel_id) { 1152 *seq_size = current_size; 1153 return data + index; 1154 } 1155 1156 index += current_size; 1157 } 1158 1159 DRM_ERROR("Sequence block detected but no valid configuration\n"); 1160 1161 return NULL; 1162 } 1163 1164 static int goto_next_sequence(const u8 *data, int index, int total) 1165 { 1166 u16 len; 1167 1168 /* Skip Sequence Byte. */ 1169 for (index = index + 1; index < total; index += len) { 1170 u8 operation_byte = *(data + index); 1171 index++; 1172 1173 switch (operation_byte) { 1174 case MIPI_SEQ_ELEM_END: 1175 return index; 1176 case MIPI_SEQ_ELEM_SEND_PKT: 1177 if (index + 4 > total) 1178 return 0; 1179 1180 len = *((const u16 *)(data + index + 2)) + 4; 1181 break; 1182 case MIPI_SEQ_ELEM_DELAY: 1183 len = 4; 1184 break; 1185 case MIPI_SEQ_ELEM_GPIO: 1186 len = 2; 1187 break; 1188 case MIPI_SEQ_ELEM_I2C: 1189 if (index + 7 > total) 1190 return 0; 1191 len = *(data + index + 6) + 7; 1192 break; 1193 default: 1194 DRM_ERROR("Unknown operation byte\n"); 1195 return 0; 1196 } 1197 } 1198 1199 return 0; 1200 } 1201 1202 static int goto_next_sequence_v3(const u8 *data, int index, int total) 1203 { 1204 int seq_end; 1205 u16 len; 1206 u32 size_of_sequence; 1207 1208 /* 1209 * Could skip sequence based on Size of Sequence alone, but also do some 1210 * checking on the structure. 1211 */ 1212 if (total < 5) { 1213 DRM_ERROR("Too small sequence size\n"); 1214 return 0; 1215 } 1216 1217 /* Skip Sequence Byte. */ 1218 index++; 1219 1220 /* 1221 * Size of Sequence. Excludes the Sequence Byte and the size itself, 1222 * includes MIPI_SEQ_ELEM_END byte, excludes the final MIPI_SEQ_END 1223 * byte. 1224 */ 1225 size_of_sequence = *((const u32 *)(data + index)); 1226 index += 4; 1227 1228 seq_end = index + size_of_sequence; 1229 if (seq_end > total) { 1230 DRM_ERROR("Invalid sequence size\n"); 1231 return 0; 1232 } 1233 1234 for (; index < total; index += len) { 1235 u8 operation_byte = *(data + index); 1236 index++; 1237 1238 if (operation_byte == MIPI_SEQ_ELEM_END) { 1239 if (index != seq_end) { 1240 DRM_ERROR("Invalid element structure\n"); 1241 return 0; 1242 } 1243 return index; 1244 } 1245 1246 len = *(data + index); 1247 index++; 1248 1249 /* 1250 * FIXME: Would be nice to check elements like for v1/v2 in 1251 * goto_next_sequence() above. 1252 */ 1253 switch (operation_byte) { 1254 case MIPI_SEQ_ELEM_SEND_PKT: 1255 case MIPI_SEQ_ELEM_DELAY: 1256 case MIPI_SEQ_ELEM_GPIO: 1257 case MIPI_SEQ_ELEM_I2C: 1258 case MIPI_SEQ_ELEM_SPI: 1259 case MIPI_SEQ_ELEM_PMIC: 1260 break; 1261 default: 1262 DRM_ERROR("Unknown operation byte %u\n", 1263 operation_byte); 1264 break; 1265 } 1266 } 1267 1268 return 0; 1269 } 1270 1271 /* 1272 * Get len of pre-fixed deassert fragment from a v1 init OTP sequence, 1273 * skip all delay + gpio operands and stop at the first DSI packet op. 1274 */ 1275 static int get_init_otp_deassert_fragment_len(struct drm_i915_private *i915) 1276 { 1277 const u8 *data = i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; 1278 int index, len; 1279 1280 if (drm_WARN_ON(&i915->drm, 1281 !data || i915->vbt.dsi.seq_version != 1)) 1282 return 0; 1283 1284 /* index = 1 to skip sequence byte */ 1285 for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) { 1286 switch (data[index]) { 1287 case MIPI_SEQ_ELEM_SEND_PKT: 1288 return index == 1 ? 0 : index; 1289 case MIPI_SEQ_ELEM_DELAY: 1290 len = 5; /* 1 byte for operand + uint32 */ 1291 break; 1292 case MIPI_SEQ_ELEM_GPIO: 1293 len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */ 1294 break; 1295 default: 1296 return 0; 1297 } 1298 } 1299 1300 return 0; 1301 } 1302 1303 /* 1304 * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence. 1305 * The deassert must be done before calling intel_dsi_device_ready, so for 1306 * these devices we split the init OTP sequence into a deassert sequence and 1307 * the actual init OTP part. 1308 */ 1309 static void fixup_mipi_sequences(struct drm_i915_private *i915) 1310 { 1311 u8 *init_otp; 1312 int len; 1313 1314 /* Limit this to VLV for now. */ 1315 if (!IS_VALLEYVIEW(i915)) 1316 return; 1317 1318 /* Limit this to v1 vid-mode sequences */ 1319 if (i915->vbt.dsi.config->is_cmd_mode || 1320 i915->vbt.dsi.seq_version != 1) 1321 return; 1322 1323 /* Only do this if there are otp and assert seqs and no deassert seq */ 1324 if (!i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] || 1325 !i915->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] || 1326 i915->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) 1327 return; 1328 1329 /* The deassert-sequence ends at the first DSI packet */ 1330 len = get_init_otp_deassert_fragment_len(i915); 1331 if (!len) 1332 return; 1333 1334 drm_dbg_kms(&i915->drm, 1335 "Using init OTP fragment to deassert reset\n"); 1336 1337 /* Copy the fragment, update seq byte and terminate it */ 1338 init_otp = (u8 *)i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; 1339 i915->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL); 1340 if (!i915->vbt.dsi.deassert_seq) 1341 return; 1342 i915->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET; 1343 i915->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END; 1344 /* Use the copy for deassert */ 1345 i915->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] = 1346 i915->vbt.dsi.deassert_seq; 1347 /* Replace the last byte of the fragment with init OTP seq byte */ 1348 init_otp[len - 1] = MIPI_SEQ_INIT_OTP; 1349 /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */ 1350 i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1; 1351 } 1352 1353 static void 1354 parse_mipi_sequence(struct drm_i915_private *i915, 1355 const struct bdb_header *bdb) 1356 { 1357 int panel_type = i915->vbt.panel_type; 1358 const struct bdb_mipi_sequence *sequence; 1359 const u8 *seq_data; 1360 u32 seq_size; 1361 u8 *data; 1362 int index = 0; 1363 1364 /* Only our generic panel driver uses the sequence block. */ 1365 if (i915->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID) 1366 return; 1367 1368 sequence = find_section(bdb, BDB_MIPI_SEQUENCE); 1369 if (!sequence) { 1370 drm_dbg_kms(&i915->drm, 1371 "No MIPI Sequence found, parsing complete\n"); 1372 return; 1373 } 1374 1375 /* Fail gracefully for forward incompatible sequence block. */ 1376 if (sequence->version >= 4) { 1377 drm_err(&i915->drm, 1378 "Unable to parse MIPI Sequence Block v%u\n", 1379 sequence->version); 1380 return; 1381 } 1382 1383 drm_dbg(&i915->drm, "Found MIPI sequence block v%u\n", 1384 sequence->version); 1385 1386 seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size); 1387 if (!seq_data) 1388 return; 1389 1390 data = kmemdup(seq_data, seq_size, GFP_KERNEL); 1391 if (!data) 1392 return; 1393 1394 /* Parse the sequences, store pointers to each sequence. */ 1395 for (;;) { 1396 u8 seq_id = *(data + index); 1397 if (seq_id == MIPI_SEQ_END) 1398 break; 1399 1400 if (seq_id >= MIPI_SEQ_MAX) { 1401 drm_err(&i915->drm, "Unknown sequence %u\n", 1402 seq_id); 1403 goto err; 1404 } 1405 1406 /* Log about presence of sequences we won't run. */ 1407 if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF) 1408 drm_dbg_kms(&i915->drm, 1409 "Unsupported sequence %u\n", seq_id); 1410 1411 i915->vbt.dsi.sequence[seq_id] = data + index; 1412 1413 if (sequence->version >= 3) 1414 index = goto_next_sequence_v3(data, index, seq_size); 1415 else 1416 index = goto_next_sequence(data, index, seq_size); 1417 if (!index) { 1418 drm_err(&i915->drm, "Invalid sequence %u\n", 1419 seq_id); 1420 goto err; 1421 } 1422 } 1423 1424 i915->vbt.dsi.data = data; 1425 i915->vbt.dsi.size = seq_size; 1426 i915->vbt.dsi.seq_version = sequence->version; 1427 1428 fixup_mipi_sequences(i915); 1429 1430 drm_dbg(&i915->drm, "MIPI related VBT parsing complete\n"); 1431 return; 1432 1433 err: 1434 kfree(data); 1435 memset(i915->vbt.dsi.sequence, 0, sizeof(i915->vbt.dsi.sequence)); 1436 } 1437 1438 static void 1439 parse_compression_parameters(struct drm_i915_private *i915, 1440 const struct bdb_header *bdb) 1441 { 1442 const struct bdb_compression_parameters *params; 1443 struct intel_bios_encoder_data *devdata; 1444 const struct child_device_config *child; 1445 u16 block_size; 1446 int index; 1447 1448 if (bdb->version < 198) 1449 return; 1450 1451 params = find_section(bdb, BDB_COMPRESSION_PARAMETERS); 1452 if (params) { 1453 /* Sanity checks */ 1454 if (params->entry_size != sizeof(params->data[0])) { 1455 drm_dbg_kms(&i915->drm, 1456 "VBT: unsupported compression param entry size\n"); 1457 return; 1458 } 1459 1460 block_size = get_blocksize(params); 1461 if (block_size < sizeof(*params)) { 1462 drm_dbg_kms(&i915->drm, 1463 "VBT: expected 16 compression param entries\n"); 1464 return; 1465 } 1466 } 1467 1468 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 1469 child = &devdata->child; 1470 1471 if (!child->compression_enable) 1472 continue; 1473 1474 if (!params) { 1475 drm_dbg_kms(&i915->drm, 1476 "VBT: compression params not available\n"); 1477 continue; 1478 } 1479 1480 if (child->compression_method_cps) { 1481 drm_dbg_kms(&i915->drm, 1482 "VBT: CPS compression not supported\n"); 1483 continue; 1484 } 1485 1486 index = child->compression_structure_index; 1487 1488 devdata->dsc = kmemdup(¶ms->data[index], 1489 sizeof(*devdata->dsc), GFP_KERNEL); 1490 } 1491 } 1492 1493 static u8 translate_iboost(u8 val) 1494 { 1495 static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */ 1496 1497 if (val >= ARRAY_SIZE(mapping)) { 1498 DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val); 1499 return 0; 1500 } 1501 return mapping[val]; 1502 } 1503 1504 static const u8 cnp_ddc_pin_map[] = { 1505 [0] = 0, /* N/A */ 1506 [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT, 1507 [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT, 1508 [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP, /* sic */ 1509 [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */ 1510 }; 1511 1512 static const u8 icp_ddc_pin_map[] = { 1513 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, 1514 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, 1515 [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT, 1516 [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP, 1517 [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP, 1518 [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP, 1519 [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP, 1520 [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP, 1521 [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP, 1522 }; 1523 1524 static const u8 rkl_pch_tgp_ddc_pin_map[] = { 1525 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, 1526 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, 1527 [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP, 1528 [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, 1529 }; 1530 1531 static const u8 adls_ddc_pin_map[] = { 1532 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, 1533 [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP, 1534 [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP, 1535 [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP, 1536 [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP, 1537 }; 1538 1539 static const u8 gen9bc_tgp_ddc_pin_map[] = { 1540 [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, 1541 [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP, 1542 [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP, 1543 }; 1544 1545 static const u8 adlp_ddc_pin_map[] = { 1546 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, 1547 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, 1548 [ADLP_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP, 1549 [ADLP_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP, 1550 [ADLP_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP, 1551 [ADLP_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP, 1552 }; 1553 1554 static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) 1555 { 1556 const u8 *ddc_pin_map; 1557 int n_entries; 1558 1559 if (IS_ALDERLAKE_P(i915)) { 1560 ddc_pin_map = adlp_ddc_pin_map; 1561 n_entries = ARRAY_SIZE(adlp_ddc_pin_map); 1562 } else if (IS_ALDERLAKE_S(i915)) { 1563 ddc_pin_map = adls_ddc_pin_map; 1564 n_entries = ARRAY_SIZE(adls_ddc_pin_map); 1565 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { 1566 return vbt_pin; 1567 } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) { 1568 ddc_pin_map = rkl_pch_tgp_ddc_pin_map; 1569 n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); 1570 } else if (HAS_PCH_TGP(i915) && DISPLAY_VER(i915) == 9) { 1571 ddc_pin_map = gen9bc_tgp_ddc_pin_map; 1572 n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); 1573 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { 1574 ddc_pin_map = icp_ddc_pin_map; 1575 n_entries = ARRAY_SIZE(icp_ddc_pin_map); 1576 } else if (HAS_PCH_CNP(i915)) { 1577 ddc_pin_map = cnp_ddc_pin_map; 1578 n_entries = ARRAY_SIZE(cnp_ddc_pin_map); 1579 } else { 1580 /* Assuming direct map */ 1581 return vbt_pin; 1582 } 1583 1584 if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0) 1585 return ddc_pin_map[vbt_pin]; 1586 1587 drm_dbg_kms(&i915->drm, 1588 "Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", 1589 vbt_pin); 1590 return 0; 1591 } 1592 1593 static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin) 1594 { 1595 const struct intel_bios_encoder_data *devdata; 1596 enum port port; 1597 1598 if (!ddc_pin) 1599 return PORT_NONE; 1600 1601 for_each_port(port) { 1602 devdata = i915->vbt.ports[port]; 1603 1604 if (devdata && ddc_pin == devdata->child.ddc_pin) 1605 return port; 1606 } 1607 1608 return PORT_NONE; 1609 } 1610 1611 static void sanitize_ddc_pin(struct intel_bios_encoder_data *devdata, 1612 enum port port) 1613 { 1614 struct drm_i915_private *i915 = devdata->i915; 1615 struct child_device_config *child; 1616 u8 mapped_ddc_pin; 1617 enum port p; 1618 1619 if (!devdata->child.ddc_pin) 1620 return; 1621 1622 mapped_ddc_pin = map_ddc_pin(i915, devdata->child.ddc_pin); 1623 if (!intel_gmbus_is_valid_pin(i915, mapped_ddc_pin)) { 1624 drm_dbg_kms(&i915->drm, 1625 "Port %c has invalid DDC pin %d, " 1626 "sticking to defaults\n", 1627 port_name(port), mapped_ddc_pin); 1628 devdata->child.ddc_pin = 0; 1629 return; 1630 } 1631 1632 p = get_port_by_ddc_pin(i915, devdata->child.ddc_pin); 1633 if (p == PORT_NONE) 1634 return; 1635 1636 drm_dbg_kms(&i915->drm, 1637 "port %c trying to use the same DDC pin (0x%x) as port %c, " 1638 "disabling port %c DVI/HDMI support\n", 1639 port_name(port), mapped_ddc_pin, 1640 port_name(p), port_name(p)); 1641 1642 /* 1643 * If we have multiple ports supposedly sharing the pin, then dvi/hdmi 1644 * couldn't exist on the shared port. Otherwise they share the same ddc 1645 * pin and system couldn't communicate with them separately. 1646 * 1647 * Give inverse child device order the priority, last one wins. Yes, 1648 * there are real machines (eg. Asrock B250M-HDV) where VBT has both 1649 * port A and port E with the same AUX ch and we must pick port E :( 1650 */ 1651 child = &i915->vbt.ports[p]->child; 1652 1653 child->device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING; 1654 child->device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT; 1655 1656 child->ddc_pin = 0; 1657 } 1658 1659 static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch) 1660 { 1661 const struct intel_bios_encoder_data *devdata; 1662 enum port port; 1663 1664 if (!aux_ch) 1665 return PORT_NONE; 1666 1667 for_each_port(port) { 1668 devdata = i915->vbt.ports[port]; 1669 1670 if (devdata && aux_ch == devdata->child.aux_channel) 1671 return port; 1672 } 1673 1674 return PORT_NONE; 1675 } 1676 1677 static void sanitize_aux_ch(struct intel_bios_encoder_data *devdata, 1678 enum port port) 1679 { 1680 struct drm_i915_private *i915 = devdata->i915; 1681 struct child_device_config *child; 1682 enum port p; 1683 1684 p = get_port_by_aux_ch(i915, devdata->child.aux_channel); 1685 if (p == PORT_NONE) 1686 return; 1687 1688 drm_dbg_kms(&i915->drm, 1689 "port %c trying to use the same AUX CH (0x%x) as port %c, " 1690 "disabling port %c DP support\n", 1691 port_name(port), devdata->child.aux_channel, 1692 port_name(p), port_name(p)); 1693 1694 /* 1695 * If we have multiple ports supposedly sharing the aux channel, then DP 1696 * couldn't exist on the shared port. Otherwise they share the same aux 1697 * channel and system couldn't communicate with them separately. 1698 * 1699 * Give inverse child device order the priority, last one wins. Yes, 1700 * there are real machines (eg. Asrock B250M-HDV) where VBT has both 1701 * port A and port E with the same AUX ch and we must pick port E :( 1702 */ 1703 child = &i915->vbt.ports[p]->child; 1704 1705 child->device_type &= ~DEVICE_TYPE_DISPLAYPORT_OUTPUT; 1706 child->aux_channel = 0; 1707 } 1708 1709 static u8 dvo_port_type(u8 dvo_port) 1710 { 1711 switch (dvo_port) { 1712 case DVO_PORT_HDMIA: 1713 case DVO_PORT_HDMIB: 1714 case DVO_PORT_HDMIC: 1715 case DVO_PORT_HDMID: 1716 case DVO_PORT_HDMIE: 1717 case DVO_PORT_HDMIF: 1718 case DVO_PORT_HDMIG: 1719 case DVO_PORT_HDMIH: 1720 case DVO_PORT_HDMII: 1721 return DVO_PORT_HDMIA; 1722 case DVO_PORT_DPA: 1723 case DVO_PORT_DPB: 1724 case DVO_PORT_DPC: 1725 case DVO_PORT_DPD: 1726 case DVO_PORT_DPE: 1727 case DVO_PORT_DPF: 1728 case DVO_PORT_DPG: 1729 case DVO_PORT_DPH: 1730 case DVO_PORT_DPI: 1731 return DVO_PORT_DPA; 1732 case DVO_PORT_MIPIA: 1733 case DVO_PORT_MIPIB: 1734 case DVO_PORT_MIPIC: 1735 case DVO_PORT_MIPID: 1736 return DVO_PORT_MIPIA; 1737 default: 1738 return dvo_port; 1739 } 1740 } 1741 1742 static enum port __dvo_port_to_port(int n_ports, int n_dvo, 1743 const int port_mapping[][3], u8 dvo_port) 1744 { 1745 enum port port; 1746 int i; 1747 1748 for (port = PORT_A; port < n_ports; port++) { 1749 for (i = 0; i < n_dvo; i++) { 1750 if (port_mapping[port][i] == -1) 1751 break; 1752 1753 if (dvo_port == port_mapping[port][i]) 1754 return port; 1755 } 1756 } 1757 1758 return PORT_NONE; 1759 } 1760 1761 static enum port dvo_port_to_port(struct drm_i915_private *i915, 1762 u8 dvo_port) 1763 { 1764 /* 1765 * Each DDI port can have more than one value on the "DVO Port" field, 1766 * so look for all the possible values for each port. 1767 */ 1768 static const int port_mapping[][3] = { 1769 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, 1770 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, 1771 [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, 1772 [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, 1773 [PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT }, 1774 [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 }, 1775 [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 }, 1776 [PORT_H] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 }, 1777 [PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, 1778 }; 1779 /* 1780 * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D 1781 * map to DDI A,B,TC1,TC2 respectively. 1782 */ 1783 static const int rkl_port_mapping[][3] = { 1784 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, 1785 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, 1786 [PORT_C] = { -1 }, 1787 [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, 1788 [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, 1789 }; 1790 /* 1791 * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E, 1792 * PORT_F and PORT_G, we need to map that to correct VBT sections. 1793 */ 1794 static const int adls_port_mapping[][3] = { 1795 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, 1796 [PORT_B] = { -1 }, 1797 [PORT_C] = { -1 }, 1798 [PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, 1799 [PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, 1800 [PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, 1801 [PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 }, 1802 }; 1803 static const int xelpd_port_mapping[][3] = { 1804 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, 1805 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, 1806 [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, 1807 [PORT_D_XELPD] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, 1808 [PORT_E_XELPD] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 }, 1809 [PORT_TC1] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 }, 1810 [PORT_TC2] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 }, 1811 [PORT_TC3] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 }, 1812 [PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, 1813 }; 1814 1815 if (DISPLAY_VER(i915) == 13) 1816 return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping), 1817 ARRAY_SIZE(xelpd_port_mapping[0]), 1818 xelpd_port_mapping, 1819 dvo_port); 1820 else if (IS_ALDERLAKE_S(i915)) 1821 return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping), 1822 ARRAY_SIZE(adls_port_mapping[0]), 1823 adls_port_mapping, 1824 dvo_port); 1825 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) 1826 return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping), 1827 ARRAY_SIZE(rkl_port_mapping[0]), 1828 rkl_port_mapping, 1829 dvo_port); 1830 else 1831 return __dvo_port_to_port(ARRAY_SIZE(port_mapping), 1832 ARRAY_SIZE(port_mapping[0]), 1833 port_mapping, 1834 dvo_port); 1835 } 1836 1837 static int parse_bdb_230_dp_max_link_rate(const int vbt_max_link_rate) 1838 { 1839 switch (vbt_max_link_rate) { 1840 default: 1841 case BDB_230_VBT_DP_MAX_LINK_RATE_DEF: 1842 return 0; 1843 case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20: 1844 return 2000000; 1845 case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5: 1846 return 1350000; 1847 case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10: 1848 return 1000000; 1849 case BDB_230_VBT_DP_MAX_LINK_RATE_HBR3: 1850 return 810000; 1851 case BDB_230_VBT_DP_MAX_LINK_RATE_HBR2: 1852 return 540000; 1853 case BDB_230_VBT_DP_MAX_LINK_RATE_HBR: 1854 return 270000; 1855 case BDB_230_VBT_DP_MAX_LINK_RATE_LBR: 1856 return 162000; 1857 } 1858 } 1859 1860 static int parse_bdb_216_dp_max_link_rate(const int vbt_max_link_rate) 1861 { 1862 switch (vbt_max_link_rate) { 1863 default: 1864 case BDB_216_VBT_DP_MAX_LINK_RATE_HBR3: 1865 return 810000; 1866 case BDB_216_VBT_DP_MAX_LINK_RATE_HBR2: 1867 return 540000; 1868 case BDB_216_VBT_DP_MAX_LINK_RATE_HBR: 1869 return 270000; 1870 case BDB_216_VBT_DP_MAX_LINK_RATE_LBR: 1871 return 162000; 1872 } 1873 } 1874 1875 static int _intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *devdata) 1876 { 1877 if (!devdata || devdata->i915->vbt.version < 216) 1878 return 0; 1879 1880 if (devdata->i915->vbt.version >= 230) 1881 return parse_bdb_230_dp_max_link_rate(devdata->child.dp_max_link_rate); 1882 else 1883 return parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate); 1884 } 1885 1886 static void sanitize_device_type(struct intel_bios_encoder_data *devdata, 1887 enum port port) 1888 { 1889 struct drm_i915_private *i915 = devdata->i915; 1890 bool is_hdmi; 1891 1892 if (port != PORT_A || DISPLAY_VER(i915) >= 12) 1893 return; 1894 1895 if (!(devdata->child.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING)) 1896 return; 1897 1898 is_hdmi = !(devdata->child.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT); 1899 1900 drm_dbg_kms(&i915->drm, "VBT claims port A supports DVI%s, ignoring\n", 1901 is_hdmi ? "/HDMI" : ""); 1902 1903 devdata->child.device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING; 1904 devdata->child.device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT; 1905 } 1906 1907 static bool 1908 intel_bios_encoder_supports_crt(const struct intel_bios_encoder_data *devdata) 1909 { 1910 return devdata->child.device_type & DEVICE_TYPE_ANALOG_OUTPUT; 1911 } 1912 1913 bool 1914 intel_bios_encoder_supports_dvi(const struct intel_bios_encoder_data *devdata) 1915 { 1916 return devdata->child.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; 1917 } 1918 1919 bool 1920 intel_bios_encoder_supports_hdmi(const struct intel_bios_encoder_data *devdata) 1921 { 1922 return intel_bios_encoder_supports_dvi(devdata) && 1923 (devdata->child.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0; 1924 } 1925 1926 bool 1927 intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdata) 1928 { 1929 return devdata->child.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; 1930 } 1931 1932 static bool 1933 intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata) 1934 { 1935 return intel_bios_encoder_supports_dp(devdata) && 1936 devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR; 1937 } 1938 1939 static int _intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata) 1940 { 1941 if (!devdata || devdata->i915->vbt.version < 158) 1942 return -1; 1943 1944 return devdata->child.hdmi_level_shifter_value; 1945 } 1946 1947 static int _intel_bios_max_tmds_clock(const struct intel_bios_encoder_data *devdata) 1948 { 1949 if (!devdata || devdata->i915->vbt.version < 204) 1950 return 0; 1951 1952 switch (devdata->child.hdmi_max_data_rate) { 1953 default: 1954 MISSING_CASE(devdata->child.hdmi_max_data_rate); 1955 fallthrough; 1956 case HDMI_MAX_DATA_RATE_PLATFORM: 1957 return 0; 1958 case HDMI_MAX_DATA_RATE_297: 1959 return 297000; 1960 case HDMI_MAX_DATA_RATE_165: 1961 return 165000; 1962 } 1963 } 1964 1965 static bool is_port_valid(struct drm_i915_private *i915, enum port port) 1966 { 1967 /* 1968 * On some ICL SKUs port F is not present, but broken VBTs mark 1969 * the port as present. Only try to initialize port F for the 1970 * SKUs that may actually have it. 1971 */ 1972 if (port == PORT_F && IS_ICELAKE(i915)) 1973 return IS_ICL_WITH_PORT_F(i915); 1974 1975 return true; 1976 } 1977 1978 static void parse_ddi_port(struct drm_i915_private *i915, 1979 struct intel_bios_encoder_data *devdata) 1980 { 1981 const struct child_device_config *child = &devdata->child; 1982 bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb, supports_tbt; 1983 int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift, max_tmds_clock; 1984 enum port port; 1985 1986 port = dvo_port_to_port(i915, child->dvo_port); 1987 if (port == PORT_NONE) 1988 return; 1989 1990 if (!is_port_valid(i915, port)) { 1991 drm_dbg_kms(&i915->drm, 1992 "VBT reports port %c as supported, but that can't be true: skipping\n", 1993 port_name(port)); 1994 return; 1995 } 1996 1997 if (i915->vbt.ports[port]) { 1998 drm_dbg_kms(&i915->drm, 1999 "More than one child device for port %c in VBT, using the first.\n", 2000 port_name(port)); 2001 return; 2002 } 2003 2004 sanitize_device_type(devdata, port); 2005 2006 is_dvi = intel_bios_encoder_supports_dvi(devdata); 2007 is_dp = intel_bios_encoder_supports_dp(devdata); 2008 is_crt = intel_bios_encoder_supports_crt(devdata); 2009 is_hdmi = intel_bios_encoder_supports_hdmi(devdata); 2010 is_edp = intel_bios_encoder_supports_edp(devdata); 2011 2012 supports_typec_usb = intel_bios_encoder_supports_typec_usb(devdata); 2013 supports_tbt = intel_bios_encoder_supports_tbt(devdata); 2014 2015 drm_dbg_kms(&i915->drm, 2016 "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n", 2017 port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp, 2018 HAS_LSPCON(i915) && child->lspcon, 2019 supports_typec_usb, supports_tbt, 2020 devdata->dsc != NULL); 2021 2022 if (is_dvi) 2023 sanitize_ddc_pin(devdata, port); 2024 2025 if (is_dp) 2026 sanitize_aux_ch(devdata, port); 2027 2028 hdmi_level_shift = _intel_bios_hdmi_level_shift(devdata); 2029 if (hdmi_level_shift >= 0) { 2030 drm_dbg_kms(&i915->drm, 2031 "Port %c VBT HDMI level shift: %d\n", 2032 port_name(port), hdmi_level_shift); 2033 } 2034 2035 max_tmds_clock = _intel_bios_max_tmds_clock(devdata); 2036 if (max_tmds_clock) 2037 drm_dbg_kms(&i915->drm, 2038 "Port %c VBT HDMI max TMDS clock: %d kHz\n", 2039 port_name(port), max_tmds_clock); 2040 2041 /* I_boost config for SKL and above */ 2042 dp_boost_level = intel_bios_encoder_dp_boost_level(devdata); 2043 if (dp_boost_level) 2044 drm_dbg_kms(&i915->drm, 2045 "Port %c VBT (e)DP boost level: %d\n", 2046 port_name(port), dp_boost_level); 2047 2048 hdmi_boost_level = intel_bios_encoder_hdmi_boost_level(devdata); 2049 if (hdmi_boost_level) 2050 drm_dbg_kms(&i915->drm, 2051 "Port %c VBT HDMI boost level: %d\n", 2052 port_name(port), hdmi_boost_level); 2053 2054 dp_max_link_rate = _intel_bios_dp_max_link_rate(devdata); 2055 if (dp_max_link_rate) 2056 drm_dbg_kms(&i915->drm, 2057 "Port %c VBT DP max link rate: %d\n", 2058 port_name(port), dp_max_link_rate); 2059 2060 i915->vbt.ports[port] = devdata; 2061 } 2062 2063 static bool has_ddi_port_info(struct drm_i915_private *i915) 2064 { 2065 return DISPLAY_VER(i915) >= 5 || IS_G4X(i915); 2066 } 2067 2068 static void parse_ddi_ports(struct drm_i915_private *i915) 2069 { 2070 struct intel_bios_encoder_data *devdata; 2071 2072 if (!has_ddi_port_info(i915)) 2073 return; 2074 2075 list_for_each_entry(devdata, &i915->vbt.display_devices, node) 2076 parse_ddi_port(i915, devdata); 2077 } 2078 2079 static void 2080 parse_general_definitions(struct drm_i915_private *i915, 2081 const struct bdb_header *bdb) 2082 { 2083 const struct bdb_general_definitions *defs; 2084 struct intel_bios_encoder_data *devdata; 2085 const struct child_device_config *child; 2086 int i, child_device_num; 2087 u8 expected_size; 2088 u16 block_size; 2089 int bus_pin; 2090 2091 defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); 2092 if (!defs) { 2093 drm_dbg_kms(&i915->drm, 2094 "No general definition block is found, no devices defined.\n"); 2095 return; 2096 } 2097 2098 block_size = get_blocksize(defs); 2099 if (block_size < sizeof(*defs)) { 2100 drm_dbg_kms(&i915->drm, 2101 "General definitions block too small (%u)\n", 2102 block_size); 2103 return; 2104 } 2105 2106 bus_pin = defs->crt_ddc_gmbus_pin; 2107 drm_dbg_kms(&i915->drm, "crt_ddc_bus_pin: %d\n", bus_pin); 2108 if (intel_gmbus_is_valid_pin(i915, bus_pin)) 2109 i915->vbt.crt_ddc_pin = bus_pin; 2110 2111 if (bdb->version < 106) { 2112 expected_size = 22; 2113 } else if (bdb->version < 111) { 2114 expected_size = 27; 2115 } else if (bdb->version < 195) { 2116 expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE; 2117 } else if (bdb->version == 195) { 2118 expected_size = 37; 2119 } else if (bdb->version <= 215) { 2120 expected_size = 38; 2121 } else if (bdb->version <= 237) { 2122 expected_size = 39; 2123 } else { 2124 expected_size = sizeof(*child); 2125 BUILD_BUG_ON(sizeof(*child) < 39); 2126 drm_dbg(&i915->drm, 2127 "Expected child device config size for VBT version %u not known; assuming %u\n", 2128 bdb->version, expected_size); 2129 } 2130 2131 /* Flag an error for unexpected size, but continue anyway. */ 2132 if (defs->child_dev_size != expected_size) 2133 drm_err(&i915->drm, 2134 "Unexpected child device config size %u (expected %u for VBT version %u)\n", 2135 defs->child_dev_size, expected_size, bdb->version); 2136 2137 /* The legacy sized child device config is the minimum we need. */ 2138 if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) { 2139 drm_dbg_kms(&i915->drm, 2140 "Child device config size %u is too small.\n", 2141 defs->child_dev_size); 2142 return; 2143 } 2144 2145 /* get the number of child device */ 2146 child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size; 2147 2148 for (i = 0; i < child_device_num; i++) { 2149 child = child_device_ptr(defs, i); 2150 if (!child->device_type) 2151 continue; 2152 2153 drm_dbg_kms(&i915->drm, 2154 "Found VBT child device with type 0x%x\n", 2155 child->device_type); 2156 2157 devdata = kzalloc(sizeof(*devdata), GFP_KERNEL); 2158 if (!devdata) 2159 break; 2160 2161 devdata->i915 = i915; 2162 2163 /* 2164 * Copy as much as we know (sizeof) and is available 2165 * (child_dev_size) of the child device config. Accessing the 2166 * data must depend on VBT version. 2167 */ 2168 memcpy(&devdata->child, child, 2169 min_t(size_t, defs->child_dev_size, sizeof(*child))); 2170 2171 list_add_tail(&devdata->node, &i915->vbt.display_devices); 2172 } 2173 2174 if (list_empty(&i915->vbt.display_devices)) 2175 drm_dbg_kms(&i915->drm, 2176 "no child dev is parsed from VBT\n"); 2177 } 2178 2179 /* Common defaults which may be overridden by VBT. */ 2180 static void 2181 init_vbt_defaults(struct drm_i915_private *i915) 2182 { 2183 i915->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; 2184 2185 /* Default to having backlight */ 2186 i915->vbt.backlight.present = true; 2187 2188 /* LFP panel data */ 2189 i915->vbt.lvds_dither = 1; 2190 2191 /* SDVO panel data */ 2192 i915->vbt.sdvo_lvds_vbt_mode = NULL; 2193 2194 /* general features */ 2195 i915->vbt.int_tv_support = 1; 2196 i915->vbt.int_crt_support = 1; 2197 2198 /* driver features */ 2199 i915->vbt.int_lvds_support = 1; 2200 2201 /* Default to using SSC */ 2202 i915->vbt.lvds_use_ssc = 1; 2203 /* 2204 * Core/SandyBridge/IvyBridge use alternative (120MHz) reference 2205 * clock for LVDS. 2206 */ 2207 i915->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(i915, 2208 !HAS_PCH_SPLIT(i915)); 2209 drm_dbg_kms(&i915->drm, "Set default to SSC at %d kHz\n", 2210 i915->vbt.lvds_ssc_freq); 2211 } 2212 2213 /* Defaults to initialize only if there is no VBT. */ 2214 static void 2215 init_vbt_missing_defaults(struct drm_i915_private *i915) 2216 { 2217 enum port port; 2218 int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | 2219 BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F); 2220 2221 if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915)) 2222 return; 2223 2224 for_each_port_masked(port, ports) { 2225 struct intel_bios_encoder_data *devdata; 2226 struct child_device_config *child; 2227 enum phy phy = intel_port_to_phy(i915, port); 2228 2229 /* 2230 * VBT has the TypeC mode (native,TBT/USB) and we don't want 2231 * to detect it. 2232 */ 2233 if (intel_phy_is_tc(i915, phy)) 2234 continue; 2235 2236 /* Create fake child device config */ 2237 devdata = kzalloc(sizeof(*devdata), GFP_KERNEL); 2238 if (!devdata) 2239 break; 2240 2241 devdata->i915 = i915; 2242 child = &devdata->child; 2243 2244 if (port == PORT_F) 2245 child->dvo_port = DVO_PORT_HDMIF; 2246 else if (port == PORT_E) 2247 child->dvo_port = DVO_PORT_HDMIE; 2248 else 2249 child->dvo_port = DVO_PORT_HDMIA + port; 2250 2251 if (port != PORT_A && port != PORT_E) 2252 child->device_type |= DEVICE_TYPE_TMDS_DVI_SIGNALING; 2253 2254 if (port != PORT_E) 2255 child->device_type |= DEVICE_TYPE_DISPLAYPORT_OUTPUT; 2256 2257 if (port == PORT_A) 2258 child->device_type |= DEVICE_TYPE_INTERNAL_CONNECTOR; 2259 2260 list_add_tail(&devdata->node, &i915->vbt.display_devices); 2261 2262 drm_dbg_kms(&i915->drm, 2263 "Generating default VBT child device with type 0x04%x on port %c\n", 2264 child->device_type, port_name(port)); 2265 } 2266 2267 /* Bypass some minimum baseline VBT version checks */ 2268 i915->vbt.version = 155; 2269 } 2270 2271 static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt) 2272 { 2273 const void *_vbt = vbt; 2274 2275 return _vbt + vbt->bdb_offset; 2276 } 2277 2278 /** 2279 * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT 2280 * @buf: pointer to a buffer to validate 2281 * @size: size of the buffer 2282 * 2283 * Returns true on valid VBT. 2284 */ 2285 bool intel_bios_is_valid_vbt(const void *buf, size_t size) 2286 { 2287 const struct vbt_header *vbt = buf; 2288 const struct bdb_header *bdb; 2289 2290 if (!vbt) 2291 return false; 2292 2293 if (sizeof(struct vbt_header) > size) { 2294 DRM_DEBUG_DRIVER("VBT header incomplete\n"); 2295 return false; 2296 } 2297 2298 if (memcmp(vbt->signature, "$VBT", 4)) { 2299 DRM_DEBUG_DRIVER("VBT invalid signature\n"); 2300 return false; 2301 } 2302 2303 if (vbt->vbt_size > size) { 2304 DRM_DEBUG_DRIVER("VBT incomplete (vbt_size overflows)\n"); 2305 return false; 2306 } 2307 2308 size = vbt->vbt_size; 2309 2310 if (range_overflows_t(size_t, 2311 vbt->bdb_offset, 2312 sizeof(struct bdb_header), 2313 size)) { 2314 DRM_DEBUG_DRIVER("BDB header incomplete\n"); 2315 return false; 2316 } 2317 2318 bdb = get_bdb_header(vbt); 2319 if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) { 2320 DRM_DEBUG_DRIVER("BDB incomplete\n"); 2321 return false; 2322 } 2323 2324 return vbt; 2325 } 2326 2327 static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915) 2328 { 2329 u32 count, data, found, store = 0; 2330 u32 static_region, oprom_offset; 2331 u32 oprom_size = 0x200000; 2332 u16 vbt_size; 2333 u32 *vbt; 2334 2335 static_region = intel_uncore_read(&i915->uncore, SPI_STATIC_REGIONS); 2336 static_region &= OPTIONROM_SPI_REGIONID_MASK; 2337 intel_uncore_write(&i915->uncore, PRIMARY_SPI_REGIONID, static_region); 2338 2339 oprom_offset = intel_uncore_read(&i915->uncore, OROM_OFFSET); 2340 oprom_offset &= OROM_OFFSET_MASK; 2341 2342 for (count = 0; count < oprom_size; count += 4) { 2343 intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, oprom_offset + count); 2344 data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER); 2345 2346 if (data == *((const u32 *)"$VBT")) { 2347 found = oprom_offset + count; 2348 break; 2349 } 2350 } 2351 2352 if (count >= oprom_size) 2353 goto err_not_found; 2354 2355 /* Get VBT size and allocate space for the VBT */ 2356 intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found + 2357 offsetof(struct vbt_header, vbt_size)); 2358 vbt_size = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER); 2359 vbt_size &= 0xffff; 2360 2361 vbt = kzalloc(round_up(vbt_size, 4), GFP_KERNEL); 2362 if (!vbt) 2363 goto err_not_found; 2364 2365 for (count = 0; count < vbt_size; count += 4) { 2366 intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found + count); 2367 data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER); 2368 *(vbt + store++) = data; 2369 } 2370 2371 if (!intel_bios_is_valid_vbt(vbt, vbt_size)) 2372 goto err_free_vbt; 2373 2374 drm_dbg_kms(&i915->drm, "Found valid VBT in SPI flash\n"); 2375 2376 return (struct vbt_header *)vbt; 2377 2378 err_free_vbt: 2379 kfree(vbt); 2380 err_not_found: 2381 return NULL; 2382 } 2383 2384 static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915) 2385 { 2386 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 2387 void __iomem *p = NULL, *oprom; 2388 struct vbt_header *vbt; 2389 u16 vbt_size; 2390 size_t i, size; 2391 2392 oprom = pci_map_rom(pdev, &size); 2393 if (!oprom) 2394 return NULL; 2395 2396 /* Scour memory looking for the VBT signature. */ 2397 for (i = 0; i + 4 < size; i += 4) { 2398 if (ioread32(oprom + i) != *((const u32 *)"$VBT")) 2399 continue; 2400 2401 p = oprom + i; 2402 size -= i; 2403 break; 2404 } 2405 2406 if (!p) 2407 goto err_unmap_oprom; 2408 2409 if (sizeof(struct vbt_header) > size) { 2410 drm_dbg(&i915->drm, "VBT header incomplete\n"); 2411 goto err_unmap_oprom; 2412 } 2413 2414 vbt_size = ioread16(p + offsetof(struct vbt_header, vbt_size)); 2415 if (vbt_size > size) { 2416 drm_dbg(&i915->drm, 2417 "VBT incomplete (vbt_size overflows)\n"); 2418 goto err_unmap_oprom; 2419 } 2420 2421 /* The rest will be validated by intel_bios_is_valid_vbt() */ 2422 vbt = kmalloc(vbt_size, GFP_KERNEL); 2423 if (!vbt) 2424 goto err_unmap_oprom; 2425 2426 memcpy_fromio(vbt, p, vbt_size); 2427 2428 if (!intel_bios_is_valid_vbt(vbt, vbt_size)) 2429 goto err_free_vbt; 2430 2431 pci_unmap_rom(pdev, oprom); 2432 2433 drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n"); 2434 2435 return vbt; 2436 2437 err_free_vbt: 2438 kfree(vbt); 2439 err_unmap_oprom: 2440 pci_unmap_rom(pdev, oprom); 2441 2442 return NULL; 2443 } 2444 2445 /** 2446 * intel_bios_init - find VBT and initialize settings from the BIOS 2447 * @i915: i915 device instance 2448 * 2449 * Parse and initialize settings from the Video BIOS Tables (VBT). If the VBT 2450 * was not found in ACPI OpRegion, try to find it in PCI ROM first. Also 2451 * initialize some defaults if the VBT is not present at all. 2452 */ 2453 void intel_bios_init(struct drm_i915_private *i915) 2454 { 2455 const struct vbt_header *vbt = i915->opregion.vbt; 2456 struct vbt_header *oprom_vbt = NULL; 2457 const struct bdb_header *bdb; 2458 2459 INIT_LIST_HEAD(&i915->vbt.display_devices); 2460 2461 if (!HAS_DISPLAY(i915)) { 2462 drm_dbg_kms(&i915->drm, 2463 "Skipping VBT init due to disabled display.\n"); 2464 return; 2465 } 2466 2467 init_vbt_defaults(i915); 2468 2469 /* 2470 * If the OpRegion does not have VBT, look in SPI flash through MMIO or 2471 * PCI mapping 2472 */ 2473 if (!vbt && IS_DGFX(i915)) { 2474 oprom_vbt = spi_oprom_get_vbt(i915); 2475 vbt = oprom_vbt; 2476 } 2477 2478 if (!vbt) { 2479 oprom_vbt = oprom_get_vbt(i915); 2480 vbt = oprom_vbt; 2481 } 2482 2483 if (!vbt) 2484 goto out; 2485 2486 bdb = get_bdb_header(vbt); 2487 i915->vbt.version = bdb->version; 2488 2489 drm_dbg_kms(&i915->drm, 2490 "VBT signature \"%.*s\", BDB version %d\n", 2491 (int)sizeof(vbt->signature), vbt->signature, bdb->version); 2492 2493 /* Grab useful general definitions */ 2494 parse_general_features(i915, bdb); 2495 parse_general_definitions(i915, bdb); 2496 parse_panel_options(i915, bdb); 2497 parse_panel_dtd(i915, bdb); 2498 parse_lfp_backlight(i915, bdb); 2499 parse_sdvo_panel_data(i915, bdb); 2500 parse_driver_features(i915, bdb); 2501 parse_power_conservation_features(i915, bdb); 2502 parse_edp(i915, bdb); 2503 parse_psr(i915, bdb); 2504 parse_mipi_config(i915, bdb); 2505 parse_mipi_sequence(i915, bdb); 2506 2507 /* Depends on child device list */ 2508 parse_compression_parameters(i915, bdb); 2509 2510 out: 2511 if (!vbt) { 2512 drm_info(&i915->drm, 2513 "Failed to find VBIOS tables (VBT)\n"); 2514 init_vbt_missing_defaults(i915); 2515 } 2516 2517 /* Further processing on pre-parsed or generated child device data */ 2518 parse_sdvo_device_mapping(i915); 2519 parse_ddi_ports(i915); 2520 2521 kfree(oprom_vbt); 2522 } 2523 2524 /** 2525 * intel_bios_driver_remove - Free any resources allocated by intel_bios_init() 2526 * @i915: i915 device instance 2527 */ 2528 void intel_bios_driver_remove(struct drm_i915_private *i915) 2529 { 2530 struct intel_bios_encoder_data *devdata, *n; 2531 2532 list_for_each_entry_safe(devdata, n, &i915->vbt.display_devices, node) { 2533 list_del(&devdata->node); 2534 kfree(devdata->dsc); 2535 kfree(devdata); 2536 } 2537 2538 kfree(i915->vbt.sdvo_lvds_vbt_mode); 2539 i915->vbt.sdvo_lvds_vbt_mode = NULL; 2540 kfree(i915->vbt.lfp_lvds_vbt_mode); 2541 i915->vbt.lfp_lvds_vbt_mode = NULL; 2542 kfree(i915->vbt.dsi.data); 2543 i915->vbt.dsi.data = NULL; 2544 kfree(i915->vbt.dsi.pps); 2545 i915->vbt.dsi.pps = NULL; 2546 kfree(i915->vbt.dsi.config); 2547 i915->vbt.dsi.config = NULL; 2548 kfree(i915->vbt.dsi.deassert_seq); 2549 i915->vbt.dsi.deassert_seq = NULL; 2550 } 2551 2552 /** 2553 * intel_bios_is_tv_present - is integrated TV present in VBT 2554 * @i915: i915 device instance 2555 * 2556 * Return true if TV is present. If no child devices were parsed from VBT, 2557 * assume TV is present. 2558 */ 2559 bool intel_bios_is_tv_present(struct drm_i915_private *i915) 2560 { 2561 const struct intel_bios_encoder_data *devdata; 2562 const struct child_device_config *child; 2563 2564 if (!i915->vbt.int_tv_support) 2565 return false; 2566 2567 if (list_empty(&i915->vbt.display_devices)) 2568 return true; 2569 2570 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 2571 child = &devdata->child; 2572 2573 /* 2574 * If the device type is not TV, continue. 2575 */ 2576 switch (child->device_type) { 2577 case DEVICE_TYPE_INT_TV: 2578 case DEVICE_TYPE_TV: 2579 case DEVICE_TYPE_TV_SVIDEO_COMPOSITE: 2580 break; 2581 default: 2582 continue; 2583 } 2584 /* Only when the addin_offset is non-zero, it is regarded 2585 * as present. 2586 */ 2587 if (child->addin_offset) 2588 return true; 2589 } 2590 2591 return false; 2592 } 2593 2594 /** 2595 * intel_bios_is_lvds_present - is LVDS present in VBT 2596 * @i915: i915 device instance 2597 * @i2c_pin: i2c pin for LVDS if present 2598 * 2599 * Return true if LVDS is present. If no child devices were parsed from VBT, 2600 * assume LVDS is present. 2601 */ 2602 bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin) 2603 { 2604 const struct intel_bios_encoder_data *devdata; 2605 const struct child_device_config *child; 2606 2607 if (list_empty(&i915->vbt.display_devices)) 2608 return true; 2609 2610 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 2611 child = &devdata->child; 2612 2613 /* If the device type is not LFP, continue. 2614 * We have to check both the new identifiers as well as the 2615 * old for compatibility with some BIOSes. 2616 */ 2617 if (child->device_type != DEVICE_TYPE_INT_LFP && 2618 child->device_type != DEVICE_TYPE_LFP) 2619 continue; 2620 2621 if (intel_gmbus_is_valid_pin(i915, child->i2c_pin)) 2622 *i2c_pin = child->i2c_pin; 2623 2624 /* However, we cannot trust the BIOS writers to populate 2625 * the VBT correctly. Since LVDS requires additional 2626 * information from AIM blocks, a non-zero addin offset is 2627 * a good indicator that the LVDS is actually present. 2628 */ 2629 if (child->addin_offset) 2630 return true; 2631 2632 /* But even then some BIOS writers perform some black magic 2633 * and instantiate the device without reference to any 2634 * additional data. Trust that if the VBT was written into 2635 * the OpRegion then they have validated the LVDS's existence. 2636 */ 2637 if (i915->opregion.vbt) 2638 return true; 2639 } 2640 2641 return false; 2642 } 2643 2644 /** 2645 * intel_bios_is_port_present - is the specified digital port present 2646 * @i915: i915 device instance 2647 * @port: port to check 2648 * 2649 * Return true if the device in %port is present. 2650 */ 2651 bool intel_bios_is_port_present(struct drm_i915_private *i915, enum port port) 2652 { 2653 if (WARN_ON(!has_ddi_port_info(i915))) 2654 return true; 2655 2656 return i915->vbt.ports[port]; 2657 } 2658 2659 /** 2660 * intel_bios_is_port_edp - is the device in given port eDP 2661 * @i915: i915 device instance 2662 * @port: port to check 2663 * 2664 * Return true if the device in %port is eDP. 2665 */ 2666 bool intel_bios_is_port_edp(struct drm_i915_private *i915, enum port port) 2667 { 2668 const struct intel_bios_encoder_data *devdata = 2669 intel_bios_encoder_data_lookup(i915, port); 2670 2671 return devdata && intel_bios_encoder_supports_edp(devdata); 2672 } 2673 2674 static bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata) 2675 { 2676 const struct child_device_config *child = &devdata->child; 2677 2678 if (!intel_bios_encoder_supports_dp(devdata) || 2679 !intel_bios_encoder_supports_hdmi(devdata)) 2680 return false; 2681 2682 if (dvo_port_type(child->dvo_port) == DVO_PORT_DPA) 2683 return true; 2684 2685 /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */ 2686 if (dvo_port_type(child->dvo_port) == DVO_PORT_HDMIA && 2687 child->aux_channel != 0) 2688 return true; 2689 2690 return false; 2691 } 2692 2693 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *i915, 2694 enum port port) 2695 { 2696 const struct intel_bios_encoder_data *devdata = 2697 intel_bios_encoder_data_lookup(i915, port); 2698 2699 return devdata && intel_bios_encoder_supports_dp_dual_mode(devdata); 2700 } 2701 2702 /** 2703 * intel_bios_is_dsi_present - is DSI present in VBT 2704 * @i915: i915 device instance 2705 * @port: port for DSI if present 2706 * 2707 * Return true if DSI is present, and return the port in %port. 2708 */ 2709 bool intel_bios_is_dsi_present(struct drm_i915_private *i915, 2710 enum port *port) 2711 { 2712 const struct intel_bios_encoder_data *devdata; 2713 const struct child_device_config *child; 2714 u8 dvo_port; 2715 2716 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 2717 child = &devdata->child; 2718 2719 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) 2720 continue; 2721 2722 dvo_port = child->dvo_port; 2723 2724 if (dvo_port == DVO_PORT_MIPIA || 2725 (dvo_port == DVO_PORT_MIPIB && DISPLAY_VER(i915) >= 11) || 2726 (dvo_port == DVO_PORT_MIPIC && DISPLAY_VER(i915) < 11)) { 2727 if (port) 2728 *port = dvo_port - DVO_PORT_MIPIA; 2729 return true; 2730 } else if (dvo_port == DVO_PORT_MIPIB || 2731 dvo_port == DVO_PORT_MIPIC || 2732 dvo_port == DVO_PORT_MIPID) { 2733 drm_dbg_kms(&i915->drm, 2734 "VBT has unsupported DSI port %c\n", 2735 port_name(dvo_port - DVO_PORT_MIPIA)); 2736 } 2737 } 2738 2739 return false; 2740 } 2741 2742 static void fill_dsc(struct intel_crtc_state *crtc_state, 2743 struct dsc_compression_parameters_entry *dsc, 2744 int dsc_max_bpc) 2745 { 2746 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 2747 int bpc = 8; 2748 2749 vdsc_cfg->dsc_version_major = dsc->version_major; 2750 vdsc_cfg->dsc_version_minor = dsc->version_minor; 2751 2752 if (dsc->support_12bpc && dsc_max_bpc >= 12) 2753 bpc = 12; 2754 else if (dsc->support_10bpc && dsc_max_bpc >= 10) 2755 bpc = 10; 2756 else if (dsc->support_8bpc && dsc_max_bpc >= 8) 2757 bpc = 8; 2758 else 2759 DRM_DEBUG_KMS("VBT: Unsupported BPC %d for DCS\n", 2760 dsc_max_bpc); 2761 2762 crtc_state->pipe_bpp = bpc * 3; 2763 2764 crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, 2765 VBT_DSC_MAX_BPP(dsc->max_bpp)); 2766 2767 /* 2768 * FIXME: This is ugly, and slice count should take DSC engine 2769 * throughput etc. into account. 2770 * 2771 * Also, per spec DSI supports 1, 2, 3 or 4 horizontal slices. 2772 */ 2773 if (dsc->slices_per_line & BIT(2)) { 2774 crtc_state->dsc.slice_count = 4; 2775 } else if (dsc->slices_per_line & BIT(1)) { 2776 crtc_state->dsc.slice_count = 2; 2777 } else { 2778 /* FIXME */ 2779 if (!(dsc->slices_per_line & BIT(0))) 2780 DRM_DEBUG_KMS("VBT: Unsupported DSC slice count for DSI\n"); 2781 2782 crtc_state->dsc.slice_count = 1; 2783 } 2784 2785 if (crtc_state->hw.adjusted_mode.crtc_hdisplay % 2786 crtc_state->dsc.slice_count != 0) 2787 DRM_DEBUG_KMS("VBT: DSC hdisplay %d not divisible by slice count %d\n", 2788 crtc_state->hw.adjusted_mode.crtc_hdisplay, 2789 crtc_state->dsc.slice_count); 2790 2791 /* 2792 * The VBT rc_buffer_block_size and rc_buffer_size definitions 2793 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. 2794 */ 2795 vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size, 2796 dsc->rc_buffer_size); 2797 2798 /* FIXME: DSI spec says bpc + 1 for this one */ 2799 vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); 2800 2801 vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; 2802 2803 vdsc_cfg->slice_height = dsc->slice_height; 2804 } 2805 2806 /* FIXME: initially DSI specific */ 2807 bool intel_bios_get_dsc_params(struct intel_encoder *encoder, 2808 struct intel_crtc_state *crtc_state, 2809 int dsc_max_bpc) 2810 { 2811 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2812 const struct intel_bios_encoder_data *devdata; 2813 const struct child_device_config *child; 2814 2815 list_for_each_entry(devdata, &i915->vbt.display_devices, node) { 2816 child = &devdata->child; 2817 2818 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) 2819 continue; 2820 2821 if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) { 2822 if (!devdata->dsc) 2823 return false; 2824 2825 if (crtc_state) 2826 fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc); 2827 2828 return true; 2829 } 2830 } 2831 2832 return false; 2833 } 2834 2835 /** 2836 * intel_bios_is_port_hpd_inverted - is HPD inverted for %port 2837 * @i915: i915 device instance 2838 * @port: port to check 2839 * 2840 * Return true if HPD should be inverted for %port. 2841 */ 2842 bool 2843 intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915, 2844 enum port port) 2845 { 2846 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port]; 2847 2848 if (drm_WARN_ON_ONCE(&i915->drm, 2849 !IS_GEMINILAKE(i915) && !IS_BROXTON(i915))) 2850 return false; 2851 2852 return devdata && devdata->child.hpd_invert; 2853 } 2854 2855 /** 2856 * intel_bios_is_lspcon_present - if LSPCON is attached on %port 2857 * @i915: i915 device instance 2858 * @port: port to check 2859 * 2860 * Return true if LSPCON is present on this port 2861 */ 2862 bool 2863 intel_bios_is_lspcon_present(const struct drm_i915_private *i915, 2864 enum port port) 2865 { 2866 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port]; 2867 2868 return HAS_LSPCON(i915) && devdata && devdata->child.lspcon; 2869 } 2870 2871 /** 2872 * intel_bios_is_lane_reversal_needed - if lane reversal needed on port 2873 * @i915: i915 device instance 2874 * @port: port to check 2875 * 2876 * Return true if port requires lane reversal 2877 */ 2878 bool 2879 intel_bios_is_lane_reversal_needed(const struct drm_i915_private *i915, 2880 enum port port) 2881 { 2882 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port]; 2883 2884 return devdata && devdata->child.lane_reversal; 2885 } 2886 2887 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915, 2888 enum port port) 2889 { 2890 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port]; 2891 enum aux_ch aux_ch; 2892 2893 if (!devdata || !devdata->child.aux_channel) { 2894 aux_ch = (enum aux_ch)port; 2895 2896 drm_dbg_kms(&i915->drm, 2897 "using AUX %c for port %c (platform default)\n", 2898 aux_ch_name(aux_ch), port_name(port)); 2899 return aux_ch; 2900 } 2901 2902 /* 2903 * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D 2904 * map to DDI A,B,TC1,TC2 respectively. 2905 * 2906 * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E 2907 * map to DDI A,TC1,TC2,TC3,TC4 respectively. 2908 */ 2909 switch (devdata->child.aux_channel) { 2910 case DP_AUX_A: 2911 aux_ch = AUX_CH_A; 2912 break; 2913 case DP_AUX_B: 2914 if (IS_ALDERLAKE_S(i915)) 2915 aux_ch = AUX_CH_USBC1; 2916 else 2917 aux_ch = AUX_CH_B; 2918 break; 2919 case DP_AUX_C: 2920 if (IS_ALDERLAKE_S(i915)) 2921 aux_ch = AUX_CH_USBC2; 2922 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) 2923 aux_ch = AUX_CH_USBC1; 2924 else 2925 aux_ch = AUX_CH_C; 2926 break; 2927 case DP_AUX_D: 2928 if (DISPLAY_VER(i915) == 13) 2929 aux_ch = AUX_CH_D_XELPD; 2930 else if (IS_ALDERLAKE_S(i915)) 2931 aux_ch = AUX_CH_USBC3; 2932 else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) 2933 aux_ch = AUX_CH_USBC2; 2934 else 2935 aux_ch = AUX_CH_D; 2936 break; 2937 case DP_AUX_E: 2938 if (DISPLAY_VER(i915) == 13) 2939 aux_ch = AUX_CH_E_XELPD; 2940 else if (IS_ALDERLAKE_S(i915)) 2941 aux_ch = AUX_CH_USBC4; 2942 else 2943 aux_ch = AUX_CH_E; 2944 break; 2945 case DP_AUX_F: 2946 if (DISPLAY_VER(i915) == 13) 2947 aux_ch = AUX_CH_USBC1; 2948 else 2949 aux_ch = AUX_CH_F; 2950 break; 2951 case DP_AUX_G: 2952 if (DISPLAY_VER(i915) == 13) 2953 aux_ch = AUX_CH_USBC2; 2954 else 2955 aux_ch = AUX_CH_G; 2956 break; 2957 case DP_AUX_H: 2958 if (DISPLAY_VER(i915) == 13) 2959 aux_ch = AUX_CH_USBC3; 2960 else 2961 aux_ch = AUX_CH_H; 2962 break; 2963 case DP_AUX_I: 2964 if (DISPLAY_VER(i915) == 13) 2965 aux_ch = AUX_CH_USBC4; 2966 else 2967 aux_ch = AUX_CH_I; 2968 break; 2969 default: 2970 MISSING_CASE(devdata->child.aux_channel); 2971 aux_ch = AUX_CH_A; 2972 break; 2973 } 2974 2975 drm_dbg_kms(&i915->drm, "using AUX %c for port %c (VBT)\n", 2976 aux_ch_name(aux_ch), port_name(port)); 2977 2978 return aux_ch; 2979 } 2980 2981 int intel_bios_max_tmds_clock(struct intel_encoder *encoder) 2982 { 2983 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2984 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port]; 2985 2986 return _intel_bios_max_tmds_clock(devdata); 2987 } 2988 2989 /* This is an index in the HDMI/DVI DDI buffer translation table, or -1 */ 2990 int intel_bios_hdmi_level_shift(struct intel_encoder *encoder) 2991 { 2992 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2993 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port]; 2994 2995 return _intel_bios_hdmi_level_shift(devdata); 2996 } 2997 2998 int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data *devdata) 2999 { 3000 if (!devdata || devdata->i915->vbt.version < 196 || !devdata->child.iboost) 3001 return 0; 3002 3003 return translate_iboost(devdata->child.dp_iboost_level); 3004 } 3005 3006 int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *devdata) 3007 { 3008 if (!devdata || devdata->i915->vbt.version < 196 || !devdata->child.iboost) 3009 return 0; 3010 3011 return translate_iboost(devdata->child.hdmi_iboost_level); 3012 } 3013 3014 int intel_bios_dp_max_link_rate(struct intel_encoder *encoder) 3015 { 3016 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3017 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port]; 3018 3019 return _intel_bios_dp_max_link_rate(devdata); 3020 } 3021 3022 int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder) 3023 { 3024 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3025 const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port]; 3026 3027 if (!devdata || !devdata->child.ddc_pin) 3028 return 0; 3029 3030 return map_ddc_pin(i915, devdata->child.ddc_pin); 3031 } 3032 3033 bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata) 3034 { 3035 return devdata->i915->vbt.version >= 195 && devdata->child.dp_usb_type_c; 3036 } 3037 3038 bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata) 3039 { 3040 return devdata->i915->vbt.version >= 209 && devdata->child.tbt; 3041 } 3042 3043 const struct intel_bios_encoder_data * 3044 intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port) 3045 { 3046 return i915->vbt.ports[port]; 3047 } 3048