1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "i915_reg.h" 26 #include "intel_color.h" 27 #include "intel_de.h" 28 #include "intel_display_types.h" 29 #include "intel_dsb.h" 30 31 struct intel_color_funcs { 32 int (*color_check)(struct intel_crtc_state *crtc_state); 33 /* 34 * Program non-arming double buffered color management registers 35 * before vblank evasion. The registers should then latch after 36 * the arming register is written (by color_commit_arm()) during 37 * the next vblank start, alongside any other double buffered 38 * registers involved with the same commit. This hook is optional. 39 */ 40 void (*color_commit_noarm)(const struct intel_crtc_state *crtc_state); 41 /* 42 * Program arming double buffered color management registers 43 * during vblank evasion. The registers (and whatever other registers 44 * they arm that were written by color_commit_noarm) should then latch 45 * during the next vblank start, alongside any other double buffered 46 * registers involved with the same commit. 47 */ 48 void (*color_commit_arm)(const struct intel_crtc_state *crtc_state); 49 /* 50 * Perform any extra tasks needed after all the 51 * double buffered registers have been latched. 52 */ 53 void (*color_post_update)(const struct intel_crtc_state *crtc_state); 54 /* 55 * Load LUTs (and other single buffered color management 56 * registers). Will (hopefully) be called during the vblank 57 * following the latching of any double buffered registers 58 * involved with the same commit. 59 */ 60 void (*load_luts)(const struct intel_crtc_state *crtc_state); 61 /* 62 * Read out the LUTs from the hardware into the software state. 63 * Used by eg. the hardware state checker. 64 */ 65 void (*read_luts)(struct intel_crtc_state *crtc_state); 66 /* 67 * Compare the LUTs 68 */ 69 bool (*lut_equal)(const struct intel_crtc_state *crtc_state, 70 const struct drm_property_blob *blob1, 71 const struct drm_property_blob *blob2, 72 bool is_pre_csc_lut); 73 }; 74 75 #define CTM_COEFF_SIGN (1ULL << 63) 76 77 #define CTM_COEFF_1_0 (1ULL << 32) 78 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1) 79 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1) 80 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1) 81 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1) 82 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1) 83 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1) 84 85 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255) 86 87 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0) 88 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1)) 89 90 #define LEGACY_LUT_LENGTH 256 91 92 /* 93 * ILK+ csc matrix: 94 * 95 * |R/Cr| | c0 c1 c2 | ( |R/Cr| |preoff0| ) |postoff0| 96 * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1| 97 * |B/Cb| | c6 c7 c8 | ( |B/Cb| |preoff2| ) |postoff2| 98 * 99 * ILK/SNB don't have explicit post offsets, and instead 100 * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used: 101 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2 102 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2 103 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0 104 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16 105 */ 106 107 /* 108 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point 109 * format). This macro takes the coefficient we want transformed and the 110 * number of fractional bits. 111 * 112 * We only have a 9 bits precision window which slides depending on the value 113 * of the CTM coefficient and we write the value from bit 3. We also round the 114 * value. 115 */ 116 #define ILK_CSC_COEFF_FP(coeff, fbits) \ 117 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8) 118 119 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0 120 #define ILK_CSC_COEFF_1_0 0x7800 121 122 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255) 123 124 /* Nop pre/post offsets */ 125 static const u16 ilk_csc_off_zero[3] = {}; 126 127 /* Identity matrix */ 128 static const u16 ilk_csc_coeff_identity[9] = { 129 ILK_CSC_COEFF_1_0, 0, 0, 130 0, ILK_CSC_COEFF_1_0, 0, 131 0, 0, ILK_CSC_COEFF_1_0, 132 }; 133 134 /* Limited range RGB post offsets */ 135 static const u16 ilk_csc_postoff_limited_range[3] = { 136 ILK_CSC_POSTOFF_LIMITED_RANGE, 137 ILK_CSC_POSTOFF_LIMITED_RANGE, 138 ILK_CSC_POSTOFF_LIMITED_RANGE, 139 }; 140 141 /* Full range RGB -> limited range RGB matrix */ 142 static const u16 ilk_csc_coeff_limited_range[9] = { 143 ILK_CSC_COEFF_LIMITED_RANGE, 0, 0, 144 0, ILK_CSC_COEFF_LIMITED_RANGE, 0, 145 0, 0, ILK_CSC_COEFF_LIMITED_RANGE, 146 }; 147 148 /* BT.709 full range RGB -> limited range YCbCr matrix */ 149 static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = { 150 0x1e08, 0x9cc0, 0xb528, 151 0x2ba8, 0x09d8, 0x37e8, 152 0xbce8, 0x9ad8, 0x1e08, 153 }; 154 155 /* Limited range YCbCr post offsets */ 156 static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = { 157 0x0800, 0x0100, 0x0800, 158 }; 159 160 static bool lut_is_legacy(const struct drm_property_blob *lut) 161 { 162 return lut && drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; 163 } 164 165 /* 166 * When using limited range, multiply the matrix given by userspace by 167 * the matrix that we would use for the limited range. 168 */ 169 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input) 170 { 171 int i; 172 173 for (i = 0; i < 9; i++) { 174 u64 user_coeff = input[i]; 175 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE; 176 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0, 177 CTM_COEFF_4_0 - 1) >> 2; 178 179 /* 180 * By scaling every co-efficient with limited range (16-235) 181 * vs full range (0-255) the final o/p will be scaled down to 182 * fit in the limited range supported by the panel. 183 */ 184 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30; 185 result[i] |= user_coeff & CTM_COEFF_SIGN; 186 } 187 188 return result; 189 } 190 191 static void ilk_update_pipe_csc(struct intel_crtc *crtc, 192 const u16 preoff[3], 193 const u16 coeff[9], 194 const u16 postoff[3]) 195 { 196 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 197 enum pipe pipe = crtc->pipe; 198 199 intel_de_write_fw(i915, PIPE_CSC_PREOFF_HI(pipe), preoff[0]); 200 intel_de_write_fw(i915, PIPE_CSC_PREOFF_ME(pipe), preoff[1]); 201 intel_de_write_fw(i915, PIPE_CSC_PREOFF_LO(pipe), preoff[2]); 202 203 intel_de_write_fw(i915, PIPE_CSC_COEFF_RY_GY(pipe), 204 coeff[0] << 16 | coeff[1]); 205 intel_de_write_fw(i915, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16); 206 207 intel_de_write_fw(i915, PIPE_CSC_COEFF_RU_GU(pipe), 208 coeff[3] << 16 | coeff[4]); 209 intel_de_write_fw(i915, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16); 210 211 intel_de_write_fw(i915, PIPE_CSC_COEFF_RV_GV(pipe), 212 coeff[6] << 16 | coeff[7]); 213 intel_de_write_fw(i915, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16); 214 215 if (DISPLAY_VER(i915) >= 7) { 216 intel_de_write_fw(i915, PIPE_CSC_POSTOFF_HI(pipe), 217 postoff[0]); 218 intel_de_write_fw(i915, PIPE_CSC_POSTOFF_ME(pipe), 219 postoff[1]); 220 intel_de_write_fw(i915, PIPE_CSC_POSTOFF_LO(pipe), 221 postoff[2]); 222 } 223 } 224 225 static void icl_update_output_csc(struct intel_crtc *crtc, 226 const u16 preoff[3], 227 const u16 coeff[9], 228 const u16 postoff[3]) 229 { 230 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 231 enum pipe pipe = crtc->pipe; 232 233 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]); 234 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]); 235 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]); 236 237 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), 238 coeff[0] << 16 | coeff[1]); 239 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BY(pipe), 240 coeff[2] << 16); 241 242 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), 243 coeff[3] << 16 | coeff[4]); 244 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BU(pipe), 245 coeff[5] << 16); 246 247 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), 248 coeff[6] << 16 | coeff[7]); 249 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BV(pipe), 250 coeff[8] << 16); 251 252 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]); 253 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]); 254 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]); 255 } 256 257 static bool ilk_limited_range(const struct intel_crtc_state *crtc_state) 258 { 259 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 260 261 /* icl+ have dedicated output CSC */ 262 if (DISPLAY_VER(i915) >= 11) 263 return false; 264 265 /* pre-hsw have TRANSCONF_COLOR_RANGE_SELECT */ 266 if (DISPLAY_VER(i915) < 7 || IS_IVYBRIDGE(i915)) 267 return false; 268 269 return crtc_state->limited_color_range; 270 } 271 272 static bool ilk_lut_limited_range(const struct intel_crtc_state *crtc_state) 273 { 274 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 275 276 if (!ilk_limited_range(crtc_state)) 277 return false; 278 279 if (crtc_state->c8_planes) 280 return false; 281 282 if (DISPLAY_VER(i915) == 10) 283 return crtc_state->hw.gamma_lut; 284 else 285 return crtc_state->hw.gamma_lut && 286 (crtc_state->hw.degamma_lut || crtc_state->hw.ctm); 287 } 288 289 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) 290 { 291 if (!ilk_limited_range(crtc_state)) 292 return false; 293 294 return !ilk_lut_limited_range(crtc_state); 295 } 296 297 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state, 298 u16 coeffs[9], bool limited_color_range) 299 { 300 const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data; 301 const u64 *input; 302 u64 temp[9]; 303 int i; 304 305 if (limited_color_range) 306 input = ctm_mult_by_limited(temp, ctm->matrix); 307 else 308 input = ctm->matrix; 309 310 /* 311 * Convert fixed point S31.32 input to format supported by the 312 * hardware. 313 */ 314 for (i = 0; i < 9; i++) { 315 u64 abs_coeff = ((1ULL << 63) - 1) & input[i]; 316 317 /* 318 * Clamp input value to min/max supported by 319 * hardware. 320 */ 321 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1); 322 323 coeffs[i] = 0; 324 325 /* sign bit */ 326 if (CTM_COEFF_NEGATIVE(input[i])) 327 coeffs[i] |= 1 << 15; 328 329 if (abs_coeff < CTM_COEFF_0_125) 330 coeffs[i] |= (3 << 12) | 331 ILK_CSC_COEFF_FP(abs_coeff, 12); 332 else if (abs_coeff < CTM_COEFF_0_25) 333 coeffs[i] |= (2 << 12) | 334 ILK_CSC_COEFF_FP(abs_coeff, 11); 335 else if (abs_coeff < CTM_COEFF_0_5) 336 coeffs[i] |= (1 << 12) | 337 ILK_CSC_COEFF_FP(abs_coeff, 10); 338 else if (abs_coeff < CTM_COEFF_1_0) 339 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9); 340 else if (abs_coeff < CTM_COEFF_2_0) 341 coeffs[i] |= (7 << 12) | 342 ILK_CSC_COEFF_FP(abs_coeff, 8); 343 else 344 coeffs[i] |= (6 << 12) | 345 ILK_CSC_COEFF_FP(abs_coeff, 7); 346 } 347 } 348 349 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) 350 { 351 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 352 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 353 bool limited_color_range = ilk_csc_limited_range(crtc_state); 354 355 if (crtc_state->hw.ctm) { 356 u16 coeff[9]; 357 358 ilk_csc_convert_ctm(crtc_state, coeff, limited_color_range); 359 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff, 360 limited_color_range ? 361 ilk_csc_postoff_limited_range : 362 ilk_csc_off_zero); 363 } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { 364 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 365 ilk_csc_coeff_rgb_to_ycbcr, 366 ilk_csc_postoff_rgb_to_ycbcr); 367 } else if (limited_color_range) { 368 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 369 ilk_csc_coeff_limited_range, 370 ilk_csc_postoff_limited_range); 371 } else if (crtc_state->csc_enable) { 372 /* 373 * On GLK both pipe CSC and degamma LUT are controlled 374 * by csc_enable. Hence for the cases where the degama 375 * LUT is needed but CSC is not we need to load an 376 * identity matrix. 377 */ 378 drm_WARN_ON(&i915->drm, !IS_GEMINILAKE(i915)); 379 380 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 381 ilk_csc_coeff_identity, 382 ilk_csc_off_zero); 383 } 384 } 385 386 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) 387 { 388 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 389 390 if (crtc_state->hw.ctm) { 391 u16 coeff[9]; 392 393 ilk_csc_convert_ctm(crtc_state, coeff, false); 394 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, 395 coeff, ilk_csc_off_zero); 396 } 397 398 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { 399 icl_update_output_csc(crtc, ilk_csc_off_zero, 400 ilk_csc_coeff_rgb_to_ycbcr, 401 ilk_csc_postoff_rgb_to_ycbcr); 402 } else if (crtc_state->limited_color_range) { 403 icl_update_output_csc(crtc, ilk_csc_off_zero, 404 ilk_csc_coeff_limited_range, 405 ilk_csc_postoff_limited_range); 406 } 407 } 408 409 static void chv_load_cgm_csc(struct intel_crtc *crtc, 410 const struct drm_property_blob *blob) 411 { 412 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 413 const struct drm_color_ctm *ctm = blob->data; 414 enum pipe pipe = crtc->pipe; 415 u16 coeffs[9]; 416 int i; 417 418 for (i = 0; i < ARRAY_SIZE(coeffs); i++) { 419 u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i]; 420 421 /* Round coefficient. */ 422 abs_coeff += 1 << (32 - 13); 423 /* Clamp to hardware limits. */ 424 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1); 425 426 coeffs[i] = 0; 427 428 /* Write coefficients in S3.12 format. */ 429 if (ctm->matrix[i] & (1ULL << 63)) 430 coeffs[i] |= 1 << 15; 431 432 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12; 433 coeffs[i] |= (abs_coeff >> 20) & 0xfff; 434 } 435 436 intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF01(pipe), 437 coeffs[1] << 16 | coeffs[0]); 438 intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF23(pipe), 439 coeffs[3] << 16 | coeffs[2]); 440 intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF45(pipe), 441 coeffs[5] << 16 | coeffs[4]); 442 intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF67(pipe), 443 coeffs[7] << 16 | coeffs[6]); 444 intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF8(pipe), 445 coeffs[8]); 446 } 447 448 /* convert hw value with given bit_precision to lut property val */ 449 static u32 intel_color_lut_pack(u32 val, int bit_precision) 450 { 451 u32 max = 0xffff >> (16 - bit_precision); 452 453 val = clamp_val(val, 0, max); 454 455 if (bit_precision < 16) 456 val <<= 16 - bit_precision; 457 458 return val; 459 } 460 461 static u32 i9xx_lut_8(const struct drm_color_lut *color) 462 { 463 return REG_FIELD_PREP(PALETTE_RED_MASK, drm_color_lut_extract(color->red, 8)) | 464 REG_FIELD_PREP(PALETTE_GREEN_MASK, drm_color_lut_extract(color->green, 8)) | 465 REG_FIELD_PREP(PALETTE_BLUE_MASK, drm_color_lut_extract(color->blue, 8)); 466 } 467 468 static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val) 469 { 470 entry->red = intel_color_lut_pack(REG_FIELD_GET(PALETTE_RED_MASK, val), 8); 471 entry->green = intel_color_lut_pack(REG_FIELD_GET(PALETTE_GREEN_MASK, val), 8); 472 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PALETTE_BLUE_MASK, val), 8); 473 } 474 475 /* i8xx/i9xx+ 10bit slope format "even DW" (low 8 bits) */ 476 static u32 _i9xx_lut_10_ldw(u16 a) 477 { 478 return drm_color_lut_extract(a, 10) & 0xff; 479 } 480 481 static u32 i9xx_lut_10_ldw(const struct drm_color_lut *color) 482 { 483 return REG_FIELD_PREP(PALETTE_RED_MASK, _i9xx_lut_10_ldw(color[0].red)) | 484 REG_FIELD_PREP(PALETTE_GREEN_MASK, _i9xx_lut_10_ldw(color[0].green)) | 485 REG_FIELD_PREP(PALETTE_BLUE_MASK, _i9xx_lut_10_ldw(color[0].blue)); 486 } 487 488 /* i8xx/i9xx+ 10bit slope format "odd DW" (high 2 bits + slope) */ 489 static u32 _i9xx_lut_10_udw(u16 a, u16 b) 490 { 491 unsigned int mantissa, exponent; 492 493 a = drm_color_lut_extract(a, 10); 494 b = drm_color_lut_extract(b, 10); 495 496 /* b = a + 8 * m * 2 ^ -e */ 497 mantissa = clamp(b - a, 0, 0x7f); 498 exponent = 3; 499 while (mantissa > 0xf) { 500 mantissa >>= 1; 501 exponent--; 502 } 503 504 return (exponent << 6) | 505 (mantissa << 2) | 506 (a >> 8); 507 } 508 509 static u32 i9xx_lut_10_udw(const struct drm_color_lut *color) 510 { 511 return REG_FIELD_PREP(PALETTE_RED_MASK, _i9xx_lut_10_udw(color[0].red, color[1].red)) | 512 REG_FIELD_PREP(PALETTE_GREEN_MASK, _i9xx_lut_10_udw(color[0].green, color[1].green)) | 513 REG_FIELD_PREP(PALETTE_BLUE_MASK, _i9xx_lut_10_udw(color[0].blue, color[1].blue)); 514 } 515 516 static void i9xx_lut_10_pack(struct drm_color_lut *color, 517 u32 ldw, u32 udw) 518 { 519 u16 red = REG_FIELD_GET(PALETTE_10BIT_RED_LDW_MASK, ldw) | 520 REG_FIELD_GET(PALETTE_10BIT_RED_UDW_MASK, udw) << 8; 521 u16 green = REG_FIELD_GET(PALETTE_10BIT_GREEN_LDW_MASK, ldw) | 522 REG_FIELD_GET(PALETTE_10BIT_GREEN_UDW_MASK, udw) << 8; 523 u16 blue = REG_FIELD_GET(PALETTE_10BIT_BLUE_LDW_MASK, ldw) | 524 REG_FIELD_GET(PALETTE_10BIT_BLUE_UDW_MASK, udw) << 8; 525 526 color->red = intel_color_lut_pack(red, 10); 527 color->green = intel_color_lut_pack(green, 10); 528 color->blue = intel_color_lut_pack(blue, 10); 529 } 530 531 static void i9xx_lut_10_pack_slope(struct drm_color_lut *color, 532 u32 ldw, u32 udw) 533 { 534 int r_exp = REG_FIELD_GET(PALETTE_10BIT_RED_EXP_MASK, udw); 535 int r_mant = REG_FIELD_GET(PALETTE_10BIT_RED_MANT_MASK, udw); 536 int g_exp = REG_FIELD_GET(PALETTE_10BIT_GREEN_EXP_MASK, udw); 537 int g_mant = REG_FIELD_GET(PALETTE_10BIT_GREEN_MANT_MASK, udw); 538 int b_exp = REG_FIELD_GET(PALETTE_10BIT_BLUE_EXP_MASK, udw); 539 int b_mant = REG_FIELD_GET(PALETTE_10BIT_BLUE_MANT_MASK, udw); 540 541 i9xx_lut_10_pack(color, ldw, udw); 542 543 color->red += r_mant << (3 - r_exp); 544 color->green += g_mant << (3 - g_exp); 545 color->blue += b_mant << (3 - b_exp); 546 } 547 548 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */ 549 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color) 550 { 551 return REG_FIELD_PREP(PALETTE_RED_MASK, color->red & 0xff) | 552 REG_FIELD_PREP(PALETTE_GREEN_MASK, color->green & 0xff) | 553 REG_FIELD_PREP(PALETTE_BLUE_MASK, color->blue & 0xff); 554 } 555 556 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */ 557 static u32 i965_lut_10p6_udw(const struct drm_color_lut *color) 558 { 559 return REG_FIELD_PREP(PALETTE_RED_MASK, color->red >> 8) | 560 REG_FIELD_PREP(PALETTE_GREEN_MASK, color->green >> 8) | 561 REG_FIELD_PREP(PALETTE_BLUE_MASK, color->blue >> 8); 562 } 563 564 static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 565 { 566 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 | 567 REG_FIELD_GET(PALETTE_RED_MASK, ldw); 568 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 | 569 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw); 570 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 | 571 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw); 572 } 573 574 static u16 i965_lut_11p6_max_pack(u32 val) 575 { 576 /* PIPEGCMAX is 11.6, clamp to 10.6 */ 577 return clamp_val(val, 0, 0xffff); 578 } 579 580 static u32 ilk_lut_10(const struct drm_color_lut *color) 581 { 582 return REG_FIELD_PREP(PREC_PALETTE_10_RED_MASK, drm_color_lut_extract(color->red, 10)) | 583 REG_FIELD_PREP(PREC_PALETTE_10_GREEN_MASK, drm_color_lut_extract(color->green, 10)) | 584 REG_FIELD_PREP(PREC_PALETTE_10_BLUE_MASK, drm_color_lut_extract(color->blue, 10)); 585 } 586 587 static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val) 588 { 589 entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_RED_MASK, val), 10); 590 entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_GREEN_MASK, val), 10); 591 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_BLUE_MASK, val), 10); 592 } 593 594 /* ilk+ "12.4" interpolated format (low 6 bits) */ 595 static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color) 596 { 597 return REG_FIELD_PREP(PREC_PALETTE_12P4_RED_LDW_MASK, color->red & 0x3f) | 598 REG_FIELD_PREP(PREC_PALETTE_12P4_GREEN_LDW_MASK, color->green & 0x3f) | 599 REG_FIELD_PREP(PREC_PALETTE_12P4_BLUE_LDW_MASK, color->blue & 0x3f); 600 } 601 602 /* ilk+ "12.4" interpolated format (high 10 bits) */ 603 static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color) 604 { 605 return REG_FIELD_PREP(PREC_PALETTE_12P4_RED_UDW_MASK, color->red >> 6) | 606 REG_FIELD_PREP(PREC_PALETTE_12P4_GREEN_UDW_MASK, color->green >> 6) | 607 REG_FIELD_PREP(PREC_PALETTE_12P4_BLUE_UDW_MASK, color->blue >> 6); 608 } 609 610 static void ilk_lut_12p4_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 611 { 612 entry->red = REG_FIELD_GET(PREC_PALETTE_12P4_RED_UDW_MASK, udw) << 6 | 613 REG_FIELD_GET(PREC_PALETTE_12P4_RED_LDW_MASK, ldw); 614 entry->green = REG_FIELD_GET(PREC_PALETTE_12P4_GREEN_UDW_MASK, udw) << 6 | 615 REG_FIELD_GET(PREC_PALETTE_12P4_GREEN_LDW_MASK, ldw); 616 entry->blue = REG_FIELD_GET(PREC_PALETTE_12P4_BLUE_UDW_MASK, udw) << 6 | 617 REG_FIELD_GET(PREC_PALETTE_12P4_BLUE_LDW_MASK, ldw); 618 } 619 620 static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state) 621 { 622 /* 623 * Despite Wa_1406463849, ICL no longer suffers from the SKL 624 * DC5/PSR CSC black screen issue (see skl_color_commit_noarm()). 625 * Possibly due to the extra sticky CSC arming 626 * (see icl_color_post_update()). 627 * 628 * On TGL+ all CSC arming issues have been properly fixed. 629 */ 630 icl_load_csc_matrix(crtc_state); 631 } 632 633 static void skl_color_commit_noarm(const struct intel_crtc_state *crtc_state) 634 { 635 /* 636 * Possibly related to display WA #1184, SKL CSC loses the latched 637 * CSC coeff/offset register values if the CSC registers are disarmed 638 * between DC5 exit and PSR exit. This will cause the plane(s) to 639 * output all black (until CSC_MODE is rearmed and properly latched). 640 * Once PSR exit (and proper register latching) has occurred the 641 * danger is over. Thus when PSR is enabled the CSC coeff/offset 642 * register programming will be peformed from skl_color_commit_arm() 643 * which is called after PSR exit. 644 */ 645 if (!crtc_state->has_psr) 646 ilk_load_csc_matrix(crtc_state); 647 } 648 649 static void ilk_color_commit_noarm(const struct intel_crtc_state *crtc_state) 650 { 651 ilk_load_csc_matrix(crtc_state); 652 } 653 654 static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state) 655 { 656 /* update TRANSCONF GAMMA_MODE */ 657 i9xx_set_pipeconf(crtc_state); 658 } 659 660 static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state) 661 { 662 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 663 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 664 665 /* update TRANSCONF GAMMA_MODE */ 666 ilk_set_pipeconf(crtc_state); 667 668 intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe), 669 crtc_state->csc_mode); 670 } 671 672 static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state) 673 { 674 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 675 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 676 677 intel_de_write(i915, GAMMA_MODE(crtc->pipe), 678 crtc_state->gamma_mode); 679 680 intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe), 681 crtc_state->csc_mode); 682 } 683 684 static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state) 685 { 686 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 687 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 688 enum pipe pipe = crtc->pipe; 689 u32 val = 0; 690 691 if (crtc_state->has_psr) 692 ilk_load_csc_matrix(crtc_state); 693 694 /* 695 * We don't (yet) allow userspace to control the pipe background color, 696 * so force it to black, but apply pipe gamma and CSC appropriately 697 * so that its handling will match how we program our planes. 698 */ 699 if (crtc_state->gamma_enable) 700 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE; 701 if (crtc_state->csc_enable) 702 val |= SKL_BOTTOM_COLOR_CSC_ENABLE; 703 intel_de_write(i915, SKL_BOTTOM_COLOR(pipe), val); 704 705 intel_de_write(i915, GAMMA_MODE(crtc->pipe), 706 crtc_state->gamma_mode); 707 708 intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe), 709 crtc_state->csc_mode); 710 } 711 712 static void icl_color_commit_arm(const struct intel_crtc_state *crtc_state) 713 { 714 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 715 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 716 enum pipe pipe = crtc->pipe; 717 718 /* 719 * We don't (yet) allow userspace to control the pipe background color, 720 * so force it to black. 721 */ 722 intel_de_write(i915, SKL_BOTTOM_COLOR(pipe), 0); 723 724 intel_de_write(i915, GAMMA_MODE(crtc->pipe), 725 crtc_state->gamma_mode); 726 727 intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe), 728 crtc_state->csc_mode); 729 } 730 731 static void icl_color_post_update(const struct intel_crtc_state *crtc_state) 732 { 733 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 734 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 735 736 /* 737 * Despite Wa_1406463849, ICL CSC is no longer disarmed by 738 * coeff/offset register *writes*. Instead, once CSC_MODE 739 * is armed it stays armed, even after it has been latched. 740 * Afterwards the coeff/offset registers become effectively 741 * self-arming. That self-arming must be disabled before the 742 * next icl_color_commit_noarm() tries to write the next set 743 * of coeff/offset registers. Fortunately register *reads* 744 * do still disarm the CSC. Naturally this must not be done 745 * until the previously written CSC registers have actually 746 * been latched. 747 * 748 * TGL+ no longer need this workaround. 749 */ 750 intel_de_read_fw(i915, PIPE_CSC_PREOFF_HI(crtc->pipe)); 751 } 752 753 static struct drm_property_blob * 754 create_linear_lut(struct drm_i915_private *i915, int lut_size) 755 { 756 struct drm_property_blob *blob; 757 struct drm_color_lut *lut; 758 int i; 759 760 blob = drm_property_create_blob(&i915->drm, 761 sizeof(lut[0]) * lut_size, 762 NULL); 763 if (IS_ERR(blob)) 764 return blob; 765 766 lut = blob->data; 767 768 for (i = 0; i < lut_size; i++) { 769 u16 val = 0xffff * i / (lut_size - 1); 770 771 lut[i].red = val; 772 lut[i].green = val; 773 lut[i].blue = val; 774 } 775 776 return blob; 777 } 778 779 static u16 lut_limited_range(unsigned int value) 780 { 781 unsigned int min = 16 << 8; 782 unsigned int max = 235 << 8; 783 784 return value * (max - min) / 0xffff + min; 785 } 786 787 static struct drm_property_blob * 788 create_resized_lut(struct drm_i915_private *i915, 789 const struct drm_property_blob *blob_in, int lut_out_size, 790 bool limited_color_range) 791 { 792 int i, lut_in_size = drm_color_lut_size(blob_in); 793 struct drm_property_blob *blob_out; 794 const struct drm_color_lut *lut_in; 795 struct drm_color_lut *lut_out; 796 797 blob_out = drm_property_create_blob(&i915->drm, 798 sizeof(lut_out[0]) * lut_out_size, 799 NULL); 800 if (IS_ERR(blob_out)) 801 return blob_out; 802 803 lut_in = blob_in->data; 804 lut_out = blob_out->data; 805 806 for (i = 0; i < lut_out_size; i++) { 807 const struct drm_color_lut *entry = 808 &lut_in[i * (lut_in_size - 1) / (lut_out_size - 1)]; 809 810 if (limited_color_range) { 811 lut_out[i].red = lut_limited_range(entry->red); 812 lut_out[i].green = lut_limited_range(entry->green); 813 lut_out[i].blue = lut_limited_range(entry->blue); 814 } else { 815 lut_out[i] = *entry; 816 } 817 } 818 819 return blob_out; 820 } 821 822 static void i9xx_load_lut_8(struct intel_crtc *crtc, 823 const struct drm_property_blob *blob) 824 { 825 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 826 const struct drm_color_lut *lut; 827 enum pipe pipe = crtc->pipe; 828 int i; 829 830 if (!blob) 831 return; 832 833 lut = blob->data; 834 835 for (i = 0; i < 256; i++) 836 intel_de_write_fw(dev_priv, PALETTE(pipe, i), 837 i9xx_lut_8(&lut[i])); 838 } 839 840 static void i9xx_load_lut_10(struct intel_crtc *crtc, 841 const struct drm_property_blob *blob) 842 { 843 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 844 const struct drm_color_lut *lut = blob->data; 845 int i, lut_size = drm_color_lut_size(blob); 846 enum pipe pipe = crtc->pipe; 847 848 for (i = 0; i < lut_size - 1; i++) { 849 intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0), 850 i9xx_lut_10_ldw(&lut[i])); 851 intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1), 852 i9xx_lut_10_udw(&lut[i])); 853 } 854 } 855 856 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state) 857 { 858 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 859 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; 860 861 switch (crtc_state->gamma_mode) { 862 case GAMMA_MODE_MODE_8BIT: 863 i9xx_load_lut_8(crtc, post_csc_lut); 864 break; 865 case GAMMA_MODE_MODE_10BIT: 866 i9xx_load_lut_10(crtc, post_csc_lut); 867 break; 868 default: 869 MISSING_CASE(crtc_state->gamma_mode); 870 break; 871 } 872 } 873 874 static void i965_load_lut_10p6(struct intel_crtc *crtc, 875 const struct drm_property_blob *blob) 876 { 877 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 878 const struct drm_color_lut *lut = blob->data; 879 int i, lut_size = drm_color_lut_size(blob); 880 enum pipe pipe = crtc->pipe; 881 882 for (i = 0; i < lut_size - 1; i++) { 883 intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0), 884 i965_lut_10p6_ldw(&lut[i])); 885 intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1), 886 i965_lut_10p6_udw(&lut[i])); 887 } 888 889 intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); 890 intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); 891 intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); 892 } 893 894 static void i965_load_luts(const struct intel_crtc_state *crtc_state) 895 { 896 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 897 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; 898 899 switch (crtc_state->gamma_mode) { 900 case GAMMA_MODE_MODE_8BIT: 901 i9xx_load_lut_8(crtc, post_csc_lut); 902 break; 903 case GAMMA_MODE_MODE_10BIT: 904 i965_load_lut_10p6(crtc, post_csc_lut); 905 break; 906 default: 907 MISSING_CASE(crtc_state->gamma_mode); 908 break; 909 } 910 } 911 912 static void ilk_lut_write(const struct intel_crtc_state *crtc_state, 913 i915_reg_t reg, u32 val) 914 { 915 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 916 917 if (crtc_state->dsb) 918 intel_dsb_reg_write(crtc_state->dsb, reg, val); 919 else 920 intel_de_write_fw(i915, reg, val); 921 } 922 923 static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state, 924 const struct drm_property_blob *blob) 925 { 926 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 927 const struct drm_color_lut *lut; 928 enum pipe pipe = crtc->pipe; 929 int i; 930 931 if (!blob) 932 return; 933 934 lut = blob->data; 935 936 for (i = 0; i < 256; i++) 937 ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), 938 i9xx_lut_8(&lut[i])); 939 } 940 941 static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state, 942 const struct drm_property_blob *blob) 943 { 944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 945 const struct drm_color_lut *lut = blob->data; 946 int i, lut_size = drm_color_lut_size(blob); 947 enum pipe pipe = crtc->pipe; 948 949 for (i = 0; i < lut_size; i++) 950 ilk_lut_write(crtc_state, PREC_PALETTE(pipe, i), 951 ilk_lut_10(&lut[i])); 952 } 953 954 static void ilk_load_luts(const struct intel_crtc_state *crtc_state) 955 { 956 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; 957 const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut; 958 const struct drm_property_blob *blob = post_csc_lut ?: pre_csc_lut; 959 960 switch (crtc_state->gamma_mode) { 961 case GAMMA_MODE_MODE_8BIT: 962 ilk_load_lut_8(crtc_state, blob); 963 break; 964 case GAMMA_MODE_MODE_10BIT: 965 ilk_load_lut_10(crtc_state, blob); 966 break; 967 default: 968 MISSING_CASE(crtc_state->gamma_mode); 969 break; 970 } 971 } 972 973 static int ivb_lut_10_size(u32 prec_index) 974 { 975 if (prec_index & PAL_PREC_SPLIT_MODE) 976 return 512; 977 else 978 return 1024; 979 } 980 981 /* 982 * IVB/HSW Bspec / PAL_PREC_INDEX: 983 * "Restriction : Index auto increment mode is not 984 * supported and must not be enabled." 985 */ 986 static void ivb_load_lut_10(const struct intel_crtc_state *crtc_state, 987 const struct drm_property_blob *blob, 988 u32 prec_index) 989 { 990 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 991 const struct drm_color_lut *lut = blob->data; 992 int i, lut_size = drm_color_lut_size(blob); 993 enum pipe pipe = crtc->pipe; 994 995 for (i = 0; i < lut_size; i++) { 996 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), 997 prec_index + i); 998 ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe), 999 ilk_lut_10(&lut[i])); 1000 } 1001 1002 /* 1003 * Reset the index, otherwise it prevents the legacy palette to be 1004 * written properly. 1005 */ 1006 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), 1007 PAL_PREC_INDEX_VALUE(0)); 1008 } 1009 1010 /* On BDW+ the index auto increment mode actually works */ 1011 static void bdw_load_lut_10(const struct intel_crtc_state *crtc_state, 1012 const struct drm_property_blob *blob, 1013 u32 prec_index) 1014 { 1015 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1016 const struct drm_color_lut *lut = blob->data; 1017 int i, lut_size = drm_color_lut_size(blob); 1018 enum pipe pipe = crtc->pipe; 1019 1020 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), 1021 prec_index); 1022 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), 1023 PAL_PREC_AUTO_INCREMENT | 1024 prec_index); 1025 1026 for (i = 0; i < lut_size; i++) 1027 ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe), 1028 ilk_lut_10(&lut[i])); 1029 1030 /* 1031 * Reset the index, otherwise it prevents the legacy palette to be 1032 * written properly. 1033 */ 1034 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), 1035 PAL_PREC_INDEX_VALUE(0)); 1036 } 1037 1038 static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state) 1039 { 1040 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1041 enum pipe pipe = crtc->pipe; 1042 1043 /* Program the max register to clamp values > 1.0. */ 1044 ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16); 1045 ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16); 1046 ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16); 1047 } 1048 1049 static void glk_load_lut_ext2_max(const struct intel_crtc_state *crtc_state) 1050 { 1051 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1052 enum pipe pipe = crtc->pipe; 1053 1054 /* Program the max register to clamp values > 1.0. */ 1055 ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16); 1056 ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16); 1057 ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16); 1058 } 1059 1060 static void ivb_load_luts(const struct intel_crtc_state *crtc_state) 1061 { 1062 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; 1063 const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut; 1064 const struct drm_property_blob *blob = post_csc_lut ?: pre_csc_lut; 1065 1066 switch (crtc_state->gamma_mode) { 1067 case GAMMA_MODE_MODE_8BIT: 1068 ilk_load_lut_8(crtc_state, blob); 1069 break; 1070 case GAMMA_MODE_MODE_SPLIT: 1071 ivb_load_lut_10(crtc_state, pre_csc_lut, PAL_PREC_SPLIT_MODE | 1072 PAL_PREC_INDEX_VALUE(0)); 1073 ivb_load_lut_ext_max(crtc_state); 1074 ivb_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_SPLIT_MODE | 1075 PAL_PREC_INDEX_VALUE(512)); 1076 break; 1077 case GAMMA_MODE_MODE_10BIT: 1078 ivb_load_lut_10(crtc_state, blob, 1079 PAL_PREC_INDEX_VALUE(0)); 1080 ivb_load_lut_ext_max(crtc_state); 1081 break; 1082 default: 1083 MISSING_CASE(crtc_state->gamma_mode); 1084 break; 1085 } 1086 } 1087 1088 static void bdw_load_luts(const struct intel_crtc_state *crtc_state) 1089 { 1090 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; 1091 const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut; 1092 const struct drm_property_blob *blob = post_csc_lut ?: pre_csc_lut; 1093 1094 switch (crtc_state->gamma_mode) { 1095 case GAMMA_MODE_MODE_8BIT: 1096 ilk_load_lut_8(crtc_state, blob); 1097 break; 1098 case GAMMA_MODE_MODE_SPLIT: 1099 bdw_load_lut_10(crtc_state, pre_csc_lut, PAL_PREC_SPLIT_MODE | 1100 PAL_PREC_INDEX_VALUE(0)); 1101 ivb_load_lut_ext_max(crtc_state); 1102 bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_SPLIT_MODE | 1103 PAL_PREC_INDEX_VALUE(512)); 1104 break; 1105 case GAMMA_MODE_MODE_10BIT: 1106 bdw_load_lut_10(crtc_state, blob, 1107 PAL_PREC_INDEX_VALUE(0)); 1108 ivb_load_lut_ext_max(crtc_state); 1109 break; 1110 default: 1111 MISSING_CASE(crtc_state->gamma_mode); 1112 break; 1113 } 1114 } 1115 1116 static int glk_degamma_lut_size(struct drm_i915_private *i915) 1117 { 1118 if (DISPLAY_VER(i915) >= 13) 1119 return 131; 1120 else 1121 return 35; 1122 } 1123 1124 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state, 1125 const struct drm_property_blob *blob) 1126 { 1127 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1128 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1129 const struct drm_color_lut *lut = blob->data; 1130 int i, lut_size = drm_color_lut_size(blob); 1131 enum pipe pipe = crtc->pipe; 1132 1133 /* 1134 * When setting the auto-increment bit, the hardware seems to 1135 * ignore the index bits, so we need to reset it to index 0 1136 * separately. 1137 */ 1138 ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe), 1139 PRE_CSC_GAMC_INDEX_VALUE(0)); 1140 ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe), 1141 PRE_CSC_GAMC_AUTO_INCREMENT | 1142 PRE_CSC_GAMC_INDEX_VALUE(0)); 1143 1144 for (i = 0; i < lut_size; i++) { 1145 /* 1146 * First lut_size entries represent range from 0 to 1.0 1147 * 3 additional lut entries will represent extended range 1148 * inputs 3.0 and 7.0 respectively, currently clamped 1149 * at 1.0. Since the precision is 16bit, the user 1150 * value can be directly filled to register. 1151 * The pipe degamma table in GLK+ onwards doesn't 1152 * support different values per channel, so this just 1153 * programs green value which will be equal to Red and 1154 * Blue into the lut registers. 1155 * ToDo: Extend to max 7.0. Enable 32 bit input value 1156 * as compared to just 16 to achieve this. 1157 */ 1158 ilk_lut_write(crtc_state, PRE_CSC_GAMC_DATA(pipe), 1159 lut[i].green); 1160 } 1161 1162 /* Clamp values > 1.0. */ 1163 while (i++ < glk_degamma_lut_size(i915)) 1164 ilk_lut_write(crtc_state, PRE_CSC_GAMC_DATA(pipe), 1 << 16); 1165 1166 ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe), 0); 1167 } 1168 1169 static void glk_load_luts(const struct intel_crtc_state *crtc_state) 1170 { 1171 const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut; 1172 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; 1173 1174 if (pre_csc_lut) 1175 glk_load_degamma_lut(crtc_state, pre_csc_lut); 1176 1177 switch (crtc_state->gamma_mode) { 1178 case GAMMA_MODE_MODE_8BIT: 1179 ilk_load_lut_8(crtc_state, post_csc_lut); 1180 break; 1181 case GAMMA_MODE_MODE_10BIT: 1182 bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_INDEX_VALUE(0)); 1183 ivb_load_lut_ext_max(crtc_state); 1184 glk_load_lut_ext2_max(crtc_state); 1185 break; 1186 default: 1187 MISSING_CASE(crtc_state->gamma_mode); 1188 break; 1189 } 1190 } 1191 1192 static void 1193 ivb_load_lut_max(const struct intel_crtc_state *crtc_state, 1194 const struct drm_color_lut *color) 1195 { 1196 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1197 enum pipe pipe = crtc->pipe; 1198 1199 /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */ 1200 ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red); 1201 ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green); 1202 ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue); 1203 } 1204 1205 static void 1206 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) 1207 { 1208 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1209 const struct drm_property_blob *blob = crtc_state->post_csc_lut; 1210 const struct drm_color_lut *lut = blob->data; 1211 enum pipe pipe = crtc->pipe; 1212 int i; 1213 1214 /* 1215 * Program Super Fine segment (let's call it seg1)... 1216 * 1217 * Super Fine segment's step is 1/(8 * 128 * 256) and it has 1218 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256), 1219 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256). 1220 */ 1221 ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), 1222 PAL_PREC_MULTI_SEG_INDEX_VALUE(0)); 1223 ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), 1224 PAL_PREC_AUTO_INCREMENT | 1225 PAL_PREC_MULTI_SEG_INDEX_VALUE(0)); 1226 1227 for (i = 0; i < 9; i++) { 1228 const struct drm_color_lut *entry = &lut[i]; 1229 1230 ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), 1231 ilk_lut_12p4_ldw(entry)); 1232 ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), 1233 ilk_lut_12p4_udw(entry)); 1234 } 1235 1236 ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), 1237 PAL_PREC_MULTI_SEG_INDEX_VALUE(0)); 1238 } 1239 1240 static void 1241 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) 1242 { 1243 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1244 const struct drm_property_blob *blob = crtc_state->post_csc_lut; 1245 const struct drm_color_lut *lut = blob->data; 1246 const struct drm_color_lut *entry; 1247 enum pipe pipe = crtc->pipe; 1248 int i; 1249 1250 /* 1251 * Program Fine segment (let's call it seg2)... 1252 * 1253 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256) 1254 * ... 256/(128 * 256). So in order to program fine segment of LUT we 1255 * need to pick every 8th entry in the LUT, and program 256 indexes. 1256 * 1257 * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1], 1258 * seg2[0] being unused by the hardware. 1259 */ 1260 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), 1261 PAL_PREC_INDEX_VALUE(0)); 1262 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), 1263 PAL_PREC_AUTO_INCREMENT | 1264 PAL_PREC_INDEX_VALUE(0)); 1265 1266 for (i = 1; i < 257; i++) { 1267 entry = &lut[i * 8]; 1268 1269 ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe), 1270 ilk_lut_12p4_ldw(entry)); 1271 ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe), 1272 ilk_lut_12p4_udw(entry)); 1273 } 1274 1275 /* 1276 * Program Coarse segment (let's call it seg3)... 1277 * 1278 * Coarse segment starts from index 0 and it's step is 1/256 ie 0, 1279 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT 1280 * above, we need to pick every (8 * 128)th entry in LUT, and 1281 * program 256 of those. 1282 * 1283 * Spec is not very clear about if entries seg3[0] and seg3[1] are 1284 * being used or not, but we still need to program these to advance 1285 * the index. 1286 */ 1287 for (i = 0; i < 256; i++) { 1288 entry = &lut[i * 8 * 128]; 1289 1290 ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe), 1291 ilk_lut_12p4_ldw(entry)); 1292 ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe), 1293 ilk_lut_12p4_udw(entry)); 1294 } 1295 1296 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe), 1297 PAL_PREC_INDEX_VALUE(0)); 1298 1299 /* The last entry in the LUT is to be programmed in GCMAX */ 1300 entry = &lut[256 * 8 * 128]; 1301 ivb_load_lut_max(crtc_state, entry); 1302 } 1303 1304 static void icl_load_luts(const struct intel_crtc_state *crtc_state) 1305 { 1306 const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut; 1307 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; 1308 1309 if (pre_csc_lut) 1310 glk_load_degamma_lut(crtc_state, pre_csc_lut); 1311 1312 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 1313 case GAMMA_MODE_MODE_8BIT: 1314 ilk_load_lut_8(crtc_state, post_csc_lut); 1315 break; 1316 case GAMMA_MODE_MODE_12BIT_MULTI_SEG: 1317 icl_program_gamma_superfine_segment(crtc_state); 1318 icl_program_gamma_multi_segment(crtc_state); 1319 ivb_load_lut_ext_max(crtc_state); 1320 glk_load_lut_ext2_max(crtc_state); 1321 break; 1322 case GAMMA_MODE_MODE_10BIT: 1323 bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_INDEX_VALUE(0)); 1324 ivb_load_lut_ext_max(crtc_state); 1325 glk_load_lut_ext2_max(crtc_state); 1326 break; 1327 default: 1328 MISSING_CASE(crtc_state->gamma_mode); 1329 break; 1330 } 1331 1332 if (crtc_state->dsb) { 1333 intel_dsb_finish(crtc_state->dsb); 1334 intel_dsb_commit(crtc_state->dsb, false); 1335 intel_dsb_wait(crtc_state->dsb); 1336 } 1337 } 1338 1339 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) 1340 { 1341 return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, drm_color_lut_extract(color->green, 14)) | 1342 REG_FIELD_PREP(CGM_PIPE_DEGAMMA_BLUE_LDW_MASK, drm_color_lut_extract(color->blue, 14)); 1343 } 1344 1345 static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color) 1346 { 1347 return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_RED_UDW_MASK, drm_color_lut_extract(color->red, 14)); 1348 } 1349 1350 static void chv_cgm_degamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 1351 { 1352 entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, ldw), 14); 1353 entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_BLUE_LDW_MASK, ldw), 14); 1354 entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_RED_UDW_MASK, udw), 14); 1355 } 1356 1357 static void chv_load_cgm_degamma(struct intel_crtc *crtc, 1358 const struct drm_property_blob *blob) 1359 { 1360 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1361 const struct drm_color_lut *lut = blob->data; 1362 int i, lut_size = drm_color_lut_size(blob); 1363 enum pipe pipe = crtc->pipe; 1364 1365 for (i = 0; i < lut_size; i++) { 1366 intel_de_write_fw(i915, CGM_PIPE_DEGAMMA(pipe, i, 0), 1367 chv_cgm_degamma_ldw(&lut[i])); 1368 intel_de_write_fw(i915, CGM_PIPE_DEGAMMA(pipe, i, 1), 1369 chv_cgm_degamma_udw(&lut[i])); 1370 } 1371 } 1372 1373 static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color) 1374 { 1375 return REG_FIELD_PREP(CGM_PIPE_GAMMA_GREEN_LDW_MASK, drm_color_lut_extract(color->green, 10)) | 1376 REG_FIELD_PREP(CGM_PIPE_GAMMA_BLUE_LDW_MASK, drm_color_lut_extract(color->blue, 10)); 1377 } 1378 1379 static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color) 1380 { 1381 return REG_FIELD_PREP(CGM_PIPE_GAMMA_RED_UDW_MASK, drm_color_lut_extract(color->red, 10)); 1382 } 1383 1384 static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) 1385 { 1386 entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_LDW_MASK, ldw), 10); 1387 entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_LDW_MASK, ldw), 10); 1388 entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_UDW_MASK, udw), 10); 1389 } 1390 1391 static void chv_load_cgm_gamma(struct intel_crtc *crtc, 1392 const struct drm_property_blob *blob) 1393 { 1394 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1395 const struct drm_color_lut *lut = blob->data; 1396 int i, lut_size = drm_color_lut_size(blob); 1397 enum pipe pipe = crtc->pipe; 1398 1399 for (i = 0; i < lut_size; i++) { 1400 intel_de_write_fw(i915, CGM_PIPE_GAMMA(pipe, i, 0), 1401 chv_cgm_gamma_ldw(&lut[i])); 1402 intel_de_write_fw(i915, CGM_PIPE_GAMMA(pipe, i, 1), 1403 chv_cgm_gamma_udw(&lut[i])); 1404 } 1405 } 1406 1407 static void chv_load_luts(const struct intel_crtc_state *crtc_state) 1408 { 1409 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1410 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1411 const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut; 1412 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut; 1413 const struct drm_property_blob *ctm = crtc_state->hw.ctm; 1414 1415 if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) 1416 chv_load_cgm_csc(crtc, ctm); 1417 1418 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA) 1419 chv_load_cgm_degamma(crtc, pre_csc_lut); 1420 1421 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 1422 chv_load_cgm_gamma(crtc, post_csc_lut); 1423 else 1424 i965_load_luts(crtc_state); 1425 1426 intel_de_write_fw(i915, CGM_PIPE_MODE(crtc->pipe), 1427 crtc_state->cgm_mode); 1428 } 1429 1430 void intel_color_load_luts(const struct intel_crtc_state *crtc_state) 1431 { 1432 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1433 1434 i915->display.funcs.color->load_luts(crtc_state); 1435 } 1436 1437 void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state) 1438 { 1439 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1440 1441 if (i915->display.funcs.color->color_commit_noarm) 1442 i915->display.funcs.color->color_commit_noarm(crtc_state); 1443 } 1444 1445 void intel_color_commit_arm(const struct intel_crtc_state *crtc_state) 1446 { 1447 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1448 1449 i915->display.funcs.color->color_commit_arm(crtc_state); 1450 } 1451 1452 void intel_color_post_update(const struct intel_crtc_state *crtc_state) 1453 { 1454 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1455 1456 if (i915->display.funcs.color->color_post_update) 1457 i915->display.funcs.color->color_post_update(crtc_state); 1458 } 1459 1460 void intel_color_prepare_commit(struct intel_crtc_state *crtc_state) 1461 { 1462 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1463 1464 /* FIXME DSB has issues loading LUTs, disable it for now */ 1465 return; 1466 1467 if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) 1468 return; 1469 1470 crtc_state->dsb = intel_dsb_prepare(crtc, 1024); 1471 } 1472 1473 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state) 1474 { 1475 if (!crtc_state->dsb) 1476 return; 1477 1478 intel_dsb_cleanup(crtc_state->dsb); 1479 crtc_state->dsb = NULL; 1480 } 1481 1482 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1483 { 1484 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1485 struct intel_atomic_state *state = 1486 to_intel_atomic_state(new_crtc_state->uapi.state); 1487 const struct intel_crtc_state *old_crtc_state = 1488 intel_atomic_get_old_crtc_state(state, crtc); 1489 1490 return !old_crtc_state->post_csc_lut && 1491 !old_crtc_state->pre_csc_lut; 1492 } 1493 1494 static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) 1495 { 1496 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1497 struct intel_atomic_state *state = 1498 to_intel_atomic_state(new_crtc_state->uapi.state); 1499 const struct intel_crtc_state *old_crtc_state = 1500 intel_atomic_get_old_crtc_state(state, crtc); 1501 1502 /* 1503 * CGM_PIPE_MODE is itself single buffered. We'd have to 1504 * somehow split it out from chv_load_luts() if we wanted 1505 * the ability to preload the CGM LUTs/CSC without tearing. 1506 */ 1507 if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode) 1508 return false; 1509 1510 return !old_crtc_state->post_csc_lut; 1511 } 1512 1513 int intel_color_check(struct intel_crtc_state *crtc_state) 1514 { 1515 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1516 1517 return i915->display.funcs.color->color_check(crtc_state); 1518 } 1519 1520 void intel_color_get_config(struct intel_crtc_state *crtc_state) 1521 { 1522 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1523 1524 i915->display.funcs.color->read_luts(crtc_state); 1525 } 1526 1527 bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state, 1528 const struct drm_property_blob *blob1, 1529 const struct drm_property_blob *blob2, 1530 bool is_pre_csc_lut) 1531 { 1532 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1533 1534 /* 1535 * FIXME c8_planes readout missing thus 1536 * .read_luts() doesn't read out post_csc_lut. 1537 */ 1538 if (!is_pre_csc_lut && crtc_state->c8_planes) 1539 return true; 1540 1541 return i915->display.funcs.color->lut_equal(crtc_state, blob1, blob2, 1542 is_pre_csc_lut); 1543 } 1544 1545 static bool need_plane_update(struct intel_plane *plane, 1546 const struct intel_crtc_state *crtc_state) 1547 { 1548 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1549 1550 /* 1551 * On pre-SKL the pipe gamma enable and pipe csc enable for 1552 * the pipe bottom color are configured via the primary plane. 1553 * We have to reconfigure that even if the plane is inactive. 1554 */ 1555 return crtc_state->active_planes & BIT(plane->id) || 1556 (DISPLAY_VER(i915) < 9 && 1557 plane->id == PLANE_PRIMARY); 1558 } 1559 1560 static int 1561 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state) 1562 { 1563 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1564 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1565 struct intel_atomic_state *state = 1566 to_intel_atomic_state(new_crtc_state->uapi.state); 1567 const struct intel_crtc_state *old_crtc_state = 1568 intel_atomic_get_old_crtc_state(state, crtc); 1569 struct intel_plane *plane; 1570 1571 if (!new_crtc_state->hw.active || 1572 intel_crtc_needs_modeset(new_crtc_state)) 1573 return 0; 1574 1575 if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable && 1576 new_crtc_state->csc_enable == old_crtc_state->csc_enable) 1577 return 0; 1578 1579 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 1580 struct intel_plane_state *plane_state; 1581 1582 if (!need_plane_update(plane, new_crtc_state)) 1583 continue; 1584 1585 plane_state = intel_atomic_get_plane_state(state, plane); 1586 if (IS_ERR(plane_state)) 1587 return PTR_ERR(plane_state); 1588 1589 new_crtc_state->update_planes |= BIT(plane->id); 1590 new_crtc_state->async_flip_planes = 0; 1591 new_crtc_state->do_async_flip = false; 1592 1593 /* plane control register changes blocked by CxSR */ 1594 if (HAS_GMCH(i915)) 1595 new_crtc_state->disable_cxsr = true; 1596 } 1597 1598 return 0; 1599 } 1600 1601 static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state) 1602 { 1603 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1604 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1605 1606 if (lut_is_legacy(gamma_lut)) 1607 return 0; 1608 1609 return INTEL_INFO(i915)->display.color.gamma_lut_tests; 1610 } 1611 1612 static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state) 1613 { 1614 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1615 1616 return INTEL_INFO(i915)->display.color.degamma_lut_tests; 1617 } 1618 1619 static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state) 1620 { 1621 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1622 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1623 1624 if (lut_is_legacy(gamma_lut)) 1625 return LEGACY_LUT_LENGTH; 1626 1627 return INTEL_INFO(i915)->display.color.gamma_lut_size; 1628 } 1629 1630 static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state) 1631 { 1632 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1633 1634 return INTEL_INFO(i915)->display.color.degamma_lut_size; 1635 } 1636 1637 static int check_lut_size(const struct drm_property_blob *lut, int expected) 1638 { 1639 int len; 1640 1641 if (!lut) 1642 return 0; 1643 1644 len = drm_color_lut_size(lut); 1645 if (len != expected) { 1646 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n", 1647 len, expected); 1648 return -EINVAL; 1649 } 1650 1651 return 0; 1652 } 1653 1654 static int _check_luts(const struct intel_crtc_state *crtc_state, 1655 u32 degamma_tests, u32 gamma_tests) 1656 { 1657 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1658 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; 1659 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; 1660 int gamma_length, degamma_length; 1661 1662 /* C8 relies on its palette being stored in the legacy LUT */ 1663 if (crtc_state->c8_planes && !lut_is_legacy(crtc_state->hw.gamma_lut)) { 1664 drm_dbg_kms(&i915->drm, 1665 "C8 pixelformat requires the legacy LUT\n"); 1666 return -EINVAL; 1667 } 1668 1669 degamma_length = intel_degamma_lut_size(crtc_state); 1670 gamma_length = intel_gamma_lut_size(crtc_state); 1671 1672 if (check_lut_size(degamma_lut, degamma_length) || 1673 check_lut_size(gamma_lut, gamma_length)) 1674 return -EINVAL; 1675 1676 if (drm_color_lut_check(degamma_lut, degamma_tests) || 1677 drm_color_lut_check(gamma_lut, gamma_tests)) 1678 return -EINVAL; 1679 1680 return 0; 1681 } 1682 1683 static int check_luts(const struct intel_crtc_state *crtc_state) 1684 { 1685 return _check_luts(crtc_state, 1686 intel_degamma_lut_tests(crtc_state), 1687 intel_gamma_lut_tests(crtc_state)); 1688 } 1689 1690 static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state) 1691 { 1692 if (!crtc_state->gamma_enable || 1693 lut_is_legacy(crtc_state->hw.gamma_lut)) 1694 return GAMMA_MODE_MODE_8BIT; 1695 else 1696 return GAMMA_MODE_MODE_10BIT; 1697 } 1698 1699 static int i9xx_lut_10_diff(u16 a, u16 b) 1700 { 1701 return drm_color_lut_extract(a, 10) - 1702 drm_color_lut_extract(b, 10); 1703 } 1704 1705 static int i9xx_check_lut_10(struct drm_i915_private *dev_priv, 1706 const struct drm_property_blob *blob) 1707 { 1708 const struct drm_color_lut *lut = blob->data; 1709 int lut_size = drm_color_lut_size(blob); 1710 const struct drm_color_lut *a = &lut[lut_size - 2]; 1711 const struct drm_color_lut *b = &lut[lut_size - 1]; 1712 1713 if (i9xx_lut_10_diff(b->red, a->red) > 0x7f || 1714 i9xx_lut_10_diff(b->green, a->green) > 0x7f || 1715 i9xx_lut_10_diff(b->blue, a->blue) > 0x7f) { 1716 drm_dbg_kms(&dev_priv->drm, "Last gamma LUT entry exceeds max slope\n"); 1717 return -EINVAL; 1718 } 1719 1720 return 0; 1721 } 1722 1723 void intel_color_assert_luts(const struct intel_crtc_state *crtc_state) 1724 { 1725 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1726 1727 /* make sure {pre,post}_csc_lut were correctly assigned */ 1728 if (DISPLAY_VER(i915) >= 11 || HAS_GMCH(i915)) { 1729 drm_WARN_ON(&i915->drm, 1730 crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut); 1731 drm_WARN_ON(&i915->drm, 1732 crtc_state->post_csc_lut != crtc_state->hw.gamma_lut); 1733 } else if (DISPLAY_VER(i915) == 10) { 1734 drm_WARN_ON(&i915->drm, 1735 crtc_state->post_csc_lut == crtc_state->hw.gamma_lut && 1736 crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut && 1737 crtc_state->pre_csc_lut != i915->display.color.glk_linear_degamma_lut); 1738 drm_WARN_ON(&i915->drm, 1739 !ilk_lut_limited_range(crtc_state) && 1740 crtc_state->post_csc_lut != NULL && 1741 crtc_state->post_csc_lut != crtc_state->hw.gamma_lut); 1742 } else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) { 1743 drm_WARN_ON(&i915->drm, 1744 crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut && 1745 crtc_state->pre_csc_lut != crtc_state->hw.gamma_lut); 1746 drm_WARN_ON(&i915->drm, 1747 !ilk_lut_limited_range(crtc_state) && 1748 crtc_state->post_csc_lut != crtc_state->hw.degamma_lut && 1749 crtc_state->post_csc_lut != crtc_state->hw.gamma_lut); 1750 } 1751 } 1752 1753 static void intel_assign_luts(struct intel_crtc_state *crtc_state) 1754 { 1755 drm_property_replace_blob(&crtc_state->pre_csc_lut, 1756 crtc_state->hw.degamma_lut); 1757 drm_property_replace_blob(&crtc_state->post_csc_lut, 1758 crtc_state->hw.gamma_lut); 1759 } 1760 1761 static int i9xx_color_check(struct intel_crtc_state *crtc_state) 1762 { 1763 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1764 int ret; 1765 1766 ret = check_luts(crtc_state); 1767 if (ret) 1768 return ret; 1769 1770 crtc_state->gamma_enable = 1771 crtc_state->hw.gamma_lut && 1772 !crtc_state->c8_planes; 1773 1774 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); 1775 1776 if (DISPLAY_VER(i915) < 4 && 1777 crtc_state->gamma_mode == GAMMA_MODE_MODE_10BIT) { 1778 ret = i9xx_check_lut_10(i915, crtc_state->hw.gamma_lut); 1779 if (ret) 1780 return ret; 1781 } 1782 1783 ret = intel_color_add_affected_planes(crtc_state); 1784 if (ret) 1785 return ret; 1786 1787 intel_assign_luts(crtc_state); 1788 1789 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1790 1791 return 0; 1792 } 1793 1794 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) 1795 { 1796 u32 cgm_mode = 0; 1797 1798 if (crtc_state->hw.degamma_lut) 1799 cgm_mode |= CGM_PIPE_MODE_DEGAMMA; 1800 if (crtc_state->hw.ctm) 1801 cgm_mode |= CGM_PIPE_MODE_CSC; 1802 if (crtc_state->hw.gamma_lut && 1803 !lut_is_legacy(crtc_state->hw.gamma_lut)) 1804 cgm_mode |= CGM_PIPE_MODE_GAMMA; 1805 1806 return cgm_mode; 1807 } 1808 1809 /* 1810 * CHV color pipeline: 1811 * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma -> 1812 * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10 1813 * 1814 * We always bypass the WGC csc and use the CGM csc 1815 * instead since it has degamma and better precision. 1816 */ 1817 static int chv_color_check(struct intel_crtc_state *crtc_state) 1818 { 1819 int ret; 1820 1821 ret = check_luts(crtc_state); 1822 if (ret) 1823 return ret; 1824 1825 /* 1826 * Pipe gamma will be used only for the legacy LUT. 1827 * Otherwise we bypass it and use the CGM gamma instead. 1828 */ 1829 crtc_state->gamma_enable = 1830 lut_is_legacy(crtc_state->hw.gamma_lut) && 1831 !crtc_state->c8_planes; 1832 1833 crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; 1834 1835 crtc_state->cgm_mode = chv_cgm_mode(crtc_state); 1836 1837 ret = intel_color_add_affected_planes(crtc_state); 1838 if (ret) 1839 return ret; 1840 1841 intel_assign_luts(crtc_state); 1842 1843 crtc_state->preload_luts = chv_can_preload_luts(crtc_state); 1844 1845 return 0; 1846 } 1847 1848 static bool ilk_gamma_enable(const struct intel_crtc_state *crtc_state) 1849 { 1850 return (crtc_state->hw.gamma_lut || 1851 crtc_state->hw.degamma_lut) && 1852 !crtc_state->c8_planes; 1853 } 1854 1855 static bool ilk_csc_enable(const struct intel_crtc_state *crtc_state) 1856 { 1857 return crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1858 ilk_csc_limited_range(crtc_state) || 1859 crtc_state->hw.ctm; 1860 } 1861 1862 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state) 1863 { 1864 if (!crtc_state->gamma_enable || 1865 lut_is_legacy(crtc_state->hw.gamma_lut)) 1866 return GAMMA_MODE_MODE_8BIT; 1867 else 1868 return GAMMA_MODE_MODE_10BIT; 1869 } 1870 1871 static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state) 1872 { 1873 /* 1874 * CSC comes after the LUT in RGB->YCbCr mode. 1875 * RGB->YCbCr needs the limited range offsets added to 1876 * the output. RGB limited range output is handled by 1877 * the hw automagically elsewhere. 1878 */ 1879 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 1880 return CSC_BLACK_SCREEN_OFFSET; 1881 1882 if (crtc_state->hw.degamma_lut) 1883 return CSC_MODE_YUV_TO_RGB; 1884 1885 return CSC_MODE_YUV_TO_RGB | 1886 CSC_POSITION_BEFORE_GAMMA; 1887 } 1888 1889 static int ilk_assign_luts(struct intel_crtc_state *crtc_state) 1890 { 1891 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1892 1893 if (ilk_lut_limited_range(crtc_state)) { 1894 struct drm_property_blob *gamma_lut; 1895 1896 gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, 1897 drm_color_lut_size(crtc_state->hw.gamma_lut), 1898 true); 1899 if (IS_ERR(gamma_lut)) 1900 return PTR_ERR(gamma_lut); 1901 1902 drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut); 1903 1904 drm_property_blob_put(gamma_lut); 1905 1906 drm_property_replace_blob(&crtc_state->pre_csc_lut, crtc_state->hw.degamma_lut); 1907 1908 return 0; 1909 } 1910 1911 if (crtc_state->hw.degamma_lut || 1912 crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) { 1913 drm_property_replace_blob(&crtc_state->pre_csc_lut, 1914 crtc_state->hw.degamma_lut); 1915 drm_property_replace_blob(&crtc_state->post_csc_lut, 1916 crtc_state->hw.gamma_lut); 1917 } else { 1918 drm_property_replace_blob(&crtc_state->pre_csc_lut, 1919 crtc_state->hw.gamma_lut); 1920 drm_property_replace_blob(&crtc_state->post_csc_lut, 1921 NULL); 1922 } 1923 1924 return 0; 1925 } 1926 1927 static int ilk_color_check(struct intel_crtc_state *crtc_state) 1928 { 1929 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1930 int ret; 1931 1932 ret = check_luts(crtc_state); 1933 if (ret) 1934 return ret; 1935 1936 if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) { 1937 drm_dbg_kms(&i915->drm, 1938 "Degamma and gamma together are not possible\n"); 1939 return -EINVAL; 1940 } 1941 1942 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB && 1943 crtc_state->hw.ctm) { 1944 drm_dbg_kms(&i915->drm, 1945 "YCbCr and CTM together are not possible\n"); 1946 return -EINVAL; 1947 } 1948 1949 crtc_state->gamma_enable = ilk_gamma_enable(crtc_state); 1950 1951 crtc_state->csc_enable = ilk_csc_enable(crtc_state); 1952 1953 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); 1954 1955 crtc_state->csc_mode = ilk_csc_mode(crtc_state); 1956 1957 ret = intel_color_add_affected_planes(crtc_state); 1958 if (ret) 1959 return ret; 1960 1961 ret = ilk_assign_luts(crtc_state); 1962 if (ret) 1963 return ret; 1964 1965 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 1966 1967 return 0; 1968 } 1969 1970 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state) 1971 { 1972 if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) 1973 return GAMMA_MODE_MODE_SPLIT; 1974 1975 return ilk_gamma_mode(crtc_state); 1976 } 1977 1978 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state) 1979 { 1980 bool limited_color_range = ilk_csc_limited_range(crtc_state); 1981 1982 /* 1983 * CSC comes after the LUT in degamma, RGB->YCbCr, 1984 * and RGB full->limited range mode. 1985 */ 1986 if (crtc_state->hw.degamma_lut || 1987 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 1988 limited_color_range) 1989 return 0; 1990 1991 return CSC_POSITION_BEFORE_GAMMA; 1992 } 1993 1994 static int ivb_assign_luts(struct intel_crtc_state *crtc_state) 1995 { 1996 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1997 struct drm_property_blob *degamma_lut, *gamma_lut; 1998 1999 if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) 2000 return ilk_assign_luts(crtc_state); 2001 2002 drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024); 2003 drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024); 2004 2005 degamma_lut = create_resized_lut(i915, crtc_state->hw.degamma_lut, 512, 2006 false); 2007 if (IS_ERR(degamma_lut)) 2008 return PTR_ERR(degamma_lut); 2009 2010 gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, 512, 2011 ilk_lut_limited_range(crtc_state)); 2012 if (IS_ERR(gamma_lut)) { 2013 drm_property_blob_put(degamma_lut); 2014 return PTR_ERR(gamma_lut); 2015 } 2016 2017 drm_property_replace_blob(&crtc_state->pre_csc_lut, degamma_lut); 2018 drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut); 2019 2020 drm_property_blob_put(degamma_lut); 2021 drm_property_blob_put(gamma_lut); 2022 2023 return 0; 2024 } 2025 2026 static int ivb_color_check(struct intel_crtc_state *crtc_state) 2027 { 2028 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2029 int ret; 2030 2031 ret = check_luts(crtc_state); 2032 if (ret) 2033 return ret; 2034 2035 if (crtc_state->c8_planes && crtc_state->hw.degamma_lut) { 2036 drm_dbg_kms(&i915->drm, 2037 "C8 pixelformat and degamma together are not possible\n"); 2038 return -EINVAL; 2039 } 2040 2041 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB && 2042 crtc_state->hw.ctm) { 2043 drm_dbg_kms(&i915->drm, 2044 "YCbCr and CTM together are not possible\n"); 2045 return -EINVAL; 2046 } 2047 2048 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB && 2049 crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) { 2050 drm_dbg_kms(&i915->drm, 2051 "YCbCr and degamma+gamma together are not possible\n"); 2052 return -EINVAL; 2053 } 2054 2055 crtc_state->gamma_enable = ilk_gamma_enable(crtc_state); 2056 2057 crtc_state->csc_enable = ilk_csc_enable(crtc_state); 2058 2059 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state); 2060 2061 crtc_state->csc_mode = ivb_csc_mode(crtc_state); 2062 2063 ret = intel_color_add_affected_planes(crtc_state); 2064 if (ret) 2065 return ret; 2066 2067 ret = ivb_assign_luts(crtc_state); 2068 if (ret) 2069 return ret; 2070 2071 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 2072 2073 return 0; 2074 } 2075 2076 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state) 2077 { 2078 if (!crtc_state->gamma_enable || 2079 lut_is_legacy(crtc_state->hw.gamma_lut)) 2080 return GAMMA_MODE_MODE_8BIT; 2081 else 2082 return GAMMA_MODE_MODE_10BIT; 2083 } 2084 2085 static bool glk_use_pre_csc_lut_for_gamma(const struct intel_crtc_state *crtc_state) 2086 { 2087 return crtc_state->hw.gamma_lut && 2088 !crtc_state->c8_planes && 2089 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB; 2090 } 2091 2092 static int glk_assign_luts(struct intel_crtc_state *crtc_state) 2093 { 2094 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2095 2096 if (glk_use_pre_csc_lut_for_gamma(crtc_state)) { 2097 struct drm_property_blob *gamma_lut; 2098 2099 gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, 2100 INTEL_INFO(i915)->display.color.degamma_lut_size, 2101 false); 2102 if (IS_ERR(gamma_lut)) 2103 return PTR_ERR(gamma_lut); 2104 2105 drm_property_replace_blob(&crtc_state->pre_csc_lut, gamma_lut); 2106 drm_property_replace_blob(&crtc_state->post_csc_lut, NULL); 2107 2108 drm_property_blob_put(gamma_lut); 2109 2110 return 0; 2111 } 2112 2113 if (ilk_lut_limited_range(crtc_state)) { 2114 struct drm_property_blob *gamma_lut; 2115 2116 gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, 2117 drm_color_lut_size(crtc_state->hw.gamma_lut), 2118 true); 2119 if (IS_ERR(gamma_lut)) 2120 return PTR_ERR(gamma_lut); 2121 2122 drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut); 2123 2124 drm_property_blob_put(gamma_lut); 2125 } else { 2126 drm_property_replace_blob(&crtc_state->post_csc_lut, crtc_state->hw.gamma_lut); 2127 } 2128 2129 drm_property_replace_blob(&crtc_state->pre_csc_lut, crtc_state->hw.degamma_lut); 2130 2131 /* 2132 * On GLK+ both pipe CSC and degamma LUT are controlled 2133 * by csc_enable. Hence for the cases where the CSC is 2134 * needed but degamma LUT is not we need to load a 2135 * linear degamma LUT. 2136 */ 2137 if (crtc_state->csc_enable && !crtc_state->pre_csc_lut) 2138 drm_property_replace_blob(&crtc_state->pre_csc_lut, 2139 i915->display.color.glk_linear_degamma_lut); 2140 2141 return 0; 2142 } 2143 2144 static int glk_check_luts(const struct intel_crtc_state *crtc_state) 2145 { 2146 u32 degamma_tests = intel_degamma_lut_tests(crtc_state); 2147 u32 gamma_tests = intel_gamma_lut_tests(crtc_state); 2148 2149 if (glk_use_pre_csc_lut_for_gamma(crtc_state)) 2150 gamma_tests |= degamma_tests; 2151 2152 return _check_luts(crtc_state, degamma_tests, gamma_tests); 2153 } 2154 2155 static int glk_color_check(struct intel_crtc_state *crtc_state) 2156 { 2157 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2158 int ret; 2159 2160 ret = glk_check_luts(crtc_state); 2161 if (ret) 2162 return ret; 2163 2164 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB && 2165 crtc_state->hw.ctm) { 2166 drm_dbg_kms(&i915->drm, 2167 "YCbCr and CTM together are not possible\n"); 2168 return -EINVAL; 2169 } 2170 2171 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB && 2172 crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) { 2173 drm_dbg_kms(&i915->drm, 2174 "YCbCr and degamma+gamma together are not possible\n"); 2175 return -EINVAL; 2176 } 2177 2178 crtc_state->gamma_enable = 2179 !glk_use_pre_csc_lut_for_gamma(crtc_state) && 2180 crtc_state->hw.gamma_lut && 2181 !crtc_state->c8_planes; 2182 2183 /* On GLK+ degamma LUT is controlled by csc_enable */ 2184 crtc_state->csc_enable = 2185 glk_use_pre_csc_lut_for_gamma(crtc_state) || 2186 crtc_state->hw.degamma_lut || 2187 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 2188 crtc_state->hw.ctm || ilk_csc_limited_range(crtc_state); 2189 2190 crtc_state->gamma_mode = glk_gamma_mode(crtc_state); 2191 2192 crtc_state->csc_mode = 0; 2193 2194 ret = intel_color_add_affected_planes(crtc_state); 2195 if (ret) 2196 return ret; 2197 2198 ret = glk_assign_luts(crtc_state); 2199 if (ret) 2200 return ret; 2201 2202 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 2203 2204 return 0; 2205 } 2206 2207 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) 2208 { 2209 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2210 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2211 u32 gamma_mode = 0; 2212 2213 if (crtc_state->hw.degamma_lut) 2214 gamma_mode |= PRE_CSC_GAMMA_ENABLE; 2215 2216 if (crtc_state->hw.gamma_lut && 2217 !crtc_state->c8_planes) 2218 gamma_mode |= POST_CSC_GAMMA_ENABLE; 2219 2220 if (!crtc_state->hw.gamma_lut || 2221 lut_is_legacy(crtc_state->hw.gamma_lut)) 2222 gamma_mode |= GAMMA_MODE_MODE_8BIT; 2223 /* 2224 * Enable 10bit gamma for D13 2225 * ToDo: Extend to Logarithmic Gamma once the new UAPI 2226 * is accepted and implemented by a userspace consumer 2227 */ 2228 else if (DISPLAY_VER(i915) >= 13) 2229 gamma_mode |= GAMMA_MODE_MODE_10BIT; 2230 else 2231 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEG; 2232 2233 return gamma_mode; 2234 } 2235 2236 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state) 2237 { 2238 u32 csc_mode = 0; 2239 2240 if (crtc_state->hw.ctm) 2241 csc_mode |= ICL_CSC_ENABLE; 2242 2243 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || 2244 crtc_state->limited_color_range) 2245 csc_mode |= ICL_OUTPUT_CSC_ENABLE; 2246 2247 return csc_mode; 2248 } 2249 2250 static int icl_color_check(struct intel_crtc_state *crtc_state) 2251 { 2252 int ret; 2253 2254 ret = check_luts(crtc_state); 2255 if (ret) 2256 return ret; 2257 2258 crtc_state->gamma_mode = icl_gamma_mode(crtc_state); 2259 2260 crtc_state->csc_mode = icl_csc_mode(crtc_state); 2261 2262 intel_assign_luts(crtc_state); 2263 2264 crtc_state->preload_luts = intel_can_preload_luts(crtc_state); 2265 2266 return 0; 2267 } 2268 2269 static int i9xx_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2270 { 2271 if (!crtc_state->gamma_enable && !crtc_state->c8_planes) 2272 return 0; 2273 2274 switch (crtc_state->gamma_mode) { 2275 case GAMMA_MODE_MODE_8BIT: 2276 return 8; 2277 case GAMMA_MODE_MODE_10BIT: 2278 return 10; 2279 default: 2280 MISSING_CASE(crtc_state->gamma_mode); 2281 return 0; 2282 } 2283 } 2284 2285 static int i9xx_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2286 { 2287 return 0; 2288 } 2289 2290 static int i965_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2291 { 2292 if (!crtc_state->gamma_enable && !crtc_state->c8_planes) 2293 return 0; 2294 2295 switch (crtc_state->gamma_mode) { 2296 case GAMMA_MODE_MODE_8BIT: 2297 return 8; 2298 case GAMMA_MODE_MODE_10BIT: 2299 return 16; 2300 default: 2301 MISSING_CASE(crtc_state->gamma_mode); 2302 return 0; 2303 } 2304 } 2305 2306 static int ilk_gamma_mode_precision(u32 gamma_mode) 2307 { 2308 switch (gamma_mode) { 2309 case GAMMA_MODE_MODE_8BIT: 2310 return 8; 2311 case GAMMA_MODE_MODE_10BIT: 2312 return 10; 2313 default: 2314 MISSING_CASE(gamma_mode); 2315 return 0; 2316 } 2317 } 2318 2319 static bool ilk_has_post_csc_lut(const struct intel_crtc_state *crtc_state) 2320 { 2321 if (crtc_state->c8_planes) 2322 return true; 2323 2324 return crtc_state->gamma_enable && 2325 (crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) != 0; 2326 } 2327 2328 static bool ilk_has_pre_csc_lut(const struct intel_crtc_state *crtc_state) 2329 { 2330 return crtc_state->gamma_enable && 2331 (crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0; 2332 } 2333 2334 static int ilk_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2335 { 2336 if (!ilk_has_post_csc_lut(crtc_state)) 2337 return 0; 2338 2339 return ilk_gamma_mode_precision(crtc_state->gamma_mode); 2340 } 2341 2342 static int ilk_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2343 { 2344 if (!ilk_has_pre_csc_lut(crtc_state)) 2345 return 0; 2346 2347 return ilk_gamma_mode_precision(crtc_state->gamma_mode); 2348 } 2349 2350 static int ivb_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2351 { 2352 if (crtc_state->gamma_enable && 2353 crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) 2354 return 10; 2355 2356 return ilk_post_csc_lut_precision(crtc_state); 2357 } 2358 2359 static int ivb_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2360 { 2361 if (crtc_state->gamma_enable && 2362 crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) 2363 return 10; 2364 2365 return ilk_pre_csc_lut_precision(crtc_state); 2366 } 2367 2368 static int chv_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2369 { 2370 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 2371 return 10; 2372 2373 return i965_post_csc_lut_precision(crtc_state); 2374 } 2375 2376 static int chv_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2377 { 2378 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA) 2379 return 14; 2380 2381 return 0; 2382 } 2383 2384 static int glk_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2385 { 2386 if (!crtc_state->gamma_enable && !crtc_state->c8_planes) 2387 return 0; 2388 2389 return ilk_gamma_mode_precision(crtc_state->gamma_mode); 2390 } 2391 2392 static int glk_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2393 { 2394 if (!crtc_state->csc_enable) 2395 return 0; 2396 2397 return 16; 2398 } 2399 2400 static bool icl_has_post_csc_lut(const struct intel_crtc_state *crtc_state) 2401 { 2402 if (crtc_state->c8_planes) 2403 return true; 2404 2405 return crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE; 2406 } 2407 2408 static bool icl_has_pre_csc_lut(const struct intel_crtc_state *crtc_state) 2409 { 2410 return crtc_state->gamma_mode & PRE_CSC_GAMMA_ENABLE; 2411 } 2412 2413 static int icl_post_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2414 { 2415 if (!icl_has_post_csc_lut(crtc_state)) 2416 return 0; 2417 2418 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 2419 case GAMMA_MODE_MODE_8BIT: 2420 return 8; 2421 case GAMMA_MODE_MODE_10BIT: 2422 return 10; 2423 case GAMMA_MODE_MODE_12BIT_MULTI_SEG: 2424 return 16; 2425 default: 2426 MISSING_CASE(crtc_state->gamma_mode); 2427 return 0; 2428 } 2429 } 2430 2431 static int icl_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state) 2432 { 2433 if (!icl_has_pre_csc_lut(crtc_state)) 2434 return 0; 2435 2436 return 16; 2437 } 2438 2439 static bool err_check(struct drm_color_lut *lut1, 2440 struct drm_color_lut *lut2, u32 err) 2441 { 2442 return ((abs((long)lut2->red - lut1->red)) <= err) && 2443 ((abs((long)lut2->blue - lut1->blue)) <= err) && 2444 ((abs((long)lut2->green - lut1->green)) <= err); 2445 } 2446 2447 static bool intel_lut_entries_equal(struct drm_color_lut *lut1, 2448 struct drm_color_lut *lut2, 2449 int lut_size, u32 err) 2450 { 2451 int i; 2452 2453 for (i = 0; i < lut_size; i++) { 2454 if (!err_check(&lut1[i], &lut2[i], err)) 2455 return false; 2456 } 2457 2458 return true; 2459 } 2460 2461 static bool intel_lut_equal(const struct drm_property_blob *blob1, 2462 const struct drm_property_blob *blob2, 2463 int check_size, int precision) 2464 { 2465 struct drm_color_lut *lut1, *lut2; 2466 int lut_size1, lut_size2; 2467 u32 err; 2468 2469 if (!blob1 != !blob2) 2470 return false; 2471 2472 if (!blob1 != !precision) 2473 return false; 2474 2475 if (!blob1) 2476 return true; 2477 2478 lut_size1 = drm_color_lut_size(blob1); 2479 lut_size2 = drm_color_lut_size(blob2); 2480 2481 if (lut_size1 != lut_size2) 2482 return false; 2483 2484 if (check_size > lut_size1) 2485 return false; 2486 2487 lut1 = blob1->data; 2488 lut2 = blob2->data; 2489 2490 err = 0xffff >> precision; 2491 2492 if (!check_size) 2493 check_size = lut_size1; 2494 2495 return intel_lut_entries_equal(lut1, lut2, check_size, err); 2496 } 2497 2498 static bool i9xx_lut_equal(const struct intel_crtc_state *crtc_state, 2499 const struct drm_property_blob *blob1, 2500 const struct drm_property_blob *blob2, 2501 bool is_pre_csc_lut) 2502 { 2503 int check_size = 0; 2504 2505 if (is_pre_csc_lut) 2506 return intel_lut_equal(blob1, blob2, 0, 2507 i9xx_pre_csc_lut_precision(crtc_state)); 2508 2509 /* 10bit mode last entry is implicit, just skip it */ 2510 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_10BIT) 2511 check_size = 128; 2512 2513 return intel_lut_equal(blob1, blob2, check_size, 2514 i9xx_post_csc_lut_precision(crtc_state)); 2515 } 2516 2517 static bool i965_lut_equal(const struct intel_crtc_state *crtc_state, 2518 const struct drm_property_blob *blob1, 2519 const struct drm_property_blob *blob2, 2520 bool is_pre_csc_lut) 2521 { 2522 if (is_pre_csc_lut) 2523 return intel_lut_equal(blob1, blob2, 0, 2524 i9xx_pre_csc_lut_precision(crtc_state)); 2525 else 2526 return intel_lut_equal(blob1, blob2, 0, 2527 i965_post_csc_lut_precision(crtc_state)); 2528 } 2529 2530 static bool chv_lut_equal(const struct intel_crtc_state *crtc_state, 2531 const struct drm_property_blob *blob1, 2532 const struct drm_property_blob *blob2, 2533 bool is_pre_csc_lut) 2534 { 2535 if (is_pre_csc_lut) 2536 return intel_lut_equal(blob1, blob2, 0, 2537 chv_pre_csc_lut_precision(crtc_state)); 2538 else 2539 return intel_lut_equal(blob1, blob2, 0, 2540 chv_post_csc_lut_precision(crtc_state)); 2541 } 2542 2543 static bool ilk_lut_equal(const struct intel_crtc_state *crtc_state, 2544 const struct drm_property_blob *blob1, 2545 const struct drm_property_blob *blob2, 2546 bool is_pre_csc_lut) 2547 { 2548 if (is_pre_csc_lut) 2549 return intel_lut_equal(blob1, blob2, 0, 2550 ilk_pre_csc_lut_precision(crtc_state)); 2551 else 2552 return intel_lut_equal(blob1, blob2, 0, 2553 ilk_post_csc_lut_precision(crtc_state)); 2554 } 2555 2556 static bool ivb_lut_equal(const struct intel_crtc_state *crtc_state, 2557 const struct drm_property_blob *blob1, 2558 const struct drm_property_blob *blob2, 2559 bool is_pre_csc_lut) 2560 { 2561 if (is_pre_csc_lut) 2562 return intel_lut_equal(blob1, blob2, 0, 2563 ivb_pre_csc_lut_precision(crtc_state)); 2564 else 2565 return intel_lut_equal(blob1, blob2, 0, 2566 ivb_post_csc_lut_precision(crtc_state)); 2567 } 2568 2569 static bool glk_lut_equal(const struct intel_crtc_state *crtc_state, 2570 const struct drm_property_blob *blob1, 2571 const struct drm_property_blob *blob2, 2572 bool is_pre_csc_lut) 2573 { 2574 if (is_pre_csc_lut) 2575 return intel_lut_equal(blob1, blob2, 0, 2576 glk_pre_csc_lut_precision(crtc_state)); 2577 else 2578 return intel_lut_equal(blob1, blob2, 0, 2579 glk_post_csc_lut_precision(crtc_state)); 2580 } 2581 2582 static bool icl_lut_equal(const struct intel_crtc_state *crtc_state, 2583 const struct drm_property_blob *blob1, 2584 const struct drm_property_blob *blob2, 2585 bool is_pre_csc_lut) 2586 { 2587 int check_size = 0; 2588 2589 if (is_pre_csc_lut) 2590 return intel_lut_equal(blob1, blob2, 0, 2591 icl_pre_csc_lut_precision(crtc_state)); 2592 2593 /* hw readout broken except for the super fine segment :( */ 2594 if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == 2595 GAMMA_MODE_MODE_12BIT_MULTI_SEG) 2596 check_size = 9; 2597 2598 return intel_lut_equal(blob1, blob2, check_size, 2599 icl_post_csc_lut_precision(crtc_state)); 2600 } 2601 2602 static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc) 2603 { 2604 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2605 enum pipe pipe = crtc->pipe; 2606 struct drm_property_blob *blob; 2607 struct drm_color_lut *lut; 2608 int i; 2609 2610 blob = drm_property_create_blob(&dev_priv->drm, 2611 sizeof(lut[0]) * LEGACY_LUT_LENGTH, 2612 NULL); 2613 if (IS_ERR(blob)) 2614 return NULL; 2615 2616 lut = blob->data; 2617 2618 for (i = 0; i < LEGACY_LUT_LENGTH; i++) { 2619 u32 val = intel_de_read_fw(dev_priv, PALETTE(pipe, i)); 2620 2621 i9xx_lut_8_pack(&lut[i], val); 2622 } 2623 2624 return blob; 2625 } 2626 2627 static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc) 2628 { 2629 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2630 u32 lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size; 2631 enum pipe pipe = crtc->pipe; 2632 struct drm_property_blob *blob; 2633 struct drm_color_lut *lut; 2634 u32 ldw, udw; 2635 int i; 2636 2637 blob = drm_property_create_blob(&dev_priv->drm, 2638 lut_size * sizeof(lut[0]), NULL); 2639 if (IS_ERR(blob)) 2640 return NULL; 2641 2642 lut = blob->data; 2643 2644 for (i = 0; i < lut_size - 1; i++) { 2645 ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0)); 2646 udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1)); 2647 2648 i9xx_lut_10_pack(&lut[i], ldw, udw); 2649 } 2650 2651 i9xx_lut_10_pack_slope(&lut[i], ldw, udw); 2652 2653 return blob; 2654 } 2655 2656 static void i9xx_read_luts(struct intel_crtc_state *crtc_state) 2657 { 2658 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2659 2660 if (!crtc_state->gamma_enable && !crtc_state->c8_planes) 2661 return; 2662 2663 switch (crtc_state->gamma_mode) { 2664 case GAMMA_MODE_MODE_8BIT: 2665 crtc_state->post_csc_lut = i9xx_read_lut_8(crtc); 2666 break; 2667 case GAMMA_MODE_MODE_10BIT: 2668 crtc_state->post_csc_lut = i9xx_read_lut_10(crtc); 2669 break; 2670 default: 2671 MISSING_CASE(crtc_state->gamma_mode); 2672 break; 2673 } 2674 } 2675 2676 static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) 2677 { 2678 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2679 int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size; 2680 enum pipe pipe = crtc->pipe; 2681 struct drm_property_blob *blob; 2682 struct drm_color_lut *lut; 2683 2684 blob = drm_property_create_blob(&dev_priv->drm, 2685 sizeof(lut[0]) * lut_size, 2686 NULL); 2687 if (IS_ERR(blob)) 2688 return NULL; 2689 2690 lut = blob->data; 2691 2692 for (i = 0; i < lut_size - 1; i++) { 2693 u32 ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0)); 2694 u32 udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1)); 2695 2696 i965_lut_10p6_pack(&lut[i], ldw, udw); 2697 } 2698 2699 lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 0))); 2700 lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 1))); 2701 lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 2))); 2702 2703 return blob; 2704 } 2705 2706 static void i965_read_luts(struct intel_crtc_state *crtc_state) 2707 { 2708 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2709 2710 if (!crtc_state->gamma_enable && !crtc_state->c8_planes) 2711 return; 2712 2713 switch (crtc_state->gamma_mode) { 2714 case GAMMA_MODE_MODE_8BIT: 2715 crtc_state->post_csc_lut = i9xx_read_lut_8(crtc); 2716 break; 2717 case GAMMA_MODE_MODE_10BIT: 2718 crtc_state->post_csc_lut = i965_read_lut_10p6(crtc); 2719 break; 2720 default: 2721 MISSING_CASE(crtc_state->gamma_mode); 2722 break; 2723 } 2724 } 2725 2726 static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc) 2727 { 2728 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2729 int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size; 2730 enum pipe pipe = crtc->pipe; 2731 struct drm_property_blob *blob; 2732 struct drm_color_lut *lut; 2733 2734 blob = drm_property_create_blob(&dev_priv->drm, 2735 sizeof(lut[0]) * lut_size, 2736 NULL); 2737 if (IS_ERR(blob)) 2738 return NULL; 2739 2740 lut = blob->data; 2741 2742 for (i = 0; i < lut_size; i++) { 2743 u32 ldw = intel_de_read_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0)); 2744 u32 udw = intel_de_read_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1)); 2745 2746 chv_cgm_degamma_pack(&lut[i], ldw, udw); 2747 } 2748 2749 return blob; 2750 } 2751 2752 static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc) 2753 { 2754 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2755 int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size; 2756 enum pipe pipe = crtc->pipe; 2757 struct drm_property_blob *blob; 2758 struct drm_color_lut *lut; 2759 2760 blob = drm_property_create_blob(&i915->drm, 2761 sizeof(lut[0]) * lut_size, 2762 NULL); 2763 if (IS_ERR(blob)) 2764 return NULL; 2765 2766 lut = blob->data; 2767 2768 for (i = 0; i < lut_size; i++) { 2769 u32 ldw = intel_de_read_fw(i915, CGM_PIPE_GAMMA(pipe, i, 0)); 2770 u32 udw = intel_de_read_fw(i915, CGM_PIPE_GAMMA(pipe, i, 1)); 2771 2772 chv_cgm_gamma_pack(&lut[i], ldw, udw); 2773 } 2774 2775 return blob; 2776 } 2777 2778 static void chv_read_luts(struct intel_crtc_state *crtc_state) 2779 { 2780 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2781 2782 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA) 2783 crtc_state->pre_csc_lut = chv_read_cgm_degamma(crtc); 2784 2785 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) 2786 crtc_state->post_csc_lut = chv_read_cgm_gamma(crtc); 2787 else 2788 i965_read_luts(crtc_state); 2789 } 2790 2791 static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc) 2792 { 2793 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2794 enum pipe pipe = crtc->pipe; 2795 struct drm_property_blob *blob; 2796 struct drm_color_lut *lut; 2797 int i; 2798 2799 blob = drm_property_create_blob(&i915->drm, 2800 sizeof(lut[0]) * LEGACY_LUT_LENGTH, 2801 NULL); 2802 if (IS_ERR(blob)) 2803 return NULL; 2804 2805 lut = blob->data; 2806 2807 for (i = 0; i < LEGACY_LUT_LENGTH; i++) { 2808 u32 val = intel_de_read_fw(i915, LGC_PALETTE(pipe, i)); 2809 2810 i9xx_lut_8_pack(&lut[i], val); 2811 } 2812 2813 return blob; 2814 } 2815 2816 static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc) 2817 { 2818 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2819 int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size; 2820 enum pipe pipe = crtc->pipe; 2821 struct drm_property_blob *blob; 2822 struct drm_color_lut *lut; 2823 2824 blob = drm_property_create_blob(&i915->drm, 2825 sizeof(lut[0]) * lut_size, 2826 NULL); 2827 if (IS_ERR(blob)) 2828 return NULL; 2829 2830 lut = blob->data; 2831 2832 for (i = 0; i < lut_size; i++) { 2833 u32 val = intel_de_read_fw(i915, PREC_PALETTE(pipe, i)); 2834 2835 ilk_lut_10_pack(&lut[i], val); 2836 } 2837 2838 return blob; 2839 } 2840 2841 static void ilk_read_luts(struct intel_crtc_state *crtc_state) 2842 { 2843 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2844 struct drm_property_blob **blob = 2845 ilk_has_post_csc_lut(crtc_state) ? 2846 &crtc_state->post_csc_lut : &crtc_state->pre_csc_lut; 2847 2848 if (!crtc_state->gamma_enable && !crtc_state->c8_planes) 2849 return; 2850 2851 switch (crtc_state->gamma_mode) { 2852 case GAMMA_MODE_MODE_8BIT: 2853 *blob = ilk_read_lut_8(crtc); 2854 break; 2855 case GAMMA_MODE_MODE_10BIT: 2856 *blob = ilk_read_lut_10(crtc); 2857 break; 2858 default: 2859 MISSING_CASE(crtc_state->gamma_mode); 2860 break; 2861 } 2862 } 2863 2864 /* 2865 * IVB/HSW Bspec / PAL_PREC_INDEX: 2866 * "Restriction : Index auto increment mode is not 2867 * supported and must not be enabled." 2868 */ 2869 static struct drm_property_blob *ivb_read_lut_10(struct intel_crtc *crtc, 2870 u32 prec_index) 2871 { 2872 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2873 int i, lut_size = ivb_lut_10_size(prec_index); 2874 enum pipe pipe = crtc->pipe; 2875 struct drm_property_blob *blob; 2876 struct drm_color_lut *lut; 2877 2878 blob = drm_property_create_blob(&dev_priv->drm, 2879 sizeof(lut[0]) * lut_size, 2880 NULL); 2881 if (IS_ERR(blob)) 2882 return NULL; 2883 2884 lut = blob->data; 2885 2886 for (i = 0; i < lut_size; i++) { 2887 u32 val; 2888 2889 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 2890 prec_index + i); 2891 val = intel_de_read_fw(dev_priv, PREC_PAL_DATA(pipe)); 2892 2893 ilk_lut_10_pack(&lut[i], val); 2894 } 2895 2896 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe), 2897 PAL_PREC_INDEX_VALUE(0)); 2898 2899 return blob; 2900 } 2901 2902 static void ivb_read_luts(struct intel_crtc_state *crtc_state) 2903 { 2904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2905 struct drm_property_blob **blob = 2906 ilk_has_post_csc_lut(crtc_state) ? 2907 &crtc_state->post_csc_lut : &crtc_state->pre_csc_lut; 2908 2909 if (!crtc_state->gamma_enable && !crtc_state->c8_planes) 2910 return; 2911 2912 switch (crtc_state->gamma_mode) { 2913 case GAMMA_MODE_MODE_8BIT: 2914 *blob = ilk_read_lut_8(crtc); 2915 break; 2916 case GAMMA_MODE_MODE_SPLIT: 2917 crtc_state->pre_csc_lut = 2918 ivb_read_lut_10(crtc, PAL_PREC_SPLIT_MODE | 2919 PAL_PREC_INDEX_VALUE(0)); 2920 crtc_state->post_csc_lut = 2921 ivb_read_lut_10(crtc, PAL_PREC_SPLIT_MODE | 2922 PAL_PREC_INDEX_VALUE(512)); 2923 break; 2924 case GAMMA_MODE_MODE_10BIT: 2925 *blob = ivb_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); 2926 break; 2927 default: 2928 MISSING_CASE(crtc_state->gamma_mode); 2929 break; 2930 } 2931 } 2932 2933 /* On BDW+ the index auto increment mode actually works */ 2934 static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc, 2935 u32 prec_index) 2936 { 2937 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2938 int i, lut_size = ivb_lut_10_size(prec_index); 2939 enum pipe pipe = crtc->pipe; 2940 struct drm_property_blob *blob; 2941 struct drm_color_lut *lut; 2942 2943 blob = drm_property_create_blob(&i915->drm, 2944 sizeof(lut[0]) * lut_size, 2945 NULL); 2946 if (IS_ERR(blob)) 2947 return NULL; 2948 2949 lut = blob->data; 2950 2951 intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), 2952 prec_index); 2953 intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), 2954 PAL_PREC_AUTO_INCREMENT | 2955 prec_index); 2956 2957 for (i = 0; i < lut_size; i++) { 2958 u32 val = intel_de_read_fw(i915, PREC_PAL_DATA(pipe)); 2959 2960 ilk_lut_10_pack(&lut[i], val); 2961 } 2962 2963 intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), 2964 PAL_PREC_INDEX_VALUE(0)); 2965 2966 return blob; 2967 } 2968 2969 static void bdw_read_luts(struct intel_crtc_state *crtc_state) 2970 { 2971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2972 struct drm_property_blob **blob = 2973 ilk_has_post_csc_lut(crtc_state) ? 2974 &crtc_state->post_csc_lut : &crtc_state->pre_csc_lut; 2975 2976 if (!crtc_state->gamma_enable && !crtc_state->c8_planes) 2977 return; 2978 2979 switch (crtc_state->gamma_mode) { 2980 case GAMMA_MODE_MODE_8BIT: 2981 *blob = ilk_read_lut_8(crtc); 2982 break; 2983 case GAMMA_MODE_MODE_SPLIT: 2984 crtc_state->pre_csc_lut = 2985 bdw_read_lut_10(crtc, PAL_PREC_SPLIT_MODE | 2986 PAL_PREC_INDEX_VALUE(0)); 2987 crtc_state->post_csc_lut = 2988 bdw_read_lut_10(crtc, PAL_PREC_SPLIT_MODE | 2989 PAL_PREC_INDEX_VALUE(512)); 2990 break; 2991 case GAMMA_MODE_MODE_10BIT: 2992 *blob = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); 2993 break; 2994 default: 2995 MISSING_CASE(crtc_state->gamma_mode); 2996 break; 2997 } 2998 } 2999 3000 static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc) 3001 { 3002 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3003 int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size; 3004 enum pipe pipe = crtc->pipe; 3005 struct drm_property_blob *blob; 3006 struct drm_color_lut *lut; 3007 3008 blob = drm_property_create_blob(&dev_priv->drm, 3009 sizeof(lut[0]) * lut_size, 3010 NULL); 3011 if (IS_ERR(blob)) 3012 return NULL; 3013 3014 lut = blob->data; 3015 3016 /* 3017 * When setting the auto-increment bit, the hardware seems to 3018 * ignore the index bits, so we need to reset it to index 0 3019 * separately. 3020 */ 3021 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 3022 PRE_CSC_GAMC_INDEX_VALUE(0)); 3023 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 3024 PRE_CSC_GAMC_AUTO_INCREMENT | 3025 PRE_CSC_GAMC_INDEX_VALUE(0)); 3026 3027 for (i = 0; i < lut_size; i++) { 3028 u32 val = intel_de_read_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe)); 3029 3030 lut[i].red = val; 3031 lut[i].green = val; 3032 lut[i].blue = val; 3033 } 3034 3035 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 3036 PRE_CSC_GAMC_INDEX_VALUE(0)); 3037 3038 return blob; 3039 } 3040 3041 static void glk_read_luts(struct intel_crtc_state *crtc_state) 3042 { 3043 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3044 3045 if (crtc_state->csc_enable) 3046 crtc_state->pre_csc_lut = glk_read_degamma_lut(crtc); 3047 3048 if (!crtc_state->gamma_enable && !crtc_state->c8_planes) 3049 return; 3050 3051 switch (crtc_state->gamma_mode) { 3052 case GAMMA_MODE_MODE_8BIT: 3053 crtc_state->post_csc_lut = ilk_read_lut_8(crtc); 3054 break; 3055 case GAMMA_MODE_MODE_10BIT: 3056 crtc_state->post_csc_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); 3057 break; 3058 default: 3059 MISSING_CASE(crtc_state->gamma_mode); 3060 break; 3061 } 3062 } 3063 3064 static struct drm_property_blob * 3065 icl_read_lut_multi_segment(struct intel_crtc *crtc) 3066 { 3067 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3068 int i, lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size; 3069 enum pipe pipe = crtc->pipe; 3070 struct drm_property_blob *blob; 3071 struct drm_color_lut *lut; 3072 3073 blob = drm_property_create_blob(&i915->drm, 3074 sizeof(lut[0]) * lut_size, 3075 NULL); 3076 if (IS_ERR(blob)) 3077 return NULL; 3078 3079 lut = blob->data; 3080 3081 intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe), 3082 PAL_PREC_MULTI_SEG_INDEX_VALUE(0)); 3083 intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe), 3084 PAL_PREC_MULTI_SEG_AUTO_INCREMENT | 3085 PAL_PREC_MULTI_SEG_INDEX_VALUE(0)); 3086 3087 for (i = 0; i < 9; i++) { 3088 u32 ldw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe)); 3089 u32 udw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe)); 3090 3091 ilk_lut_12p4_pack(&lut[i], ldw, udw); 3092 } 3093 3094 intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe), 3095 PAL_PREC_MULTI_SEG_INDEX_VALUE(0)); 3096 3097 /* 3098 * FIXME readouts from PAL_PREC_DATA register aren't giving 3099 * correct values in the case of fine and coarse segments. 3100 * Restricting readouts only for super fine segment as of now. 3101 */ 3102 3103 return blob; 3104 } 3105 3106 static void icl_read_luts(struct intel_crtc_state *crtc_state) 3107 { 3108 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3109 3110 if (icl_has_pre_csc_lut(crtc_state)) 3111 crtc_state->pre_csc_lut = glk_read_degamma_lut(crtc); 3112 3113 if (!icl_has_post_csc_lut(crtc_state)) 3114 return; 3115 3116 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { 3117 case GAMMA_MODE_MODE_8BIT: 3118 crtc_state->post_csc_lut = ilk_read_lut_8(crtc); 3119 break; 3120 case GAMMA_MODE_MODE_10BIT: 3121 crtc_state->post_csc_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); 3122 break; 3123 case GAMMA_MODE_MODE_12BIT_MULTI_SEG: 3124 crtc_state->post_csc_lut = icl_read_lut_multi_segment(crtc); 3125 break; 3126 default: 3127 MISSING_CASE(crtc_state->gamma_mode); 3128 break; 3129 } 3130 } 3131 3132 static const struct intel_color_funcs chv_color_funcs = { 3133 .color_check = chv_color_check, 3134 .color_commit_arm = i9xx_color_commit_arm, 3135 .load_luts = chv_load_luts, 3136 .read_luts = chv_read_luts, 3137 .lut_equal = chv_lut_equal, 3138 }; 3139 3140 static const struct intel_color_funcs i965_color_funcs = { 3141 .color_check = i9xx_color_check, 3142 .color_commit_arm = i9xx_color_commit_arm, 3143 .load_luts = i965_load_luts, 3144 .read_luts = i965_read_luts, 3145 .lut_equal = i965_lut_equal, 3146 }; 3147 3148 static const struct intel_color_funcs i9xx_color_funcs = { 3149 .color_check = i9xx_color_check, 3150 .color_commit_arm = i9xx_color_commit_arm, 3151 .load_luts = i9xx_load_luts, 3152 .read_luts = i9xx_read_luts, 3153 .lut_equal = i9xx_lut_equal, 3154 }; 3155 3156 static const struct intel_color_funcs tgl_color_funcs = { 3157 .color_check = icl_color_check, 3158 .color_commit_noarm = icl_color_commit_noarm, 3159 .color_commit_arm = icl_color_commit_arm, 3160 .load_luts = icl_load_luts, 3161 .read_luts = icl_read_luts, 3162 .lut_equal = icl_lut_equal, 3163 }; 3164 3165 static const struct intel_color_funcs icl_color_funcs = { 3166 .color_check = icl_color_check, 3167 .color_commit_noarm = icl_color_commit_noarm, 3168 .color_commit_arm = icl_color_commit_arm, 3169 .color_post_update = icl_color_post_update, 3170 .load_luts = icl_load_luts, 3171 .read_luts = icl_read_luts, 3172 .lut_equal = icl_lut_equal, 3173 }; 3174 3175 static const struct intel_color_funcs glk_color_funcs = { 3176 .color_check = glk_color_check, 3177 .color_commit_noarm = skl_color_commit_noarm, 3178 .color_commit_arm = skl_color_commit_arm, 3179 .load_luts = glk_load_luts, 3180 .read_luts = glk_read_luts, 3181 .lut_equal = glk_lut_equal, 3182 }; 3183 3184 static const struct intel_color_funcs skl_color_funcs = { 3185 .color_check = ivb_color_check, 3186 .color_commit_noarm = skl_color_commit_noarm, 3187 .color_commit_arm = skl_color_commit_arm, 3188 .load_luts = bdw_load_luts, 3189 .read_luts = bdw_read_luts, 3190 .lut_equal = ivb_lut_equal, 3191 }; 3192 3193 static const struct intel_color_funcs bdw_color_funcs = { 3194 .color_check = ivb_color_check, 3195 .color_commit_noarm = ilk_color_commit_noarm, 3196 .color_commit_arm = hsw_color_commit_arm, 3197 .load_luts = bdw_load_luts, 3198 .read_luts = bdw_read_luts, 3199 .lut_equal = ivb_lut_equal, 3200 }; 3201 3202 static const struct intel_color_funcs hsw_color_funcs = { 3203 .color_check = ivb_color_check, 3204 .color_commit_noarm = ilk_color_commit_noarm, 3205 .color_commit_arm = hsw_color_commit_arm, 3206 .load_luts = ivb_load_luts, 3207 .read_luts = ivb_read_luts, 3208 .lut_equal = ivb_lut_equal, 3209 }; 3210 3211 static const struct intel_color_funcs ivb_color_funcs = { 3212 .color_check = ivb_color_check, 3213 .color_commit_noarm = ilk_color_commit_noarm, 3214 .color_commit_arm = ilk_color_commit_arm, 3215 .load_luts = ivb_load_luts, 3216 .read_luts = ivb_read_luts, 3217 .lut_equal = ivb_lut_equal, 3218 }; 3219 3220 static const struct intel_color_funcs ilk_color_funcs = { 3221 .color_check = ilk_color_check, 3222 .color_commit_noarm = ilk_color_commit_noarm, 3223 .color_commit_arm = ilk_color_commit_arm, 3224 .load_luts = ilk_load_luts, 3225 .read_luts = ilk_read_luts, 3226 .lut_equal = ilk_lut_equal, 3227 }; 3228 3229 void intel_color_crtc_init(struct intel_crtc *crtc) 3230 { 3231 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3232 int degamma_lut_size, gamma_lut_size; 3233 bool has_ctm; 3234 3235 drm_mode_crtc_set_gamma_size(&crtc->base, 256); 3236 3237 gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size; 3238 degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size; 3239 has_ctm = degamma_lut_size != 0; 3240 3241 /* 3242 * "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the 3243 * only mode supported by Alviso and Grantsdale." 3244 * 3245 * Actually looks like this affects all of gen3. 3246 * Confirmed on alv,cst,pnv. Mobile gen2 parts (alm,mgm) 3247 * are confirmed not to suffer from this restriction. 3248 */ 3249 if (DISPLAY_VER(i915) == 3 && crtc->pipe == PIPE_A) 3250 gamma_lut_size = 256; 3251 3252 drm_crtc_enable_color_mgmt(&crtc->base, degamma_lut_size, 3253 has_ctm, gamma_lut_size); 3254 } 3255 3256 int intel_color_init(struct drm_i915_private *i915) 3257 { 3258 struct drm_property_blob *blob; 3259 3260 if (DISPLAY_VER(i915) != 10) 3261 return 0; 3262 3263 blob = create_linear_lut(i915, INTEL_INFO(i915)->display.color.degamma_lut_size); 3264 if (IS_ERR(blob)) 3265 return PTR_ERR(blob); 3266 3267 i915->display.color.glk_linear_degamma_lut = blob; 3268 3269 return 0; 3270 } 3271 3272 void intel_color_init_hooks(struct drm_i915_private *i915) 3273 { 3274 if (HAS_GMCH(i915)) { 3275 if (IS_CHERRYVIEW(i915)) 3276 i915->display.funcs.color = &chv_color_funcs; 3277 else if (DISPLAY_VER(i915) >= 4) 3278 i915->display.funcs.color = &i965_color_funcs; 3279 else 3280 i915->display.funcs.color = &i9xx_color_funcs; 3281 } else { 3282 if (DISPLAY_VER(i915) >= 12) 3283 i915->display.funcs.color = &tgl_color_funcs; 3284 else if (DISPLAY_VER(i915) == 11) 3285 i915->display.funcs.color = &icl_color_funcs; 3286 else if (DISPLAY_VER(i915) == 10) 3287 i915->display.funcs.color = &glk_color_funcs; 3288 else if (DISPLAY_VER(i915) == 9) 3289 i915->display.funcs.color = &skl_color_funcs; 3290 else if (DISPLAY_VER(i915) == 8) 3291 i915->display.funcs.color = &bdw_color_funcs; 3292 else if (IS_HASWELL(i915)) 3293 i915->display.funcs.color = &hsw_color_funcs; 3294 else if (DISPLAY_VER(i915) == 7) 3295 i915->display.funcs.color = &ivb_color_funcs; 3296 else 3297 i915->display.funcs.color = &ilk_color_funcs; 3298 } 3299 } 3300