1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef __INTEL_COMBO_PHY_REGS__
7 #define __INTEL_COMBO_PHY_REGS__
8 
9 #include "i915_reg_defs.h"
10 
11 #define _ICL_COMBOPHY_A				0x162000
12 #define _ICL_COMBOPHY_B				0x6C000
13 #define _EHL_COMBOPHY_C				0x160000
14 #define _RKL_COMBOPHY_D				0x161000
15 #define _ADL_COMBOPHY_E				0x16B000
16 
17 #define _ICL_COMBOPHY(phy)			_PICK(phy, _ICL_COMBOPHY_A, \
18 						      _ICL_COMBOPHY_B, \
19 						      _EHL_COMBOPHY_C, \
20 						      _RKL_COMBOPHY_D, \
21 						      _ADL_COMBOPHY_E)
22 
23 /* ICL Port CL_DW registers */
24 #define _ICL_PORT_CL_DW(dw, phy)		(_ICL_COMBOPHY(phy) + \
25 						 4 * (dw))
26 
27 #define ICL_PORT_CL_DW5(phy)			_MMIO(_ICL_PORT_CL_DW(5, phy))
28 #define   CL_POWER_DOWN_ENABLE			(1 << 4)
29 #define   SUS_CLOCK_CONFIG			(3 << 0)
30 
31 #define ICL_PORT_CL_DW10(phy)			_MMIO(_ICL_PORT_CL_DW(10, phy))
32 #define  PG_SEQ_DELAY_OVERRIDE_MASK		(3 << 25)
33 #define  PG_SEQ_DELAY_OVERRIDE_SHIFT		25
34 #define  PG_SEQ_DELAY_OVERRIDE_ENABLE		(1 << 24)
35 #define  PWR_UP_ALL_LANES			(0x0 << 4)
36 #define  PWR_DOWN_LN_3_2_1			(0xe << 4)
37 #define  PWR_DOWN_LN_3_2			(0xc << 4)
38 #define  PWR_DOWN_LN_3				(0x8 << 4)
39 #define  PWR_DOWN_LN_2_1_0			(0x7 << 4)
40 #define  PWR_DOWN_LN_1_0			(0x3 << 4)
41 #define  PWR_DOWN_LN_3_1			(0xa << 4)
42 #define  PWR_DOWN_LN_3_1_0			(0xb << 4)
43 #define  PWR_DOWN_LN_MASK			(0xf << 4)
44 #define  PWR_DOWN_LN_SHIFT			4
45 #define  EDP4K2K_MODE_OVRD_EN			(1 << 3)
46 #define  EDP4K2K_MODE_OVRD_OPTIMIZED		(1 << 2)
47 
48 #define ICL_PORT_CL_DW12(phy)			_MMIO(_ICL_PORT_CL_DW(12, phy))
49 #define   ICL_LANE_ENABLE_AUX			(1 << 0)
50 
51 /* ICL Port COMP_DW registers */
52 #define _ICL_PORT_COMP				0x100
53 #define _ICL_PORT_COMP_DW(dw, phy)		(_ICL_COMBOPHY(phy) + \
54 						 _ICL_PORT_COMP + 4 * (dw))
55 
56 #define ICL_PORT_COMP_DW0(phy)			_MMIO(_ICL_PORT_COMP_DW(0, phy))
57 #define   COMP_INIT				(1 << 31)
58 
59 #define ICL_PORT_COMP_DW1(phy)			_MMIO(_ICL_PORT_COMP_DW(1, phy))
60 
61 #define ICL_PORT_COMP_DW3(phy)			_MMIO(_ICL_PORT_COMP_DW(3, phy))
62 #define   PROCESS_INFO_DOT_0			(0 << 26)
63 #define   PROCESS_INFO_DOT_1			(1 << 26)
64 #define   PROCESS_INFO_DOT_4			(2 << 26)
65 #define   PROCESS_INFO_MASK			(7 << 26)
66 #define   PROCESS_INFO_SHIFT			26
67 #define   VOLTAGE_INFO_0_85V			(0 << 24)
68 #define   VOLTAGE_INFO_0_95V			(1 << 24)
69 #define   VOLTAGE_INFO_1_05V			(2 << 24)
70 #define   VOLTAGE_INFO_MASK			(3 << 24)
71 #define   VOLTAGE_INFO_SHIFT			24
72 
73 #define ICL_PORT_COMP_DW8(phy)			_MMIO(_ICL_PORT_COMP_DW(8, phy))
74 #define   IREFGEN				(1 << 24)
75 
76 #define ICL_PORT_COMP_DW9(phy)			_MMIO(_ICL_PORT_COMP_DW(9, phy))
77 
78 #define ICL_PORT_COMP_DW10(phy)			_MMIO(_ICL_PORT_COMP_DW(10, phy))
79 
80 /* ICL Port PCS registers */
81 #define _ICL_PORT_PCS_AUX			0x300
82 #define _ICL_PORT_PCS_GRP			0x600
83 #define _ICL_PORT_PCS_LN(ln)			(0x800 + (ln) * 0x100)
84 #define _ICL_PORT_PCS_DW_AUX(dw, phy)		(_ICL_COMBOPHY(phy) + \
85 						 _ICL_PORT_PCS_AUX + 4 * (dw))
86 #define _ICL_PORT_PCS_DW_GRP(dw, phy)		(_ICL_COMBOPHY(phy) + \
87 						 _ICL_PORT_PCS_GRP + 4 * (dw))
88 #define _ICL_PORT_PCS_DW_LN(dw, ln, phy)	 (_ICL_COMBOPHY(phy) + \
89 						  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
90 #define ICL_PORT_PCS_DW1_AUX(phy)		_MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
91 #define ICL_PORT_PCS_DW1_GRP(phy)		_MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
92 #define ICL_PORT_PCS_DW1_LN(ln, phy)		_MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
93 #define   DCC_MODE_SELECT_MASK			REG_GENMASK(21, 20)
94 #define   RUN_DCC_ONCE				REG_FIELD_PREP(DCC_MODE_SELECT_MASK, 0)
95 #define   COMMON_KEEPER_EN			(1 << 26)
96 #define   LATENCY_OPTIM_MASK			(0x3 << 2)
97 #define   LATENCY_OPTIM_VAL(x)			((x) << 2)
98 
99 /* ICL Port TX registers */
100 #define _ICL_PORT_TX_AUX			0x380
101 #define _ICL_PORT_TX_GRP			0x680
102 #define _ICL_PORT_TX_LN(ln)			(0x880 + (ln) * 0x100)
103 
104 #define _ICL_PORT_TX_DW_AUX(dw, phy)		(_ICL_COMBOPHY(phy) + \
105 						 _ICL_PORT_TX_AUX + 4 * (dw))
106 #define _ICL_PORT_TX_DW_GRP(dw, phy)		(_ICL_COMBOPHY(phy) + \
107 						 _ICL_PORT_TX_GRP + 4 * (dw))
108 #define _ICL_PORT_TX_DW_LN(dw, ln, phy) 	(_ICL_COMBOPHY(phy) + \
109 						  _ICL_PORT_TX_LN(ln) + 4 * (dw))
110 
111 #define ICL_PORT_TX_DW2_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
112 #define ICL_PORT_TX_DW2_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
113 #define ICL_PORT_TX_DW2_LN(ln, phy)		_MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
114 #define   SWING_SEL_UPPER(x)			(((x) >> 3) << 15)
115 #define   SWING_SEL_UPPER_MASK			(1 << 15)
116 #define   SWING_SEL_LOWER(x)			(((x) & 0x7) << 11)
117 #define   SWING_SEL_LOWER_MASK			(0x7 << 11)
118 #define   FRC_LATENCY_OPTIM_MASK		(0x7 << 8)
119 #define   FRC_LATENCY_OPTIM_VAL(x)		((x) << 8)
120 #define   RCOMP_SCALAR(x)			((x) << 0)
121 #define   RCOMP_SCALAR_MASK			(0xFF << 0)
122 
123 #define ICL_PORT_TX_DW4_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
124 #define ICL_PORT_TX_DW4_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
125 #define ICL_PORT_TX_DW4_LN(ln, phy)		_MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
126 #define   LOADGEN_SELECT			(1 << 31)
127 #define   POST_CURSOR_1(x)			((x) << 12)
128 #define   POST_CURSOR_1_MASK			(0x3F << 12)
129 #define   POST_CURSOR_2(x)			((x) << 6)
130 #define   POST_CURSOR_2_MASK			(0x3F << 6)
131 #define   CURSOR_COEFF(x)			((x) << 0)
132 #define   CURSOR_COEFF_MASK			(0x3F << 0)
133 
134 #define ICL_PORT_TX_DW5_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
135 #define ICL_PORT_TX_DW5_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
136 #define ICL_PORT_TX_DW5_LN(ln, phy)		_MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
137 #define   TX_TRAINING_EN			(1 << 31)
138 #define   TAP2_DISABLE				(1 << 30)
139 #define   TAP3_DISABLE				(1 << 29)
140 #define   SCALING_MODE_SEL(x)			((x) << 18)
141 #define   SCALING_MODE_SEL_MASK			(0x7 << 18)
142 #define   RTERM_SELECT(x)			((x) << 3)
143 #define   RTERM_SELECT_MASK			(0x7 << 3)
144 
145 #define ICL_PORT_TX_DW7_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
146 #define ICL_PORT_TX_DW7_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
147 #define ICL_PORT_TX_DW7_LN(ln, phy)		_MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
148 #define   N_SCALAR(x)				((x) << 24)
149 #define   N_SCALAR_MASK				(0x7F << 24)
150 
151 #define ICL_PORT_TX_DW8_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
152 #define ICL_PORT_TX_DW8_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
153 #define ICL_PORT_TX_DW8_LN(ln, phy)		_MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
154 #define   ICL_PORT_TX_DW8_ODCC_CLK_SEL		REG_BIT(31)
155 #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK	REG_GENMASK(30, 29)
156 #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2	REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
157 
158 #define _ICL_DPHY_CHKN_REG			0x194
159 #define ICL_DPHY_CHKN(port)			_MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
160 #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP	REG_BIT(7)
161 
162 #endif /* __INTEL_COMBO_PHY_REGS__ */
163