1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/string_helpers.h> 29 30 #include <drm/display/drm_scdc_helper.h> 31 #include <drm/drm_privacy_screen_consumer.h> 32 33 #include "i915_drv.h" 34 #include "intel_audio.h" 35 #include "intel_backlight.h" 36 #include "intel_combo_phy.h" 37 #include "intel_combo_phy_regs.h" 38 #include "intel_connector.h" 39 #include "intel_crtc.h" 40 #include "intel_ddi.h" 41 #include "intel_ddi_buf_trans.h" 42 #include "intel_de.h" 43 #include "intel_display_power.h" 44 #include "intel_display_types.h" 45 #include "intel_dp.h" 46 #include "intel_dp_link_training.h" 47 #include "intel_dp_mst.h" 48 #include "intel_dpio_phy.h" 49 #include "intel_dsi.h" 50 #include "intel_fdi.h" 51 #include "intel_fifo_underrun.h" 52 #include "intel_gmbus.h" 53 #include "intel_hdcp.h" 54 #include "intel_hdmi.h" 55 #include "intel_hotplug.h" 56 #include "intel_lspcon.h" 57 #include "intel_pps.h" 58 #include "intel_psr.h" 59 #include "intel_snps_phy.h" 60 #include "intel_sprite.h" 61 #include "intel_tc.h" 62 #include "intel_tc_phy_regs.h" 63 #include "intel_vdsc.h" 64 #include "intel_vrr.h" 65 #include "skl_scaler.h" 66 #include "skl_universal_plane.h" 67 68 static const u8 index_to_dp_signal_levels[] = { 69 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 71 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 72 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 73 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 74 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 75 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 76 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 77 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 78 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 79 }; 80 81 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 82 const struct intel_ddi_buf_trans *trans) 83 { 84 int level; 85 86 level = intel_bios_hdmi_level_shift(encoder); 87 if (level < 0) 88 level = trans->hdmi_default_entry; 89 90 return level; 91 } 92 93 static bool has_buf_trans_select(struct drm_i915_private *i915) 94 { 95 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 96 } 97 98 static bool has_iboost(struct drm_i915_private *i915) 99 { 100 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 101 } 102 103 /* 104 * Starting with Haswell, DDI port buffers must be programmed with correct 105 * values in advance. This function programs the correct values for 106 * DP/eDP/FDI use cases. 107 */ 108 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 109 const struct intel_crtc_state *crtc_state) 110 { 111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 112 u32 iboost_bit = 0; 113 int i, n_entries; 114 enum port port = encoder->port; 115 const struct intel_ddi_buf_trans *trans; 116 117 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 118 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 119 return; 120 121 /* If we're boosting the current, set bit 31 of trans1 */ 122 if (has_iboost(dev_priv) && 123 intel_bios_encoder_dp_boost_level(encoder->devdata)) 124 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 125 126 for (i = 0; i < n_entries; i++) { 127 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 128 trans->entries[i].hsw.trans1 | iboost_bit); 129 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 130 trans->entries[i].hsw.trans2); 131 } 132 } 133 134 /* 135 * Starting with Haswell, DDI port buffers must be programmed with correct 136 * values in advance. This function programs the correct values for 137 * HDMI/DVI use cases. 138 */ 139 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 140 const struct intel_crtc_state *crtc_state) 141 { 142 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 143 int level = intel_ddi_level(encoder, crtc_state, 0); 144 u32 iboost_bit = 0; 145 int n_entries; 146 enum port port = encoder->port; 147 const struct intel_ddi_buf_trans *trans; 148 149 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 150 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 151 return; 152 153 /* If we're boosting the current, set bit 31 of trans1 */ 154 if (has_iboost(dev_priv) && 155 intel_bios_encoder_hdmi_boost_level(encoder->devdata)) 156 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 157 158 /* Entry 9 is for HDMI: */ 159 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 160 trans->entries[level].hsw.trans1 | iboost_bit); 161 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 162 trans->entries[level].hsw.trans2); 163 } 164 165 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 166 enum port port) 167 { 168 if (IS_BROXTON(dev_priv)) { 169 udelay(16); 170 return; 171 } 172 173 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 174 DDI_BUF_IS_IDLE), 8)) 175 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 176 port_name(port)); 177 } 178 179 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 180 enum port port) 181 { 182 int ret; 183 184 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 185 if (DISPLAY_VER(dev_priv) < 10) { 186 usleep_range(518, 1000); 187 return; 188 } 189 190 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 191 DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); 192 193 if (ret) 194 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 195 port_name(port)); 196 } 197 198 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 199 { 200 switch (pll->info->id) { 201 case DPLL_ID_WRPLL1: 202 return PORT_CLK_SEL_WRPLL1; 203 case DPLL_ID_WRPLL2: 204 return PORT_CLK_SEL_WRPLL2; 205 case DPLL_ID_SPLL: 206 return PORT_CLK_SEL_SPLL; 207 case DPLL_ID_LCPLL_810: 208 return PORT_CLK_SEL_LCPLL_810; 209 case DPLL_ID_LCPLL_1350: 210 return PORT_CLK_SEL_LCPLL_1350; 211 case DPLL_ID_LCPLL_2700: 212 return PORT_CLK_SEL_LCPLL_2700; 213 default: 214 MISSING_CASE(pll->info->id); 215 return PORT_CLK_SEL_NONE; 216 } 217 } 218 219 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 220 const struct intel_crtc_state *crtc_state) 221 { 222 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 223 int clock = crtc_state->port_clock; 224 const enum intel_dpll_id id = pll->info->id; 225 226 switch (id) { 227 default: 228 /* 229 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 230 * here, so do warn if this get passed in 231 */ 232 MISSING_CASE(id); 233 return DDI_CLK_SEL_NONE; 234 case DPLL_ID_ICL_TBTPLL: 235 switch (clock) { 236 case 162000: 237 return DDI_CLK_SEL_TBT_162; 238 case 270000: 239 return DDI_CLK_SEL_TBT_270; 240 case 540000: 241 return DDI_CLK_SEL_TBT_540; 242 case 810000: 243 return DDI_CLK_SEL_TBT_810; 244 default: 245 MISSING_CASE(clock); 246 return DDI_CLK_SEL_NONE; 247 } 248 case DPLL_ID_ICL_MGPLL1: 249 case DPLL_ID_ICL_MGPLL2: 250 case DPLL_ID_ICL_MGPLL3: 251 case DPLL_ID_ICL_MGPLL4: 252 case DPLL_ID_TGL_MGPLL5: 253 case DPLL_ID_TGL_MGPLL6: 254 return DDI_CLK_SEL_MG; 255 } 256 } 257 258 static u32 ddi_buf_phy_link_rate(int port_clock) 259 { 260 switch (port_clock) { 261 case 162000: 262 return DDI_BUF_PHY_LINK_RATE(0); 263 case 216000: 264 return DDI_BUF_PHY_LINK_RATE(4); 265 case 243000: 266 return DDI_BUF_PHY_LINK_RATE(5); 267 case 270000: 268 return DDI_BUF_PHY_LINK_RATE(1); 269 case 324000: 270 return DDI_BUF_PHY_LINK_RATE(6); 271 case 432000: 272 return DDI_BUF_PHY_LINK_RATE(7); 273 case 540000: 274 return DDI_BUF_PHY_LINK_RATE(2); 275 case 810000: 276 return DDI_BUF_PHY_LINK_RATE(3); 277 default: 278 MISSING_CASE(port_clock); 279 return DDI_BUF_PHY_LINK_RATE(0); 280 } 281 } 282 283 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 284 const struct intel_crtc_state *crtc_state) 285 { 286 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 287 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 288 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 289 enum phy phy = intel_port_to_phy(i915, encoder->port); 290 291 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 292 intel_dp->DP = dig_port->saved_port_bits | 293 DDI_PORT_WIDTH(crtc_state->lane_count) | 294 DDI_BUF_TRANS_SELECT(0); 295 296 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 297 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 298 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 299 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 300 } 301 } 302 303 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 304 enum port port) 305 { 306 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 307 308 switch (val) { 309 case DDI_CLK_SEL_NONE: 310 return 0; 311 case DDI_CLK_SEL_TBT_162: 312 return 162000; 313 case DDI_CLK_SEL_TBT_270: 314 return 270000; 315 case DDI_CLK_SEL_TBT_540: 316 return 540000; 317 case DDI_CLK_SEL_TBT_810: 318 return 810000; 319 default: 320 MISSING_CASE(val); 321 return 0; 322 } 323 } 324 325 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 326 { 327 int dotclock; 328 329 /* CRT dotclock is determined via other means */ 330 if (pipe_config->has_pch_encoder) 331 return; 332 333 if (intel_crtc_has_dp_encoder(pipe_config)) 334 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 335 &pipe_config->dp_m_n); 336 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 337 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 338 else 339 dotclock = pipe_config->port_clock; 340 341 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 342 !intel_crtc_has_dp_encoder(pipe_config)) 343 dotclock *= 2; 344 345 if (pipe_config->pixel_multiplier) 346 dotclock /= pipe_config->pixel_multiplier; 347 348 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 349 } 350 351 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 352 const struct drm_connector_state *conn_state) 353 { 354 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 355 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 356 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 357 u32 temp; 358 359 if (!intel_crtc_has_dp_encoder(crtc_state)) 360 return; 361 362 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 363 364 temp = DP_MSA_MISC_SYNC_CLOCK; 365 366 switch (crtc_state->pipe_bpp) { 367 case 18: 368 temp |= DP_MSA_MISC_6_BPC; 369 break; 370 case 24: 371 temp |= DP_MSA_MISC_8_BPC; 372 break; 373 case 30: 374 temp |= DP_MSA_MISC_10_BPC; 375 break; 376 case 36: 377 temp |= DP_MSA_MISC_12_BPC; 378 break; 379 default: 380 MISSING_CASE(crtc_state->pipe_bpp); 381 break; 382 } 383 384 /* nonsense combination */ 385 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 386 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 387 388 if (crtc_state->limited_color_range) 389 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 390 391 /* 392 * As per DP 1.2 spec section 2.3.4.3 while sending 393 * YCBCR 444 signals we should program MSA MISC1/0 fields with 394 * colorspace information. 395 */ 396 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 397 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 398 399 /* 400 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 401 * of Color Encoding Format and Content Color Gamut] while sending 402 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 403 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 404 */ 405 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 406 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 407 408 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 409 } 410 411 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 412 { 413 if (master_transcoder == TRANSCODER_EDP) 414 return 0; 415 else 416 return master_transcoder + 1; 417 } 418 419 static void 420 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 421 const struct intel_crtc_state *crtc_state) 422 { 423 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 424 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 425 u32 val = 0; 426 427 if (intel_dp_is_uhbr(crtc_state)) 428 val = TRANS_DP2_128B132B_CHANNEL_CODING; 429 430 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 431 } 432 433 /* 434 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 435 * 436 * Only intended to be used by intel_ddi_enable_transcoder_func() and 437 * intel_ddi_config_transcoder_func(). 438 */ 439 static u32 440 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 441 const struct intel_crtc_state *crtc_state) 442 { 443 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 444 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 445 enum pipe pipe = crtc->pipe; 446 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 447 enum port port = encoder->port; 448 u32 temp; 449 450 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 451 temp = TRANS_DDI_FUNC_ENABLE; 452 if (DISPLAY_VER(dev_priv) >= 12) 453 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 454 else 455 temp |= TRANS_DDI_SELECT_PORT(port); 456 457 switch (crtc_state->pipe_bpp) { 458 case 18: 459 temp |= TRANS_DDI_BPC_6; 460 break; 461 case 24: 462 temp |= TRANS_DDI_BPC_8; 463 break; 464 case 30: 465 temp |= TRANS_DDI_BPC_10; 466 break; 467 case 36: 468 temp |= TRANS_DDI_BPC_12; 469 break; 470 default: 471 BUG(); 472 } 473 474 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 475 temp |= TRANS_DDI_PVSYNC; 476 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 477 temp |= TRANS_DDI_PHSYNC; 478 479 if (cpu_transcoder == TRANSCODER_EDP) { 480 switch (pipe) { 481 case PIPE_A: 482 /* On Haswell, can only use the always-on power well for 483 * eDP when not using the panel fitter, and when not 484 * using motion blur mitigation (which we don't 485 * support). */ 486 if (crtc_state->pch_pfit.force_thru) 487 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 488 else 489 temp |= TRANS_DDI_EDP_INPUT_A_ON; 490 break; 491 case PIPE_B: 492 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 493 break; 494 case PIPE_C: 495 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 496 break; 497 default: 498 BUG(); 499 break; 500 } 501 } 502 503 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 504 if (crtc_state->has_hdmi_sink) 505 temp |= TRANS_DDI_MODE_SELECT_HDMI; 506 else 507 temp |= TRANS_DDI_MODE_SELECT_DVI; 508 509 if (crtc_state->hdmi_scrambling) 510 temp |= TRANS_DDI_HDMI_SCRAMBLING; 511 if (crtc_state->hdmi_high_tmds_clock_ratio) 512 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 513 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 514 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 515 temp |= (crtc_state->fdi_lanes - 1) << 1; 516 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 517 if (intel_dp_is_uhbr(crtc_state)) 518 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 519 else 520 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 521 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 522 523 if (DISPLAY_VER(dev_priv) >= 12) { 524 enum transcoder master; 525 526 master = crtc_state->mst_master_transcoder; 527 drm_WARN_ON(&dev_priv->drm, 528 master == INVALID_TRANSCODER); 529 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 530 } 531 } else { 532 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 533 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 534 } 535 536 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 537 crtc_state->master_transcoder != INVALID_TRANSCODER) { 538 u8 master_select = 539 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 540 541 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 542 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 543 } 544 545 return temp; 546 } 547 548 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 549 const struct intel_crtc_state *crtc_state) 550 { 551 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 552 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 553 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 554 555 if (DISPLAY_VER(dev_priv) >= 11) { 556 enum transcoder master_transcoder = crtc_state->master_transcoder; 557 u32 ctl2 = 0; 558 559 if (master_transcoder != INVALID_TRANSCODER) { 560 u8 master_select = 561 bdw_trans_port_sync_master_select(master_transcoder); 562 563 ctl2 |= PORT_SYNC_MODE_ENABLE | 564 PORT_SYNC_MODE_MASTER_SELECT(master_select); 565 } 566 567 intel_de_write(dev_priv, 568 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 569 } 570 571 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 572 intel_ddi_transcoder_func_reg_val_get(encoder, 573 crtc_state)); 574 } 575 576 /* 577 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 578 * bit. 579 */ 580 static void 581 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 582 const struct intel_crtc_state *crtc_state) 583 { 584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 585 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 586 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 587 u32 ctl; 588 589 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 590 ctl &= ~TRANS_DDI_FUNC_ENABLE; 591 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 592 } 593 594 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 595 { 596 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 597 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 598 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 599 u32 ctl; 600 601 if (DISPLAY_VER(dev_priv) >= 11) 602 intel_de_write(dev_priv, 603 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 604 605 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 606 607 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 608 609 ctl &= ~TRANS_DDI_FUNC_ENABLE; 610 611 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 612 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 613 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 614 615 if (DISPLAY_VER(dev_priv) >= 12) { 616 if (!intel_dp_mst_is_master_trans(crtc_state)) { 617 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 618 TRANS_DDI_MODE_SELECT_MASK); 619 } 620 } else { 621 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 622 } 623 624 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 625 626 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 627 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 628 drm_dbg_kms(&dev_priv->drm, 629 "Quirk Increase DDI disabled time\n"); 630 /* Quirk time at 100ms for reliable operation */ 631 msleep(100); 632 } 633 } 634 635 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 636 enum transcoder cpu_transcoder, 637 bool enable, u32 hdcp_mask) 638 { 639 struct drm_device *dev = intel_encoder->base.dev; 640 struct drm_i915_private *dev_priv = to_i915(dev); 641 intel_wakeref_t wakeref; 642 int ret = 0; 643 u32 tmp; 644 645 wakeref = intel_display_power_get_if_enabled(dev_priv, 646 intel_encoder->power_domain); 647 if (drm_WARN_ON(dev, !wakeref)) 648 return -ENXIO; 649 650 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 651 if (enable) 652 tmp |= hdcp_mask; 653 else 654 tmp &= ~hdcp_mask; 655 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 656 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 657 return ret; 658 } 659 660 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 661 { 662 struct drm_device *dev = intel_connector->base.dev; 663 struct drm_i915_private *dev_priv = to_i915(dev); 664 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 665 int type = intel_connector->base.connector_type; 666 enum port port = encoder->port; 667 enum transcoder cpu_transcoder; 668 intel_wakeref_t wakeref; 669 enum pipe pipe = 0; 670 u32 tmp; 671 bool ret; 672 673 wakeref = intel_display_power_get_if_enabled(dev_priv, 674 encoder->power_domain); 675 if (!wakeref) 676 return false; 677 678 if (!encoder->get_hw_state(encoder, &pipe)) { 679 ret = false; 680 goto out; 681 } 682 683 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 684 cpu_transcoder = TRANSCODER_EDP; 685 else 686 cpu_transcoder = (enum transcoder) pipe; 687 688 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 689 690 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 691 case TRANS_DDI_MODE_SELECT_HDMI: 692 case TRANS_DDI_MODE_SELECT_DVI: 693 ret = type == DRM_MODE_CONNECTOR_HDMIA; 694 break; 695 696 case TRANS_DDI_MODE_SELECT_DP_SST: 697 ret = type == DRM_MODE_CONNECTOR_eDP || 698 type == DRM_MODE_CONNECTOR_DisplayPort; 699 break; 700 701 case TRANS_DDI_MODE_SELECT_DP_MST: 702 /* if the transcoder is in MST state then 703 * connector isn't connected */ 704 ret = false; 705 break; 706 707 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 708 if (HAS_DP20(dev_priv)) 709 /* 128b/132b */ 710 ret = false; 711 else 712 /* FDI */ 713 ret = type == DRM_MODE_CONNECTOR_VGA; 714 break; 715 716 default: 717 ret = false; 718 break; 719 } 720 721 out: 722 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 723 724 return ret; 725 } 726 727 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 728 u8 *pipe_mask, bool *is_dp_mst) 729 { 730 struct drm_device *dev = encoder->base.dev; 731 struct drm_i915_private *dev_priv = to_i915(dev); 732 enum port port = encoder->port; 733 intel_wakeref_t wakeref; 734 enum pipe p; 735 u32 tmp; 736 u8 mst_pipe_mask; 737 738 *pipe_mask = 0; 739 *is_dp_mst = false; 740 741 wakeref = intel_display_power_get_if_enabled(dev_priv, 742 encoder->power_domain); 743 if (!wakeref) 744 return; 745 746 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 747 if (!(tmp & DDI_BUF_CTL_ENABLE)) 748 goto out; 749 750 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 751 tmp = intel_de_read(dev_priv, 752 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 753 754 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 755 default: 756 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 757 fallthrough; 758 case TRANS_DDI_EDP_INPUT_A_ON: 759 case TRANS_DDI_EDP_INPUT_A_ONOFF: 760 *pipe_mask = BIT(PIPE_A); 761 break; 762 case TRANS_DDI_EDP_INPUT_B_ONOFF: 763 *pipe_mask = BIT(PIPE_B); 764 break; 765 case TRANS_DDI_EDP_INPUT_C_ONOFF: 766 *pipe_mask = BIT(PIPE_C); 767 break; 768 } 769 770 goto out; 771 } 772 773 mst_pipe_mask = 0; 774 for_each_pipe(dev_priv, p) { 775 enum transcoder cpu_transcoder = (enum transcoder)p; 776 unsigned int port_mask, ddi_select; 777 intel_wakeref_t trans_wakeref; 778 779 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 780 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 781 if (!trans_wakeref) 782 continue; 783 784 if (DISPLAY_VER(dev_priv) >= 12) { 785 port_mask = TGL_TRANS_DDI_PORT_MASK; 786 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 787 } else { 788 port_mask = TRANS_DDI_PORT_MASK; 789 ddi_select = TRANS_DDI_SELECT_PORT(port); 790 } 791 792 tmp = intel_de_read(dev_priv, 793 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 794 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 795 trans_wakeref); 796 797 if ((tmp & port_mask) != ddi_select) 798 continue; 799 800 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 801 (HAS_DP20(dev_priv) && 802 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 803 mst_pipe_mask |= BIT(p); 804 805 *pipe_mask |= BIT(p); 806 } 807 808 if (!*pipe_mask) 809 drm_dbg_kms(&dev_priv->drm, 810 "No pipe for [ENCODER:%d:%s] found\n", 811 encoder->base.base.id, encoder->base.name); 812 813 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 814 drm_dbg_kms(&dev_priv->drm, 815 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 816 encoder->base.base.id, encoder->base.name, 817 *pipe_mask); 818 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 819 } 820 821 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 822 drm_dbg_kms(&dev_priv->drm, 823 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 824 encoder->base.base.id, encoder->base.name, 825 *pipe_mask, mst_pipe_mask); 826 else 827 *is_dp_mst = mst_pipe_mask; 828 829 out: 830 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 831 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 832 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 833 BXT_PHY_LANE_POWERDOWN_ACK | 834 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 835 drm_err(&dev_priv->drm, 836 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 837 encoder->base.base.id, encoder->base.name, tmp); 838 } 839 840 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 841 } 842 843 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 844 enum pipe *pipe) 845 { 846 u8 pipe_mask; 847 bool is_mst; 848 849 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 850 851 if (is_mst || !pipe_mask) 852 return false; 853 854 *pipe = ffs(pipe_mask) - 1; 855 856 return true; 857 } 858 859 static enum intel_display_power_domain 860 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 861 { 862 /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 863 * DC states enabled at the same time, while for driver initiated AUX 864 * transfers we need the same AUX IOs to be powered but with DC states 865 * disabled. Accordingly use the AUX power domain here which leaves DC 866 * states enabled. 867 * However, for non-A AUX ports the corresponding non-EDP transcoders 868 * would have already enabled power well 2 and DC_OFF. This means we can 869 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 870 * specific AUX_IO reference without powering up any extra wells. 871 * Note that PSR is enabled only on Port A even though this function 872 * returns the correct domain for other ports too. 873 */ 874 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 875 intel_aux_power_domain(dig_port); 876 } 877 878 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 879 struct intel_crtc_state *crtc_state) 880 { 881 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 882 struct intel_digital_port *dig_port; 883 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 884 885 /* 886 * TODO: Add support for MST encoders. Atm, the following should never 887 * happen since fake-MST encoders don't set their get_power_domains() 888 * hook. 889 */ 890 if (drm_WARN_ON(&dev_priv->drm, 891 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 892 return; 893 894 dig_port = enc_to_dig_port(encoder); 895 896 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 897 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 898 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 899 dig_port->ddi_io_power_domain); 900 } 901 902 /* 903 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 904 * ports. 905 */ 906 if (intel_crtc_has_dp_encoder(crtc_state) || 907 intel_phy_is_tc(dev_priv, phy)) { 908 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 909 dig_port->aux_wakeref = 910 intel_display_power_get(dev_priv, 911 intel_ddi_main_link_aux_domain(dig_port)); 912 } 913 } 914 915 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 916 const struct intel_crtc_state *crtc_state) 917 { 918 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 919 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 920 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 921 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 922 u32 val; 923 924 if (cpu_transcoder != TRANSCODER_EDP) { 925 if (DISPLAY_VER(dev_priv) >= 13) 926 val = TGL_TRANS_CLK_SEL_PORT(phy); 927 else if (DISPLAY_VER(dev_priv) >= 12) 928 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 929 else 930 val = TRANS_CLK_SEL_PORT(encoder->port); 931 932 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 933 } 934 } 935 936 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 937 { 938 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 939 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 940 941 if (cpu_transcoder != TRANSCODER_EDP) { 942 if (DISPLAY_VER(dev_priv) >= 12) 943 intel_de_write(dev_priv, 944 TRANS_CLK_SEL(cpu_transcoder), 945 TGL_TRANS_CLK_SEL_DISABLED); 946 else 947 intel_de_write(dev_priv, 948 TRANS_CLK_SEL(cpu_transcoder), 949 TRANS_CLK_SEL_DISABLED); 950 } 951 } 952 953 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 954 enum port port, u8 iboost) 955 { 956 u32 tmp; 957 958 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 959 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 960 if (iboost) 961 tmp |= iboost << BALANCE_LEG_SHIFT(port); 962 else 963 tmp |= BALANCE_LEG_DISABLE(port); 964 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 965 } 966 967 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 968 const struct intel_crtc_state *crtc_state, 969 int level) 970 { 971 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 972 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 973 u8 iboost; 974 975 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 976 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); 977 else 978 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); 979 980 if (iboost == 0) { 981 const struct intel_ddi_buf_trans *trans; 982 int n_entries; 983 984 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 985 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 986 return; 987 988 iboost = trans->entries[level].hsw.i_boost; 989 } 990 991 /* Make sure that the requested I_boost is valid */ 992 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 993 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 994 return; 995 } 996 997 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 998 999 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1000 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1001 } 1002 1003 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1004 const struct intel_crtc_state *crtc_state) 1005 { 1006 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1007 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1008 int n_entries; 1009 1010 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1011 1012 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1013 n_entries = 1; 1014 if (drm_WARN_ON(&dev_priv->drm, 1015 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1016 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1017 1018 return index_to_dp_signal_levels[n_entries - 1] & 1019 DP_TRAIN_VOLTAGE_SWING_MASK; 1020 } 1021 1022 /* 1023 * We assume that the full set of pre-emphasis values can be 1024 * used on all DDI platforms. Should that change we need to 1025 * rethink this code. 1026 */ 1027 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1028 { 1029 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1030 } 1031 1032 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1033 int lane) 1034 { 1035 if (crtc_state->port_clock > 600000) 1036 return 0; 1037 1038 if (crtc_state->lane_count == 4) 1039 return lane >= 1 ? LOADGEN_SELECT : 0; 1040 else 1041 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1042 } 1043 1044 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1045 const struct intel_crtc_state *crtc_state) 1046 { 1047 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1048 const struct intel_ddi_buf_trans *trans; 1049 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1050 int n_entries, ln; 1051 u32 val; 1052 1053 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1054 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1055 return; 1056 1057 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1058 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1059 1060 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1061 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1062 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1063 intel_dp->hobl_active ? val : 0); 1064 } 1065 1066 /* Set PORT_TX_DW5 */ 1067 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1068 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1069 TAP2_DISABLE | TAP3_DISABLE); 1070 val |= SCALING_MODE_SEL(0x2); 1071 val |= RTERM_SELECT(0x6); 1072 val |= TAP3_DISABLE; 1073 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1074 1075 /* Program PORT_TX_DW2 */ 1076 for (ln = 0; ln < 4; ln++) { 1077 int level = intel_ddi_level(encoder, crtc_state, ln); 1078 1079 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1080 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1081 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1082 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1083 RCOMP_SCALAR(0x98)); 1084 } 1085 1086 /* Program PORT_TX_DW4 */ 1087 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1088 for (ln = 0; ln < 4; ln++) { 1089 int level = intel_ddi_level(encoder, crtc_state, ln); 1090 1091 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1092 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1093 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1094 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1095 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1096 } 1097 1098 /* Program PORT_TX_DW7 */ 1099 for (ln = 0; ln < 4; ln++) { 1100 int level = intel_ddi_level(encoder, crtc_state, ln); 1101 1102 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1103 N_SCALAR_MASK, 1104 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1105 } 1106 } 1107 1108 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1109 const struct intel_crtc_state *crtc_state) 1110 { 1111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1112 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1113 u32 val; 1114 int ln; 1115 1116 /* 1117 * 1. If port type is eDP or DP, 1118 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1119 * else clear to 0b. 1120 */ 1121 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1122 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1123 val &= ~COMMON_KEEPER_EN; 1124 else 1125 val |= COMMON_KEEPER_EN; 1126 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1127 1128 /* 2. Program loadgen select */ 1129 /* 1130 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1131 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1132 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1133 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1134 */ 1135 for (ln = 0; ln < 4; ln++) { 1136 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1137 LOADGEN_SELECT, 1138 icl_combo_phy_loadgen_select(crtc_state, ln)); 1139 } 1140 1141 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1142 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1143 0, SUS_CLOCK_CONFIG); 1144 1145 /* 4. Clear training enable to change swing values */ 1146 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1147 val &= ~TX_TRAINING_EN; 1148 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1149 1150 /* 5. Program swing and de-emphasis */ 1151 icl_ddi_combo_vswing_program(encoder, crtc_state); 1152 1153 /* 6. Set training enable to trigger update */ 1154 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1155 val |= TX_TRAINING_EN; 1156 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1157 } 1158 1159 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1160 const struct intel_crtc_state *crtc_state) 1161 { 1162 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1163 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1164 const struct intel_ddi_buf_trans *trans; 1165 int n_entries, ln; 1166 1167 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1168 return; 1169 1170 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1171 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1172 return; 1173 1174 for (ln = 0; ln < 2; ln++) { 1175 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1176 CRI_USE_FS32, 0); 1177 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1178 CRI_USE_FS32, 0); 1179 } 1180 1181 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1182 for (ln = 0; ln < 2; ln++) { 1183 int level; 1184 1185 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1186 1187 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1188 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1189 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1190 1191 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1192 1193 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1194 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1195 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1196 } 1197 1198 /* Program MG_TX_DRVCTRL with values from vswing table */ 1199 for (ln = 0; ln < 2; ln++) { 1200 int level; 1201 1202 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1203 1204 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1205 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1206 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1207 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1208 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1209 CRI_TXDEEMPH_OVERRIDE_EN); 1210 1211 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1212 1213 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1214 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1215 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1216 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1217 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1218 CRI_TXDEEMPH_OVERRIDE_EN); 1219 1220 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1221 } 1222 1223 /* 1224 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1225 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1226 * values from table for which TX1 and TX2 enabled. 1227 */ 1228 for (ln = 0; ln < 2; ln++) { 1229 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1230 CFG_LOW_RATE_LKREN_EN, 1231 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1232 } 1233 1234 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1235 for (ln = 0; ln < 2; ln++) { 1236 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1237 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1238 CFG_AMI_CK_DIV_OVERRIDE_EN, 1239 crtc_state->port_clock > 500000 ? 1240 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1241 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1242 1243 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1244 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1245 CFG_AMI_CK_DIV_OVERRIDE_EN, 1246 crtc_state->port_clock > 500000 ? 1247 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1248 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1249 } 1250 1251 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1252 for (ln = 0; ln < 2; ln++) { 1253 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1254 0, CRI_CALCINIT); 1255 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1256 0, CRI_CALCINIT); 1257 } 1258 } 1259 1260 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1261 const struct intel_crtc_state *crtc_state) 1262 { 1263 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1264 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1265 const struct intel_ddi_buf_trans *trans; 1266 int n_entries, ln; 1267 1268 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1269 return; 1270 1271 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1272 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1273 return; 1274 1275 for (ln = 0; ln < 2; ln++) { 1276 int level; 1277 1278 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 1279 HIP_INDEX_VAL(tc_port, ln)); 1280 1281 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 1282 1283 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1284 1285 intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), 1286 DKL_TX_PRESHOOT_COEFF_MASK | 1287 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1288 DKL_TX_VSWING_CONTROL_MASK, 1289 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1290 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1291 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1292 1293 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1294 1295 intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), 1296 DKL_TX_PRESHOOT_COEFF_MASK | 1297 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1298 DKL_TX_VSWING_CONTROL_MASK, 1299 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1300 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1301 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1302 1303 intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), 1304 DKL_TX_DP20BITMODE, 0); 1305 1306 if (IS_ALDERLAKE_P(dev_priv)) { 1307 u32 val; 1308 1309 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1310 if (ln == 0) { 1311 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1312 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1313 } else { 1314 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1315 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1316 } 1317 } else { 1318 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1319 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1320 } 1321 1322 intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), 1323 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1324 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1325 val); 1326 } 1327 } 1328 } 1329 1330 static int translate_signal_level(struct intel_dp *intel_dp, 1331 u8 signal_levels) 1332 { 1333 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1334 int i; 1335 1336 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1337 if (index_to_dp_signal_levels[i] == signal_levels) 1338 return i; 1339 } 1340 1341 drm_WARN(&i915->drm, 1, 1342 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1343 signal_levels); 1344 1345 return 0; 1346 } 1347 1348 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1349 const struct intel_crtc_state *crtc_state, 1350 int lane) 1351 { 1352 u8 train_set = intel_dp->train_set[lane]; 1353 1354 if (intel_dp_is_uhbr(crtc_state)) { 1355 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1356 } else { 1357 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1358 DP_TRAIN_PRE_EMPHASIS_MASK); 1359 1360 return translate_signal_level(intel_dp, signal_levels); 1361 } 1362 } 1363 1364 int intel_ddi_level(struct intel_encoder *encoder, 1365 const struct intel_crtc_state *crtc_state, 1366 int lane) 1367 { 1368 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1369 const struct intel_ddi_buf_trans *trans; 1370 int level, n_entries; 1371 1372 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1373 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1374 return 0; 1375 1376 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1377 level = intel_ddi_hdmi_level(encoder, trans); 1378 else 1379 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1380 lane); 1381 1382 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1383 level = n_entries - 1; 1384 1385 return level; 1386 } 1387 1388 static void 1389 hsw_set_signal_levels(struct intel_encoder *encoder, 1390 const struct intel_crtc_state *crtc_state) 1391 { 1392 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1393 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1394 int level = intel_ddi_level(encoder, crtc_state, 0); 1395 enum port port = encoder->port; 1396 u32 signal_levels; 1397 1398 if (has_iboost(dev_priv)) 1399 skl_ddi_set_iboost(encoder, crtc_state, level); 1400 1401 /* HDMI ignores the rest */ 1402 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1403 return; 1404 1405 signal_levels = DDI_BUF_TRANS_SELECT(level); 1406 1407 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1408 signal_levels); 1409 1410 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1411 intel_dp->DP |= signal_levels; 1412 1413 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1414 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1415 } 1416 1417 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1418 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1419 { 1420 mutex_lock(&i915->dpll.lock); 1421 1422 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1423 1424 /* 1425 * "This step and the step before must be 1426 * done with separate register writes." 1427 */ 1428 intel_de_rmw(i915, reg, clk_off, 0); 1429 1430 mutex_unlock(&i915->dpll.lock); 1431 } 1432 1433 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1434 u32 clk_off) 1435 { 1436 mutex_lock(&i915->dpll.lock); 1437 1438 intel_de_rmw(i915, reg, 0, clk_off); 1439 1440 mutex_unlock(&i915->dpll.lock); 1441 } 1442 1443 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1444 u32 clk_off) 1445 { 1446 return !(intel_de_read(i915, reg) & clk_off); 1447 } 1448 1449 static struct intel_shared_dpll * 1450 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1451 u32 clk_sel_mask, u32 clk_sel_shift) 1452 { 1453 enum intel_dpll_id id; 1454 1455 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1456 1457 return intel_get_shared_dpll_by_id(i915, id); 1458 } 1459 1460 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1461 const struct intel_crtc_state *crtc_state) 1462 { 1463 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1464 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1465 enum phy phy = intel_port_to_phy(i915, encoder->port); 1466 1467 if (drm_WARN_ON(&i915->drm, !pll)) 1468 return; 1469 1470 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1471 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1472 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1473 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1474 } 1475 1476 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1477 { 1478 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1479 enum phy phy = intel_port_to_phy(i915, encoder->port); 1480 1481 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1482 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1483 } 1484 1485 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1486 { 1487 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1488 enum phy phy = intel_port_to_phy(i915, encoder->port); 1489 1490 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1491 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1492 } 1493 1494 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1495 { 1496 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1497 enum phy phy = intel_port_to_phy(i915, encoder->port); 1498 1499 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1500 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1501 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1502 } 1503 1504 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1505 const struct intel_crtc_state *crtc_state) 1506 { 1507 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1508 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1509 enum phy phy = intel_port_to_phy(i915, encoder->port); 1510 1511 if (drm_WARN_ON(&i915->drm, !pll)) 1512 return; 1513 1514 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1515 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1516 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1517 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1518 } 1519 1520 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1521 { 1522 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1523 enum phy phy = intel_port_to_phy(i915, encoder->port); 1524 1525 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1526 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1527 } 1528 1529 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1530 { 1531 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1532 enum phy phy = intel_port_to_phy(i915, encoder->port); 1533 1534 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1535 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1536 } 1537 1538 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1539 { 1540 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1541 enum phy phy = intel_port_to_phy(i915, encoder->port); 1542 1543 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1544 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1545 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1546 } 1547 1548 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1549 const struct intel_crtc_state *crtc_state) 1550 { 1551 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1552 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1553 enum phy phy = intel_port_to_phy(i915, encoder->port); 1554 1555 if (drm_WARN_ON(&i915->drm, !pll)) 1556 return; 1557 1558 /* 1559 * If we fail this, something went very wrong: first 2 PLLs should be 1560 * used by first 2 phys and last 2 PLLs by last phys 1561 */ 1562 if (drm_WARN_ON(&i915->drm, 1563 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1564 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1565 return; 1566 1567 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1568 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1569 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1570 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1571 } 1572 1573 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1574 { 1575 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1576 enum phy phy = intel_port_to_phy(i915, encoder->port); 1577 1578 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1579 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1580 } 1581 1582 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1583 { 1584 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1585 enum phy phy = intel_port_to_phy(i915, encoder->port); 1586 1587 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1588 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1589 } 1590 1591 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1592 { 1593 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1594 enum phy phy = intel_port_to_phy(i915, encoder->port); 1595 enum intel_dpll_id id; 1596 u32 val; 1597 1598 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1599 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1600 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1601 id = val; 1602 1603 /* 1604 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1605 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1606 * bit for phy C and D. 1607 */ 1608 if (phy >= PHY_C) 1609 id += DPLL_ID_DG1_DPLL2; 1610 1611 return intel_get_shared_dpll_by_id(i915, id); 1612 } 1613 1614 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1615 const struct intel_crtc_state *crtc_state) 1616 { 1617 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1618 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1619 enum phy phy = intel_port_to_phy(i915, encoder->port); 1620 1621 if (drm_WARN_ON(&i915->drm, !pll)) 1622 return; 1623 1624 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1625 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1626 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1627 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1628 } 1629 1630 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1631 { 1632 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1633 enum phy phy = intel_port_to_phy(i915, encoder->port); 1634 1635 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1636 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1637 } 1638 1639 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1640 { 1641 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1642 enum phy phy = intel_port_to_phy(i915, encoder->port); 1643 1644 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1645 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1646 } 1647 1648 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1649 { 1650 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1651 enum phy phy = intel_port_to_phy(i915, encoder->port); 1652 1653 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1654 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1655 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1656 } 1657 1658 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1659 const struct intel_crtc_state *crtc_state) 1660 { 1661 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1662 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1663 enum port port = encoder->port; 1664 1665 if (drm_WARN_ON(&i915->drm, !pll)) 1666 return; 1667 1668 /* 1669 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1670 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1671 */ 1672 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1673 1674 icl_ddi_combo_enable_clock(encoder, crtc_state); 1675 } 1676 1677 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1678 { 1679 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1680 enum port port = encoder->port; 1681 1682 icl_ddi_combo_disable_clock(encoder); 1683 1684 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1685 } 1686 1687 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1688 { 1689 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1690 enum port port = encoder->port; 1691 u32 tmp; 1692 1693 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1694 1695 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1696 return false; 1697 1698 return icl_ddi_combo_is_clock_enabled(encoder); 1699 } 1700 1701 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1702 const struct intel_crtc_state *crtc_state) 1703 { 1704 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1705 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1706 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1707 enum port port = encoder->port; 1708 1709 if (drm_WARN_ON(&i915->drm, !pll)) 1710 return; 1711 1712 intel_de_write(i915, DDI_CLK_SEL(port), 1713 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1714 1715 mutex_lock(&i915->dpll.lock); 1716 1717 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1718 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1719 1720 mutex_unlock(&i915->dpll.lock); 1721 } 1722 1723 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1724 { 1725 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1726 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1727 enum port port = encoder->port; 1728 1729 mutex_lock(&i915->dpll.lock); 1730 1731 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1732 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1733 1734 mutex_unlock(&i915->dpll.lock); 1735 1736 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1737 } 1738 1739 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1740 { 1741 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1742 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1743 enum port port = encoder->port; 1744 u32 tmp; 1745 1746 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1747 1748 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1749 return false; 1750 1751 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1752 1753 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1754 } 1755 1756 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1757 { 1758 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1759 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1760 enum port port = encoder->port; 1761 enum intel_dpll_id id; 1762 u32 tmp; 1763 1764 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1765 1766 switch (tmp & DDI_CLK_SEL_MASK) { 1767 case DDI_CLK_SEL_TBT_162: 1768 case DDI_CLK_SEL_TBT_270: 1769 case DDI_CLK_SEL_TBT_540: 1770 case DDI_CLK_SEL_TBT_810: 1771 id = DPLL_ID_ICL_TBTPLL; 1772 break; 1773 case DDI_CLK_SEL_MG: 1774 id = icl_tc_port_to_pll_id(tc_port); 1775 break; 1776 default: 1777 MISSING_CASE(tmp); 1778 fallthrough; 1779 case DDI_CLK_SEL_NONE: 1780 return NULL; 1781 } 1782 1783 return intel_get_shared_dpll_by_id(i915, id); 1784 } 1785 1786 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1787 { 1788 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1789 enum intel_dpll_id id; 1790 1791 switch (encoder->port) { 1792 case PORT_A: 1793 id = DPLL_ID_SKL_DPLL0; 1794 break; 1795 case PORT_B: 1796 id = DPLL_ID_SKL_DPLL1; 1797 break; 1798 case PORT_C: 1799 id = DPLL_ID_SKL_DPLL2; 1800 break; 1801 default: 1802 MISSING_CASE(encoder->port); 1803 return NULL; 1804 } 1805 1806 return intel_get_shared_dpll_by_id(i915, id); 1807 } 1808 1809 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1810 const struct intel_crtc_state *crtc_state) 1811 { 1812 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1813 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1814 enum port port = encoder->port; 1815 1816 if (drm_WARN_ON(&i915->drm, !pll)) 1817 return; 1818 1819 mutex_lock(&i915->dpll.lock); 1820 1821 intel_de_rmw(i915, DPLL_CTRL2, 1822 DPLL_CTRL2_DDI_CLK_OFF(port) | 1823 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1824 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1825 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1826 1827 mutex_unlock(&i915->dpll.lock); 1828 } 1829 1830 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1831 { 1832 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1833 enum port port = encoder->port; 1834 1835 mutex_lock(&i915->dpll.lock); 1836 1837 intel_de_rmw(i915, DPLL_CTRL2, 1838 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1839 1840 mutex_unlock(&i915->dpll.lock); 1841 } 1842 1843 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1844 { 1845 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1846 enum port port = encoder->port; 1847 1848 /* 1849 * FIXME Not sure if the override affects both 1850 * the PLL selection and the CLK_OFF bit. 1851 */ 1852 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1853 } 1854 1855 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1856 { 1857 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1858 enum port port = encoder->port; 1859 enum intel_dpll_id id; 1860 u32 tmp; 1861 1862 tmp = intel_de_read(i915, DPLL_CTRL2); 1863 1864 /* 1865 * FIXME Not sure if the override affects both 1866 * the PLL selection and the CLK_OFF bit. 1867 */ 1868 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1869 return NULL; 1870 1871 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1872 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1873 1874 return intel_get_shared_dpll_by_id(i915, id); 1875 } 1876 1877 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1878 const struct intel_crtc_state *crtc_state) 1879 { 1880 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1881 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1882 enum port port = encoder->port; 1883 1884 if (drm_WARN_ON(&i915->drm, !pll)) 1885 return; 1886 1887 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1888 } 1889 1890 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1891 { 1892 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1893 enum port port = encoder->port; 1894 1895 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1896 } 1897 1898 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1899 { 1900 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1901 enum port port = encoder->port; 1902 1903 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1904 } 1905 1906 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1907 { 1908 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1909 enum port port = encoder->port; 1910 enum intel_dpll_id id; 1911 u32 tmp; 1912 1913 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1914 1915 switch (tmp & PORT_CLK_SEL_MASK) { 1916 case PORT_CLK_SEL_WRPLL1: 1917 id = DPLL_ID_WRPLL1; 1918 break; 1919 case PORT_CLK_SEL_WRPLL2: 1920 id = DPLL_ID_WRPLL2; 1921 break; 1922 case PORT_CLK_SEL_SPLL: 1923 id = DPLL_ID_SPLL; 1924 break; 1925 case PORT_CLK_SEL_LCPLL_810: 1926 id = DPLL_ID_LCPLL_810; 1927 break; 1928 case PORT_CLK_SEL_LCPLL_1350: 1929 id = DPLL_ID_LCPLL_1350; 1930 break; 1931 case PORT_CLK_SEL_LCPLL_2700: 1932 id = DPLL_ID_LCPLL_2700; 1933 break; 1934 default: 1935 MISSING_CASE(tmp); 1936 fallthrough; 1937 case PORT_CLK_SEL_NONE: 1938 return NULL; 1939 } 1940 1941 return intel_get_shared_dpll_by_id(i915, id); 1942 } 1943 1944 void intel_ddi_enable_clock(struct intel_encoder *encoder, 1945 const struct intel_crtc_state *crtc_state) 1946 { 1947 if (encoder->enable_clock) 1948 encoder->enable_clock(encoder, crtc_state); 1949 } 1950 1951 void intel_ddi_disable_clock(struct intel_encoder *encoder) 1952 { 1953 if (encoder->disable_clock) 1954 encoder->disable_clock(encoder); 1955 } 1956 1957 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 1958 { 1959 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1960 u32 port_mask; 1961 bool ddi_clk_needed; 1962 1963 /* 1964 * In case of DP MST, we sanitize the primary encoder only, not the 1965 * virtual ones. 1966 */ 1967 if (encoder->type == INTEL_OUTPUT_DP_MST) 1968 return; 1969 1970 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 1971 u8 pipe_mask; 1972 bool is_mst; 1973 1974 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 1975 /* 1976 * In the unlikely case that BIOS enables DP in MST mode, just 1977 * warn since our MST HW readout is incomplete. 1978 */ 1979 if (drm_WARN_ON(&i915->drm, is_mst)) 1980 return; 1981 } 1982 1983 port_mask = BIT(encoder->port); 1984 ddi_clk_needed = encoder->base.crtc; 1985 1986 if (encoder->type == INTEL_OUTPUT_DSI) { 1987 struct intel_encoder *other_encoder; 1988 1989 port_mask = intel_dsi_encoder_ports(encoder); 1990 /* 1991 * Sanity check that we haven't incorrectly registered another 1992 * encoder using any of the ports of this DSI encoder. 1993 */ 1994 for_each_intel_encoder(&i915->drm, other_encoder) { 1995 if (other_encoder == encoder) 1996 continue; 1997 1998 if (drm_WARN_ON(&i915->drm, 1999 port_mask & BIT(other_encoder->port))) 2000 return; 2001 } 2002 /* 2003 * For DSI we keep the ddi clocks gated 2004 * except during enable/disable sequence. 2005 */ 2006 ddi_clk_needed = false; 2007 } 2008 2009 if (ddi_clk_needed || !encoder->is_clock_enabled || 2010 !encoder->is_clock_enabled(encoder)) 2011 return; 2012 2013 drm_notice(&i915->drm, 2014 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2015 encoder->base.base.id, encoder->base.name); 2016 2017 encoder->disable_clock(encoder); 2018 } 2019 2020 static void 2021 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2022 const struct intel_crtc_state *crtc_state) 2023 { 2024 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2025 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2026 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2027 u32 ln0, ln1, pin_assignment; 2028 u8 width; 2029 2030 if (!intel_phy_is_tc(dev_priv, phy) || 2031 intel_tc_port_in_tbt_alt_mode(dig_port)) 2032 return; 2033 2034 if (DISPLAY_VER(dev_priv) >= 12) { 2035 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2036 HIP_INDEX_VAL(tc_port, 0x0)); 2037 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2038 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2039 HIP_INDEX_VAL(tc_port, 0x1)); 2040 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2041 } else { 2042 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2043 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2044 } 2045 2046 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2047 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2048 2049 /* DPPATC */ 2050 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2051 width = crtc_state->lane_count; 2052 2053 switch (pin_assignment) { 2054 case 0x0: 2055 drm_WARN_ON(&dev_priv->drm, 2056 !intel_tc_port_in_legacy_mode(dig_port)); 2057 if (width == 1) { 2058 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2059 } else { 2060 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2061 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2062 } 2063 break; 2064 case 0x1: 2065 if (width == 4) { 2066 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2067 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2068 } 2069 break; 2070 case 0x2: 2071 if (width == 2) { 2072 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2073 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2074 } 2075 break; 2076 case 0x3: 2077 case 0x5: 2078 if (width == 1) { 2079 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2080 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2081 } else { 2082 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2083 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2084 } 2085 break; 2086 case 0x4: 2087 case 0x6: 2088 if (width == 1) { 2089 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2090 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2091 } else { 2092 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2093 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2094 } 2095 break; 2096 default: 2097 MISSING_CASE(pin_assignment); 2098 } 2099 2100 if (DISPLAY_VER(dev_priv) >= 12) { 2101 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2102 HIP_INDEX_VAL(tc_port, 0x0)); 2103 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 2104 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2105 HIP_INDEX_VAL(tc_port, 0x1)); 2106 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 2107 } else { 2108 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2109 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2110 } 2111 } 2112 2113 static enum transcoder 2114 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2115 { 2116 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2117 return crtc_state->mst_master_transcoder; 2118 else 2119 return crtc_state->cpu_transcoder; 2120 } 2121 2122 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2123 const struct intel_crtc_state *crtc_state) 2124 { 2125 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2126 2127 if (DISPLAY_VER(dev_priv) >= 12) 2128 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2129 else 2130 return DP_TP_CTL(encoder->port); 2131 } 2132 2133 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2134 const struct intel_crtc_state *crtc_state) 2135 { 2136 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2137 2138 if (DISPLAY_VER(dev_priv) >= 12) 2139 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2140 else 2141 return DP_TP_STATUS(encoder->port); 2142 } 2143 2144 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2145 const struct intel_crtc_state *crtc_state, 2146 bool enable) 2147 { 2148 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2149 2150 if (!crtc_state->vrr.enable) 2151 return; 2152 2153 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2154 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2155 drm_dbg_kms(&i915->drm, 2156 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2157 str_enable_disable(enable)); 2158 } 2159 2160 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2161 const struct intel_crtc_state *crtc_state) 2162 { 2163 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2164 2165 if (!crtc_state->fec_enable) 2166 return; 2167 2168 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2169 drm_dbg_kms(&i915->drm, 2170 "Failed to set FEC_READY in the sink\n"); 2171 } 2172 2173 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2174 const struct intel_crtc_state *crtc_state) 2175 { 2176 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2177 struct intel_dp *intel_dp; 2178 u32 val; 2179 2180 if (!crtc_state->fec_enable) 2181 return; 2182 2183 intel_dp = enc_to_intel_dp(encoder); 2184 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2185 val |= DP_TP_CTL_FEC_ENABLE; 2186 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2187 } 2188 2189 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2190 const struct intel_crtc_state *crtc_state) 2191 { 2192 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2193 struct intel_dp *intel_dp; 2194 u32 val; 2195 2196 if (!crtc_state->fec_enable) 2197 return; 2198 2199 intel_dp = enc_to_intel_dp(encoder); 2200 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2201 val &= ~DP_TP_CTL_FEC_ENABLE; 2202 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2203 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2204 } 2205 2206 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2207 const struct intel_crtc_state *crtc_state) 2208 { 2209 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2210 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2211 enum phy phy = intel_port_to_phy(i915, encoder->port); 2212 2213 if (intel_phy_is_combo(i915, phy)) { 2214 bool lane_reversal = 2215 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2216 2217 intel_combo_phy_power_up_lanes(i915, phy, false, 2218 crtc_state->lane_count, 2219 lane_reversal); 2220 } 2221 } 2222 2223 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2224 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2225 { 2226 if (IS_ALDERLAKE_P(i915)) 2227 return BIT(PIPE_A) | BIT(PIPE_B); 2228 else 2229 return BIT(PIPE_A); 2230 } 2231 2232 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2233 struct intel_crtc_state *pipe_config) 2234 { 2235 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2236 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2237 enum pipe pipe = crtc->pipe; 2238 u32 dss1; 2239 2240 if (!HAS_MSO(i915)) 2241 return; 2242 2243 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2244 2245 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2246 if (!pipe_config->splitter.enable) 2247 return; 2248 2249 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2250 pipe_config->splitter.enable = false; 2251 return; 2252 } 2253 2254 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2255 default: 2256 drm_WARN(&i915->drm, true, 2257 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2258 fallthrough; 2259 case SPLITTER_CONFIGURATION_2_SEGMENT: 2260 pipe_config->splitter.link_count = 2; 2261 break; 2262 case SPLITTER_CONFIGURATION_4_SEGMENT: 2263 pipe_config->splitter.link_count = 4; 2264 break; 2265 } 2266 2267 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2268 } 2269 2270 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2271 { 2272 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2273 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2274 enum pipe pipe = crtc->pipe; 2275 u32 dss1 = 0; 2276 2277 if (!HAS_MSO(i915)) 2278 return; 2279 2280 if (crtc_state->splitter.enable) { 2281 dss1 |= SPLITTER_ENABLE; 2282 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2283 if (crtc_state->splitter.link_count == 2) 2284 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2285 else 2286 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2287 } 2288 2289 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2290 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2291 OVERLAP_PIXELS_MASK, dss1); 2292 } 2293 2294 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2295 struct intel_encoder *encoder, 2296 const struct intel_crtc_state *crtc_state, 2297 const struct drm_connector_state *conn_state) 2298 { 2299 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2301 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2302 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2303 2304 intel_dp_set_link_params(intel_dp, 2305 crtc_state->port_clock, 2306 crtc_state->lane_count); 2307 2308 /* 2309 * We only configure what the register value will be here. Actual 2310 * enabling happens during link training farther down. 2311 */ 2312 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2313 2314 /* 2315 * 1. Enable Power Wells 2316 * 2317 * This was handled at the beginning of intel_atomic_commit_tail(), 2318 * before we called down into this function. 2319 */ 2320 2321 /* 2. Enable Panel Power if PPS is required */ 2322 intel_pps_on(intel_dp); 2323 2324 /* 2325 * 3. For non-TBT Type-C ports, set FIA lane count 2326 * (DFLEXDPSP.DPX4TXLATC) 2327 * 2328 * This was done before tgl_ddi_pre_enable_dp by 2329 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2330 */ 2331 2332 /* 2333 * 4. Enable the port PLL. 2334 * 2335 * The PLL enabling itself was already done before this function by 2336 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2337 * configure the PLL to port mapping here. 2338 */ 2339 intel_ddi_enable_clock(encoder, crtc_state); 2340 2341 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2342 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2343 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2344 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2345 dig_port->ddi_io_power_domain); 2346 } 2347 2348 /* 6. Program DP_MODE */ 2349 icl_program_mg_dp_mode(dig_port, crtc_state); 2350 2351 /* 2352 * 7. The rest of the below are substeps under the bspec's "Enable and 2353 * Train Display Port" step. Note that steps that are specific to 2354 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2355 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2356 * us when active_mst_links==0, so any steps designated for "single 2357 * stream or multi-stream master transcoder" can just be performed 2358 * unconditionally here. 2359 */ 2360 2361 /* 2362 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2363 * Transcoder. 2364 */ 2365 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2366 2367 if (HAS_DP20(dev_priv)) 2368 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2369 2370 /* 2371 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2372 * Transport Select 2373 */ 2374 intel_ddi_config_transcoder_func(encoder, crtc_state); 2375 2376 /* 2377 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2378 * selected 2379 * 2380 * This will be handled by the intel_dp_start_link_train() farther 2381 * down this function. 2382 */ 2383 2384 /* 7.e Configure voltage swing and related IO settings */ 2385 encoder->set_signal_levels(encoder, crtc_state); 2386 2387 /* 2388 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2389 * the used lanes of the DDI. 2390 */ 2391 intel_ddi_power_up_lanes(encoder, crtc_state); 2392 2393 /* 2394 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2395 */ 2396 intel_ddi_mso_configure(crtc_state); 2397 2398 if (!is_mst) 2399 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2400 2401 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2402 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2403 /* 2404 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2405 * in the FEC_CONFIGURATION register to 1 before initiating link 2406 * training 2407 */ 2408 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2409 2410 intel_dp_check_frl_training(intel_dp); 2411 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2412 2413 /* 2414 * 7.i Follow DisplayPort specification training sequence (see notes for 2415 * failure handling) 2416 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2417 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2418 * (timeout after 800 us) 2419 */ 2420 intel_dp_start_link_train(intel_dp, crtc_state); 2421 2422 /* 7.k Set DP_TP_CTL link training to Normal */ 2423 if (!is_trans_port_sync_mode(crtc_state)) 2424 intel_dp_stop_link_train(intel_dp, crtc_state); 2425 2426 /* 7.l Configure and enable FEC if needed */ 2427 intel_ddi_enable_fec(encoder, crtc_state); 2428 2429 intel_dsc_dp_pps_write(encoder, crtc_state); 2430 } 2431 2432 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2433 struct intel_encoder *encoder, 2434 const struct intel_crtc_state *crtc_state, 2435 const struct drm_connector_state *conn_state) 2436 { 2437 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2438 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2439 enum port port = encoder->port; 2440 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2441 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2442 2443 if (DISPLAY_VER(dev_priv) < 11) 2444 drm_WARN_ON(&dev_priv->drm, 2445 is_mst && (port == PORT_A || port == PORT_E)); 2446 else 2447 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2448 2449 intel_dp_set_link_params(intel_dp, 2450 crtc_state->port_clock, 2451 crtc_state->lane_count); 2452 2453 /* 2454 * We only configure what the register value will be here. Actual 2455 * enabling happens during link training farther down. 2456 */ 2457 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2458 2459 intel_pps_on(intel_dp); 2460 2461 intel_ddi_enable_clock(encoder, crtc_state); 2462 2463 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2464 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2465 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2466 dig_port->ddi_io_power_domain); 2467 } 2468 2469 icl_program_mg_dp_mode(dig_port, crtc_state); 2470 2471 if (has_buf_trans_select(dev_priv)) 2472 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2473 2474 encoder->set_signal_levels(encoder, crtc_state); 2475 2476 intel_ddi_power_up_lanes(encoder, crtc_state); 2477 2478 if (!is_mst) 2479 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2480 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2481 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2482 true); 2483 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2484 intel_dp_start_link_train(intel_dp, crtc_state); 2485 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2486 !is_trans_port_sync_mode(crtc_state)) 2487 intel_dp_stop_link_train(intel_dp, crtc_state); 2488 2489 intel_ddi_enable_fec(encoder, crtc_state); 2490 2491 if (!is_mst) 2492 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2493 2494 intel_dsc_dp_pps_write(encoder, crtc_state); 2495 } 2496 2497 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2498 struct intel_encoder *encoder, 2499 const struct intel_crtc_state *crtc_state, 2500 const struct drm_connector_state *conn_state) 2501 { 2502 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2503 2504 if (DISPLAY_VER(dev_priv) >= 12) 2505 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2506 else 2507 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2508 2509 /* MST will call a setting of MSA after an allocating of Virtual Channel 2510 * from MST encoder pre_enable callback. 2511 */ 2512 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2513 intel_ddi_set_dp_msa(crtc_state, conn_state); 2514 } 2515 2516 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2517 struct intel_encoder *encoder, 2518 const struct intel_crtc_state *crtc_state, 2519 const struct drm_connector_state *conn_state) 2520 { 2521 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2522 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2523 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2524 2525 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2526 intel_ddi_enable_clock(encoder, crtc_state); 2527 2528 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2529 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2530 dig_port->ddi_io_power_domain); 2531 2532 icl_program_mg_dp_mode(dig_port, crtc_state); 2533 2534 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2535 2536 dig_port->set_infoframes(encoder, 2537 crtc_state->has_infoframe, 2538 crtc_state, conn_state); 2539 } 2540 2541 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2542 struct intel_encoder *encoder, 2543 const struct intel_crtc_state *crtc_state, 2544 const struct drm_connector_state *conn_state) 2545 { 2546 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2547 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2548 enum pipe pipe = crtc->pipe; 2549 2550 /* 2551 * When called from DP MST code: 2552 * - conn_state will be NULL 2553 * - encoder will be the main encoder (ie. mst->primary) 2554 * - the main connector associated with this port 2555 * won't be active or linked to a crtc 2556 * - crtc_state will be the state of the first stream to 2557 * be activated on this port, and it may not be the same 2558 * stream that will be deactivated last, but each stream 2559 * should have a state that is identical when it comes to 2560 * the DP link parameteres 2561 */ 2562 2563 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2564 2565 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2566 2567 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2568 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2569 conn_state); 2570 } else { 2571 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2572 2573 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2574 conn_state); 2575 2576 /* FIXME precompute everything properly */ 2577 /* FIXME how do we turn infoframes off again? */ 2578 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2579 dig_port->set_infoframes(encoder, 2580 crtc_state->has_infoframe, 2581 crtc_state, conn_state); 2582 } 2583 } 2584 2585 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2586 const struct intel_crtc_state *crtc_state) 2587 { 2588 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2589 enum port port = encoder->port; 2590 bool wait = false; 2591 u32 val; 2592 2593 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2594 if (val & DDI_BUF_CTL_ENABLE) { 2595 val &= ~DDI_BUF_CTL_ENABLE; 2596 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2597 wait = true; 2598 } 2599 2600 if (intel_crtc_has_dp_encoder(crtc_state)) { 2601 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2602 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2603 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2604 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2605 } 2606 2607 /* Disable FEC in DP Sink */ 2608 intel_ddi_disable_fec_state(encoder, crtc_state); 2609 2610 if (wait) 2611 intel_wait_ddi_buf_idle(dev_priv, port); 2612 } 2613 2614 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2615 struct intel_encoder *encoder, 2616 const struct intel_crtc_state *old_crtc_state, 2617 const struct drm_connector_state *old_conn_state) 2618 { 2619 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2620 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2621 struct intel_dp *intel_dp = &dig_port->dp; 2622 bool is_mst = intel_crtc_has_type(old_crtc_state, 2623 INTEL_OUTPUT_DP_MST); 2624 2625 if (!is_mst) 2626 intel_dp_set_infoframes(encoder, false, 2627 old_crtc_state, old_conn_state); 2628 2629 /* 2630 * Power down sink before disabling the port, otherwise we end 2631 * up getting interrupts from the sink on detecting link loss. 2632 */ 2633 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2634 2635 if (DISPLAY_VER(dev_priv) >= 12) { 2636 if (is_mst) { 2637 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2638 u32 val; 2639 2640 val = intel_de_read(dev_priv, 2641 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2642 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2643 TRANS_DDI_MODE_SELECT_MASK); 2644 intel_de_write(dev_priv, 2645 TRANS_DDI_FUNC_CTL(cpu_transcoder), 2646 val); 2647 } 2648 } else { 2649 if (!is_mst) 2650 intel_ddi_disable_pipe_clock(old_crtc_state); 2651 } 2652 2653 intel_disable_ddi_buf(encoder, old_crtc_state); 2654 2655 /* 2656 * From TGL spec: "If single stream or multi-stream master transcoder: 2657 * Configure Transcoder Clock select to direct no clock to the 2658 * transcoder" 2659 */ 2660 if (DISPLAY_VER(dev_priv) >= 12) 2661 intel_ddi_disable_pipe_clock(old_crtc_state); 2662 2663 intel_pps_vdd_on(intel_dp); 2664 intel_pps_off(intel_dp); 2665 2666 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 2667 intel_display_power_put(dev_priv, 2668 dig_port->ddi_io_power_domain, 2669 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2670 2671 intel_ddi_disable_clock(encoder); 2672 } 2673 2674 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2675 struct intel_encoder *encoder, 2676 const struct intel_crtc_state *old_crtc_state, 2677 const struct drm_connector_state *old_conn_state) 2678 { 2679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2680 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2681 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2682 2683 dig_port->set_infoframes(encoder, false, 2684 old_crtc_state, old_conn_state); 2685 2686 intel_ddi_disable_pipe_clock(old_crtc_state); 2687 2688 intel_disable_ddi_buf(encoder, old_crtc_state); 2689 2690 intel_display_power_put(dev_priv, 2691 dig_port->ddi_io_power_domain, 2692 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2693 2694 intel_ddi_disable_clock(encoder); 2695 2696 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2697 } 2698 2699 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2700 struct intel_encoder *encoder, 2701 const struct intel_crtc_state *old_crtc_state, 2702 const struct drm_connector_state *old_conn_state) 2703 { 2704 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2705 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2706 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2707 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2708 struct intel_crtc *slave_crtc; 2709 2710 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2711 intel_crtc_vblank_off(old_crtc_state); 2712 2713 intel_disable_transcoder(old_crtc_state); 2714 2715 intel_vrr_disable(old_crtc_state); 2716 2717 intel_ddi_disable_transcoder_func(old_crtc_state); 2718 2719 intel_dsc_disable(old_crtc_state); 2720 2721 if (DISPLAY_VER(dev_priv) >= 9) 2722 skl_scaler_disable(old_crtc_state); 2723 else 2724 ilk_pfit_disable(old_crtc_state); 2725 } 2726 2727 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 2728 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) { 2729 const struct intel_crtc_state *old_slave_crtc_state = 2730 intel_atomic_get_old_crtc_state(state, slave_crtc); 2731 2732 intel_crtc_vblank_off(old_slave_crtc_state); 2733 2734 intel_dsc_disable(old_slave_crtc_state); 2735 skl_scaler_disable(old_slave_crtc_state); 2736 } 2737 2738 /* 2739 * When called from DP MST code: 2740 * - old_conn_state will be NULL 2741 * - encoder will be the main encoder (ie. mst->primary) 2742 * - the main connector associated with this port 2743 * won't be active or linked to a crtc 2744 * - old_crtc_state will be the state of the last stream to 2745 * be deactivated on this port, and it may not be the same 2746 * stream that was activated last, but each stream 2747 * should have a state that is identical when it comes to 2748 * the DP link parameteres 2749 */ 2750 2751 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2752 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2753 old_conn_state); 2754 else 2755 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2756 old_conn_state); 2757 2758 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 2759 intel_display_power_put(dev_priv, 2760 intel_ddi_main_link_aux_domain(dig_port), 2761 fetch_and_zero(&dig_port->aux_wakeref)); 2762 2763 if (is_tc_port) 2764 intel_tc_port_put_link(dig_port); 2765 } 2766 2767 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 2768 struct intel_encoder *encoder, 2769 const struct intel_crtc_state *crtc_state) 2770 { 2771 const struct drm_connector_state *conn_state; 2772 struct drm_connector *conn; 2773 int i; 2774 2775 if (!crtc_state->sync_mode_slaves_mask) 2776 return; 2777 2778 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 2779 struct intel_encoder *slave_encoder = 2780 to_intel_encoder(conn_state->best_encoder); 2781 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 2782 const struct intel_crtc_state *slave_crtc_state; 2783 2784 if (!slave_crtc) 2785 continue; 2786 2787 slave_crtc_state = 2788 intel_atomic_get_new_crtc_state(state, slave_crtc); 2789 2790 if (slave_crtc_state->master_transcoder != 2791 crtc_state->cpu_transcoder) 2792 continue; 2793 2794 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 2795 slave_crtc_state); 2796 } 2797 2798 usleep_range(200, 400); 2799 2800 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 2801 crtc_state); 2802 } 2803 2804 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 2805 struct intel_encoder *encoder, 2806 const struct intel_crtc_state *crtc_state, 2807 const struct drm_connector_state *conn_state) 2808 { 2809 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2810 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2811 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2812 enum port port = encoder->port; 2813 2814 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 2815 intel_dp_stop_link_train(intel_dp, crtc_state); 2816 2817 drm_connector_update_privacy_screen(conn_state); 2818 intel_edp_backlight_on(crtc_state, conn_state); 2819 2820 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 2821 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 2822 2823 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2824 2825 trans_port_sync_stop_link_train(state, encoder, crtc_state); 2826 } 2827 2828 static i915_reg_t 2829 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 2830 enum port port) 2831 { 2832 static const enum transcoder trans[] = { 2833 [PORT_A] = TRANSCODER_EDP, 2834 [PORT_B] = TRANSCODER_A, 2835 [PORT_C] = TRANSCODER_B, 2836 [PORT_D] = TRANSCODER_C, 2837 [PORT_E] = TRANSCODER_A, 2838 }; 2839 2840 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 2841 2842 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 2843 port = PORT_A; 2844 2845 return CHICKEN_TRANS(trans[port]); 2846 } 2847 2848 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 2849 struct intel_encoder *encoder, 2850 const struct intel_crtc_state *crtc_state, 2851 const struct drm_connector_state *conn_state) 2852 { 2853 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2854 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2855 struct drm_connector *connector = conn_state->connector; 2856 enum port port = encoder->port; 2857 2858 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2859 crtc_state->hdmi_high_tmds_clock_ratio, 2860 crtc_state->hdmi_scrambling)) 2861 drm_dbg_kms(&dev_priv->drm, 2862 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 2863 connector->base.id, connector->name); 2864 2865 if (has_buf_trans_select(dev_priv)) 2866 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 2867 2868 encoder->set_signal_levels(encoder, crtc_state); 2869 2870 /* Display WA #1143: skl,kbl,cfl */ 2871 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 2872 /* 2873 * For some reason these chicken bits have been 2874 * stuffed into a transcoder register, event though 2875 * the bits affect a specific DDI port rather than 2876 * a specific transcoder. 2877 */ 2878 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 2879 u32 val; 2880 2881 val = intel_de_read(dev_priv, reg); 2882 2883 if (port == PORT_E) 2884 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 2885 DDIE_TRAINING_OVERRIDE_VALUE; 2886 else 2887 val |= DDI_TRAINING_OVERRIDE_ENABLE | 2888 DDI_TRAINING_OVERRIDE_VALUE; 2889 2890 intel_de_write(dev_priv, reg, val); 2891 intel_de_posting_read(dev_priv, reg); 2892 2893 udelay(1); 2894 2895 if (port == PORT_E) 2896 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 2897 DDIE_TRAINING_OVERRIDE_VALUE); 2898 else 2899 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 2900 DDI_TRAINING_OVERRIDE_VALUE); 2901 2902 intel_de_write(dev_priv, reg, val); 2903 } 2904 2905 intel_ddi_power_up_lanes(encoder, crtc_state); 2906 2907 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2908 * are ignored so nothing special needs to be done besides 2909 * enabling the port. 2910 * 2911 * On ADL_P the PHY link rate and lane count must be programmed but 2912 * these are both 0 for HDMI. 2913 */ 2914 intel_de_write(dev_priv, DDI_BUF_CTL(port), 2915 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 2916 2917 intel_audio_codec_enable(encoder, crtc_state, conn_state); 2918 } 2919 2920 static void intel_enable_ddi(struct intel_atomic_state *state, 2921 struct intel_encoder *encoder, 2922 const struct intel_crtc_state *crtc_state, 2923 const struct drm_connector_state *conn_state) 2924 { 2925 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 2926 2927 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 2928 intel_ddi_enable_transcoder_func(encoder, crtc_state); 2929 2930 intel_vrr_enable(encoder, crtc_state); 2931 2932 intel_enable_transcoder(crtc_state); 2933 2934 intel_crtc_vblank_on(crtc_state); 2935 2936 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2937 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 2938 else 2939 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 2940 2941 /* Enable hdcp if it's desired */ 2942 if (conn_state->content_protection == 2943 DRM_MODE_CONTENT_PROTECTION_DESIRED) 2944 intel_hdcp_enable(to_intel_connector(conn_state->connector), 2945 crtc_state, 2946 (u8)conn_state->hdcp_content_type); 2947 } 2948 2949 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 2950 struct intel_encoder *encoder, 2951 const struct intel_crtc_state *old_crtc_state, 2952 const struct drm_connector_state *old_conn_state) 2953 { 2954 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2955 2956 intel_dp->link_trained = false; 2957 2958 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 2959 2960 intel_psr_disable(intel_dp, old_crtc_state); 2961 intel_edp_backlight_off(old_conn_state); 2962 /* Disable the decompression in DP Sink */ 2963 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 2964 false); 2965 /* Disable Ignore_MSA bit in DP Sink */ 2966 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 2967 false); 2968 } 2969 2970 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 2971 struct intel_encoder *encoder, 2972 const struct intel_crtc_state *old_crtc_state, 2973 const struct drm_connector_state *old_conn_state) 2974 { 2975 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2976 struct drm_connector *connector = old_conn_state->connector; 2977 2978 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 2979 2980 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 2981 false, false)) 2982 drm_dbg_kms(&i915->drm, 2983 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 2984 connector->base.id, connector->name); 2985 } 2986 2987 static void intel_disable_ddi(struct intel_atomic_state *state, 2988 struct intel_encoder *encoder, 2989 const struct intel_crtc_state *old_crtc_state, 2990 const struct drm_connector_state *old_conn_state) 2991 { 2992 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 2993 2994 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2995 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 2996 old_conn_state); 2997 else 2998 intel_disable_ddi_dp(state, encoder, old_crtc_state, 2999 old_conn_state); 3000 } 3001 3002 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3003 struct intel_encoder *encoder, 3004 const struct intel_crtc_state *crtc_state, 3005 const struct drm_connector_state *conn_state) 3006 { 3007 intel_ddi_set_dp_msa(crtc_state, conn_state); 3008 3009 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3010 3011 intel_backlight_update(state, encoder, crtc_state, conn_state); 3012 drm_connector_update_privacy_screen(conn_state); 3013 } 3014 3015 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3016 struct intel_encoder *encoder, 3017 const struct intel_crtc_state *crtc_state, 3018 const struct drm_connector_state *conn_state) 3019 { 3020 3021 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3022 !intel_encoder_is_mst(encoder)) 3023 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3024 conn_state); 3025 3026 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3027 } 3028 3029 static void 3030 intel_ddi_update_prepare(struct intel_atomic_state *state, 3031 struct intel_encoder *encoder, 3032 struct intel_crtc *crtc) 3033 { 3034 struct drm_i915_private *i915 = to_i915(state->base.dev); 3035 struct intel_crtc_state *crtc_state = 3036 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3037 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3038 3039 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3040 3041 intel_tc_port_get_link(enc_to_dig_port(encoder), 3042 required_lanes); 3043 if (crtc_state && crtc_state->hw.active) { 3044 struct intel_crtc *slave_crtc; 3045 3046 intel_update_active_dpll(state, crtc, encoder); 3047 3048 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 3049 intel_crtc_bigjoiner_slave_pipes(crtc_state)) 3050 intel_update_active_dpll(state, slave_crtc, encoder); 3051 } 3052 } 3053 3054 static void 3055 intel_ddi_update_complete(struct intel_atomic_state *state, 3056 struct intel_encoder *encoder, 3057 struct intel_crtc *crtc) 3058 { 3059 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3060 } 3061 3062 static void 3063 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3064 struct intel_encoder *encoder, 3065 const struct intel_crtc_state *crtc_state, 3066 const struct drm_connector_state *conn_state) 3067 { 3068 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3069 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3070 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3071 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3072 3073 if (is_tc_port) 3074 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3075 3076 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) { 3077 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 3078 dig_port->aux_wakeref = 3079 intel_display_power_get(dev_priv, 3080 intel_ddi_main_link_aux_domain(dig_port)); 3081 } 3082 3083 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3084 /* 3085 * Program the lane count for static/dynamic connections on 3086 * Type-C ports. Skip this step for TBT. 3087 */ 3088 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3089 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3090 bxt_ddi_phy_set_lane_optim_mask(encoder, 3091 crtc_state->lane_lat_optim_mask); 3092 } 3093 3094 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3095 { 3096 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3097 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 3098 int ln; 3099 3100 for (ln = 0; ln < 2; ln++) { 3101 intel_de_write(i915, HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); 3102 intel_de_rmw(i915, DKL_PCS_DW5(tc_port), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3103 } 3104 } 3105 3106 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3107 const struct intel_crtc_state *crtc_state) 3108 { 3109 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3110 struct intel_encoder *encoder = &dig_port->base; 3111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3112 enum port port = encoder->port; 3113 u32 dp_tp_ctl, ddi_buf_ctl; 3114 bool wait = false; 3115 3116 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3117 3118 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3119 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3120 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3121 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3122 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3123 wait = true; 3124 } 3125 3126 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3127 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3128 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3129 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3130 3131 if (wait) 3132 intel_wait_ddi_buf_idle(dev_priv, port); 3133 } 3134 3135 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3136 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3137 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3138 } else { 3139 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3140 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3141 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3142 } 3143 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3144 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3145 3146 if (IS_ALDERLAKE_P(dev_priv) && 3147 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3148 adlp_tbt_to_dp_alt_switch_wa(encoder); 3149 3150 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3151 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3152 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3153 3154 intel_wait_ddi_buf_active(dev_priv, port); 3155 } 3156 3157 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3158 const struct intel_crtc_state *crtc_state, 3159 u8 dp_train_pat) 3160 { 3161 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3162 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3163 u32 temp; 3164 3165 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3166 3167 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3168 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3169 case DP_TRAINING_PATTERN_DISABLE: 3170 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3171 break; 3172 case DP_TRAINING_PATTERN_1: 3173 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3174 break; 3175 case DP_TRAINING_PATTERN_2: 3176 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3177 break; 3178 case DP_TRAINING_PATTERN_3: 3179 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3180 break; 3181 case DP_TRAINING_PATTERN_4: 3182 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3183 break; 3184 } 3185 3186 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3187 } 3188 3189 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3190 const struct intel_crtc_state *crtc_state) 3191 { 3192 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3193 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3194 enum port port = encoder->port; 3195 u32 val; 3196 3197 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3198 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3199 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3200 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3201 3202 /* 3203 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3204 * reason we need to set idle transmission mode is to work around a HW 3205 * issue where we enable the pipe while not in idle link-training mode. 3206 * In this case there is requirement to wait for a minimum number of 3207 * idle patterns to be sent. 3208 */ 3209 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3210 return; 3211 3212 if (intel_de_wait_for_set(dev_priv, 3213 dp_tp_status_reg(encoder, crtc_state), 3214 DP_TP_STATUS_IDLE_DONE, 1)) 3215 drm_err(&dev_priv->drm, 3216 "Timed out waiting for DP idle patterns\n"); 3217 } 3218 3219 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3220 enum transcoder cpu_transcoder) 3221 { 3222 if (cpu_transcoder == TRANSCODER_EDP) 3223 return false; 3224 3225 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3226 return false; 3227 3228 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3229 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3230 } 3231 3232 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3233 struct intel_crtc_state *crtc_state) 3234 { 3235 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3236 crtc_state->min_voltage_level = 2; 3237 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3238 crtc_state->min_voltage_level = 3; 3239 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3240 crtc_state->min_voltage_level = 1; 3241 } 3242 3243 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3244 enum transcoder cpu_transcoder) 3245 { 3246 u32 master_select; 3247 3248 if (DISPLAY_VER(dev_priv) >= 11) { 3249 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3250 3251 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3252 return INVALID_TRANSCODER; 3253 3254 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3255 } else { 3256 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3257 3258 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3259 return INVALID_TRANSCODER; 3260 3261 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3262 } 3263 3264 if (master_select == 0) 3265 return TRANSCODER_EDP; 3266 else 3267 return master_select - 1; 3268 } 3269 3270 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3271 { 3272 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3273 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3274 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3275 enum transcoder cpu_transcoder; 3276 3277 crtc_state->master_transcoder = 3278 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3279 3280 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3281 enum intel_display_power_domain power_domain; 3282 intel_wakeref_t trans_wakeref; 3283 3284 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3285 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3286 power_domain); 3287 3288 if (!trans_wakeref) 3289 continue; 3290 3291 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3292 crtc_state->cpu_transcoder) 3293 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3294 3295 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3296 } 3297 3298 drm_WARN_ON(&dev_priv->drm, 3299 crtc_state->master_transcoder != INVALID_TRANSCODER && 3300 crtc_state->sync_mode_slaves_mask); 3301 } 3302 3303 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3304 struct intel_crtc_state *pipe_config) 3305 { 3306 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3307 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3308 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3309 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3310 u32 temp, flags = 0; 3311 3312 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3313 if (temp & TRANS_DDI_PHSYNC) 3314 flags |= DRM_MODE_FLAG_PHSYNC; 3315 else 3316 flags |= DRM_MODE_FLAG_NHSYNC; 3317 if (temp & TRANS_DDI_PVSYNC) 3318 flags |= DRM_MODE_FLAG_PVSYNC; 3319 else 3320 flags |= DRM_MODE_FLAG_NVSYNC; 3321 3322 pipe_config->hw.adjusted_mode.flags |= flags; 3323 3324 switch (temp & TRANS_DDI_BPC_MASK) { 3325 case TRANS_DDI_BPC_6: 3326 pipe_config->pipe_bpp = 18; 3327 break; 3328 case TRANS_DDI_BPC_8: 3329 pipe_config->pipe_bpp = 24; 3330 break; 3331 case TRANS_DDI_BPC_10: 3332 pipe_config->pipe_bpp = 30; 3333 break; 3334 case TRANS_DDI_BPC_12: 3335 pipe_config->pipe_bpp = 36; 3336 break; 3337 default: 3338 break; 3339 } 3340 3341 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3342 case TRANS_DDI_MODE_SELECT_HDMI: 3343 pipe_config->has_hdmi_sink = true; 3344 3345 pipe_config->infoframes.enable |= 3346 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3347 3348 if (pipe_config->infoframes.enable) 3349 pipe_config->has_infoframe = true; 3350 3351 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3352 pipe_config->hdmi_scrambling = true; 3353 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3354 pipe_config->hdmi_high_tmds_clock_ratio = true; 3355 fallthrough; 3356 case TRANS_DDI_MODE_SELECT_DVI: 3357 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3358 pipe_config->lane_count = 4; 3359 break; 3360 case TRANS_DDI_MODE_SELECT_DP_SST: 3361 if (encoder->type == INTEL_OUTPUT_EDP) 3362 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3363 else 3364 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3365 pipe_config->lane_count = 3366 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3367 3368 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3369 &pipe_config->dp_m_n); 3370 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3371 &pipe_config->dp_m2_n2); 3372 3373 if (DISPLAY_VER(dev_priv) >= 11) { 3374 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3375 3376 pipe_config->fec_enable = 3377 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3378 3379 drm_dbg_kms(&dev_priv->drm, 3380 "[ENCODER:%d:%s] Fec status: %u\n", 3381 encoder->base.base.id, encoder->base.name, 3382 pipe_config->fec_enable); 3383 } 3384 3385 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3386 pipe_config->infoframes.enable |= 3387 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3388 else 3389 pipe_config->infoframes.enable |= 3390 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3391 break; 3392 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3393 if (!HAS_DP20(dev_priv)) { 3394 /* FDI */ 3395 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3396 break; 3397 } 3398 fallthrough; /* 128b/132b */ 3399 case TRANS_DDI_MODE_SELECT_DP_MST: 3400 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3401 pipe_config->lane_count = 3402 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3403 3404 if (DISPLAY_VER(dev_priv) >= 12) 3405 pipe_config->mst_master_transcoder = 3406 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3407 3408 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3409 &pipe_config->dp_m_n); 3410 3411 pipe_config->infoframes.enable |= 3412 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3413 break; 3414 default: 3415 break; 3416 } 3417 } 3418 3419 static void intel_ddi_get_config(struct intel_encoder *encoder, 3420 struct intel_crtc_state *pipe_config) 3421 { 3422 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3423 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3424 3425 /* XXX: DSI transcoder paranoia */ 3426 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3427 return; 3428 3429 intel_ddi_read_func_ctl(encoder, pipe_config); 3430 3431 intel_ddi_mso_get_config(encoder, pipe_config); 3432 3433 pipe_config->has_audio = 3434 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3435 3436 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 3437 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3438 /* 3439 * This is a big fat ugly hack. 3440 * 3441 * Some machines in UEFI boot mode provide us a VBT that has 18 3442 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3443 * unknown we fail to light up. Yet the same BIOS boots up with 3444 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3445 * max, not what it tells us to use. 3446 * 3447 * Note: This will still be broken if the eDP panel is not lit 3448 * up by the BIOS, and thus we can't get the mode at module 3449 * load. 3450 */ 3451 drm_dbg_kms(&dev_priv->drm, 3452 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3453 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3454 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3455 } 3456 3457 ddi_dotclock_get(pipe_config); 3458 3459 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3460 pipe_config->lane_lat_optim_mask = 3461 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3462 3463 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3464 3465 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3466 3467 intel_read_infoframe(encoder, pipe_config, 3468 HDMI_INFOFRAME_TYPE_AVI, 3469 &pipe_config->infoframes.avi); 3470 intel_read_infoframe(encoder, pipe_config, 3471 HDMI_INFOFRAME_TYPE_SPD, 3472 &pipe_config->infoframes.spd); 3473 intel_read_infoframe(encoder, pipe_config, 3474 HDMI_INFOFRAME_TYPE_VENDOR, 3475 &pipe_config->infoframes.hdmi); 3476 intel_read_infoframe(encoder, pipe_config, 3477 HDMI_INFOFRAME_TYPE_DRM, 3478 &pipe_config->infoframes.drm); 3479 3480 if (DISPLAY_VER(dev_priv) >= 8) 3481 bdw_get_trans_port_sync_config(pipe_config); 3482 3483 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3484 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3485 3486 intel_psr_get_config(encoder, pipe_config); 3487 } 3488 3489 void intel_ddi_get_clock(struct intel_encoder *encoder, 3490 struct intel_crtc_state *crtc_state, 3491 struct intel_shared_dpll *pll) 3492 { 3493 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3494 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3495 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3496 bool pll_active; 3497 3498 if (drm_WARN_ON(&i915->drm, !pll)) 3499 return; 3500 3501 port_dpll->pll = pll; 3502 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3503 drm_WARN_ON(&i915->drm, !pll_active); 3504 3505 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3506 3507 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3508 &crtc_state->dpll_hw_state); 3509 } 3510 3511 static void dg2_ddi_get_config(struct intel_encoder *encoder, 3512 struct intel_crtc_state *crtc_state) 3513 { 3514 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 3515 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 3516 3517 intel_ddi_get_config(encoder, crtc_state); 3518 } 3519 3520 static void adls_ddi_get_config(struct intel_encoder *encoder, 3521 struct intel_crtc_state *crtc_state) 3522 { 3523 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3524 intel_ddi_get_config(encoder, crtc_state); 3525 } 3526 3527 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3528 struct intel_crtc_state *crtc_state) 3529 { 3530 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3531 intel_ddi_get_config(encoder, crtc_state); 3532 } 3533 3534 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3535 struct intel_crtc_state *crtc_state) 3536 { 3537 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3538 intel_ddi_get_config(encoder, crtc_state); 3539 } 3540 3541 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3542 struct intel_crtc_state *crtc_state) 3543 { 3544 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3545 intel_ddi_get_config(encoder, crtc_state); 3546 } 3547 3548 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3549 struct intel_crtc_state *crtc_state, 3550 struct intel_shared_dpll *pll) 3551 { 3552 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3553 enum icl_port_dpll_id port_dpll_id; 3554 struct icl_port_dpll *port_dpll; 3555 bool pll_active; 3556 3557 if (drm_WARN_ON(&i915->drm, !pll)) 3558 return; 3559 3560 if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL) 3561 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3562 else 3563 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3564 3565 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3566 3567 port_dpll->pll = pll; 3568 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3569 drm_WARN_ON(&i915->drm, !pll_active); 3570 3571 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3572 3573 if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL) 3574 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3575 else 3576 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3577 &crtc_state->dpll_hw_state); 3578 } 3579 3580 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3581 struct intel_crtc_state *crtc_state) 3582 { 3583 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3584 intel_ddi_get_config(encoder, crtc_state); 3585 } 3586 3587 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3588 struct intel_crtc_state *crtc_state) 3589 { 3590 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3591 intel_ddi_get_config(encoder, crtc_state); 3592 } 3593 3594 static void skl_ddi_get_config(struct intel_encoder *encoder, 3595 struct intel_crtc_state *crtc_state) 3596 { 3597 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3598 intel_ddi_get_config(encoder, crtc_state); 3599 } 3600 3601 void hsw_ddi_get_config(struct intel_encoder *encoder, 3602 struct intel_crtc_state *crtc_state) 3603 { 3604 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3605 intel_ddi_get_config(encoder, crtc_state); 3606 } 3607 3608 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3609 const struct intel_crtc_state *crtc_state) 3610 { 3611 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3612 enum phy phy = intel_port_to_phy(i915, encoder->port); 3613 3614 if (intel_phy_is_tc(i915, phy)) 3615 intel_tc_port_sanitize(enc_to_dig_port(encoder)); 3616 3617 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 3618 intel_dp_sync_state(encoder, crtc_state); 3619 } 3620 3621 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3622 struct intel_crtc_state *crtc_state) 3623 { 3624 if (intel_crtc_has_dp_encoder(crtc_state)) 3625 return intel_dp_initial_fastset_check(encoder, crtc_state); 3626 3627 return true; 3628 } 3629 3630 static enum intel_output_type 3631 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3632 struct intel_crtc_state *crtc_state, 3633 struct drm_connector_state *conn_state) 3634 { 3635 switch (conn_state->connector->connector_type) { 3636 case DRM_MODE_CONNECTOR_HDMIA: 3637 return INTEL_OUTPUT_HDMI; 3638 case DRM_MODE_CONNECTOR_eDP: 3639 return INTEL_OUTPUT_EDP; 3640 case DRM_MODE_CONNECTOR_DisplayPort: 3641 return INTEL_OUTPUT_DP; 3642 default: 3643 MISSING_CASE(conn_state->connector->connector_type); 3644 return INTEL_OUTPUT_UNUSED; 3645 } 3646 } 3647 3648 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3649 struct intel_crtc_state *pipe_config, 3650 struct drm_connector_state *conn_state) 3651 { 3652 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3653 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3654 enum port port = encoder->port; 3655 int ret; 3656 3657 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3658 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3659 3660 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3661 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3662 } else { 3663 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3664 } 3665 3666 if (ret) 3667 return ret; 3668 3669 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3670 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3671 pipe_config->pch_pfit.force_thru = 3672 pipe_config->pch_pfit.enabled || 3673 pipe_config->crc_enabled; 3674 3675 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3676 pipe_config->lane_lat_optim_mask = 3677 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3678 3679 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3680 3681 return 0; 3682 } 3683 3684 static bool mode_equal(const struct drm_display_mode *mode1, 3685 const struct drm_display_mode *mode2) 3686 { 3687 return drm_mode_match(mode1, mode2, 3688 DRM_MODE_MATCH_TIMINGS | 3689 DRM_MODE_MATCH_FLAGS | 3690 DRM_MODE_MATCH_3D_FLAGS) && 3691 mode1->clock == mode2->clock; /* we want an exact match */ 3692 } 3693 3694 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3695 const struct intel_link_m_n *m_n_2) 3696 { 3697 return m_n_1->tu == m_n_2->tu && 3698 m_n_1->data_m == m_n_2->data_m && 3699 m_n_1->data_n == m_n_2->data_n && 3700 m_n_1->link_m == m_n_2->link_m && 3701 m_n_1->link_n == m_n_2->link_n; 3702 } 3703 3704 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3705 const struct intel_crtc_state *crtc_state2) 3706 { 3707 return crtc_state1->hw.active && crtc_state2->hw.active && 3708 crtc_state1->output_types == crtc_state2->output_types && 3709 crtc_state1->output_format == crtc_state2->output_format && 3710 crtc_state1->lane_count == crtc_state2->lane_count && 3711 crtc_state1->port_clock == crtc_state2->port_clock && 3712 mode_equal(&crtc_state1->hw.adjusted_mode, 3713 &crtc_state2->hw.adjusted_mode) && 3714 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3715 } 3716 3717 static u8 3718 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3719 int tile_group_id) 3720 { 3721 struct drm_connector *connector; 3722 const struct drm_connector_state *conn_state; 3723 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3724 struct intel_atomic_state *state = 3725 to_intel_atomic_state(ref_crtc_state->uapi.state); 3726 u8 transcoders = 0; 3727 int i; 3728 3729 /* 3730 * We don't enable port sync on BDW due to missing w/as and 3731 * due to not having adjusted the modeset sequence appropriately. 3732 */ 3733 if (DISPLAY_VER(dev_priv) < 9) 3734 return 0; 3735 3736 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 3737 return 0; 3738 3739 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 3740 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 3741 const struct intel_crtc_state *crtc_state; 3742 3743 if (!crtc) 3744 continue; 3745 3746 if (!connector->has_tile || 3747 connector->tile_group->id != 3748 tile_group_id) 3749 continue; 3750 crtc_state = intel_atomic_get_new_crtc_state(state, 3751 crtc); 3752 if (!crtcs_port_sync_compatible(ref_crtc_state, 3753 crtc_state)) 3754 continue; 3755 transcoders |= BIT(crtc_state->cpu_transcoder); 3756 } 3757 3758 return transcoders; 3759 } 3760 3761 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 3762 struct intel_crtc_state *crtc_state, 3763 struct drm_connector_state *conn_state) 3764 { 3765 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3766 struct drm_connector *connector = conn_state->connector; 3767 u8 port_sync_transcoders = 0; 3768 3769 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 3770 encoder->base.base.id, encoder->base.name, 3771 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 3772 3773 if (connector->has_tile) 3774 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 3775 connector->tile_group->id); 3776 3777 /* 3778 * EDP Transcoders cannot be ensalved 3779 * make them a master always when present 3780 */ 3781 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 3782 crtc_state->master_transcoder = TRANSCODER_EDP; 3783 else 3784 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 3785 3786 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 3787 crtc_state->master_transcoder = INVALID_TRANSCODER; 3788 crtc_state->sync_mode_slaves_mask = 3789 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 3790 } 3791 3792 return 0; 3793 } 3794 3795 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 3796 { 3797 struct drm_i915_private *i915 = to_i915(encoder->dev); 3798 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 3799 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 3800 3801 intel_dp_encoder_flush_work(encoder); 3802 if (intel_phy_is_tc(i915, phy)) 3803 intel_tc_port_flush_work(dig_port); 3804 intel_display_power_flush_work(i915); 3805 3806 drm_encoder_cleanup(encoder); 3807 kfree(dig_port->hdcp_port_data.streams); 3808 kfree(dig_port); 3809 } 3810 3811 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 3812 { 3813 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 3814 3815 intel_dp->reset_link_params = true; 3816 3817 intel_pps_encoder_reset(intel_dp); 3818 } 3819 3820 static const struct drm_encoder_funcs intel_ddi_funcs = { 3821 .reset = intel_ddi_encoder_reset, 3822 .destroy = intel_ddi_encoder_destroy, 3823 }; 3824 3825 static struct intel_connector * 3826 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 3827 { 3828 struct intel_connector *connector; 3829 enum port port = dig_port->base.port; 3830 3831 connector = intel_connector_alloc(); 3832 if (!connector) 3833 return NULL; 3834 3835 dig_port->dp.output_reg = DDI_BUF_CTL(port); 3836 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 3837 dig_port->dp.set_link_train = intel_ddi_set_link_train; 3838 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 3839 3840 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 3841 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 3842 3843 if (!intel_dp_init_connector(dig_port, connector)) { 3844 kfree(connector); 3845 return NULL; 3846 } 3847 3848 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 3849 struct drm_device *dev = dig_port->base.base.dev; 3850 struct drm_privacy_screen *privacy_screen; 3851 3852 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 3853 if (!IS_ERR(privacy_screen)) { 3854 drm_connector_attach_privacy_screen_provider(&connector->base, 3855 privacy_screen); 3856 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 3857 drm_warn(dev, "Error getting privacy-screen\n"); 3858 } 3859 } 3860 3861 return connector; 3862 } 3863 3864 static int modeset_pipe(struct drm_crtc *crtc, 3865 struct drm_modeset_acquire_ctx *ctx) 3866 { 3867 struct drm_atomic_state *state; 3868 struct drm_crtc_state *crtc_state; 3869 int ret; 3870 3871 state = drm_atomic_state_alloc(crtc->dev); 3872 if (!state) 3873 return -ENOMEM; 3874 3875 state->acquire_ctx = ctx; 3876 3877 crtc_state = drm_atomic_get_crtc_state(state, crtc); 3878 if (IS_ERR(crtc_state)) { 3879 ret = PTR_ERR(crtc_state); 3880 goto out; 3881 } 3882 3883 crtc_state->connectors_changed = true; 3884 3885 ret = drm_atomic_commit(state); 3886 out: 3887 drm_atomic_state_put(state); 3888 3889 return ret; 3890 } 3891 3892 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 3893 struct drm_modeset_acquire_ctx *ctx) 3894 { 3895 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3896 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 3897 struct intel_connector *connector = hdmi->attached_connector; 3898 struct i2c_adapter *adapter = 3899 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 3900 struct drm_connector_state *conn_state; 3901 struct intel_crtc_state *crtc_state; 3902 struct intel_crtc *crtc; 3903 u8 config; 3904 int ret; 3905 3906 if (!connector || connector->base.status != connector_status_connected) 3907 return 0; 3908 3909 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 3910 ctx); 3911 if (ret) 3912 return ret; 3913 3914 conn_state = connector->base.state; 3915 3916 crtc = to_intel_crtc(conn_state->crtc); 3917 if (!crtc) 3918 return 0; 3919 3920 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 3921 if (ret) 3922 return ret; 3923 3924 crtc_state = to_intel_crtc_state(crtc->base.state); 3925 3926 drm_WARN_ON(&dev_priv->drm, 3927 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 3928 3929 if (!crtc_state->hw.active) 3930 return 0; 3931 3932 if (!crtc_state->hdmi_high_tmds_clock_ratio && 3933 !crtc_state->hdmi_scrambling) 3934 return 0; 3935 3936 if (conn_state->commit && 3937 !try_wait_for_completion(&conn_state->commit->hw_done)) 3938 return 0; 3939 3940 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 3941 if (ret < 0) { 3942 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 3943 ret); 3944 return 0; 3945 } 3946 3947 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 3948 crtc_state->hdmi_high_tmds_clock_ratio && 3949 !!(config & SCDC_SCRAMBLING_ENABLE) == 3950 crtc_state->hdmi_scrambling) 3951 return 0; 3952 3953 /* 3954 * HDMI 2.0 says that one should not send scrambled data 3955 * prior to configuring the sink scrambling, and that 3956 * TMDS clock/data transmission should be suspended when 3957 * changing the TMDS clock rate in the sink. So let's 3958 * just do a full modeset here, even though some sinks 3959 * would be perfectly happy if were to just reconfigure 3960 * the SCDC settings on the fly. 3961 */ 3962 return modeset_pipe(&crtc->base, ctx); 3963 } 3964 3965 static enum intel_hotplug_state 3966 intel_ddi_hotplug(struct intel_encoder *encoder, 3967 struct intel_connector *connector) 3968 { 3969 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3970 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3971 struct intel_dp *intel_dp = &dig_port->dp; 3972 enum phy phy = intel_port_to_phy(i915, encoder->port); 3973 bool is_tc = intel_phy_is_tc(i915, phy); 3974 struct drm_modeset_acquire_ctx ctx; 3975 enum intel_hotplug_state state; 3976 int ret; 3977 3978 if (intel_dp->compliance.test_active && 3979 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 3980 intel_dp_phy_test(encoder); 3981 /* just do the PHY test and nothing else */ 3982 return INTEL_HOTPLUG_UNCHANGED; 3983 } 3984 3985 state = intel_encoder_hotplug(encoder, connector); 3986 3987 drm_modeset_acquire_init(&ctx, 0); 3988 3989 for (;;) { 3990 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 3991 ret = intel_hdmi_reset_link(encoder, &ctx); 3992 else 3993 ret = intel_dp_retrain_link(encoder, &ctx); 3994 3995 if (ret == -EDEADLK) { 3996 drm_modeset_backoff(&ctx); 3997 continue; 3998 } 3999 4000 break; 4001 } 4002 4003 drm_modeset_drop_locks(&ctx); 4004 drm_modeset_acquire_fini(&ctx); 4005 drm_WARN(encoder->base.dev, ret, 4006 "Acquiring modeset locks failed with %i\n", ret); 4007 4008 /* 4009 * Unpowered type-c dongles can take some time to boot and be 4010 * responsible, so here giving some time to those dongles to power up 4011 * and then retrying the probe. 4012 * 4013 * On many platforms the HDMI live state signal is known to be 4014 * unreliable, so we can't use it to detect if a sink is connected or 4015 * not. Instead we detect if it's connected based on whether we can 4016 * read the EDID or not. That in turn has a problem during disconnect, 4017 * since the HPD interrupt may be raised before the DDC lines get 4018 * disconnected (due to how the required length of DDC vs. HPD 4019 * connector pins are specified) and so we'll still be able to get a 4020 * valid EDID. To solve this schedule another detection cycle if this 4021 * time around we didn't detect any change in the sink's connection 4022 * status. 4023 * 4024 * Type-c connectors which get their HPD signal deasserted then 4025 * reasserted, without unplugging/replugging the sink from the 4026 * connector, introduce a delay until the AUX channel communication 4027 * becomes functional. Retry the detection for 5 seconds on type-c 4028 * connectors to account for this delay. 4029 */ 4030 if (state == INTEL_HOTPLUG_UNCHANGED && 4031 connector->hotplug_retries < (is_tc ? 5 : 1) && 4032 !dig_port->dp.is_mst) 4033 state = INTEL_HOTPLUG_RETRY; 4034 4035 return state; 4036 } 4037 4038 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4039 { 4040 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4041 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4042 4043 return intel_de_read(dev_priv, SDEISR) & bit; 4044 } 4045 4046 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4047 { 4048 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4049 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4050 4051 return intel_de_read(dev_priv, DEISR) & bit; 4052 } 4053 4054 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4055 { 4056 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4057 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4058 4059 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4060 } 4061 4062 static struct intel_connector * 4063 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4064 { 4065 struct intel_connector *connector; 4066 enum port port = dig_port->base.port; 4067 4068 connector = intel_connector_alloc(); 4069 if (!connector) 4070 return NULL; 4071 4072 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4073 intel_hdmi_init_connector(dig_port, connector); 4074 4075 return connector; 4076 } 4077 4078 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4079 { 4080 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4081 4082 if (dig_port->base.port != PORT_A) 4083 return false; 4084 4085 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4086 return false; 4087 4088 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4089 * supported configuration 4090 */ 4091 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4092 return true; 4093 4094 return false; 4095 } 4096 4097 static int 4098 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4099 { 4100 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4101 enum port port = dig_port->base.port; 4102 int max_lanes = 4; 4103 4104 if (DISPLAY_VER(dev_priv) >= 11) 4105 return max_lanes; 4106 4107 if (port == PORT_A || port == PORT_E) { 4108 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4109 max_lanes = port == PORT_A ? 4 : 0; 4110 else 4111 /* Both A and E share 2 lanes */ 4112 max_lanes = 2; 4113 } 4114 4115 /* 4116 * Some BIOS might fail to set this bit on port A if eDP 4117 * wasn't lit up at boot. Force this bit set when needed 4118 * so we use the proper lane count for our calculations. 4119 */ 4120 if (intel_ddi_a_force_4_lanes(dig_port)) { 4121 drm_dbg_kms(&dev_priv->drm, 4122 "Forcing DDI_A_4_LANES for port A\n"); 4123 dig_port->saved_port_bits |= DDI_A_4_LANES; 4124 max_lanes = 4; 4125 } 4126 4127 return max_lanes; 4128 } 4129 4130 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 4131 { 4132 return i915->hti_state & HDPORT_ENABLED && 4133 i915->hti_state & HDPORT_DDI_USED(phy); 4134 } 4135 4136 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4137 enum port port) 4138 { 4139 if (port >= PORT_D_XELPD) 4140 return HPD_PORT_D + port - PORT_D_XELPD; 4141 else if (port >= PORT_TC1) 4142 return HPD_PORT_TC1 + port - PORT_TC1; 4143 else 4144 return HPD_PORT_A + port - PORT_A; 4145 } 4146 4147 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4148 enum port port) 4149 { 4150 if (port >= PORT_TC1) 4151 return HPD_PORT_C + port - PORT_TC1; 4152 else 4153 return HPD_PORT_A + port - PORT_A; 4154 } 4155 4156 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4157 enum port port) 4158 { 4159 if (port >= PORT_TC1) 4160 return HPD_PORT_TC1 + port - PORT_TC1; 4161 else 4162 return HPD_PORT_A + port - PORT_A; 4163 } 4164 4165 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4166 enum port port) 4167 { 4168 if (HAS_PCH_TGP(dev_priv)) 4169 return tgl_hpd_pin(dev_priv, port); 4170 4171 if (port >= PORT_TC1) 4172 return HPD_PORT_C + port - PORT_TC1; 4173 else 4174 return HPD_PORT_A + port - PORT_A; 4175 } 4176 4177 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4178 enum port port) 4179 { 4180 if (port >= PORT_C) 4181 return HPD_PORT_TC1 + port - PORT_C; 4182 else 4183 return HPD_PORT_A + port - PORT_A; 4184 } 4185 4186 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4187 enum port port) 4188 { 4189 if (port == PORT_D) 4190 return HPD_PORT_A; 4191 4192 if (HAS_PCH_MCC(dev_priv)) 4193 return icl_hpd_pin(dev_priv, port); 4194 4195 return HPD_PORT_A + port - PORT_A; 4196 } 4197 4198 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4199 { 4200 if (HAS_PCH_TGP(dev_priv)) 4201 return icl_hpd_pin(dev_priv, port); 4202 4203 return HPD_PORT_A + port - PORT_A; 4204 } 4205 4206 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4207 { 4208 if (DISPLAY_VER(i915) >= 12) 4209 return port >= PORT_TC1; 4210 else if (DISPLAY_VER(i915) >= 11) 4211 return port >= PORT_C; 4212 else 4213 return false; 4214 } 4215 4216 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4217 { 4218 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4219 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4220 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4221 enum phy phy = intel_port_to_phy(i915, encoder->port); 4222 4223 intel_dp_encoder_suspend(encoder); 4224 4225 if (!intel_phy_is_tc(i915, phy)) 4226 return; 4227 4228 intel_tc_port_flush_work(dig_port); 4229 } 4230 4231 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4232 { 4233 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4234 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4235 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4236 enum phy phy = intel_port_to_phy(i915, encoder->port); 4237 4238 intel_dp_encoder_shutdown(encoder); 4239 intel_hdmi_encoder_shutdown(encoder); 4240 4241 if (!intel_phy_is_tc(i915, phy)) 4242 return; 4243 4244 intel_tc_port_flush_work(dig_port); 4245 } 4246 4247 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4248 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4249 4250 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4251 { 4252 struct intel_digital_port *dig_port; 4253 struct intel_encoder *encoder; 4254 const struct intel_bios_encoder_data *devdata; 4255 bool init_hdmi, init_dp; 4256 enum phy phy = intel_port_to_phy(dev_priv, port); 4257 4258 /* 4259 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4260 * have taken over some of the PHYs and made them unavailable to the 4261 * driver. In that case we should skip initializing the corresponding 4262 * outputs. 4263 */ 4264 if (hti_uses_phy(dev_priv, phy)) { 4265 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4266 port_name(port), phy_name(phy)); 4267 return; 4268 } 4269 4270 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4271 if (!devdata) { 4272 drm_dbg_kms(&dev_priv->drm, 4273 "VBT says port %c is not present\n", 4274 port_name(port)); 4275 return; 4276 } 4277 4278 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4279 intel_bios_encoder_supports_hdmi(devdata); 4280 init_dp = intel_bios_encoder_supports_dp(devdata); 4281 4282 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4283 /* 4284 * Lspcon device needs to be driven with DP connector 4285 * with special detection sequence. So make sure DP 4286 * is initialized before lspcon. 4287 */ 4288 init_dp = true; 4289 init_hdmi = false; 4290 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4291 port_name(port)); 4292 } 4293 4294 if (!init_dp && !init_hdmi) { 4295 drm_dbg_kms(&dev_priv->drm, 4296 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4297 port_name(port)); 4298 return; 4299 } 4300 4301 if (intel_phy_is_snps(dev_priv, phy) && 4302 dev_priv->snps_phy_failed_calibration & BIT(phy)) { 4303 drm_dbg_kms(&dev_priv->drm, 4304 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4305 phy_name(phy)); 4306 } 4307 4308 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4309 if (!dig_port) 4310 return; 4311 4312 encoder = &dig_port->base; 4313 encoder->devdata = devdata; 4314 4315 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4316 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4317 DRM_MODE_ENCODER_TMDS, 4318 "DDI %c/PHY %c", 4319 port_name(port - PORT_D_XELPD + PORT_D), 4320 phy_name(phy)); 4321 } else if (DISPLAY_VER(dev_priv) >= 12) { 4322 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4323 4324 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4325 DRM_MODE_ENCODER_TMDS, 4326 "DDI %s%c/PHY %s%c", 4327 port >= PORT_TC1 ? "TC" : "", 4328 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4329 tc_port != TC_PORT_NONE ? "TC" : "", 4330 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4331 } else if (DISPLAY_VER(dev_priv) >= 11) { 4332 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4333 4334 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4335 DRM_MODE_ENCODER_TMDS, 4336 "DDI %c%s/PHY %s%c", 4337 port_name(port), 4338 port >= PORT_C ? " (TC)" : "", 4339 tc_port != TC_PORT_NONE ? "TC" : "", 4340 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4341 } else { 4342 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4343 DRM_MODE_ENCODER_TMDS, 4344 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4345 } 4346 4347 mutex_init(&dig_port->hdcp_mutex); 4348 dig_port->num_hdcp_streams = 0; 4349 4350 encoder->hotplug = intel_ddi_hotplug; 4351 encoder->compute_output_type = intel_ddi_compute_output_type; 4352 encoder->compute_config = intel_ddi_compute_config; 4353 encoder->compute_config_late = intel_ddi_compute_config_late; 4354 encoder->enable = intel_enable_ddi; 4355 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4356 encoder->pre_enable = intel_ddi_pre_enable; 4357 encoder->disable = intel_disable_ddi; 4358 encoder->post_disable = intel_ddi_post_disable; 4359 encoder->update_pipe = intel_ddi_update_pipe; 4360 encoder->get_hw_state = intel_ddi_get_hw_state; 4361 encoder->sync_state = intel_ddi_sync_state; 4362 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4363 encoder->suspend = intel_ddi_encoder_suspend; 4364 encoder->shutdown = intel_ddi_encoder_shutdown; 4365 encoder->get_power_domains = intel_ddi_get_power_domains; 4366 4367 encoder->type = INTEL_OUTPUT_DDI; 4368 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 4369 encoder->port = port; 4370 encoder->cloneable = 0; 4371 encoder->pipe_mask = ~0; 4372 4373 if (IS_DG2(dev_priv)) { 4374 encoder->enable_clock = intel_mpllb_enable; 4375 encoder->disable_clock = intel_mpllb_disable; 4376 encoder->get_config = dg2_ddi_get_config; 4377 } else if (IS_ALDERLAKE_S(dev_priv)) { 4378 encoder->enable_clock = adls_ddi_enable_clock; 4379 encoder->disable_clock = adls_ddi_disable_clock; 4380 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4381 encoder->get_config = adls_ddi_get_config; 4382 } else if (IS_ROCKETLAKE(dev_priv)) { 4383 encoder->enable_clock = rkl_ddi_enable_clock; 4384 encoder->disable_clock = rkl_ddi_disable_clock; 4385 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4386 encoder->get_config = rkl_ddi_get_config; 4387 } else if (IS_DG1(dev_priv)) { 4388 encoder->enable_clock = dg1_ddi_enable_clock; 4389 encoder->disable_clock = dg1_ddi_disable_clock; 4390 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4391 encoder->get_config = dg1_ddi_get_config; 4392 } else if (IS_JSL_EHL(dev_priv)) { 4393 if (intel_ddi_is_tc(dev_priv, port)) { 4394 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4395 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4396 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4397 encoder->get_config = icl_ddi_combo_get_config; 4398 } else { 4399 encoder->enable_clock = icl_ddi_combo_enable_clock; 4400 encoder->disable_clock = icl_ddi_combo_disable_clock; 4401 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4402 encoder->get_config = icl_ddi_combo_get_config; 4403 } 4404 } else if (DISPLAY_VER(dev_priv) >= 11) { 4405 if (intel_ddi_is_tc(dev_priv, port)) { 4406 encoder->enable_clock = icl_ddi_tc_enable_clock; 4407 encoder->disable_clock = icl_ddi_tc_disable_clock; 4408 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4409 encoder->get_config = icl_ddi_tc_get_config; 4410 } else { 4411 encoder->enable_clock = icl_ddi_combo_enable_clock; 4412 encoder->disable_clock = icl_ddi_combo_disable_clock; 4413 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4414 encoder->get_config = icl_ddi_combo_get_config; 4415 } 4416 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4417 /* BXT/GLK have fixed PLL->port mapping */ 4418 encoder->get_config = bxt_ddi_get_config; 4419 } else if (DISPLAY_VER(dev_priv) == 9) { 4420 encoder->enable_clock = skl_ddi_enable_clock; 4421 encoder->disable_clock = skl_ddi_disable_clock; 4422 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4423 encoder->get_config = skl_ddi_get_config; 4424 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4425 encoder->enable_clock = hsw_ddi_enable_clock; 4426 encoder->disable_clock = hsw_ddi_disable_clock; 4427 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4428 encoder->get_config = hsw_ddi_get_config; 4429 } 4430 4431 if (IS_DG2(dev_priv)) { 4432 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 4433 } else if (DISPLAY_VER(dev_priv) >= 12) { 4434 if (intel_phy_is_combo(dev_priv, phy)) 4435 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4436 else 4437 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 4438 } else if (DISPLAY_VER(dev_priv) >= 11) { 4439 if (intel_phy_is_combo(dev_priv, phy)) 4440 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 4441 else 4442 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 4443 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4444 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 4445 } else { 4446 encoder->set_signal_levels = hsw_set_signal_levels; 4447 } 4448 4449 intel_ddi_buf_trans_init(encoder); 4450 4451 if (DISPLAY_VER(dev_priv) >= 13) 4452 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4453 else if (IS_DG1(dev_priv)) 4454 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4455 else if (IS_ROCKETLAKE(dev_priv)) 4456 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4457 else if (DISPLAY_VER(dev_priv) >= 12) 4458 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4459 else if (IS_JSL_EHL(dev_priv)) 4460 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4461 else if (DISPLAY_VER(dev_priv) == 11) 4462 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4463 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4464 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4465 else 4466 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4467 4468 if (DISPLAY_VER(dev_priv) >= 11) 4469 dig_port->saved_port_bits = 4470 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4471 & DDI_BUF_PORT_REVERSAL; 4472 else 4473 dig_port->saved_port_bits = 4474 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4475 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4476 4477 if (intel_bios_is_lane_reversal_needed(dev_priv, port)) 4478 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4479 4480 dig_port->dp.output_reg = INVALID_MMIO_REG; 4481 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4482 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4483 4484 if (intel_phy_is_tc(dev_priv, phy)) { 4485 bool is_legacy = 4486 !intel_bios_encoder_supports_typec_usb(devdata) && 4487 !intel_bios_encoder_supports_tbt(devdata); 4488 4489 intel_tc_port_init(dig_port, is_legacy); 4490 4491 encoder->update_prepare = intel_ddi_update_prepare; 4492 encoder->update_complete = intel_ddi_update_complete; 4493 } 4494 4495 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4496 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 4497 4498 if (init_dp) { 4499 if (!intel_ddi_init_dp_connector(dig_port)) 4500 goto err; 4501 4502 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4503 4504 if (dig_port->dp.mso_link_count) 4505 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 4506 } 4507 4508 /* In theory we don't need the encoder->type check, but leave it just in 4509 * case we have some really bad VBTs... */ 4510 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4511 if (!intel_ddi_init_hdmi_connector(dig_port)) 4512 goto err; 4513 } 4514 4515 if (DISPLAY_VER(dev_priv) >= 11) { 4516 if (intel_phy_is_tc(dev_priv, phy)) 4517 dig_port->connected = intel_tc_port_connected; 4518 else 4519 dig_port->connected = lpt_digital_port_connected; 4520 } else if (DISPLAY_VER(dev_priv) >= 8) { 4521 if (port == PORT_A || IS_GEMINILAKE(dev_priv) || 4522 IS_BROXTON(dev_priv)) 4523 dig_port->connected = bdw_digital_port_connected; 4524 else 4525 dig_port->connected = lpt_digital_port_connected; 4526 } else { 4527 if (port == PORT_A) 4528 dig_port->connected = hsw_digital_port_connected; 4529 else 4530 dig_port->connected = lpt_digital_port_connected; 4531 } 4532 4533 intel_infoframe_init(dig_port); 4534 4535 return; 4536 4537 err: 4538 drm_encoder_cleanup(&encoder->base); 4539 kfree(dig_port); 4540 } 4541