1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_display_types.h" 36 #include "intel_dp.h" 37 #include "intel_dp_link_training.h" 38 #include "intel_dpio_phy.h" 39 #include "intel_dsi.h" 40 #include "intel_fifo_underrun.h" 41 #include "intel_gmbus.h" 42 #include "intel_hdcp.h" 43 #include "intel_hdmi.h" 44 #include "intel_hotplug.h" 45 #include "intel_lspcon.h" 46 #include "intel_panel.h" 47 #include "intel_psr.h" 48 #include "intel_sprite.h" 49 #include "intel_tc.h" 50 #include "intel_vdsc.h" 51 52 struct ddi_buf_trans { 53 u32 trans1; /* balance leg enable, de-emph level */ 54 u32 trans2; /* vref sel, vswing */ 55 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 56 }; 57 58 static const u8 index_to_dp_signal_levels[] = { 59 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 60 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 61 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 62 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 63 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 64 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 65 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 66 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 67 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 68 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 69 }; 70 71 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 72 * them for both DP and FDI transports, allowing those ports to 73 * automatically adapt to HDMI connections as well 74 */ 75 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 76 { 0x00FFFFFF, 0x0006000E, 0x0 }, 77 { 0x00D75FFF, 0x0005000A, 0x0 }, 78 { 0x00C30FFF, 0x00040006, 0x0 }, 79 { 0x80AAAFFF, 0x000B0000, 0x0 }, 80 { 0x00FFFFFF, 0x0005000A, 0x0 }, 81 { 0x00D75FFF, 0x000C0004, 0x0 }, 82 { 0x80C30FFF, 0x000B0000, 0x0 }, 83 { 0x00FFFFFF, 0x00040006, 0x0 }, 84 { 0x80D75FFF, 0x000B0000, 0x0 }, 85 }; 86 87 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 88 { 0x00FFFFFF, 0x0007000E, 0x0 }, 89 { 0x00D75FFF, 0x000F000A, 0x0 }, 90 { 0x00C30FFF, 0x00060006, 0x0 }, 91 { 0x00AAAFFF, 0x001E0000, 0x0 }, 92 { 0x00FFFFFF, 0x000F000A, 0x0 }, 93 { 0x00D75FFF, 0x00160004, 0x0 }, 94 { 0x00C30FFF, 0x001E0000, 0x0 }, 95 { 0x00FFFFFF, 0x00060006, 0x0 }, 96 { 0x00D75FFF, 0x001E0000, 0x0 }, 97 }; 98 99 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 100 /* Idx NT mV d T mV d db */ 101 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 102 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 103 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 104 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 105 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 106 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 107 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 108 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 109 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 110 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 111 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 112 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 113 }; 114 115 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 116 { 0x00FFFFFF, 0x00000012, 0x0 }, 117 { 0x00EBAFFF, 0x00020011, 0x0 }, 118 { 0x00C71FFF, 0x0006000F, 0x0 }, 119 { 0x00AAAFFF, 0x000E000A, 0x0 }, 120 { 0x00FFFFFF, 0x00020011, 0x0 }, 121 { 0x00DB6FFF, 0x0005000F, 0x0 }, 122 { 0x00BEEFFF, 0x000A000C, 0x0 }, 123 { 0x00FFFFFF, 0x0005000F, 0x0 }, 124 { 0x00DB6FFF, 0x000A000C, 0x0 }, 125 }; 126 127 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 128 { 0x00FFFFFF, 0x0007000E, 0x0 }, 129 { 0x00D75FFF, 0x000E000A, 0x0 }, 130 { 0x00BEFFFF, 0x00140006, 0x0 }, 131 { 0x80B2CFFF, 0x001B0002, 0x0 }, 132 { 0x00FFFFFF, 0x000E000A, 0x0 }, 133 { 0x00DB6FFF, 0x00160005, 0x0 }, 134 { 0x80C71FFF, 0x001A0002, 0x0 }, 135 { 0x00F7DFFF, 0x00180004, 0x0 }, 136 { 0x80D75FFF, 0x001B0002, 0x0 }, 137 }; 138 139 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 140 { 0x00FFFFFF, 0x0001000E, 0x0 }, 141 { 0x00D75FFF, 0x0004000A, 0x0 }, 142 { 0x00C30FFF, 0x00070006, 0x0 }, 143 { 0x00AAAFFF, 0x000C0000, 0x0 }, 144 { 0x00FFFFFF, 0x0004000A, 0x0 }, 145 { 0x00D75FFF, 0x00090004, 0x0 }, 146 { 0x00C30FFF, 0x000C0000, 0x0 }, 147 { 0x00FFFFFF, 0x00070006, 0x0 }, 148 { 0x00D75FFF, 0x000C0000, 0x0 }, 149 }; 150 151 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 152 /* Idx NT mV d T mV df db */ 153 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 154 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 155 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 156 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 157 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 158 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 159 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 160 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 161 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 162 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 163 }; 164 165 /* Skylake H and S */ 166 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 167 { 0x00002016, 0x000000A0, 0x0 }, 168 { 0x00005012, 0x0000009B, 0x0 }, 169 { 0x00007011, 0x00000088, 0x0 }, 170 { 0x80009010, 0x000000C0, 0x1 }, 171 { 0x00002016, 0x0000009B, 0x0 }, 172 { 0x00005012, 0x00000088, 0x0 }, 173 { 0x80007011, 0x000000C0, 0x1 }, 174 { 0x00002016, 0x000000DF, 0x0 }, 175 { 0x80005012, 0x000000C0, 0x1 }, 176 }; 177 178 /* Skylake U */ 179 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 180 { 0x0000201B, 0x000000A2, 0x0 }, 181 { 0x00005012, 0x00000088, 0x0 }, 182 { 0x80007011, 0x000000CD, 0x1 }, 183 { 0x80009010, 0x000000C0, 0x1 }, 184 { 0x0000201B, 0x0000009D, 0x0 }, 185 { 0x80005012, 0x000000C0, 0x1 }, 186 { 0x80007011, 0x000000C0, 0x1 }, 187 { 0x00002016, 0x00000088, 0x0 }, 188 { 0x80005012, 0x000000C0, 0x1 }, 189 }; 190 191 /* Skylake Y */ 192 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 193 { 0x00000018, 0x000000A2, 0x0 }, 194 { 0x00005012, 0x00000088, 0x0 }, 195 { 0x80007011, 0x000000CD, 0x3 }, 196 { 0x80009010, 0x000000C0, 0x3 }, 197 { 0x00000018, 0x0000009D, 0x0 }, 198 { 0x80005012, 0x000000C0, 0x3 }, 199 { 0x80007011, 0x000000C0, 0x3 }, 200 { 0x00000018, 0x00000088, 0x0 }, 201 { 0x80005012, 0x000000C0, 0x3 }, 202 }; 203 204 /* Kabylake H and S */ 205 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 206 { 0x00002016, 0x000000A0, 0x0 }, 207 { 0x00005012, 0x0000009B, 0x0 }, 208 { 0x00007011, 0x00000088, 0x0 }, 209 { 0x80009010, 0x000000C0, 0x1 }, 210 { 0x00002016, 0x0000009B, 0x0 }, 211 { 0x00005012, 0x00000088, 0x0 }, 212 { 0x80007011, 0x000000C0, 0x1 }, 213 { 0x00002016, 0x00000097, 0x0 }, 214 { 0x80005012, 0x000000C0, 0x1 }, 215 }; 216 217 /* Kabylake U */ 218 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 219 { 0x0000201B, 0x000000A1, 0x0 }, 220 { 0x00005012, 0x00000088, 0x0 }, 221 { 0x80007011, 0x000000CD, 0x3 }, 222 { 0x80009010, 0x000000C0, 0x3 }, 223 { 0x0000201B, 0x0000009D, 0x0 }, 224 { 0x80005012, 0x000000C0, 0x3 }, 225 { 0x80007011, 0x000000C0, 0x3 }, 226 { 0x00002016, 0x0000004F, 0x0 }, 227 { 0x80005012, 0x000000C0, 0x3 }, 228 }; 229 230 /* Kabylake Y */ 231 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 232 { 0x00001017, 0x000000A1, 0x0 }, 233 { 0x00005012, 0x00000088, 0x0 }, 234 { 0x80007011, 0x000000CD, 0x3 }, 235 { 0x8000800F, 0x000000C0, 0x3 }, 236 { 0x00001017, 0x0000009D, 0x0 }, 237 { 0x80005012, 0x000000C0, 0x3 }, 238 { 0x80007011, 0x000000C0, 0x3 }, 239 { 0x00001017, 0x0000004C, 0x0 }, 240 { 0x80005012, 0x000000C0, 0x3 }, 241 }; 242 243 /* 244 * Skylake/Kabylake H and S 245 * eDP 1.4 low vswing translation parameters 246 */ 247 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 248 { 0x00000018, 0x000000A8, 0x0 }, 249 { 0x00004013, 0x000000A9, 0x0 }, 250 { 0x00007011, 0x000000A2, 0x0 }, 251 { 0x00009010, 0x0000009C, 0x0 }, 252 { 0x00000018, 0x000000A9, 0x0 }, 253 { 0x00006013, 0x000000A2, 0x0 }, 254 { 0x00007011, 0x000000A6, 0x0 }, 255 { 0x00000018, 0x000000AB, 0x0 }, 256 { 0x00007013, 0x0000009F, 0x0 }, 257 { 0x00000018, 0x000000DF, 0x0 }, 258 }; 259 260 /* 261 * Skylake/Kabylake U 262 * eDP 1.4 low vswing translation parameters 263 */ 264 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 265 { 0x00000018, 0x000000A8, 0x0 }, 266 { 0x00004013, 0x000000A9, 0x0 }, 267 { 0x00007011, 0x000000A2, 0x0 }, 268 { 0x00009010, 0x0000009C, 0x0 }, 269 { 0x00000018, 0x000000A9, 0x0 }, 270 { 0x00006013, 0x000000A2, 0x0 }, 271 { 0x00007011, 0x000000A6, 0x0 }, 272 { 0x00002016, 0x000000AB, 0x0 }, 273 { 0x00005013, 0x0000009F, 0x0 }, 274 { 0x00000018, 0x000000DF, 0x0 }, 275 }; 276 277 /* 278 * Skylake/Kabylake Y 279 * eDP 1.4 low vswing translation parameters 280 */ 281 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 282 { 0x00000018, 0x000000A8, 0x0 }, 283 { 0x00004013, 0x000000AB, 0x0 }, 284 { 0x00007011, 0x000000A4, 0x0 }, 285 { 0x00009010, 0x000000DF, 0x0 }, 286 { 0x00000018, 0x000000AA, 0x0 }, 287 { 0x00006013, 0x000000A4, 0x0 }, 288 { 0x00007011, 0x0000009D, 0x0 }, 289 { 0x00000018, 0x000000A0, 0x0 }, 290 { 0x00006012, 0x000000DF, 0x0 }, 291 { 0x00000018, 0x0000008A, 0x0 }, 292 }; 293 294 /* Skylake/Kabylake U, H and S */ 295 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 296 { 0x00000018, 0x000000AC, 0x0 }, 297 { 0x00005012, 0x0000009D, 0x0 }, 298 { 0x00007011, 0x00000088, 0x0 }, 299 { 0x00000018, 0x000000A1, 0x0 }, 300 { 0x00000018, 0x00000098, 0x0 }, 301 { 0x00004013, 0x00000088, 0x0 }, 302 { 0x80006012, 0x000000CD, 0x1 }, 303 { 0x00000018, 0x000000DF, 0x0 }, 304 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 305 { 0x80003015, 0x000000C0, 0x1 }, 306 { 0x80000018, 0x000000C0, 0x1 }, 307 }; 308 309 /* Skylake/Kabylake Y */ 310 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 311 { 0x00000018, 0x000000A1, 0x0 }, 312 { 0x00005012, 0x000000DF, 0x0 }, 313 { 0x80007011, 0x000000CB, 0x3 }, 314 { 0x00000018, 0x000000A4, 0x0 }, 315 { 0x00000018, 0x0000009D, 0x0 }, 316 { 0x00004013, 0x00000080, 0x0 }, 317 { 0x80006013, 0x000000C0, 0x3 }, 318 { 0x00000018, 0x0000008A, 0x0 }, 319 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 320 { 0x80003015, 0x000000C0, 0x3 }, 321 { 0x80000018, 0x000000C0, 0x3 }, 322 }; 323 324 struct bxt_ddi_buf_trans { 325 u8 margin; /* swing value */ 326 u8 scale; /* scale value */ 327 u8 enable; /* scale enable */ 328 u8 deemphasis; 329 }; 330 331 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 332 /* Idx NT mV diff db */ 333 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 334 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 335 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 336 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 337 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 338 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 339 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 340 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 341 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 342 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 343 }; 344 345 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 346 /* Idx NT mV diff db */ 347 { 26, 0, 0, 128, }, /* 0: 200 0 */ 348 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 349 { 48, 0, 0, 96, }, /* 2: 200 4 */ 350 { 54, 0, 0, 69, }, /* 3: 200 6 */ 351 { 32, 0, 0, 128, }, /* 4: 250 0 */ 352 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 353 { 54, 0, 0, 85, }, /* 6: 250 4 */ 354 { 43, 0, 0, 128, }, /* 7: 300 0 */ 355 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 356 { 48, 0, 0, 128, }, /* 9: 300 0 */ 357 }; 358 359 /* BSpec has 2 recommended values - entries 0 and 8. 360 * Using the entry with higher vswing. 361 */ 362 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 363 /* Idx NT mV diff db */ 364 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 365 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 366 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 367 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 368 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 369 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 370 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 371 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 372 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 373 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 374 }; 375 376 struct cnl_ddi_buf_trans { 377 u8 dw2_swing_sel; 378 u8 dw7_n_scalar; 379 u8 dw4_cursor_coeff; 380 u8 dw4_post_cursor_2; 381 u8 dw4_post_cursor_1; 382 }; 383 384 /* Voltage Swing Programming for VccIO 0.85V for DP */ 385 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 386 /* NT mV Trans mV db */ 387 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 388 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 389 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 390 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 391 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 392 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 393 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 394 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 395 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 396 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 397 }; 398 399 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 400 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 401 /* NT mV Trans mV db */ 402 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 403 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 404 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 405 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 406 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 407 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 408 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 409 }; 410 411 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 412 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 413 /* NT mV Trans mV db */ 414 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 415 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 416 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 417 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 418 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 419 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 420 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 421 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 422 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 423 }; 424 425 /* Voltage Swing Programming for VccIO 0.95V for DP */ 426 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 427 /* NT mV Trans mV db */ 428 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 429 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 430 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 431 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 432 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 433 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 434 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 435 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 436 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 437 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 438 }; 439 440 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 441 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 442 /* NT mV Trans mV db */ 443 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 444 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 445 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 446 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 447 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 448 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 449 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 450 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 451 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 452 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 453 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 454 }; 455 456 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 457 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 458 /* NT mV Trans mV db */ 459 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 460 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 461 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 462 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 463 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 464 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 465 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 466 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 467 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 468 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 469 }; 470 471 /* Voltage Swing Programming for VccIO 1.05V for DP */ 472 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 473 /* NT mV Trans mV db */ 474 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 475 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 476 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 477 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 478 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 479 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 480 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 481 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 482 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 483 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 484 }; 485 486 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 487 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 488 /* NT mV Trans mV db */ 489 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 490 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 491 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 492 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 493 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 494 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 495 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 496 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 497 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 498 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 499 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 500 }; 501 502 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 503 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 504 /* NT mV Trans mV db */ 505 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 506 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 507 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 508 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 509 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 510 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 511 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 512 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 513 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 514 }; 515 516 /* icl_combo_phy_ddi_translations */ 517 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 518 /* NT mV Trans mV db */ 519 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 520 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 521 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 522 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 523 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 524 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 525 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 526 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 527 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 528 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 529 }; 530 531 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 532 /* NT mV Trans mV db */ 533 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 534 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 535 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 536 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 537 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 538 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 539 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 540 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 541 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 542 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 543 }; 544 545 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 546 /* NT mV Trans mV db */ 547 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 548 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 549 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 550 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 551 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 552 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 553 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 554 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 555 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 556 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 557 }; 558 559 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 560 /* NT mV Trans mV db */ 561 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 562 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 563 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 564 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 565 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 566 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 567 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 568 }; 569 570 struct icl_mg_phy_ddi_buf_trans { 571 u32 cri_txdeemph_override_5_0; 572 u32 cri_txdeemph_override_11_6; 573 u32 cri_txdeemph_override_17_12; 574 }; 575 576 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = { 577 /* Voltage swing pre-emphasis */ 578 { 0x0, 0x1B, 0x00 }, /* 0 0 */ 579 { 0x0, 0x23, 0x08 }, /* 0 1 */ 580 { 0x0, 0x2D, 0x12 }, /* 0 2 */ 581 { 0x0, 0x00, 0x00 }, /* 0 3 */ 582 { 0x0, 0x23, 0x00 }, /* 1 0 */ 583 { 0x0, 0x2B, 0x09 }, /* 1 1 */ 584 { 0x0, 0x2E, 0x11 }, /* 1 2 */ 585 { 0x0, 0x2F, 0x00 }, /* 2 0 */ 586 { 0x0, 0x33, 0x0C }, /* 2 1 */ 587 { 0x0, 0x00, 0x00 }, /* 3 0 */ 588 }; 589 590 struct tgl_dkl_phy_ddi_buf_trans { 591 u32 dkl_vswing_control; 592 u32 dkl_preshoot_control; 593 u32 dkl_de_emphasis_control; 594 }; 595 596 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 597 /* VS pre-emp Non-trans mV Pre-emph dB */ 598 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 599 { 0x5, 0x0, 0x03 }, /* 0 1 400mV 3.5 dB */ 600 { 0x2, 0x0, 0x0b }, /* 0 2 400mV 6 dB */ 601 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 602 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 603 { 0x2, 0x0, 0x03 }, /* 1 1 600mV 3.5 dB */ 604 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 605 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 606 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 607 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 608 }; 609 610 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 611 /* HDMI Preset VS Pre-emph */ 612 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 613 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 614 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 615 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 616 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 617 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 618 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 619 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 620 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 621 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 622 }; 623 624 static const struct ddi_buf_trans * 625 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 626 { 627 if (dev_priv->vbt.edp.low_vswing) { 628 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 629 return bdw_ddi_translations_edp; 630 } else { 631 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 632 return bdw_ddi_translations_dp; 633 } 634 } 635 636 static const struct ddi_buf_trans * 637 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 638 { 639 if (IS_SKL_ULX(dev_priv)) { 640 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 641 return skl_y_ddi_translations_dp; 642 } else if (IS_SKL_ULT(dev_priv)) { 643 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 644 return skl_u_ddi_translations_dp; 645 } else { 646 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 647 return skl_ddi_translations_dp; 648 } 649 } 650 651 static const struct ddi_buf_trans * 652 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 653 { 654 if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { 655 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 656 return kbl_y_ddi_translations_dp; 657 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { 658 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 659 return kbl_u_ddi_translations_dp; 660 } else { 661 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 662 return kbl_ddi_translations_dp; 663 } 664 } 665 666 static const struct ddi_buf_trans * 667 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 668 { 669 if (dev_priv->vbt.edp.low_vswing) { 670 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 671 IS_CFL_ULX(dev_priv)) { 672 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 673 return skl_y_ddi_translations_edp; 674 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || 675 IS_CFL_ULT(dev_priv)) { 676 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 677 return skl_u_ddi_translations_edp; 678 } else { 679 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 680 return skl_ddi_translations_edp; 681 } 682 } 683 684 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) 685 return kbl_get_buf_trans_dp(dev_priv, n_entries); 686 else 687 return skl_get_buf_trans_dp(dev_priv, n_entries); 688 } 689 690 static const struct ddi_buf_trans * 691 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 692 { 693 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || 694 IS_CFL_ULX(dev_priv)) { 695 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 696 return skl_y_ddi_translations_hdmi; 697 } else { 698 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 699 return skl_ddi_translations_hdmi; 700 } 701 } 702 703 static int skl_buf_trans_num_entries(enum port port, int n_entries) 704 { 705 /* Only DDIA and DDIE can select the 10th register with DP */ 706 if (port == PORT_A || port == PORT_E) 707 return min(n_entries, 10); 708 else 709 return min(n_entries, 9); 710 } 711 712 static const struct ddi_buf_trans * 713 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, 714 enum port port, int *n_entries) 715 { 716 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { 717 const struct ddi_buf_trans *ddi_translations = 718 kbl_get_buf_trans_dp(dev_priv, n_entries); 719 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 720 return ddi_translations; 721 } else if (IS_SKYLAKE(dev_priv)) { 722 const struct ddi_buf_trans *ddi_translations = 723 skl_get_buf_trans_dp(dev_priv, n_entries); 724 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 725 return ddi_translations; 726 } else if (IS_BROADWELL(dev_priv)) { 727 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 728 return bdw_ddi_translations_dp; 729 } else if (IS_HASWELL(dev_priv)) { 730 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 731 return hsw_ddi_translations_dp; 732 } 733 734 *n_entries = 0; 735 return NULL; 736 } 737 738 static const struct ddi_buf_trans * 739 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, 740 enum port port, int *n_entries) 741 { 742 if (IS_GEN9_BC(dev_priv)) { 743 const struct ddi_buf_trans *ddi_translations = 744 skl_get_buf_trans_edp(dev_priv, n_entries); 745 *n_entries = skl_buf_trans_num_entries(port, *n_entries); 746 return ddi_translations; 747 } else if (IS_BROADWELL(dev_priv)) { 748 return bdw_get_buf_trans_edp(dev_priv, n_entries); 749 } else if (IS_HASWELL(dev_priv)) { 750 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 751 return hsw_ddi_translations_dp; 752 } 753 754 *n_entries = 0; 755 return NULL; 756 } 757 758 static const struct ddi_buf_trans * 759 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 760 int *n_entries) 761 { 762 if (IS_BROADWELL(dev_priv)) { 763 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 764 return bdw_ddi_translations_fdi; 765 } else if (IS_HASWELL(dev_priv)) { 766 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 767 return hsw_ddi_translations_fdi; 768 } 769 770 *n_entries = 0; 771 return NULL; 772 } 773 774 static const struct ddi_buf_trans * 775 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, 776 int *n_entries) 777 { 778 if (IS_GEN9_BC(dev_priv)) { 779 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 780 } else if (IS_BROADWELL(dev_priv)) { 781 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 782 return bdw_ddi_translations_hdmi; 783 } else if (IS_HASWELL(dev_priv)) { 784 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 785 return hsw_ddi_translations_hdmi; 786 } 787 788 *n_entries = 0; 789 return NULL; 790 } 791 792 static const struct bxt_ddi_buf_trans * 793 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 794 { 795 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 796 return bxt_ddi_translations_dp; 797 } 798 799 static const struct bxt_ddi_buf_trans * 800 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 801 { 802 if (dev_priv->vbt.edp.low_vswing) { 803 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 804 return bxt_ddi_translations_edp; 805 } 806 807 return bxt_get_buf_trans_dp(dev_priv, n_entries); 808 } 809 810 static const struct bxt_ddi_buf_trans * 811 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 812 { 813 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 814 return bxt_ddi_translations_hdmi; 815 } 816 817 static const struct cnl_ddi_buf_trans * 818 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 819 { 820 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 821 822 if (voltage == VOLTAGE_INFO_0_85V) { 823 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 824 return cnl_ddi_translations_hdmi_0_85V; 825 } else if (voltage == VOLTAGE_INFO_0_95V) { 826 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 827 return cnl_ddi_translations_hdmi_0_95V; 828 } else if (voltage == VOLTAGE_INFO_1_05V) { 829 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 830 return cnl_ddi_translations_hdmi_1_05V; 831 } else { 832 *n_entries = 1; /* shut up gcc */ 833 MISSING_CASE(voltage); 834 } 835 return NULL; 836 } 837 838 static const struct cnl_ddi_buf_trans * 839 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 840 { 841 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 842 843 if (voltage == VOLTAGE_INFO_0_85V) { 844 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 845 return cnl_ddi_translations_dp_0_85V; 846 } else if (voltage == VOLTAGE_INFO_0_95V) { 847 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 848 return cnl_ddi_translations_dp_0_95V; 849 } else if (voltage == VOLTAGE_INFO_1_05V) { 850 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 851 return cnl_ddi_translations_dp_1_05V; 852 } else { 853 *n_entries = 1; /* shut up gcc */ 854 MISSING_CASE(voltage); 855 } 856 return NULL; 857 } 858 859 static const struct cnl_ddi_buf_trans * 860 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 861 { 862 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 863 864 if (dev_priv->vbt.edp.low_vswing) { 865 if (voltage == VOLTAGE_INFO_0_85V) { 866 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 867 return cnl_ddi_translations_edp_0_85V; 868 } else if (voltage == VOLTAGE_INFO_0_95V) { 869 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 870 return cnl_ddi_translations_edp_0_95V; 871 } else if (voltage == VOLTAGE_INFO_1_05V) { 872 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 873 return cnl_ddi_translations_edp_1_05V; 874 } else { 875 *n_entries = 1; /* shut up gcc */ 876 MISSING_CASE(voltage); 877 } 878 return NULL; 879 } else { 880 return cnl_get_buf_trans_dp(dev_priv, n_entries); 881 } 882 } 883 884 static const struct cnl_ddi_buf_trans * 885 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, 886 int *n_entries) 887 { 888 if (type == INTEL_OUTPUT_HDMI) { 889 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 890 return icl_combo_phy_ddi_translations_hdmi; 891 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) { 892 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 893 return icl_combo_phy_ddi_translations_edp_hbr3; 894 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 895 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 896 return icl_combo_phy_ddi_translations_edp_hbr2; 897 } 898 899 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 900 return icl_combo_phy_ddi_translations_dp_hbr2; 901 } 902 903 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) 904 { 905 int n_entries, level, default_entry; 906 enum phy phy = intel_port_to_phy(dev_priv, port); 907 908 level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 909 910 if (INTEL_GEN(dev_priv) >= 12) { 911 if (intel_phy_is_combo(dev_priv, phy)) 912 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 913 0, &n_entries); 914 else 915 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 916 default_entry = n_entries - 1; 917 } else if (INTEL_GEN(dev_priv) == 11) { 918 if (intel_phy_is_combo(dev_priv, phy)) 919 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 920 0, &n_entries); 921 else 922 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 923 default_entry = n_entries - 1; 924 } else if (IS_CANNONLAKE(dev_priv)) { 925 cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 926 default_entry = n_entries - 1; 927 } else if (IS_GEN9_LP(dev_priv)) { 928 bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 929 default_entry = n_entries - 1; 930 } else if (IS_GEN9_BC(dev_priv)) { 931 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 932 default_entry = 8; 933 } else if (IS_BROADWELL(dev_priv)) { 934 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 935 default_entry = 7; 936 } else if (IS_HASWELL(dev_priv)) { 937 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 938 default_entry = 6; 939 } else { 940 WARN(1, "ddi translation table missing\n"); 941 return 0; 942 } 943 944 /* Choose a good default if VBT is badly populated */ 945 if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries) 946 level = default_entry; 947 948 if (WARN_ON_ONCE(n_entries == 0)) 949 return 0; 950 if (WARN_ON_ONCE(level >= n_entries)) 951 level = n_entries - 1; 952 953 return level; 954 } 955 956 /* 957 * Starting with Haswell, DDI port buffers must be programmed with correct 958 * values in advance. This function programs the correct values for 959 * DP/eDP/FDI use cases. 960 */ 961 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 962 const struct intel_crtc_state *crtc_state) 963 { 964 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 965 u32 iboost_bit = 0; 966 int i, n_entries; 967 enum port port = encoder->port; 968 const struct ddi_buf_trans *ddi_translations; 969 970 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 971 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 972 &n_entries); 973 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 974 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, 975 &n_entries); 976 else 977 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, 978 &n_entries); 979 980 /* If we're boosting the current, set bit 31 of trans1 */ 981 if (IS_GEN9_BC(dev_priv) && 982 dev_priv->vbt.ddi_port_info[port].dp_boost_level) 983 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 984 985 for (i = 0; i < n_entries; i++) { 986 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 987 ddi_translations[i].trans1 | iboost_bit); 988 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 989 ddi_translations[i].trans2); 990 } 991 } 992 993 /* 994 * Starting with Haswell, DDI port buffers must be programmed with correct 995 * values in advance. This function programs the correct values for 996 * HDMI/DVI use cases. 997 */ 998 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 999 int level) 1000 { 1001 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1002 u32 iboost_bit = 0; 1003 int n_entries; 1004 enum port port = encoder->port; 1005 const struct ddi_buf_trans *ddi_translations; 1006 1007 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 1008 1009 if (WARN_ON_ONCE(!ddi_translations)) 1010 return; 1011 if (WARN_ON_ONCE(level >= n_entries)) 1012 level = n_entries - 1; 1013 1014 /* If we're boosting the current, set bit 31 of trans1 */ 1015 if (IS_GEN9_BC(dev_priv) && 1016 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) 1017 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1018 1019 /* Entry 9 is for HDMI: */ 1020 I915_WRITE(DDI_BUF_TRANS_LO(port, 9), 1021 ddi_translations[level].trans1 | iboost_bit); 1022 I915_WRITE(DDI_BUF_TRANS_HI(port, 9), 1023 ddi_translations[level].trans2); 1024 } 1025 1026 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 1027 enum port port) 1028 { 1029 i915_reg_t reg = DDI_BUF_CTL(port); 1030 int i; 1031 1032 for (i = 0; i < 16; i++) { 1033 udelay(1); 1034 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 1035 return; 1036 } 1037 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 1038 } 1039 1040 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 1041 { 1042 switch (pll->info->id) { 1043 case DPLL_ID_WRPLL1: 1044 return PORT_CLK_SEL_WRPLL1; 1045 case DPLL_ID_WRPLL2: 1046 return PORT_CLK_SEL_WRPLL2; 1047 case DPLL_ID_SPLL: 1048 return PORT_CLK_SEL_SPLL; 1049 case DPLL_ID_LCPLL_810: 1050 return PORT_CLK_SEL_LCPLL_810; 1051 case DPLL_ID_LCPLL_1350: 1052 return PORT_CLK_SEL_LCPLL_1350; 1053 case DPLL_ID_LCPLL_2700: 1054 return PORT_CLK_SEL_LCPLL_2700; 1055 default: 1056 MISSING_CASE(pll->info->id); 1057 return PORT_CLK_SEL_NONE; 1058 } 1059 } 1060 1061 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1062 const struct intel_crtc_state *crtc_state) 1063 { 1064 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1065 int clock = crtc_state->port_clock; 1066 const enum intel_dpll_id id = pll->info->id; 1067 1068 switch (id) { 1069 default: 1070 /* 1071 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1072 * here, so do warn if this get passed in 1073 */ 1074 MISSING_CASE(id); 1075 return DDI_CLK_SEL_NONE; 1076 case DPLL_ID_ICL_TBTPLL: 1077 switch (clock) { 1078 case 162000: 1079 return DDI_CLK_SEL_TBT_162; 1080 case 270000: 1081 return DDI_CLK_SEL_TBT_270; 1082 case 540000: 1083 return DDI_CLK_SEL_TBT_540; 1084 case 810000: 1085 return DDI_CLK_SEL_TBT_810; 1086 default: 1087 MISSING_CASE(clock); 1088 return DDI_CLK_SEL_NONE; 1089 } 1090 case DPLL_ID_ICL_MGPLL1: 1091 case DPLL_ID_ICL_MGPLL2: 1092 case DPLL_ID_ICL_MGPLL3: 1093 case DPLL_ID_ICL_MGPLL4: 1094 case DPLL_ID_TGL_MGPLL5: 1095 case DPLL_ID_TGL_MGPLL6: 1096 return DDI_CLK_SEL_MG; 1097 } 1098 } 1099 1100 /* Starting with Haswell, different DDI ports can work in FDI mode for 1101 * connection to the PCH-located connectors. For this, it is necessary to train 1102 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1103 * 1104 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1105 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1106 * DDI A (which is used for eDP) 1107 */ 1108 1109 void hsw_fdi_link_train(struct intel_crtc *crtc, 1110 const struct intel_crtc_state *crtc_state) 1111 { 1112 struct drm_device *dev = crtc->base.dev; 1113 struct drm_i915_private *dev_priv = to_i915(dev); 1114 struct intel_encoder *encoder; 1115 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1116 1117 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 1118 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); 1119 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1120 } 1121 1122 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1123 * mode set "sequence for CRT port" document: 1124 * - TP1 to TP2 time with the default value 1125 * - FDI delay to 90h 1126 * 1127 * WaFDIAutoLinkSetTimingOverrride:hsw 1128 */ 1129 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | 1130 FDI_RX_PWRDN_LANE0_VAL(2) | 1131 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1132 1133 /* Enable the PCH Receiver FDI PLL */ 1134 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1135 FDI_RX_PLL_ENABLE | 1136 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1137 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1138 POSTING_READ(FDI_RX_CTL(PIPE_A)); 1139 udelay(220); 1140 1141 /* Switch from Rawclk to PCDclk */ 1142 rx_ctl_val |= FDI_PCDCLK; 1143 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1144 1145 /* Configure Port Clock Select */ 1146 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1147 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1148 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL); 1149 1150 /* Start the training iterating through available voltages and emphasis, 1151 * testing each value twice. */ 1152 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1153 /* Configure DP_TP_CTL with auto-training */ 1154 I915_WRITE(DP_TP_CTL(PORT_E), 1155 DP_TP_CTL_FDI_AUTOTRAIN | 1156 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1157 DP_TP_CTL_LINK_TRAIN_PAT1 | 1158 DP_TP_CTL_ENABLE); 1159 1160 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1161 * DDI E does not support port reversal, the functionality is 1162 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1163 * port reversal bit */ 1164 I915_WRITE(DDI_BUF_CTL(PORT_E), 1165 DDI_BUF_CTL_ENABLE | 1166 ((crtc_state->fdi_lanes - 1) << 1) | 1167 DDI_BUF_TRANS_SELECT(i / 2)); 1168 POSTING_READ(DDI_BUF_CTL(PORT_E)); 1169 1170 udelay(600); 1171 1172 /* Program PCH FDI Receiver TU */ 1173 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1174 1175 /* Enable PCH FDI Receiver with auto-training */ 1176 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1177 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1178 POSTING_READ(FDI_RX_CTL(PIPE_A)); 1179 1180 /* Wait for FDI receiver lane calibration */ 1181 udelay(30); 1182 1183 /* Unset FDI_RX_MISC pwrdn lanes */ 1184 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 1185 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1186 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 1187 POSTING_READ(FDI_RX_MISC(PIPE_A)); 1188 1189 /* Wait for FDI auto training time */ 1190 udelay(5); 1191 1192 temp = I915_READ(DP_TP_STATUS(PORT_E)); 1193 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1194 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 1195 break; 1196 } 1197 1198 /* 1199 * Leave things enabled even if we failed to train FDI. 1200 * Results in less fireworks from the state checker. 1201 */ 1202 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1203 DRM_ERROR("FDI link training failed!\n"); 1204 break; 1205 } 1206 1207 rx_ctl_val &= ~FDI_RX_ENABLE; 1208 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 1209 POSTING_READ(FDI_RX_CTL(PIPE_A)); 1210 1211 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 1212 temp &= ~DDI_BUF_CTL_ENABLE; 1213 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 1214 POSTING_READ(DDI_BUF_CTL(PORT_E)); 1215 1216 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1217 temp = I915_READ(DP_TP_CTL(PORT_E)); 1218 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1219 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1220 I915_WRITE(DP_TP_CTL(PORT_E), temp); 1221 POSTING_READ(DP_TP_CTL(PORT_E)); 1222 1223 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1224 1225 /* Reset FDI_RX_MISC pwrdn lanes */ 1226 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 1227 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1228 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1229 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 1230 POSTING_READ(FDI_RX_MISC(PIPE_A)); 1231 } 1232 1233 /* Enable normal pixel sending for FDI */ 1234 I915_WRITE(DP_TP_CTL(PORT_E), 1235 DP_TP_CTL_FDI_AUTOTRAIN | 1236 DP_TP_CTL_LINK_TRAIN_NORMAL | 1237 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1238 DP_TP_CTL_ENABLE); 1239 } 1240 1241 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 1242 { 1243 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1244 struct intel_digital_port *intel_dig_port = 1245 enc_to_dig_port(&encoder->base); 1246 1247 intel_dp->DP = intel_dig_port->saved_port_bits | 1248 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1249 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 1250 } 1251 1252 static struct intel_encoder * 1253 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) 1254 { 1255 struct drm_device *dev = crtc->base.dev; 1256 struct intel_encoder *encoder, *ret = NULL; 1257 int num_encoders = 0; 1258 1259 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 1260 ret = encoder; 1261 num_encoders++; 1262 } 1263 1264 if (num_encoders != 1) 1265 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 1266 pipe_name(crtc->pipe)); 1267 1268 BUG_ON(ret == NULL); 1269 return ret; 1270 } 1271 1272 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 1273 i915_reg_t reg) 1274 { 1275 int refclk; 1276 int n, p, r; 1277 u32 wrpll; 1278 1279 wrpll = I915_READ(reg); 1280 switch (wrpll & WRPLL_REF_MASK) { 1281 case WRPLL_REF_SPECIAL_HSW: 1282 /* 1283 * muxed-SSC for BDW. 1284 * non-SSC for non-ULT HSW. Check FUSE_STRAP3 1285 * for the non-SSC reference frequency. 1286 */ 1287 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) { 1288 if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT) 1289 refclk = 24; 1290 else 1291 refclk = 135; 1292 break; 1293 } 1294 /* fall through */ 1295 case WRPLL_REF_PCH_SSC: 1296 /* 1297 * We could calculate spread here, but our checking 1298 * code only cares about 5% accuracy, and spread is a max of 1299 * 0.5% downspread. 1300 */ 1301 refclk = 135; 1302 break; 1303 case WRPLL_REF_LCPLL: 1304 refclk = 2700; 1305 break; 1306 default: 1307 MISSING_CASE(wrpll); 1308 return 0; 1309 } 1310 1311 r = wrpll & WRPLL_DIVIDER_REF_MASK; 1312 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 1313 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 1314 1315 /* Convert to KHz, p & r have a fixed point portion */ 1316 return (refclk * n * 100) / (p * r); 1317 } 1318 1319 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state) 1320 { 1321 u32 p0, p1, p2, dco_freq; 1322 1323 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; 1324 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; 1325 1326 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) 1327 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 1328 else 1329 p1 = 1; 1330 1331 1332 switch (p0) { 1333 case DPLL_CFGCR2_PDIV_1: 1334 p0 = 1; 1335 break; 1336 case DPLL_CFGCR2_PDIV_2: 1337 p0 = 2; 1338 break; 1339 case DPLL_CFGCR2_PDIV_3: 1340 p0 = 3; 1341 break; 1342 case DPLL_CFGCR2_PDIV_7: 1343 p0 = 7; 1344 break; 1345 } 1346 1347 switch (p2) { 1348 case DPLL_CFGCR2_KDIV_5: 1349 p2 = 5; 1350 break; 1351 case DPLL_CFGCR2_KDIV_2: 1352 p2 = 2; 1353 break; 1354 case DPLL_CFGCR2_KDIV_3: 1355 p2 = 3; 1356 break; 1357 case DPLL_CFGCR2_KDIV_1: 1358 p2 = 1; 1359 break; 1360 } 1361 1362 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) 1363 * 24 * 1000; 1364 1365 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) 1366 * 24 * 1000) / 0x8000; 1367 1368 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) 1369 return 0; 1370 1371 return dco_freq / (p0 * p1 * p2 * 5); 1372 } 1373 1374 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, 1375 struct intel_dpll_hw_state *pll_state) 1376 { 1377 u32 p0, p1, p2, dco_freq, ref_clock; 1378 1379 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; 1380 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; 1381 1382 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) 1383 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> 1384 DPLL_CFGCR1_QDIV_RATIO_SHIFT; 1385 else 1386 p1 = 1; 1387 1388 1389 switch (p0) { 1390 case DPLL_CFGCR1_PDIV_2: 1391 p0 = 2; 1392 break; 1393 case DPLL_CFGCR1_PDIV_3: 1394 p0 = 3; 1395 break; 1396 case DPLL_CFGCR1_PDIV_5: 1397 p0 = 5; 1398 break; 1399 case DPLL_CFGCR1_PDIV_7: 1400 p0 = 7; 1401 break; 1402 } 1403 1404 switch (p2) { 1405 case DPLL_CFGCR1_KDIV_1: 1406 p2 = 1; 1407 break; 1408 case DPLL_CFGCR1_KDIV_2: 1409 p2 = 2; 1410 break; 1411 case DPLL_CFGCR1_KDIV_3: 1412 p2 = 3; 1413 break; 1414 } 1415 1416 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv); 1417 1418 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) 1419 * ref_clock; 1420 1421 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> 1422 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000; 1423 1424 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) 1425 return 0; 1426 1427 return dco_freq / (p0 * p1 * p2 * 5); 1428 } 1429 1430 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1431 enum port port) 1432 { 1433 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1434 1435 switch (val) { 1436 case DDI_CLK_SEL_NONE: 1437 return 0; 1438 case DDI_CLK_SEL_TBT_162: 1439 return 162000; 1440 case DDI_CLK_SEL_TBT_270: 1441 return 270000; 1442 case DDI_CLK_SEL_TBT_540: 1443 return 540000; 1444 case DDI_CLK_SEL_TBT_810: 1445 return 810000; 1446 default: 1447 MISSING_CASE(val); 1448 return 0; 1449 } 1450 } 1451 1452 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv, 1453 const struct intel_dpll_hw_state *pll_state) 1454 { 1455 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; 1456 u64 tmp; 1457 1458 ref_clock = dev_priv->cdclk.hw.ref; 1459 1460 if (INTEL_GEN(dev_priv) >= 12) { 1461 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; 1462 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT; 1463 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; 1464 1465 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) { 1466 m2_frac = pll_state->mg_pll_bias & 1467 DKL_PLL_BIAS_FBDIV_FRAC_MASK; 1468 m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT; 1469 } else { 1470 m2_frac = 0; 1471 } 1472 } else { 1473 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; 1474 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; 1475 1476 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) { 1477 m2_frac = pll_state->mg_pll_div0 & 1478 MG_PLL_DIV0_FBDIV_FRAC_MASK; 1479 m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT; 1480 } else { 1481 m2_frac = 0; 1482 } 1483 } 1484 1485 switch (pll_state->mg_clktop2_hsclkctl & 1486 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) { 1487 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2: 1488 div1 = 2; 1489 break; 1490 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3: 1491 div1 = 3; 1492 break; 1493 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5: 1494 div1 = 5; 1495 break; 1496 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7: 1497 div1 = 7; 1498 break; 1499 default: 1500 MISSING_CASE(pll_state->mg_clktop2_hsclkctl); 1501 return 0; 1502 } 1503 1504 div2 = (pll_state->mg_clktop2_hsclkctl & 1505 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >> 1506 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT; 1507 1508 /* div2 value of 0 is same as 1 means no div */ 1509 if (div2 == 0) 1510 div2 = 1; 1511 1512 /* 1513 * Adjust the original formula to delay the division by 2^22 in order to 1514 * minimize possible rounding errors. 1515 */ 1516 tmp = (u64)m1 * m2_int * ref_clock + 1517 (((u64)m1 * m2_frac * ref_clock) >> 22); 1518 tmp = div_u64(tmp, 5 * div1 * div2); 1519 1520 return tmp; 1521 } 1522 1523 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1524 { 1525 int dotclock; 1526 1527 if (pipe_config->has_pch_encoder) 1528 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1529 &pipe_config->fdi_m_n); 1530 else if (intel_crtc_has_dp_encoder(pipe_config)) 1531 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1532 &pipe_config->dp_m_n); 1533 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 1534 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 1535 else 1536 dotclock = pipe_config->port_clock; 1537 1538 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1539 !intel_crtc_has_dp_encoder(pipe_config)) 1540 dotclock *= 2; 1541 1542 if (pipe_config->pixel_multiplier) 1543 dotclock /= pipe_config->pixel_multiplier; 1544 1545 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1546 } 1547 1548 static void icl_ddi_clock_get(struct intel_encoder *encoder, 1549 struct intel_crtc_state *pipe_config) 1550 { 1551 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1552 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1553 enum port port = encoder->port; 1554 enum phy phy = intel_port_to_phy(dev_priv, port); 1555 int link_clock; 1556 1557 if (intel_phy_is_combo(dev_priv, phy)) { 1558 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); 1559 } else { 1560 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv, 1561 pipe_config->shared_dpll); 1562 1563 if (pll_id == DPLL_ID_ICL_TBTPLL) 1564 link_clock = icl_calc_tbt_pll_link(dev_priv, port); 1565 else 1566 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state); 1567 } 1568 1569 pipe_config->port_clock = link_clock; 1570 1571 ddi_dotclock_get(pipe_config); 1572 } 1573 1574 static void cnl_ddi_clock_get(struct intel_encoder *encoder, 1575 struct intel_crtc_state *pipe_config) 1576 { 1577 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1578 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1579 int link_clock; 1580 1581 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { 1582 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); 1583 } else { 1584 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; 1585 1586 switch (link_clock) { 1587 case DPLL_CFGCR0_LINK_RATE_810: 1588 link_clock = 81000; 1589 break; 1590 case DPLL_CFGCR0_LINK_RATE_1080: 1591 link_clock = 108000; 1592 break; 1593 case DPLL_CFGCR0_LINK_RATE_1350: 1594 link_clock = 135000; 1595 break; 1596 case DPLL_CFGCR0_LINK_RATE_1620: 1597 link_clock = 162000; 1598 break; 1599 case DPLL_CFGCR0_LINK_RATE_2160: 1600 link_clock = 216000; 1601 break; 1602 case DPLL_CFGCR0_LINK_RATE_2700: 1603 link_clock = 270000; 1604 break; 1605 case DPLL_CFGCR0_LINK_RATE_3240: 1606 link_clock = 324000; 1607 break; 1608 case DPLL_CFGCR0_LINK_RATE_4050: 1609 link_clock = 405000; 1610 break; 1611 default: 1612 WARN(1, "Unsupported link rate\n"); 1613 break; 1614 } 1615 link_clock *= 2; 1616 } 1617 1618 pipe_config->port_clock = link_clock; 1619 1620 ddi_dotclock_get(pipe_config); 1621 } 1622 1623 static void skl_ddi_clock_get(struct intel_encoder *encoder, 1624 struct intel_crtc_state *pipe_config) 1625 { 1626 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; 1627 int link_clock; 1628 1629 /* 1630 * ctrl1 register is already shifted for each pll, just use 0 to get 1631 * the internal shift for each field 1632 */ 1633 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) { 1634 link_clock = skl_calc_wrpll_link(pll_state); 1635 } else { 1636 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0); 1637 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0); 1638 1639 switch (link_clock) { 1640 case DPLL_CTRL1_LINK_RATE_810: 1641 link_clock = 81000; 1642 break; 1643 case DPLL_CTRL1_LINK_RATE_1080: 1644 link_clock = 108000; 1645 break; 1646 case DPLL_CTRL1_LINK_RATE_1350: 1647 link_clock = 135000; 1648 break; 1649 case DPLL_CTRL1_LINK_RATE_1620: 1650 link_clock = 162000; 1651 break; 1652 case DPLL_CTRL1_LINK_RATE_2160: 1653 link_clock = 216000; 1654 break; 1655 case DPLL_CTRL1_LINK_RATE_2700: 1656 link_clock = 270000; 1657 break; 1658 default: 1659 WARN(1, "Unsupported link rate\n"); 1660 break; 1661 } 1662 link_clock *= 2; 1663 } 1664 1665 pipe_config->port_clock = link_clock; 1666 1667 ddi_dotclock_get(pipe_config); 1668 } 1669 1670 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 1671 struct intel_crtc_state *pipe_config) 1672 { 1673 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1674 int link_clock = 0; 1675 u32 val, pll; 1676 1677 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); 1678 switch (val & PORT_CLK_SEL_MASK) { 1679 case PORT_CLK_SEL_LCPLL_810: 1680 link_clock = 81000; 1681 break; 1682 case PORT_CLK_SEL_LCPLL_1350: 1683 link_clock = 135000; 1684 break; 1685 case PORT_CLK_SEL_LCPLL_2700: 1686 link_clock = 270000; 1687 break; 1688 case PORT_CLK_SEL_WRPLL1: 1689 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); 1690 break; 1691 case PORT_CLK_SEL_WRPLL2: 1692 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); 1693 break; 1694 case PORT_CLK_SEL_SPLL: 1695 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK; 1696 if (pll == SPLL_FREQ_810MHz) 1697 link_clock = 81000; 1698 else if (pll == SPLL_FREQ_1350MHz) 1699 link_clock = 135000; 1700 else if (pll == SPLL_FREQ_2700MHz) 1701 link_clock = 270000; 1702 else { 1703 WARN(1, "bad spll freq\n"); 1704 return; 1705 } 1706 break; 1707 default: 1708 WARN(1, "bad port clock sel\n"); 1709 return; 1710 } 1711 1712 pipe_config->port_clock = link_clock * 2; 1713 1714 ddi_dotclock_get(pipe_config); 1715 } 1716 1717 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state) 1718 { 1719 struct dpll clock; 1720 1721 clock.m1 = 2; 1722 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22; 1723 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) 1724 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK; 1725 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 1726 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 1727 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 1728 1729 return chv_calc_dpll_params(100000, &clock); 1730 } 1731 1732 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 1733 struct intel_crtc_state *pipe_config) 1734 { 1735 pipe_config->port_clock = 1736 bxt_calc_pll_link(&pipe_config->dpll_hw_state); 1737 1738 ddi_dotclock_get(pipe_config); 1739 } 1740 1741 static void intel_ddi_clock_get(struct intel_encoder *encoder, 1742 struct intel_crtc_state *pipe_config) 1743 { 1744 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1745 1746 if (INTEL_GEN(dev_priv) >= 11) 1747 icl_ddi_clock_get(encoder, pipe_config); 1748 else if (IS_CANNONLAKE(dev_priv)) 1749 cnl_ddi_clock_get(encoder, pipe_config); 1750 else if (IS_GEN9_LP(dev_priv)) 1751 bxt_ddi_clock_get(encoder, pipe_config); 1752 else if (IS_GEN9_BC(dev_priv)) 1753 skl_ddi_clock_get(encoder, pipe_config); 1754 else if (INTEL_GEN(dev_priv) <= 8) 1755 hsw_ddi_clock_get(encoder, pipe_config); 1756 } 1757 1758 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 1759 const struct drm_connector_state *conn_state) 1760 { 1761 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1763 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1764 u32 temp; 1765 1766 if (!intel_crtc_has_dp_encoder(crtc_state)) 1767 return; 1768 1769 WARN_ON(transcoder_is_dsi(cpu_transcoder)); 1770 1771 temp = DP_MSA_MISC_SYNC_CLOCK; 1772 1773 switch (crtc_state->pipe_bpp) { 1774 case 18: 1775 temp |= DP_MSA_MISC_6_BPC; 1776 break; 1777 case 24: 1778 temp |= DP_MSA_MISC_8_BPC; 1779 break; 1780 case 30: 1781 temp |= DP_MSA_MISC_10_BPC; 1782 break; 1783 case 36: 1784 temp |= DP_MSA_MISC_12_BPC; 1785 break; 1786 default: 1787 MISSING_CASE(crtc_state->pipe_bpp); 1788 break; 1789 } 1790 1791 /* nonsense combination */ 1792 WARN_ON(crtc_state->limited_color_range && 1793 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 1794 1795 if (crtc_state->limited_color_range) 1796 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 1797 1798 /* 1799 * As per DP 1.2 spec section 2.3.4.3 while sending 1800 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1801 * colorspace information. 1802 */ 1803 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1804 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1805 1806 /* 1807 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1808 * of Color Encoding Format and Content Color Gamut] while sending 1809 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 1810 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1811 */ 1812 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1813 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 1814 1815 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1816 } 1817 1818 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, 1819 bool state) 1820 { 1821 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1823 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1824 u32 temp; 1825 1826 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1827 if (state == true) 1828 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1829 else 1830 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1831 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1832 } 1833 1834 /* 1835 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 1836 * 1837 * Only intended to be used by intel_ddi_enable_transcoder_func() and 1838 * intel_ddi_config_transcoder_func(). 1839 */ 1840 static u32 1841 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state) 1842 { 1843 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1844 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 1845 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1846 enum pipe pipe = crtc->pipe; 1847 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1848 enum port port = encoder->port; 1849 u32 temp; 1850 1851 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1852 temp = TRANS_DDI_FUNC_ENABLE; 1853 if (INTEL_GEN(dev_priv) >= 12) 1854 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1855 else 1856 temp |= TRANS_DDI_SELECT_PORT(port); 1857 1858 switch (crtc_state->pipe_bpp) { 1859 case 18: 1860 temp |= TRANS_DDI_BPC_6; 1861 break; 1862 case 24: 1863 temp |= TRANS_DDI_BPC_8; 1864 break; 1865 case 30: 1866 temp |= TRANS_DDI_BPC_10; 1867 break; 1868 case 36: 1869 temp |= TRANS_DDI_BPC_12; 1870 break; 1871 default: 1872 BUG(); 1873 } 1874 1875 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1876 temp |= TRANS_DDI_PVSYNC; 1877 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1878 temp |= TRANS_DDI_PHSYNC; 1879 1880 if (cpu_transcoder == TRANSCODER_EDP) { 1881 switch (pipe) { 1882 case PIPE_A: 1883 /* On Haswell, can only use the always-on power well for 1884 * eDP when not using the panel fitter, and when not 1885 * using motion blur mitigation (which we don't 1886 * support). */ 1887 if (crtc_state->pch_pfit.force_thru) 1888 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1889 else 1890 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1891 break; 1892 case PIPE_B: 1893 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1894 break; 1895 case PIPE_C: 1896 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1897 break; 1898 default: 1899 BUG(); 1900 break; 1901 } 1902 } 1903 1904 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1905 if (crtc_state->has_hdmi_sink) 1906 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1907 else 1908 temp |= TRANS_DDI_MODE_SELECT_DVI; 1909 1910 if (crtc_state->hdmi_scrambling) 1911 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1912 if (crtc_state->hdmi_high_tmds_clock_ratio) 1913 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1914 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1915 temp |= TRANS_DDI_MODE_SELECT_FDI; 1916 temp |= (crtc_state->fdi_lanes - 1) << 1; 1917 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1918 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1919 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1920 1921 if (INTEL_GEN(dev_priv) >= 12) 1922 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder); 1923 } else { 1924 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1925 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1926 } 1927 1928 return temp; 1929 } 1930 1931 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) 1932 { 1933 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1934 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1935 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1936 u32 temp; 1937 1938 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); 1939 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1940 } 1941 1942 /* 1943 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 1944 * bit. 1945 */ 1946 static void 1947 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state) 1948 { 1949 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1950 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1951 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1952 u32 temp; 1953 1954 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); 1955 temp &= ~TRANS_DDI_FUNC_ENABLE; 1956 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1957 } 1958 1959 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 1960 { 1961 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1962 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1963 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1964 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1965 u32 val = I915_READ(reg); 1966 1967 if (INTEL_GEN(dev_priv) >= 12) { 1968 val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK | 1969 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1970 } else { 1971 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | 1972 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1973 } 1974 I915_WRITE(reg, val); 1975 1976 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 1977 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1978 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n"); 1979 /* Quirk time at 100ms for reliable operation */ 1980 msleep(100); 1981 } 1982 } 1983 1984 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 1985 bool enable) 1986 { 1987 struct drm_device *dev = intel_encoder->base.dev; 1988 struct drm_i915_private *dev_priv = to_i915(dev); 1989 intel_wakeref_t wakeref; 1990 enum pipe pipe = 0; 1991 int ret = 0; 1992 u32 tmp; 1993 1994 wakeref = intel_display_power_get_if_enabled(dev_priv, 1995 intel_encoder->power_domain); 1996 if (WARN_ON(!wakeref)) 1997 return -ENXIO; 1998 1999 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) { 2000 ret = -EIO; 2001 goto out; 2002 } 2003 2004 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe)); 2005 if (enable) 2006 tmp |= TRANS_DDI_HDCP_SIGNALLING; 2007 else 2008 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 2009 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp); 2010 out: 2011 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 2012 return ret; 2013 } 2014 2015 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 2016 { 2017 struct drm_device *dev = intel_connector->base.dev; 2018 struct drm_i915_private *dev_priv = to_i915(dev); 2019 struct intel_encoder *encoder = intel_connector->encoder; 2020 int type = intel_connector->base.connector_type; 2021 enum port port = encoder->port; 2022 enum transcoder cpu_transcoder; 2023 intel_wakeref_t wakeref; 2024 enum pipe pipe = 0; 2025 u32 tmp; 2026 bool ret; 2027 2028 wakeref = intel_display_power_get_if_enabled(dev_priv, 2029 encoder->power_domain); 2030 if (!wakeref) 2031 return false; 2032 2033 if (!encoder->get_hw_state(encoder, &pipe)) { 2034 ret = false; 2035 goto out; 2036 } 2037 2038 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) 2039 cpu_transcoder = TRANSCODER_EDP; 2040 else 2041 cpu_transcoder = (enum transcoder) pipe; 2042 2043 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2044 2045 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 2046 case TRANS_DDI_MODE_SELECT_HDMI: 2047 case TRANS_DDI_MODE_SELECT_DVI: 2048 ret = type == DRM_MODE_CONNECTOR_HDMIA; 2049 break; 2050 2051 case TRANS_DDI_MODE_SELECT_DP_SST: 2052 ret = type == DRM_MODE_CONNECTOR_eDP || 2053 type == DRM_MODE_CONNECTOR_DisplayPort; 2054 break; 2055 2056 case TRANS_DDI_MODE_SELECT_DP_MST: 2057 /* if the transcoder is in MST state then 2058 * connector isn't connected */ 2059 ret = false; 2060 break; 2061 2062 case TRANS_DDI_MODE_SELECT_FDI: 2063 ret = type == DRM_MODE_CONNECTOR_VGA; 2064 break; 2065 2066 default: 2067 ret = false; 2068 break; 2069 } 2070 2071 out: 2072 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2073 2074 return ret; 2075 } 2076 2077 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 2078 u8 *pipe_mask, bool *is_dp_mst) 2079 { 2080 struct drm_device *dev = encoder->base.dev; 2081 struct drm_i915_private *dev_priv = to_i915(dev); 2082 enum port port = encoder->port; 2083 intel_wakeref_t wakeref; 2084 enum pipe p; 2085 u32 tmp; 2086 u8 mst_pipe_mask; 2087 2088 *pipe_mask = 0; 2089 *is_dp_mst = false; 2090 2091 wakeref = intel_display_power_get_if_enabled(dev_priv, 2092 encoder->power_domain); 2093 if (!wakeref) 2094 return; 2095 2096 tmp = I915_READ(DDI_BUF_CTL(port)); 2097 if (!(tmp & DDI_BUF_CTL_ENABLE)) 2098 goto out; 2099 2100 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) { 2101 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 2102 2103 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 2104 default: 2105 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 2106 /* fallthrough */ 2107 case TRANS_DDI_EDP_INPUT_A_ON: 2108 case TRANS_DDI_EDP_INPUT_A_ONOFF: 2109 *pipe_mask = BIT(PIPE_A); 2110 break; 2111 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2112 *pipe_mask = BIT(PIPE_B); 2113 break; 2114 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2115 *pipe_mask = BIT(PIPE_C); 2116 break; 2117 } 2118 2119 goto out; 2120 } 2121 2122 mst_pipe_mask = 0; 2123 for_each_pipe(dev_priv, p) { 2124 enum transcoder cpu_transcoder = (enum transcoder)p; 2125 unsigned int port_mask, ddi_select; 2126 intel_wakeref_t trans_wakeref; 2127 2128 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 2129 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 2130 if (!trans_wakeref) 2131 continue; 2132 2133 if (INTEL_GEN(dev_priv) >= 12) { 2134 port_mask = TGL_TRANS_DDI_PORT_MASK; 2135 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 2136 } else { 2137 port_mask = TRANS_DDI_PORT_MASK; 2138 ddi_select = TRANS_DDI_SELECT_PORT(port); 2139 } 2140 2141 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2142 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 2143 trans_wakeref); 2144 2145 if ((tmp & port_mask) != ddi_select) 2146 continue; 2147 2148 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 2149 TRANS_DDI_MODE_SELECT_DP_MST) 2150 mst_pipe_mask |= BIT(p); 2151 2152 *pipe_mask |= BIT(p); 2153 } 2154 2155 if (!*pipe_mask) 2156 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n", 2157 encoder->base.base.id, encoder->base.name); 2158 2159 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 2160 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 2161 encoder->base.base.id, encoder->base.name, 2162 *pipe_mask); 2163 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 2164 } 2165 2166 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 2167 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 2168 encoder->base.base.id, encoder->base.name, 2169 *pipe_mask, mst_pipe_mask); 2170 else 2171 *is_dp_mst = mst_pipe_mask; 2172 2173 out: 2174 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 2175 tmp = I915_READ(BXT_PHY_CTL(port)); 2176 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 2177 BXT_PHY_LANE_POWERDOWN_ACK | 2178 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 2179 DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? " 2180 "(PHY_CTL %08x)\n", encoder->base.base.id, 2181 encoder->base.name, tmp); 2182 } 2183 2184 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2185 } 2186 2187 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 2188 enum pipe *pipe) 2189 { 2190 u8 pipe_mask; 2191 bool is_mst; 2192 2193 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2194 2195 if (is_mst || !pipe_mask) 2196 return false; 2197 2198 *pipe = ffs(pipe_mask) - 1; 2199 2200 return true; 2201 } 2202 2203 static inline enum intel_display_power_domain 2204 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 2205 { 2206 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 2207 * DC states enabled at the same time, while for driver initiated AUX 2208 * transfers we need the same AUX IOs to be powered but with DC states 2209 * disabled. Accordingly use the AUX power domain here which leaves DC 2210 * states enabled. 2211 * However, for non-A AUX ports the corresponding non-EDP transcoders 2212 * would have already enabled power well 2 and DC_OFF. This means we can 2213 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 2214 * specific AUX_IO reference without powering up any extra wells. 2215 * Note that PSR is enabled only on Port A even though this function 2216 * returns the correct domain for other ports too. 2217 */ 2218 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 2219 intel_aux_power_domain(dig_port); 2220 } 2221 2222 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 2223 struct intel_crtc_state *crtc_state) 2224 { 2225 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2226 struct intel_digital_port *dig_port; 2227 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2228 2229 /* 2230 * TODO: Add support for MST encoders. Atm, the following should never 2231 * happen since fake-MST encoders don't set their get_power_domains() 2232 * hook. 2233 */ 2234 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 2235 return; 2236 2237 dig_port = enc_to_dig_port(&encoder->base); 2238 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 2239 2240 /* 2241 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 2242 * ports. 2243 */ 2244 if (intel_crtc_has_dp_encoder(crtc_state) || 2245 intel_phy_is_tc(dev_priv, phy)) 2246 intel_display_power_get(dev_priv, 2247 intel_ddi_main_link_aux_domain(dig_port)); 2248 2249 /* 2250 * VDSC power is needed when DSC is enabled 2251 */ 2252 if (crtc_state->dsc.compression_enable) 2253 intel_display_power_get(dev_priv, 2254 intel_dsc_power_domain(crtc_state)); 2255 } 2256 2257 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) 2258 { 2259 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 2260 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2261 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 2262 enum port port = encoder->port; 2263 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2264 2265 if (cpu_transcoder != TRANSCODER_EDP) { 2266 if (INTEL_GEN(dev_priv) >= 12) 2267 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2268 TGL_TRANS_CLK_SEL_PORT(port)); 2269 else 2270 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2271 TRANS_CLK_SEL_PORT(port)); 2272 } 2273 } 2274 2275 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 2276 { 2277 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); 2278 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2279 2280 if (cpu_transcoder != TRANSCODER_EDP) { 2281 if (INTEL_GEN(dev_priv) >= 12) 2282 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2283 TGL_TRANS_CLK_SEL_DISABLED); 2284 else 2285 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2286 TRANS_CLK_SEL_DISABLED); 2287 } 2288 } 2289 2290 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2291 enum port port, u8 iboost) 2292 { 2293 u32 tmp; 2294 2295 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); 2296 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 2297 if (iboost) 2298 tmp |= iboost << BALANCE_LEG_SHIFT(port); 2299 else 2300 tmp |= BALANCE_LEG_DISABLE(port); 2301 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); 2302 } 2303 2304 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 2305 int level, enum intel_output_type type) 2306 { 2307 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 2308 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2309 enum port port = encoder->port; 2310 u8 iboost; 2311 2312 if (type == INTEL_OUTPUT_HDMI) 2313 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; 2314 else 2315 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; 2316 2317 if (iboost == 0) { 2318 const struct ddi_buf_trans *ddi_translations; 2319 int n_entries; 2320 2321 if (type == INTEL_OUTPUT_HDMI) 2322 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); 2323 else if (type == INTEL_OUTPUT_EDP) 2324 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2325 else 2326 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2327 2328 if (WARN_ON_ONCE(!ddi_translations)) 2329 return; 2330 if (WARN_ON_ONCE(level >= n_entries)) 2331 level = n_entries - 1; 2332 2333 iboost = ddi_translations[level].i_boost; 2334 } 2335 2336 /* Make sure that the requested I_boost is valid */ 2337 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2338 DRM_ERROR("Invalid I_boost value %u\n", iboost); 2339 return; 2340 } 2341 2342 _skl_ddi_set_iboost(dev_priv, port, iboost); 2343 2344 if (port == PORT_A && intel_dig_port->max_lanes == 4) 2345 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 2346 } 2347 2348 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 2349 int level, enum intel_output_type type) 2350 { 2351 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2352 const struct bxt_ddi_buf_trans *ddi_translations; 2353 enum port port = encoder->port; 2354 int n_entries; 2355 2356 if (type == INTEL_OUTPUT_HDMI) 2357 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); 2358 else if (type == INTEL_OUTPUT_EDP) 2359 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); 2360 else 2361 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); 2362 2363 if (WARN_ON_ONCE(!ddi_translations)) 2364 return; 2365 if (WARN_ON_ONCE(level >= n_entries)) 2366 level = n_entries - 1; 2367 2368 bxt_ddi_phy_set_signal_level(dev_priv, port, 2369 ddi_translations[level].margin, 2370 ddi_translations[level].scale, 2371 ddi_translations[level].enable, 2372 ddi_translations[level].deemphasis); 2373 } 2374 2375 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 2376 { 2377 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2378 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2379 enum port port = encoder->port; 2380 enum phy phy = intel_port_to_phy(dev_priv, port); 2381 int n_entries; 2382 2383 if (INTEL_GEN(dev_priv) >= 12) { 2384 if (intel_phy_is_combo(dev_priv, phy)) 2385 icl_get_combo_buf_trans(dev_priv, encoder->type, 2386 intel_dp->link_rate, &n_entries); 2387 else 2388 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 2389 } else if (INTEL_GEN(dev_priv) == 11) { 2390 if (intel_phy_is_combo(dev_priv, phy)) 2391 icl_get_combo_buf_trans(dev_priv, encoder->type, 2392 intel_dp->link_rate, &n_entries); 2393 else 2394 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2395 } else if (IS_CANNONLAKE(dev_priv)) { 2396 if (encoder->type == INTEL_OUTPUT_EDP) 2397 cnl_get_buf_trans_edp(dev_priv, &n_entries); 2398 else 2399 cnl_get_buf_trans_dp(dev_priv, &n_entries); 2400 } else if (IS_GEN9_LP(dev_priv)) { 2401 if (encoder->type == INTEL_OUTPUT_EDP) 2402 bxt_get_buf_trans_edp(dev_priv, &n_entries); 2403 else 2404 bxt_get_buf_trans_dp(dev_priv, &n_entries); 2405 } else { 2406 if (encoder->type == INTEL_OUTPUT_EDP) 2407 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); 2408 else 2409 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); 2410 } 2411 2412 if (WARN_ON(n_entries < 1)) 2413 n_entries = 1; 2414 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2415 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2416 2417 return index_to_dp_signal_levels[n_entries - 1] & 2418 DP_TRAIN_VOLTAGE_SWING_MASK; 2419 } 2420 2421 /* 2422 * We assume that the full set of pre-emphasis values can be 2423 * used on all DDI platforms. Should that change we need to 2424 * rethink this code. 2425 */ 2426 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing) 2427 { 2428 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2429 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2430 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2431 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2432 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2433 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2434 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2435 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2436 default: 2437 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2438 } 2439 } 2440 2441 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2442 int level, enum intel_output_type type) 2443 { 2444 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2445 const struct cnl_ddi_buf_trans *ddi_translations; 2446 enum port port = encoder->port; 2447 int n_entries, ln; 2448 u32 val; 2449 2450 if (type == INTEL_OUTPUT_HDMI) 2451 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); 2452 else if (type == INTEL_OUTPUT_EDP) 2453 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); 2454 else 2455 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); 2456 2457 if (WARN_ON_ONCE(!ddi_translations)) 2458 return; 2459 if (WARN_ON_ONCE(level >= n_entries)) 2460 level = n_entries - 1; 2461 2462 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2463 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2464 val &= ~SCALING_MODE_SEL_MASK; 2465 val |= SCALING_MODE_SEL(2); 2466 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2467 2468 /* Program PORT_TX_DW2 */ 2469 val = I915_READ(CNL_PORT_TX_DW2_LN0(port)); 2470 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2471 RCOMP_SCALAR_MASK); 2472 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2473 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2474 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2475 val |= RCOMP_SCALAR(0x98); 2476 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val); 2477 2478 /* Program PORT_TX_DW4 */ 2479 /* We cannot write to GRP. It would overrite individual loadgen */ 2480 for (ln = 0; ln < 4; ln++) { 2481 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); 2482 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2483 CURSOR_COEFF_MASK); 2484 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2485 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2486 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2487 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); 2488 } 2489 2490 /* Program PORT_TX_DW5 */ 2491 /* All DW5 values are fixed for every table entry */ 2492 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2493 val &= ~RTERM_SELECT_MASK; 2494 val |= RTERM_SELECT(6); 2495 val |= TAP3_DISABLE; 2496 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2497 2498 /* Program PORT_TX_DW7 */ 2499 val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); 2500 val &= ~N_SCALAR_MASK; 2501 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2502 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val); 2503 } 2504 2505 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2506 int level, enum intel_output_type type) 2507 { 2508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2509 enum port port = encoder->port; 2510 int width, rate, ln; 2511 u32 val; 2512 2513 if (type == INTEL_OUTPUT_HDMI) { 2514 width = 4; 2515 rate = 0; /* Rate is always < than 6GHz for HDMI */ 2516 } else { 2517 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2518 2519 width = intel_dp->lane_count; 2520 rate = intel_dp->link_rate; 2521 } 2522 2523 /* 2524 * 1. If port type is eDP or DP, 2525 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2526 * else clear to 0b. 2527 */ 2528 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port)); 2529 if (type != INTEL_OUTPUT_HDMI) 2530 val |= COMMON_KEEPER_EN; 2531 else 2532 val &= ~COMMON_KEEPER_EN; 2533 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val); 2534 2535 /* 2. Program loadgen select */ 2536 /* 2537 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2538 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2539 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2540 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2541 */ 2542 for (ln = 0; ln <= 3; ln++) { 2543 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); 2544 val &= ~LOADGEN_SELECT; 2545 2546 if ((rate <= 600000 && width == 4 && ln >= 1) || 2547 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2548 val |= LOADGEN_SELECT; 2549 } 2550 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); 2551 } 2552 2553 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2554 val = I915_READ(CNL_PORT_CL1CM_DW5); 2555 val |= SUS_CLOCK_CONFIG; 2556 I915_WRITE(CNL_PORT_CL1CM_DW5, val); 2557 2558 /* 4. Clear training enable to change swing values */ 2559 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2560 val &= ~TX_TRAINING_EN; 2561 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2562 2563 /* 5. Program swing and de-emphasis */ 2564 cnl_ddi_vswing_program(encoder, level, type); 2565 2566 /* 6. Set training enable to trigger update */ 2567 val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); 2568 val |= TX_TRAINING_EN; 2569 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); 2570 } 2571 2572 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, 2573 u32 level, enum phy phy, int type, 2574 int rate) 2575 { 2576 const struct cnl_ddi_buf_trans *ddi_translations = NULL; 2577 u32 n_entries, val; 2578 int ln; 2579 2580 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, 2581 &n_entries); 2582 if (!ddi_translations) 2583 return; 2584 2585 if (level >= n_entries) { 2586 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1); 2587 level = n_entries - 1; 2588 } 2589 2590 /* Set PORT_TX_DW5 */ 2591 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 2592 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2593 TAP2_DISABLE | TAP3_DISABLE); 2594 val |= SCALING_MODE_SEL(0x2); 2595 val |= RTERM_SELECT(0x6); 2596 val |= TAP3_DISABLE; 2597 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); 2598 2599 /* Program PORT_TX_DW2 */ 2600 val = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); 2601 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2602 RCOMP_SCALAR_MASK); 2603 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2604 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2605 /* Program Rcomp scalar for every table entry */ 2606 val |= RCOMP_SCALAR(0x98); 2607 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val); 2608 2609 /* Program PORT_TX_DW4 */ 2610 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2611 for (ln = 0; ln <= 3; ln++) { 2612 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); 2613 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2614 CURSOR_COEFF_MASK); 2615 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2616 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2617 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2618 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); 2619 } 2620 2621 /* Program PORT_TX_DW7 */ 2622 val = I915_READ(ICL_PORT_TX_DW7_LN0(phy)); 2623 val &= ~N_SCALAR_MASK; 2624 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2625 I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val); 2626 } 2627 2628 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2629 u32 level, 2630 enum intel_output_type type) 2631 { 2632 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2633 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2634 int width = 0; 2635 int rate = 0; 2636 u32 val; 2637 int ln = 0; 2638 2639 if (type == INTEL_OUTPUT_HDMI) { 2640 width = 4; 2641 /* Rate is always < than 6GHz for HDMI */ 2642 } else { 2643 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2644 2645 width = intel_dp->lane_count; 2646 rate = intel_dp->link_rate; 2647 } 2648 2649 /* 2650 * 1. If port type is eDP or DP, 2651 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2652 * else clear to 0b. 2653 */ 2654 val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); 2655 if (type == INTEL_OUTPUT_HDMI) 2656 val &= ~COMMON_KEEPER_EN; 2657 else 2658 val |= COMMON_KEEPER_EN; 2659 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val); 2660 2661 /* 2. Program loadgen select */ 2662 /* 2663 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2664 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2665 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2666 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2667 */ 2668 for (ln = 0; ln <= 3; ln++) { 2669 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); 2670 val &= ~LOADGEN_SELECT; 2671 2672 if ((rate <= 600000 && width == 4 && ln >= 1) || 2673 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2674 val |= LOADGEN_SELECT; 2675 } 2676 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); 2677 } 2678 2679 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2680 val = I915_READ(ICL_PORT_CL_DW5(phy)); 2681 val |= SUS_CLOCK_CONFIG; 2682 I915_WRITE(ICL_PORT_CL_DW5(phy), val); 2683 2684 /* 4. Clear training enable to change swing values */ 2685 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 2686 val &= ~TX_TRAINING_EN; 2687 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); 2688 2689 /* 5. Program swing and de-emphasis */ 2690 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); 2691 2692 /* 6. Set training enable to trigger update */ 2693 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); 2694 val |= TX_TRAINING_EN; 2695 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); 2696 } 2697 2698 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2699 int link_clock, 2700 u32 level) 2701 { 2702 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2703 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2704 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2705 u32 n_entries, val; 2706 int ln; 2707 2708 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); 2709 ddi_translations = icl_mg_phy_ddi_translations; 2710 /* The table does not have values for level 3 and level 9. */ 2711 if (level >= n_entries || level == 3 || level == 9) { 2712 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", 2713 level, n_entries - 2); 2714 level = n_entries - 2; 2715 } 2716 2717 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2718 for (ln = 0; ln < 2; ln++) { 2719 val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port)); 2720 val &= ~CRI_USE_FS32; 2721 I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val); 2722 2723 val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port)); 2724 val &= ~CRI_USE_FS32; 2725 I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val); 2726 } 2727 2728 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2729 for (ln = 0; ln < 2; ln++) { 2730 val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port)); 2731 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2732 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2733 ddi_translations[level].cri_txdeemph_override_17_12); 2734 I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val); 2735 2736 val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port)); 2737 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2738 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2739 ddi_translations[level].cri_txdeemph_override_17_12); 2740 I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val); 2741 } 2742 2743 /* Program MG_TX_DRVCTRL with values from vswing table */ 2744 for (ln = 0; ln < 2; ln++) { 2745 val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port)); 2746 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2747 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2748 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2749 ddi_translations[level].cri_txdeemph_override_5_0) | 2750 CRI_TXDEEMPH_OVERRIDE_11_6( 2751 ddi_translations[level].cri_txdeemph_override_11_6) | 2752 CRI_TXDEEMPH_OVERRIDE_EN; 2753 I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val); 2754 2755 val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port)); 2756 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2757 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2758 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2759 ddi_translations[level].cri_txdeemph_override_5_0) | 2760 CRI_TXDEEMPH_OVERRIDE_11_6( 2761 ddi_translations[level].cri_txdeemph_override_11_6) | 2762 CRI_TXDEEMPH_OVERRIDE_EN; 2763 I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val); 2764 2765 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2766 } 2767 2768 /* 2769 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2770 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2771 * values from table for which TX1 and TX2 enabled. 2772 */ 2773 for (ln = 0; ln < 2; ln++) { 2774 val = I915_READ(MG_CLKHUB(ln, tc_port)); 2775 if (link_clock < 300000) 2776 val |= CFG_LOW_RATE_LKREN_EN; 2777 else 2778 val &= ~CFG_LOW_RATE_LKREN_EN; 2779 I915_WRITE(MG_CLKHUB(ln, tc_port), val); 2780 } 2781 2782 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2783 for (ln = 0; ln < 2; ln++) { 2784 val = I915_READ(MG_TX1_DCC(ln, tc_port)); 2785 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2786 if (link_clock <= 500000) { 2787 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2788 } else { 2789 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2790 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2791 } 2792 I915_WRITE(MG_TX1_DCC(ln, tc_port), val); 2793 2794 val = I915_READ(MG_TX2_DCC(ln, tc_port)); 2795 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2796 if (link_clock <= 500000) { 2797 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2798 } else { 2799 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2800 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2801 } 2802 I915_WRITE(MG_TX2_DCC(ln, tc_port), val); 2803 } 2804 2805 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2806 for (ln = 0; ln < 2; ln++) { 2807 val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port)); 2808 val |= CRI_CALCINIT; 2809 I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val); 2810 2811 val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port)); 2812 val |= CRI_CALCINIT; 2813 I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val); 2814 } 2815 } 2816 2817 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2818 int link_clock, 2819 u32 level, 2820 enum intel_output_type type) 2821 { 2822 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2823 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2824 2825 if (intel_phy_is_combo(dev_priv, phy)) 2826 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2827 else 2828 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level); 2829 } 2830 2831 static void 2832 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, 2833 u32 level) 2834 { 2835 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2836 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2837 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2838 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; 2839 2840 if (encoder->type == INTEL_OUTPUT_HDMI) { 2841 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 2842 ddi_translations = tgl_dkl_phy_hdmi_ddi_trans; 2843 } else { 2844 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 2845 ddi_translations = tgl_dkl_phy_dp_ddi_trans; 2846 } 2847 2848 if (level >= n_entries) 2849 level = n_entries - 1; 2850 2851 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 2852 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 2853 DKL_TX_VSWING_CONTROL_MASK); 2854 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 2855 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 2856 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 2857 2858 for (ln = 0; ln < 2; ln++) { 2859 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); 2860 2861 I915_WRITE(DKL_TX_PMD_LANE_SUS(tc_port), 0); 2862 2863 /* All the registers are RMW */ 2864 val = I915_READ(DKL_TX_DPCNTL0(tc_port)); 2865 val &= ~dpcnt_mask; 2866 val |= dpcnt_val; 2867 I915_WRITE(DKL_TX_DPCNTL0(tc_port), val); 2868 2869 val = I915_READ(DKL_TX_DPCNTL1(tc_port)); 2870 val &= ~dpcnt_mask; 2871 val |= dpcnt_val; 2872 I915_WRITE(DKL_TX_DPCNTL1(tc_port), val); 2873 2874 val = I915_READ(DKL_TX_DPCNTL2(tc_port)); 2875 val &= ~DKL_TX_DP20BITMODE; 2876 I915_WRITE(DKL_TX_DPCNTL2(tc_port), val); 2877 } 2878 } 2879 2880 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 2881 int link_clock, 2882 u32 level, 2883 enum intel_output_type type) 2884 { 2885 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2886 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2887 2888 if (intel_phy_is_combo(dev_priv, phy)) 2889 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2890 else 2891 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level); 2892 } 2893 2894 static u32 translate_signal_level(int signal_levels) 2895 { 2896 int i; 2897 2898 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 2899 if (index_to_dp_signal_levels[i] == signal_levels) 2900 return i; 2901 } 2902 2903 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2904 signal_levels); 2905 2906 return 0; 2907 } 2908 2909 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp) 2910 { 2911 u8 train_set = intel_dp->train_set[0]; 2912 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2913 DP_TRAIN_PRE_EMPHASIS_MASK); 2914 2915 return translate_signal_level(signal_levels); 2916 } 2917 2918 u32 bxt_signal_levels(struct intel_dp *intel_dp) 2919 { 2920 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2921 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 2922 struct intel_encoder *encoder = &dport->base; 2923 int level = intel_ddi_dp_level(intel_dp); 2924 2925 if (INTEL_GEN(dev_priv) >= 12) 2926 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2927 level, encoder->type); 2928 else if (INTEL_GEN(dev_priv) >= 11) 2929 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2930 level, encoder->type); 2931 else if (IS_CANNONLAKE(dev_priv)) 2932 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 2933 else 2934 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 2935 2936 return 0; 2937 } 2938 2939 u32 ddi_signal_levels(struct intel_dp *intel_dp) 2940 { 2941 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2942 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 2943 struct intel_encoder *encoder = &dport->base; 2944 int level = intel_ddi_dp_level(intel_dp); 2945 2946 if (IS_GEN9_BC(dev_priv)) 2947 skl_ddi_set_iboost(encoder, level, encoder->type); 2948 2949 return DDI_BUF_TRANS_SELECT(level); 2950 } 2951 2952 static inline 2953 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 2954 enum phy phy) 2955 { 2956 if (intel_phy_is_combo(dev_priv, phy)) { 2957 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2958 } else if (intel_phy_is_tc(dev_priv, phy)) { 2959 enum tc_port tc_port = intel_port_to_tc(dev_priv, 2960 (enum port)phy); 2961 2962 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 2963 } 2964 2965 return 0; 2966 } 2967 2968 static void icl_map_plls_to_ports(struct intel_encoder *encoder, 2969 const struct intel_crtc_state *crtc_state) 2970 { 2971 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2972 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2973 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2974 u32 val; 2975 2976 mutex_lock(&dev_priv->dpll_lock); 2977 2978 val = I915_READ(ICL_DPCLKA_CFGCR0); 2979 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 2980 2981 if (intel_phy_is_combo(dev_priv, phy)) { 2982 /* 2983 * Even though this register references DDIs, note that we 2984 * want to pass the PHY rather than the port (DDI). For 2985 * ICL, port=phy in all cases so it doesn't matter, but for 2986 * EHL the bspec notes the following: 2987 * 2988 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 2989 * Clock Select chooses the PLL for both DDIA and DDID and 2990 * drives port A in all cases." 2991 */ 2992 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2993 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2994 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 2995 POSTING_READ(ICL_DPCLKA_CFGCR0); 2996 } 2997 2998 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2999 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 3000 3001 mutex_unlock(&dev_priv->dpll_lock); 3002 } 3003 3004 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 3005 { 3006 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3007 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3008 u32 val; 3009 3010 mutex_lock(&dev_priv->dpll_lock); 3011 3012 val = I915_READ(ICL_DPCLKA_CFGCR0); 3013 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3014 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 3015 3016 mutex_unlock(&dev_priv->dpll_lock); 3017 } 3018 3019 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 3020 { 3021 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3022 u32 val; 3023 enum port port; 3024 u32 port_mask; 3025 bool ddi_clk_needed; 3026 3027 /* 3028 * In case of DP MST, we sanitize the primary encoder only, not the 3029 * virtual ones. 3030 */ 3031 if (encoder->type == INTEL_OUTPUT_DP_MST) 3032 return; 3033 3034 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 3035 u8 pipe_mask; 3036 bool is_mst; 3037 3038 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 3039 /* 3040 * In the unlikely case that BIOS enables DP in MST mode, just 3041 * warn since our MST HW readout is incomplete. 3042 */ 3043 if (WARN_ON(is_mst)) 3044 return; 3045 } 3046 3047 port_mask = BIT(encoder->port); 3048 ddi_clk_needed = encoder->base.crtc; 3049 3050 if (encoder->type == INTEL_OUTPUT_DSI) { 3051 struct intel_encoder *other_encoder; 3052 3053 port_mask = intel_dsi_encoder_ports(encoder); 3054 /* 3055 * Sanity check that we haven't incorrectly registered another 3056 * encoder using any of the ports of this DSI encoder. 3057 */ 3058 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 3059 if (other_encoder == encoder) 3060 continue; 3061 3062 if (WARN_ON(port_mask & BIT(other_encoder->port))) 3063 return; 3064 } 3065 /* 3066 * For DSI we keep the ddi clocks gated 3067 * except during enable/disable sequence. 3068 */ 3069 ddi_clk_needed = false; 3070 } 3071 3072 val = I915_READ(ICL_DPCLKA_CFGCR0); 3073 for_each_port_masked(port, port_mask) { 3074 enum phy phy = intel_port_to_phy(dev_priv, port); 3075 3076 bool ddi_clk_ungated = !(val & 3077 icl_dpclka_cfgcr0_clk_off(dev_priv, 3078 phy)); 3079 3080 if (ddi_clk_needed == ddi_clk_ungated) 3081 continue; 3082 3083 /* 3084 * Punt on the case now where clock is gated, but it would 3085 * be needed by the port. Something else is really broken then. 3086 */ 3087 if (WARN_ON(ddi_clk_needed)) 3088 continue; 3089 3090 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 3091 phy_name(port)); 3092 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 3093 I915_WRITE(ICL_DPCLKA_CFGCR0, val); 3094 } 3095 } 3096 3097 static void intel_ddi_clk_select(struct intel_encoder *encoder, 3098 const struct intel_crtc_state *crtc_state) 3099 { 3100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3101 enum port port = encoder->port; 3102 enum phy phy = intel_port_to_phy(dev_priv, port); 3103 u32 val; 3104 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 3105 3106 if (WARN_ON(!pll)) 3107 return; 3108 3109 mutex_lock(&dev_priv->dpll_lock); 3110 3111 if (INTEL_GEN(dev_priv) >= 11) { 3112 if (!intel_phy_is_combo(dev_priv, phy)) 3113 I915_WRITE(DDI_CLK_SEL(port), 3114 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 3115 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) 3116 /* 3117 * MG does not exist but the programming is required 3118 * to ungate DDIC and DDID 3119 */ 3120 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 3121 } else if (IS_CANNONLAKE(dev_priv)) { 3122 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 3123 val = I915_READ(DPCLKA_CFGCR0); 3124 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 3125 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 3126 I915_WRITE(DPCLKA_CFGCR0, val); 3127 3128 /* 3129 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 3130 * This step and the step before must be done with separate 3131 * register writes. 3132 */ 3133 val = I915_READ(DPCLKA_CFGCR0); 3134 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 3135 I915_WRITE(DPCLKA_CFGCR0, val); 3136 } else if (IS_GEN9_BC(dev_priv)) { 3137 /* DDI -> PLL mapping */ 3138 val = I915_READ(DPLL_CTRL2); 3139 3140 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 3141 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 3142 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 3143 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 3144 3145 I915_WRITE(DPLL_CTRL2, val); 3146 3147 } else if (INTEL_GEN(dev_priv) < 9) { 3148 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 3149 } 3150 3151 mutex_unlock(&dev_priv->dpll_lock); 3152 } 3153 3154 static void intel_ddi_clk_disable(struct intel_encoder *encoder) 3155 { 3156 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3157 enum port port = encoder->port; 3158 enum phy phy = intel_port_to_phy(dev_priv, port); 3159 3160 if (INTEL_GEN(dev_priv) >= 11) { 3161 if (!intel_phy_is_combo(dev_priv, phy) || 3162 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) 3163 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 3164 } else if (IS_CANNONLAKE(dev_priv)) { 3165 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) | 3166 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 3167 } else if (IS_GEN9_BC(dev_priv)) { 3168 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) | 3169 DPLL_CTRL2_DDI_CLK_OFF(port)); 3170 } else if (INTEL_GEN(dev_priv) < 9) { 3171 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 3172 } 3173 } 3174 3175 static void 3176 icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable) 3177 { 3178 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 3179 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 3180 u32 val, bits; 3181 int ln; 3182 3183 if (tc_port == PORT_TC_NONE) 3184 return; 3185 3186 bits = MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING | 3187 MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING | 3188 MG_DP_MODE_CFG_GAONPWR_GATING; 3189 3190 for (ln = 0; ln < 2; ln++) { 3191 if (INTEL_GEN(dev_priv) >= 12) { 3192 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); 3193 val = I915_READ(DKL_DP_MODE(tc_port)); 3194 } else { 3195 val = I915_READ(MG_DP_MODE(ln, tc_port)); 3196 } 3197 3198 if (enable) 3199 val |= bits; 3200 else 3201 val &= ~bits; 3202 3203 if (INTEL_GEN(dev_priv) >= 12) 3204 I915_WRITE(DKL_DP_MODE(tc_port), val); 3205 else 3206 I915_WRITE(MG_DP_MODE(ln, tc_port), val); 3207 } 3208 3209 if (INTEL_GEN(dev_priv) == 11) { 3210 bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | 3211 MG_MISC_SUS0_CFG_CL2PWR_GATING | 3212 MG_MISC_SUS0_CFG_GAONPWR_GATING | 3213 MG_MISC_SUS0_CFG_TRPWR_GATING | 3214 MG_MISC_SUS0_CFG_CL1PWR_GATING | 3215 MG_MISC_SUS0_CFG_DGPWR_GATING; 3216 3217 val = I915_READ(MG_MISC_SUS0(tc_port)); 3218 if (enable) 3219 val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3)); 3220 else 3221 val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK); 3222 I915_WRITE(MG_MISC_SUS0(tc_port), val); 3223 } 3224 } 3225 3226 static void 3227 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, 3228 const struct intel_crtc_state *crtc_state) 3229 { 3230 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 3231 enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port); 3232 u32 ln0, ln1, pin_assignment; 3233 u8 width; 3234 3235 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) 3236 return; 3237 3238 if (INTEL_GEN(dev_priv) >= 12) { 3239 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0)); 3240 ln0 = I915_READ(DKL_DP_MODE(tc_port)); 3241 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1)); 3242 ln1 = I915_READ(DKL_DP_MODE(tc_port)); 3243 } else { 3244 ln0 = I915_READ(MG_DP_MODE(0, tc_port)); 3245 ln1 = I915_READ(MG_DP_MODE(1, tc_port)); 3246 } 3247 3248 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE); 3249 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3250 3251 /* DPPATC */ 3252 pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port); 3253 width = crtc_state->lane_count; 3254 3255 switch (pin_assignment) { 3256 case 0x0: 3257 WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY); 3258 if (width == 1) { 3259 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3260 } else { 3261 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3262 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3263 } 3264 break; 3265 case 0x1: 3266 if (width == 4) { 3267 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3268 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3269 } 3270 break; 3271 case 0x2: 3272 if (width == 2) { 3273 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3274 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3275 } 3276 break; 3277 case 0x3: 3278 case 0x5: 3279 if (width == 1) { 3280 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3281 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3282 } else { 3283 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3284 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3285 } 3286 break; 3287 case 0x4: 3288 case 0x6: 3289 if (width == 1) { 3290 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3291 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3292 } else { 3293 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3294 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3295 } 3296 break; 3297 default: 3298 MISSING_CASE(pin_assignment); 3299 } 3300 3301 if (INTEL_GEN(dev_priv) >= 12) { 3302 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0)); 3303 I915_WRITE(DKL_DP_MODE(tc_port), ln0); 3304 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1)); 3305 I915_WRITE(DKL_DP_MODE(tc_port), ln1); 3306 } else { 3307 I915_WRITE(MG_DP_MODE(0, tc_port), ln0); 3308 I915_WRITE(MG_DP_MODE(1, tc_port), ln1); 3309 } 3310 } 3311 3312 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 3313 const struct intel_crtc_state *crtc_state) 3314 { 3315 if (!crtc_state->fec_enable) 3316 return; 3317 3318 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 3319 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n"); 3320 } 3321 3322 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 3323 const struct intel_crtc_state *crtc_state) 3324 { 3325 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3326 struct intel_dp *intel_dp; 3327 u32 val; 3328 3329 if (!crtc_state->fec_enable) 3330 return; 3331 3332 intel_dp = enc_to_intel_dp(&encoder->base); 3333 val = I915_READ(intel_dp->regs.dp_tp_ctl); 3334 val |= DP_TP_CTL_FEC_ENABLE; 3335 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 3336 3337 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 3338 DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) 3339 DRM_ERROR("Timed out waiting for FEC Enable Status\n"); 3340 } 3341 3342 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 3343 const struct intel_crtc_state *crtc_state) 3344 { 3345 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3346 struct intel_dp *intel_dp; 3347 u32 val; 3348 3349 if (!crtc_state->fec_enable) 3350 return; 3351 3352 intel_dp = enc_to_intel_dp(&encoder->base); 3353 val = I915_READ(intel_dp->regs.dp_tp_ctl); 3354 val &= ~DP_TP_CTL_FEC_ENABLE; 3355 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 3356 POSTING_READ(intel_dp->regs.dp_tp_ctl); 3357 } 3358 3359 static void 3360 tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) 3361 { 3362 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); 3363 u32 val; 3364 3365 if (!cstate->dc3co_exitline) 3366 return; 3367 3368 val = I915_READ(EXITLINE(cstate->cpu_transcoder)); 3369 val &= ~(EXITLINE_MASK | EXITLINE_ENABLE); 3370 I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); 3371 } 3372 3373 static void 3374 tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) 3375 { 3376 u32 val, exit_scanlines; 3377 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); 3378 3379 if (!cstate->dc3co_exitline) 3380 return; 3381 3382 exit_scanlines = cstate->dc3co_exitline; 3383 exit_scanlines <<= EXITLINE_SHIFT; 3384 val = I915_READ(EXITLINE(cstate->cpu_transcoder)); 3385 val &= ~(EXITLINE_MASK | EXITLINE_ENABLE); 3386 val |= exit_scanlines; 3387 val |= EXITLINE_ENABLE; 3388 I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); 3389 } 3390 3391 static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder, 3392 struct intel_crtc_state *cstate) 3393 { 3394 u32 exit_scanlines; 3395 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); 3396 u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay; 3397 3398 cstate->dc3co_exitline = 0; 3399 3400 if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) 3401 return; 3402 3403 /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ 3404 if (to_intel_crtc(cstate->base.crtc)->pipe != PIPE_A || 3405 encoder->port != PORT_A) 3406 return; 3407 3408 if (!cstate->has_psr2 || !cstate->base.active) 3409 return; 3410 3411 /* 3412 * DC3CO Exit time 200us B.Spec 49196 3413 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 3414 */ 3415 exit_scanlines = 3416 intel_usecs_to_scanlines(&cstate->base.adjusted_mode, 200) + 1; 3417 3418 if (WARN_ON(exit_scanlines > crtc_vdisplay)) 3419 return; 3420 3421 cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines; 3422 DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline); 3423 } 3424 3425 static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state) 3426 { 3427 u32 val; 3428 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); 3429 3430 if (INTEL_GEN(dev_priv) < 12) 3431 return; 3432 3433 val = I915_READ(EXITLINE(crtc_state->cpu_transcoder)); 3434 3435 if (val & EXITLINE_ENABLE) 3436 crtc_state->dc3co_exitline = val & EXITLINE_MASK; 3437 } 3438 3439 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, 3440 const struct intel_crtc_state *crtc_state, 3441 const struct drm_connector_state *conn_state) 3442 { 3443 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3444 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3445 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3446 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3447 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3448 int level = intel_ddi_dp_level(intel_dp); 3449 enum transcoder transcoder = crtc_state->cpu_transcoder; 3450 3451 tgl_set_psr2_transcoder_exitline(crtc_state); 3452 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3453 crtc_state->lane_count, is_mst); 3454 3455 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 3456 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 3457 3458 /* 1.a got on intel_atomic_commit_tail() */ 3459 3460 /* 2. */ 3461 intel_edp_panel_on(intel_dp); 3462 3463 /* 3464 * 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by: 3465 * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and 3466 * haswell_crtc_enable()->intel_enable_shared_dpll() 3467 */ 3468 3469 /* 4.b */ 3470 intel_ddi_clk_select(encoder, crtc_state); 3471 3472 /* 5. */ 3473 if (!intel_phy_is_tc(dev_priv, phy) || 3474 dig_port->tc_mode != TC_PORT_TBT_ALT) 3475 intel_display_power_get(dev_priv, 3476 dig_port->ddi_io_power_domain); 3477 3478 /* 6. */ 3479 icl_program_mg_dp_mode(dig_port, crtc_state); 3480 3481 /* 3482 * 7.a - Steps in this function should only be executed over MST 3483 * master, what will be taken in care by MST hook 3484 * intel_mst_pre_enable_dp() 3485 */ 3486 intel_ddi_enable_pipe_clock(crtc_state); 3487 3488 /* 7.b */ 3489 intel_ddi_config_transcoder_func(crtc_state); 3490 3491 /* 7.d */ 3492 icl_phy_set_clock_gating(dig_port, false); 3493 3494 /* 7.e */ 3495 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, 3496 encoder->type); 3497 3498 /* 7.f */ 3499 if (intel_phy_is_combo(dev_priv, phy)) { 3500 bool lane_reversal = 3501 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3502 3503 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3504 crtc_state->lane_count, 3505 lane_reversal); 3506 } 3507 3508 /* 7.g */ 3509 intel_ddi_init_dp_buf_reg(encoder); 3510 3511 if (!is_mst) 3512 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3513 3514 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 3515 /* 3516 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 3517 * in the FEC_CONFIGURATION register to 1 before initiating link 3518 * training 3519 */ 3520 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3521 /* 7.c, 7.h, 7.i, 7.j */ 3522 intel_dp_start_link_train(intel_dp); 3523 3524 /* 7.k */ 3525 if (!is_trans_port_sync_mode(crtc_state)) 3526 intel_dp_stop_link_train(intel_dp); 3527 3528 /* 3529 * TODO: enable clock gating 3530 * 3531 * It is not written in DP enabling sequence but "PHY Clockgating 3532 * programming" states that clock gating should be enabled after the 3533 * link training but doing so causes all the following trainings to fail 3534 * so not enabling it for now. 3535 */ 3536 3537 /* 7.l */ 3538 intel_ddi_enable_fec(encoder, crtc_state); 3539 intel_dsc_enable(encoder, crtc_state); 3540 } 3541 3542 static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, 3543 const struct intel_crtc_state *crtc_state, 3544 const struct drm_connector_state *conn_state) 3545 { 3546 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3547 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3548 enum port port = encoder->port; 3549 enum phy phy = intel_port_to_phy(dev_priv, port); 3550 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3551 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3552 int level = intel_ddi_dp_level(intel_dp); 3553 3554 WARN_ON(is_mst && (port == PORT_A || port == PORT_E)); 3555 3556 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3557 crtc_state->lane_count, is_mst); 3558 3559 intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port); 3560 intel_dp->regs.dp_tp_status = DP_TP_STATUS(port); 3561 3562 intel_edp_panel_on(intel_dp); 3563 3564 intel_ddi_clk_select(encoder, crtc_state); 3565 3566 if (!intel_phy_is_tc(dev_priv, phy) || 3567 dig_port->tc_mode != TC_PORT_TBT_ALT) 3568 intel_display_power_get(dev_priv, 3569 dig_port->ddi_io_power_domain); 3570 3571 icl_program_mg_dp_mode(dig_port, crtc_state); 3572 icl_phy_set_clock_gating(dig_port, false); 3573 3574 if (INTEL_GEN(dev_priv) >= 11) 3575 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3576 level, encoder->type); 3577 else if (IS_CANNONLAKE(dev_priv)) 3578 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 3579 else if (IS_GEN9_LP(dev_priv)) 3580 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 3581 else 3582 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3583 3584 if (intel_phy_is_combo(dev_priv, phy)) { 3585 bool lane_reversal = 3586 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3587 3588 intel_combo_phy_power_up_lanes(dev_priv, phy, false, 3589 crtc_state->lane_count, 3590 lane_reversal); 3591 } 3592 3593 intel_ddi_init_dp_buf_reg(encoder); 3594 if (!is_mst) 3595 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3596 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3597 true); 3598 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3599 intel_dp_start_link_train(intel_dp); 3600 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && 3601 !is_trans_port_sync_mode(crtc_state)) 3602 intel_dp_stop_link_train(intel_dp); 3603 3604 intel_ddi_enable_fec(encoder, crtc_state); 3605 3606 icl_phy_set_clock_gating(dig_port, true); 3607 3608 if (!is_mst) 3609 intel_ddi_enable_pipe_clock(crtc_state); 3610 3611 intel_dsc_enable(encoder, crtc_state); 3612 } 3613 3614 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, 3615 const struct intel_crtc_state *crtc_state, 3616 const struct drm_connector_state *conn_state) 3617 { 3618 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3619 3620 if (INTEL_GEN(dev_priv) >= 12) 3621 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3622 else 3623 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3624 3625 /* MST will call a setting of MSA after an allocating of Virtual Channel 3626 * from MST encoder pre_enable callback. 3627 */ 3628 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 3629 intel_ddi_set_dp_msa(crtc_state, conn_state); 3630 } 3631 3632 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, 3633 const struct intel_crtc_state *crtc_state, 3634 const struct drm_connector_state *conn_state) 3635 { 3636 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 3637 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 3638 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3639 enum port port = encoder->port; 3640 int level = intel_ddi_hdmi_level(dev_priv, port); 3641 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3642 3643 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3644 intel_ddi_clk_select(encoder, crtc_state); 3645 3646 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 3647 3648 icl_program_mg_dp_mode(dig_port, crtc_state); 3649 icl_phy_set_clock_gating(dig_port, false); 3650 3651 if (INTEL_GEN(dev_priv) >= 12) 3652 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3653 level, INTEL_OUTPUT_HDMI); 3654 else if (INTEL_GEN(dev_priv) == 11) 3655 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3656 level, INTEL_OUTPUT_HDMI); 3657 else if (IS_CANNONLAKE(dev_priv)) 3658 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3659 else if (IS_GEN9_LP(dev_priv)) 3660 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3661 else 3662 intel_prepare_hdmi_ddi_buffers(encoder, level); 3663 3664 icl_phy_set_clock_gating(dig_port, true); 3665 3666 if (IS_GEN9_BC(dev_priv)) 3667 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); 3668 3669 intel_ddi_enable_pipe_clock(crtc_state); 3670 3671 intel_dig_port->set_infoframes(encoder, 3672 crtc_state->has_infoframe, 3673 crtc_state, conn_state); 3674 } 3675 3676 static void intel_ddi_pre_enable(struct intel_encoder *encoder, 3677 const struct intel_crtc_state *crtc_state, 3678 const struct drm_connector_state *conn_state) 3679 { 3680 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 3681 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3682 enum pipe pipe = crtc->pipe; 3683 3684 /* 3685 * When called from DP MST code: 3686 * - conn_state will be NULL 3687 * - encoder will be the main encoder (ie. mst->primary) 3688 * - the main connector associated with this port 3689 * won't be active or linked to a crtc 3690 * - crtc_state will be the state of the first stream to 3691 * be activated on this port, and it may not be the same 3692 * stream that will be deactivated last, but each stream 3693 * should have a state that is identical when it comes to 3694 * the DP link parameteres 3695 */ 3696 3697 WARN_ON(crtc_state->has_pch_encoder); 3698 3699 if (INTEL_GEN(dev_priv) >= 11) 3700 icl_map_plls_to_ports(encoder, crtc_state); 3701 3702 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3703 3704 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3705 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state); 3706 } else { 3707 struct intel_lspcon *lspcon = 3708 enc_to_intel_lspcon(&encoder->base); 3709 3710 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state); 3711 if (lspcon->active) { 3712 struct intel_digital_port *dig_port = 3713 enc_to_dig_port(&encoder->base); 3714 3715 dig_port->set_infoframes(encoder, 3716 crtc_state->has_infoframe, 3717 crtc_state, conn_state); 3718 } 3719 } 3720 } 3721 3722 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3723 const struct intel_crtc_state *crtc_state) 3724 { 3725 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3726 enum port port = encoder->port; 3727 bool wait = false; 3728 u32 val; 3729 3730 val = I915_READ(DDI_BUF_CTL(port)); 3731 if (val & DDI_BUF_CTL_ENABLE) { 3732 val &= ~DDI_BUF_CTL_ENABLE; 3733 I915_WRITE(DDI_BUF_CTL(port), val); 3734 wait = true; 3735 } 3736 3737 if (intel_crtc_has_dp_encoder(crtc_state)) { 3738 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3739 3740 val = I915_READ(intel_dp->regs.dp_tp_ctl); 3741 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3742 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3743 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 3744 } 3745 3746 /* Disable FEC in DP Sink */ 3747 intel_ddi_disable_fec_state(encoder, crtc_state); 3748 3749 if (wait) 3750 intel_wait_ddi_buf_idle(dev_priv, port); 3751 } 3752 3753 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, 3754 const struct intel_crtc_state *old_crtc_state, 3755 const struct drm_connector_state *old_conn_state) 3756 { 3757 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3758 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3759 struct intel_dp *intel_dp = &dig_port->dp; 3760 bool is_mst = intel_crtc_has_type(old_crtc_state, 3761 INTEL_OUTPUT_DP_MST); 3762 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3763 3764 if (!is_mst) { 3765 intel_ddi_disable_pipe_clock(old_crtc_state); 3766 /* 3767 * Power down sink before disabling the port, otherwise we end 3768 * up getting interrupts from the sink on detecting link loss. 3769 */ 3770 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 3771 } 3772 3773 intel_disable_ddi_buf(encoder, old_crtc_state); 3774 3775 intel_edp_panel_vdd_on(intel_dp); 3776 intel_edp_panel_off(intel_dp); 3777 3778 if (!intel_phy_is_tc(dev_priv, phy) || 3779 dig_port->tc_mode != TC_PORT_TBT_ALT) 3780 intel_display_power_put_unchecked(dev_priv, 3781 dig_port->ddi_io_power_domain); 3782 3783 intel_ddi_clk_disable(encoder); 3784 tgl_clear_psr2_transcoder_exitline(old_crtc_state); 3785 } 3786 3787 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder, 3788 const struct intel_crtc_state *old_crtc_state, 3789 const struct drm_connector_state *old_conn_state) 3790 { 3791 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3792 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3793 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3794 3795 dig_port->set_infoframes(encoder, false, 3796 old_crtc_state, old_conn_state); 3797 3798 intel_ddi_disable_pipe_clock(old_crtc_state); 3799 3800 intel_disable_ddi_buf(encoder, old_crtc_state); 3801 3802 intel_display_power_put_unchecked(dev_priv, 3803 dig_port->ddi_io_power_domain); 3804 3805 intel_ddi_clk_disable(encoder); 3806 3807 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3808 } 3809 3810 static void intel_ddi_post_disable(struct intel_encoder *encoder, 3811 const struct intel_crtc_state *old_crtc_state, 3812 const struct drm_connector_state *old_conn_state) 3813 { 3814 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3815 3816 /* 3817 * When called from DP MST code: 3818 * - old_conn_state will be NULL 3819 * - encoder will be the main encoder (ie. mst->primary) 3820 * - the main connector associated with this port 3821 * won't be active or linked to a crtc 3822 * - old_crtc_state will be the state of the last stream to 3823 * be deactivated on this port, and it may not be the same 3824 * stream that was activated last, but each stream 3825 * should have a state that is identical when it comes to 3826 * the DP link parameteres 3827 */ 3828 3829 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3830 intel_ddi_post_disable_hdmi(encoder, 3831 old_crtc_state, old_conn_state); 3832 else 3833 intel_ddi_post_disable_dp(encoder, 3834 old_crtc_state, old_conn_state); 3835 3836 if (INTEL_GEN(dev_priv) >= 11) 3837 icl_unmap_plls_to_ports(encoder); 3838 } 3839 3840 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, 3841 const struct intel_crtc_state *old_crtc_state, 3842 const struct drm_connector_state *old_conn_state) 3843 { 3844 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3845 u32 val; 3846 3847 /* 3848 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3849 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3850 * step 13 is the correct place for it. Step 18 is where it was 3851 * originally before the BUN. 3852 */ 3853 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3854 val &= ~FDI_RX_ENABLE; 3855 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3856 3857 intel_disable_ddi_buf(encoder, old_crtc_state); 3858 intel_ddi_clk_disable(encoder); 3859 3860 val = I915_READ(FDI_RX_MISC(PIPE_A)); 3861 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3862 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3863 I915_WRITE(FDI_RX_MISC(PIPE_A), val); 3864 3865 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3866 val &= ~FDI_PCDCLK; 3867 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3868 3869 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3870 val &= ~FDI_RX_PLL_ENABLE; 3871 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3872 } 3873 3874 static void intel_enable_ddi_dp(struct intel_encoder *encoder, 3875 const struct intel_crtc_state *crtc_state, 3876 const struct drm_connector_state *conn_state) 3877 { 3878 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3879 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3880 enum port port = encoder->port; 3881 3882 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 3883 intel_dp_stop_link_train(intel_dp); 3884 3885 intel_edp_backlight_on(crtc_state, conn_state); 3886 intel_psr_enable(intel_dp, crtc_state); 3887 intel_dp_vsc_enable(intel_dp, crtc_state, conn_state); 3888 intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state); 3889 intel_edp_drrs_enable(intel_dp, crtc_state); 3890 3891 if (crtc_state->has_audio) 3892 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3893 } 3894 3895 static i915_reg_t 3896 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3897 enum port port) 3898 { 3899 static const enum transcoder trans[] = { 3900 [PORT_A] = TRANSCODER_EDP, 3901 [PORT_B] = TRANSCODER_A, 3902 [PORT_C] = TRANSCODER_B, 3903 [PORT_D] = TRANSCODER_C, 3904 [PORT_E] = TRANSCODER_A, 3905 }; 3906 3907 WARN_ON(INTEL_GEN(dev_priv) < 9); 3908 3909 if (WARN_ON(port < PORT_A || port > PORT_E)) 3910 port = PORT_A; 3911 3912 return CHICKEN_TRANS(trans[port]); 3913 } 3914 3915 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, 3916 const struct intel_crtc_state *crtc_state, 3917 const struct drm_connector_state *conn_state) 3918 { 3919 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3920 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 3921 struct drm_connector *connector = conn_state->connector; 3922 enum port port = encoder->port; 3923 3924 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3925 crtc_state->hdmi_high_tmds_clock_ratio, 3926 crtc_state->hdmi_scrambling)) 3927 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3928 connector->base.id, connector->name); 3929 3930 /* Display WA #1143: skl,kbl,cfl */ 3931 if (IS_GEN9_BC(dev_priv)) { 3932 /* 3933 * For some reason these chicken bits have been 3934 * stuffed into a transcoder register, event though 3935 * the bits affect a specific DDI port rather than 3936 * a specific transcoder. 3937 */ 3938 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3939 u32 val; 3940 3941 val = I915_READ(reg); 3942 3943 if (port == PORT_E) 3944 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3945 DDIE_TRAINING_OVERRIDE_VALUE; 3946 else 3947 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3948 DDI_TRAINING_OVERRIDE_VALUE; 3949 3950 I915_WRITE(reg, val); 3951 POSTING_READ(reg); 3952 3953 udelay(1); 3954 3955 if (port == PORT_E) 3956 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3957 DDIE_TRAINING_OVERRIDE_VALUE); 3958 else 3959 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3960 DDI_TRAINING_OVERRIDE_VALUE); 3961 3962 I915_WRITE(reg, val); 3963 } 3964 3965 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3966 * are ignored so nothing special needs to be done besides 3967 * enabling the port. 3968 */ 3969 I915_WRITE(DDI_BUF_CTL(port), 3970 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3971 3972 if (crtc_state->has_audio) 3973 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3974 } 3975 3976 static void intel_enable_ddi(struct intel_encoder *encoder, 3977 const struct intel_crtc_state *crtc_state, 3978 const struct drm_connector_state *conn_state) 3979 { 3980 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3981 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state); 3982 else 3983 intel_enable_ddi_dp(encoder, crtc_state, conn_state); 3984 3985 /* Enable hdcp if it's desired */ 3986 if (conn_state->content_protection == 3987 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3988 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3989 crtc_state->cpu_transcoder, 3990 (u8)conn_state->hdcp_content_type); 3991 } 3992 3993 static void intel_disable_ddi_dp(struct intel_encoder *encoder, 3994 const struct intel_crtc_state *old_crtc_state, 3995 const struct drm_connector_state *old_conn_state) 3996 { 3997 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3998 3999 intel_dp->link_trained = false; 4000 4001 if (old_crtc_state->has_audio) 4002 intel_audio_codec_disable(encoder, 4003 old_crtc_state, old_conn_state); 4004 4005 intel_edp_drrs_disable(intel_dp, old_crtc_state); 4006 intel_psr_disable(intel_dp, old_crtc_state); 4007 intel_edp_backlight_off(old_conn_state); 4008 /* Disable the decompression in DP Sink */ 4009 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 4010 false); 4011 } 4012 4013 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder, 4014 const struct intel_crtc_state *old_crtc_state, 4015 const struct drm_connector_state *old_conn_state) 4016 { 4017 struct drm_connector *connector = old_conn_state->connector; 4018 4019 if (old_crtc_state->has_audio) 4020 intel_audio_codec_disable(encoder, 4021 old_crtc_state, old_conn_state); 4022 4023 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 4024 false, false)) 4025 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 4026 connector->base.id, connector->name); 4027 } 4028 4029 static void intel_disable_ddi(struct intel_encoder *encoder, 4030 const struct intel_crtc_state *old_crtc_state, 4031 const struct drm_connector_state *old_conn_state) 4032 { 4033 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 4034 4035 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 4036 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state); 4037 else 4038 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state); 4039 } 4040 4041 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, 4042 const struct intel_crtc_state *crtc_state, 4043 const struct drm_connector_state *conn_state) 4044 { 4045 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 4046 4047 intel_ddi_set_dp_msa(crtc_state, conn_state); 4048 4049 intel_psr_update(intel_dp, crtc_state); 4050 intel_edp_drrs_enable(intel_dp, crtc_state); 4051 4052 intel_panel_update_backlight(encoder, crtc_state, conn_state); 4053 } 4054 4055 static void intel_ddi_update_pipe(struct intel_encoder *encoder, 4056 const struct intel_crtc_state *crtc_state, 4057 const struct drm_connector_state *conn_state) 4058 { 4059 struct intel_connector *connector = 4060 to_intel_connector(conn_state->connector); 4061 struct intel_hdcp *hdcp = &connector->hdcp; 4062 bool content_protection_type_changed = 4063 (conn_state->hdcp_content_type != hdcp->content_type && 4064 conn_state->content_protection != 4065 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 4066 4067 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 4068 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state); 4069 4070 /* 4071 * During the HDCP encryption session if Type change is requested, 4072 * disable the HDCP and reenable it with new TYPE value. 4073 */ 4074 if (conn_state->content_protection == 4075 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 4076 content_protection_type_changed) 4077 intel_hdcp_disable(connector); 4078 4079 /* 4080 * Mark the hdcp state as DESIRED after the hdcp disable of type 4081 * change procedure. 4082 */ 4083 if (content_protection_type_changed) { 4084 mutex_lock(&hdcp->mutex); 4085 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 4086 schedule_work(&hdcp->prop_work); 4087 mutex_unlock(&hdcp->mutex); 4088 } 4089 4090 if (conn_state->content_protection == 4091 DRM_MODE_CONTENT_PROTECTION_DESIRED || 4092 content_protection_type_changed) 4093 intel_hdcp_enable(connector, 4094 crtc_state->cpu_transcoder, 4095 (u8)conn_state->hdcp_content_type); 4096 } 4097 4098 static void 4099 intel_ddi_update_prepare(struct intel_atomic_state *state, 4100 struct intel_encoder *encoder, 4101 struct intel_crtc *crtc) 4102 { 4103 struct intel_crtc_state *crtc_state = 4104 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 4105 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 4106 4107 WARN_ON(crtc && crtc->active); 4108 4109 intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes); 4110 if (crtc_state && crtc_state->base.active) 4111 intel_update_active_dpll(state, crtc, encoder); 4112 } 4113 4114 static void 4115 intel_ddi_update_complete(struct intel_atomic_state *state, 4116 struct intel_encoder *encoder, 4117 struct intel_crtc *crtc) 4118 { 4119 intel_tc_port_put_link(enc_to_dig_port(&encoder->base)); 4120 } 4121 4122 static void 4123 intel_ddi_pre_pll_enable(struct intel_encoder *encoder, 4124 const struct intel_crtc_state *crtc_state, 4125 const struct drm_connector_state *conn_state) 4126 { 4127 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4128 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 4129 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 4130 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 4131 4132 if (is_tc_port) 4133 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 4134 4135 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 4136 intel_display_power_get(dev_priv, 4137 intel_ddi_main_link_aux_domain(dig_port)); 4138 4139 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 4140 /* 4141 * Program the lane count for static/dynamic connections on 4142 * Type-C ports. Skip this step for TBT. 4143 */ 4144 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 4145 else if (IS_GEN9_LP(dev_priv)) 4146 bxt_ddi_phy_set_lane_optim_mask(encoder, 4147 crtc_state->lane_lat_optim_mask); 4148 } 4149 4150 static void 4151 intel_ddi_post_pll_disable(struct intel_encoder *encoder, 4152 const struct intel_crtc_state *crtc_state, 4153 const struct drm_connector_state *conn_state) 4154 { 4155 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4156 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 4157 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 4158 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 4159 4160 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 4161 intel_display_power_put_unchecked(dev_priv, 4162 intel_ddi_main_link_aux_domain(dig_port)); 4163 4164 if (is_tc_port) 4165 intel_tc_port_put_link(dig_port); 4166 } 4167 4168 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 4169 { 4170 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4171 struct drm_i915_private *dev_priv = 4172 to_i915(intel_dig_port->base.base.dev); 4173 enum port port = intel_dig_port->base.port; 4174 u32 val; 4175 bool wait = false; 4176 4177 if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) { 4178 val = I915_READ(DDI_BUF_CTL(port)); 4179 if (val & DDI_BUF_CTL_ENABLE) { 4180 val &= ~DDI_BUF_CTL_ENABLE; 4181 I915_WRITE(DDI_BUF_CTL(port), val); 4182 wait = true; 4183 } 4184 4185 val = I915_READ(intel_dp->regs.dp_tp_ctl); 4186 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 4187 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 4188 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 4189 POSTING_READ(intel_dp->regs.dp_tp_ctl); 4190 4191 if (wait) 4192 intel_wait_ddi_buf_idle(dev_priv, port); 4193 } 4194 4195 val = DP_TP_CTL_ENABLE | 4196 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 4197 if (intel_dp->link_mst) 4198 val |= DP_TP_CTL_MODE_MST; 4199 else { 4200 val |= DP_TP_CTL_MODE_SST; 4201 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 4202 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4203 } 4204 I915_WRITE(intel_dp->regs.dp_tp_ctl, val); 4205 POSTING_READ(intel_dp->regs.dp_tp_ctl); 4206 4207 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 4208 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 4209 POSTING_READ(DDI_BUF_CTL(port)); 4210 4211 udelay(600); 4212 } 4213 4214 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 4215 enum transcoder cpu_transcoder) 4216 { 4217 if (cpu_transcoder == TRANSCODER_EDP) 4218 return false; 4219 4220 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 4221 return false; 4222 4223 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) & 4224 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 4225 } 4226 4227 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 4228 struct intel_crtc_state *crtc_state) 4229 { 4230 if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 4231 crtc_state->min_voltage_level = 1; 4232 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 4233 crtc_state->min_voltage_level = 2; 4234 } 4235 4236 void intel_ddi_get_config(struct intel_encoder *encoder, 4237 struct intel_crtc_state *pipe_config) 4238 { 4239 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4240 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 4241 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4242 u32 temp, flags = 0; 4243 4244 /* XXX: DSI transcoder paranoia */ 4245 if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) 4246 return; 4247 4248 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4249 if (temp & TRANS_DDI_PHSYNC) 4250 flags |= DRM_MODE_FLAG_PHSYNC; 4251 else 4252 flags |= DRM_MODE_FLAG_NHSYNC; 4253 if (temp & TRANS_DDI_PVSYNC) 4254 flags |= DRM_MODE_FLAG_PVSYNC; 4255 else 4256 flags |= DRM_MODE_FLAG_NVSYNC; 4257 4258 pipe_config->base.adjusted_mode.flags |= flags; 4259 4260 switch (temp & TRANS_DDI_BPC_MASK) { 4261 case TRANS_DDI_BPC_6: 4262 pipe_config->pipe_bpp = 18; 4263 break; 4264 case TRANS_DDI_BPC_8: 4265 pipe_config->pipe_bpp = 24; 4266 break; 4267 case TRANS_DDI_BPC_10: 4268 pipe_config->pipe_bpp = 30; 4269 break; 4270 case TRANS_DDI_BPC_12: 4271 pipe_config->pipe_bpp = 36; 4272 break; 4273 default: 4274 break; 4275 } 4276 4277 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 4278 case TRANS_DDI_MODE_SELECT_HDMI: 4279 pipe_config->has_hdmi_sink = true; 4280 4281 pipe_config->infoframes.enable |= 4282 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4283 4284 if (pipe_config->infoframes.enable) 4285 pipe_config->has_infoframe = true; 4286 4287 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 4288 pipe_config->hdmi_scrambling = true; 4289 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4290 pipe_config->hdmi_high_tmds_clock_ratio = true; 4291 /* fall through */ 4292 case TRANS_DDI_MODE_SELECT_DVI: 4293 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 4294 pipe_config->lane_count = 4; 4295 break; 4296 case TRANS_DDI_MODE_SELECT_FDI: 4297 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4298 break; 4299 case TRANS_DDI_MODE_SELECT_DP_SST: 4300 if (encoder->type == INTEL_OUTPUT_EDP) 4301 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 4302 else 4303 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 4304 pipe_config->lane_count = 4305 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4306 intel_dp_get_m_n(intel_crtc, pipe_config); 4307 4308 if (INTEL_GEN(dev_priv) >= 11) { 4309 i915_reg_t dp_tp_ctl; 4310 4311 if (IS_GEN(dev_priv, 11)) 4312 dp_tp_ctl = DP_TP_CTL(encoder->port); 4313 else 4314 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); 4315 4316 pipe_config->fec_enable = 4317 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 4318 4319 DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n", 4320 encoder->base.base.id, encoder->base.name, 4321 pipe_config->fec_enable); 4322 } 4323 4324 break; 4325 case TRANS_DDI_MODE_SELECT_DP_MST: 4326 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4327 pipe_config->lane_count = 4328 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4329 intel_dp_get_m_n(intel_crtc, pipe_config); 4330 break; 4331 default: 4332 break; 4333 } 4334 4335 if (encoder->type == INTEL_OUTPUT_EDP) 4336 tgl_dc3co_exitline_get_config(pipe_config); 4337 4338 pipe_config->has_audio = 4339 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4340 4341 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 4342 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 4343 /* 4344 * This is a big fat ugly hack. 4345 * 4346 * Some machines in UEFI boot mode provide us a VBT that has 18 4347 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4348 * unknown we fail to light up. Yet the same BIOS boots up with 4349 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4350 * max, not what it tells us to use. 4351 * 4352 * Note: This will still be broken if the eDP panel is not lit 4353 * up by the BIOS, and thus we can't get the mode at module 4354 * load. 4355 */ 4356 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4357 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 4358 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 4359 } 4360 4361 intel_ddi_clock_get(encoder, pipe_config); 4362 4363 if (IS_GEN9_LP(dev_priv)) 4364 pipe_config->lane_lat_optim_mask = 4365 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 4366 4367 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4368 4369 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4370 4371 intel_read_infoframe(encoder, pipe_config, 4372 HDMI_INFOFRAME_TYPE_AVI, 4373 &pipe_config->infoframes.avi); 4374 intel_read_infoframe(encoder, pipe_config, 4375 HDMI_INFOFRAME_TYPE_SPD, 4376 &pipe_config->infoframes.spd); 4377 intel_read_infoframe(encoder, pipe_config, 4378 HDMI_INFOFRAME_TYPE_VENDOR, 4379 &pipe_config->infoframes.hdmi); 4380 intel_read_infoframe(encoder, pipe_config, 4381 HDMI_INFOFRAME_TYPE_DRM, 4382 &pipe_config->infoframes.drm); 4383 } 4384 4385 static enum intel_output_type 4386 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4387 struct intel_crtc_state *crtc_state, 4388 struct drm_connector_state *conn_state) 4389 { 4390 switch (conn_state->connector->connector_type) { 4391 case DRM_MODE_CONNECTOR_HDMIA: 4392 return INTEL_OUTPUT_HDMI; 4393 case DRM_MODE_CONNECTOR_eDP: 4394 return INTEL_OUTPUT_EDP; 4395 case DRM_MODE_CONNECTOR_DisplayPort: 4396 return INTEL_OUTPUT_DP; 4397 default: 4398 MISSING_CASE(conn_state->connector->connector_type); 4399 return INTEL_OUTPUT_UNUSED; 4400 } 4401 } 4402 4403 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4404 struct intel_crtc_state *pipe_config, 4405 struct drm_connector_state *conn_state) 4406 { 4407 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 4408 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4409 enum port port = encoder->port; 4410 int ret; 4411 4412 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) 4413 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4414 4415 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4416 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4417 } else { 4418 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4419 tgl_dc3co_exitline_compute_config(encoder, pipe_config); 4420 } 4421 4422 if (ret) 4423 return ret; 4424 4425 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4426 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4427 pipe_config->pch_pfit.force_thru = 4428 pipe_config->pch_pfit.enabled || 4429 pipe_config->crc_enabled; 4430 4431 if (IS_GEN9_LP(dev_priv)) 4432 pipe_config->lane_lat_optim_mask = 4433 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4434 4435 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4436 4437 return 0; 4438 } 4439 4440 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4441 { 4442 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4443 4444 intel_dp_encoder_flush_work(encoder); 4445 4446 drm_encoder_cleanup(encoder); 4447 kfree(dig_port); 4448 } 4449 4450 static const struct drm_encoder_funcs intel_ddi_funcs = { 4451 .reset = intel_dp_encoder_reset, 4452 .destroy = intel_ddi_encoder_destroy, 4453 }; 4454 4455 static struct intel_connector * 4456 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 4457 { 4458 struct intel_connector *connector; 4459 enum port port = intel_dig_port->base.port; 4460 4461 connector = intel_connector_alloc(); 4462 if (!connector) 4463 return NULL; 4464 4465 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 4466 intel_dig_port->dp.prepare_link_retrain = 4467 intel_ddi_prepare_link_retrain; 4468 4469 if (!intel_dp_init_connector(intel_dig_port, connector)) { 4470 kfree(connector); 4471 return NULL; 4472 } 4473 4474 return connector; 4475 } 4476 4477 static int modeset_pipe(struct drm_crtc *crtc, 4478 struct drm_modeset_acquire_ctx *ctx) 4479 { 4480 struct drm_atomic_state *state; 4481 struct drm_crtc_state *crtc_state; 4482 int ret; 4483 4484 state = drm_atomic_state_alloc(crtc->dev); 4485 if (!state) 4486 return -ENOMEM; 4487 4488 state->acquire_ctx = ctx; 4489 4490 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4491 if (IS_ERR(crtc_state)) { 4492 ret = PTR_ERR(crtc_state); 4493 goto out; 4494 } 4495 4496 crtc_state->connectors_changed = true; 4497 4498 ret = drm_atomic_commit(state); 4499 out: 4500 drm_atomic_state_put(state); 4501 4502 return ret; 4503 } 4504 4505 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4506 struct drm_modeset_acquire_ctx *ctx) 4507 { 4508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4509 struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base); 4510 struct intel_connector *connector = hdmi->attached_connector; 4511 struct i2c_adapter *adapter = 4512 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4513 struct drm_connector_state *conn_state; 4514 struct intel_crtc_state *crtc_state; 4515 struct intel_crtc *crtc; 4516 u8 config; 4517 int ret; 4518 4519 if (!connector || connector->base.status != connector_status_connected) 4520 return 0; 4521 4522 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4523 ctx); 4524 if (ret) 4525 return ret; 4526 4527 conn_state = connector->base.state; 4528 4529 crtc = to_intel_crtc(conn_state->crtc); 4530 if (!crtc) 4531 return 0; 4532 4533 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4534 if (ret) 4535 return ret; 4536 4537 crtc_state = to_intel_crtc_state(crtc->base.state); 4538 4539 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4540 4541 if (!crtc_state->base.active) 4542 return 0; 4543 4544 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4545 !crtc_state->hdmi_scrambling) 4546 return 0; 4547 4548 if (conn_state->commit && 4549 !try_wait_for_completion(&conn_state->commit->hw_done)) 4550 return 0; 4551 4552 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4553 if (ret < 0) { 4554 DRM_ERROR("Failed to read TMDS config: %d\n", ret); 4555 return 0; 4556 } 4557 4558 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4559 crtc_state->hdmi_high_tmds_clock_ratio && 4560 !!(config & SCDC_SCRAMBLING_ENABLE) == 4561 crtc_state->hdmi_scrambling) 4562 return 0; 4563 4564 /* 4565 * HDMI 2.0 says that one should not send scrambled data 4566 * prior to configuring the sink scrambling, and that 4567 * TMDS clock/data transmission should be suspended when 4568 * changing the TMDS clock rate in the sink. So let's 4569 * just do a full modeset here, even though some sinks 4570 * would be perfectly happy if were to just reconfigure 4571 * the SCDC settings on the fly. 4572 */ 4573 return modeset_pipe(&crtc->base, ctx); 4574 } 4575 4576 static enum intel_hotplug_state 4577 intel_ddi_hotplug(struct intel_encoder *encoder, 4578 struct intel_connector *connector, 4579 bool irq_received) 4580 { 4581 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 4582 struct drm_modeset_acquire_ctx ctx; 4583 enum intel_hotplug_state state; 4584 int ret; 4585 4586 state = intel_encoder_hotplug(encoder, connector, irq_received); 4587 4588 drm_modeset_acquire_init(&ctx, 0); 4589 4590 for (;;) { 4591 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4592 ret = intel_hdmi_reset_link(encoder, &ctx); 4593 else 4594 ret = intel_dp_retrain_link(encoder, &ctx); 4595 4596 if (ret == -EDEADLK) { 4597 drm_modeset_backoff(&ctx); 4598 continue; 4599 } 4600 4601 break; 4602 } 4603 4604 drm_modeset_drop_locks(&ctx); 4605 drm_modeset_acquire_fini(&ctx); 4606 WARN(ret, "Acquiring modeset locks failed with %i\n", ret); 4607 4608 /* 4609 * Unpowered type-c dongles can take some time to boot and be 4610 * responsible, so here giving some time to those dongles to power up 4611 * and then retrying the probe. 4612 * 4613 * On many platforms the HDMI live state signal is known to be 4614 * unreliable, so we can't use it to detect if a sink is connected or 4615 * not. Instead we detect if it's connected based on whether we can 4616 * read the EDID or not. That in turn has a problem during disconnect, 4617 * since the HPD interrupt may be raised before the DDC lines get 4618 * disconnected (due to how the required length of DDC vs. HPD 4619 * connector pins are specified) and so we'll still be able to get a 4620 * valid EDID. To solve this schedule another detection cycle if this 4621 * time around we didn't detect any change in the sink's connection 4622 * status. 4623 */ 4624 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received && 4625 !dig_port->dp.is_mst) 4626 state = INTEL_HOTPLUG_RETRY; 4627 4628 return state; 4629 } 4630 4631 static struct intel_connector * 4632 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 4633 { 4634 struct intel_connector *connector; 4635 enum port port = intel_dig_port->base.port; 4636 4637 connector = intel_connector_alloc(); 4638 if (!connector) 4639 return NULL; 4640 4641 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4642 intel_hdmi_init_connector(intel_dig_port, connector); 4643 4644 return connector; 4645 } 4646 4647 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) 4648 { 4649 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 4650 4651 if (dport->base.port != PORT_A) 4652 return false; 4653 4654 if (dport->saved_port_bits & DDI_A_4_LANES) 4655 return false; 4656 4657 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4658 * supported configuration 4659 */ 4660 if (IS_GEN9_LP(dev_priv)) 4661 return true; 4662 4663 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4664 * one who does also have a full A/E split called 4665 * DDI_F what makes DDI_E useless. However for this 4666 * case let's trust VBT info. 4667 */ 4668 if (IS_CANNONLAKE(dev_priv) && 4669 !intel_bios_is_port_present(dev_priv, PORT_E)) 4670 return true; 4671 4672 return false; 4673 } 4674 4675 static int 4676 intel_ddi_max_lanes(struct intel_digital_port *intel_dport) 4677 { 4678 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); 4679 enum port port = intel_dport->base.port; 4680 int max_lanes = 4; 4681 4682 if (INTEL_GEN(dev_priv) >= 11) 4683 return max_lanes; 4684 4685 if (port == PORT_A || port == PORT_E) { 4686 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4687 max_lanes = port == PORT_A ? 4 : 0; 4688 else 4689 /* Both A and E share 2 lanes */ 4690 max_lanes = 2; 4691 } 4692 4693 /* 4694 * Some BIOS might fail to set this bit on port A if eDP 4695 * wasn't lit up at boot. Force this bit set when needed 4696 * so we use the proper lane count for our calculations. 4697 */ 4698 if (intel_ddi_a_force_4_lanes(intel_dport)) { 4699 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n"); 4700 intel_dport->saved_port_bits |= DDI_A_4_LANES; 4701 max_lanes = 4; 4702 } 4703 4704 return max_lanes; 4705 } 4706 4707 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4708 { 4709 struct ddi_vbt_port_info *port_info = 4710 &dev_priv->vbt.ddi_port_info[port]; 4711 struct intel_digital_port *intel_dig_port; 4712 struct intel_encoder *intel_encoder; 4713 struct drm_encoder *encoder; 4714 bool init_hdmi, init_dp, init_lspcon = false; 4715 enum phy phy = intel_port_to_phy(dev_priv, port); 4716 4717 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi; 4718 init_dp = port_info->supports_dp; 4719 4720 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4721 /* 4722 * Lspcon device needs to be driven with DP connector 4723 * with special detection sequence. So make sure DP 4724 * is initialized before lspcon. 4725 */ 4726 init_dp = true; 4727 init_lspcon = true; 4728 init_hdmi = false; 4729 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); 4730 } 4731 4732 if (!init_dp && !init_hdmi) { 4733 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4734 port_name(port)); 4735 return; 4736 } 4737 4738 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4739 if (!intel_dig_port) 4740 return; 4741 4742 intel_encoder = &intel_dig_port->base; 4743 encoder = &intel_encoder->base; 4744 4745 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs, 4746 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); 4747 4748 intel_encoder->hotplug = intel_ddi_hotplug; 4749 intel_encoder->compute_output_type = intel_ddi_compute_output_type; 4750 intel_encoder->compute_config = intel_ddi_compute_config; 4751 intel_encoder->enable = intel_enable_ddi; 4752 intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4753 intel_encoder->post_pll_disable = intel_ddi_post_pll_disable; 4754 intel_encoder->pre_enable = intel_ddi_pre_enable; 4755 intel_encoder->disable = intel_disable_ddi; 4756 intel_encoder->post_disable = intel_ddi_post_disable; 4757 intel_encoder->update_pipe = intel_ddi_update_pipe; 4758 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 4759 intel_encoder->get_config = intel_ddi_get_config; 4760 intel_encoder->suspend = intel_dp_encoder_suspend; 4761 intel_encoder->get_power_domains = intel_ddi_get_power_domains; 4762 intel_encoder->type = INTEL_OUTPUT_DDI; 4763 intel_encoder->power_domain = intel_port_to_power_domain(port); 4764 intel_encoder->port = port; 4765 intel_encoder->cloneable = 0; 4766 intel_encoder->pipe_mask = ~0; 4767 4768 if (INTEL_GEN(dev_priv) >= 11) 4769 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 4770 DDI_BUF_PORT_REVERSAL; 4771 else 4772 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 4773 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4774 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 4775 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); 4776 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4777 4778 if (intel_phy_is_tc(dev_priv, phy)) { 4779 bool is_legacy = !port_info->supports_typec_usb && 4780 !port_info->supports_tbt; 4781 4782 intel_tc_port_init(intel_dig_port, is_legacy); 4783 4784 intel_encoder->update_prepare = intel_ddi_update_prepare; 4785 intel_encoder->update_complete = intel_ddi_update_complete; 4786 } 4787 4788 WARN_ON(port > PORT_I); 4789 intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4790 port - PORT_A; 4791 4792 if (init_dp) { 4793 if (!intel_ddi_init_dp_connector(intel_dig_port)) 4794 goto err; 4795 4796 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4797 } 4798 4799 /* In theory we don't need the encoder->type check, but leave it just in 4800 * case we have some really bad VBTs... */ 4801 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4802 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 4803 goto err; 4804 } 4805 4806 if (init_lspcon) { 4807 if (lspcon_init(intel_dig_port)) 4808 /* TODO: handle hdmi info frame part */ 4809 DRM_DEBUG_KMS("LSPCON init success on port %c\n", 4810 port_name(port)); 4811 else 4812 /* 4813 * LSPCON init faied, but DP init was success, so 4814 * lets try to drive as DP++ port. 4815 */ 4816 DRM_ERROR("LSPCON init failed on port %c\n", 4817 port_name(port)); 4818 } 4819 4820 intel_infoframe_init(intel_dig_port); 4821 4822 return; 4823 4824 err: 4825 drm_encoder_cleanup(encoder); 4826 kfree(intel_dig_port); 4827 } 4828