1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_scdc_helper.h> 32 #include <drm/drm_privacy_screen_consumer.h> 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "icl_dsi.h" 37 #include "intel_audio.h" 38 #include "intel_audio_regs.h" 39 #include "intel_backlight.h" 40 #include "intel_combo_phy.h" 41 #include "intel_combo_phy_regs.h" 42 #include "intel_connector.h" 43 #include "intel_crtc.h" 44 #include "intel_cx0_phy.h" 45 #include "intel_cx0_phy_regs.h" 46 #include "intel_ddi.h" 47 #include "intel_ddi_buf_trans.h" 48 #include "intel_de.h" 49 #include "intel_display_power.h" 50 #include "intel_display_types.h" 51 #include "intel_dkl_phy.h" 52 #include "intel_dkl_phy_regs.h" 53 #include "intel_dp.h" 54 #include "intel_dp_aux.h" 55 #include "intel_dp_link_training.h" 56 #include "intel_dp_mst.h" 57 #include "intel_dpio_phy.h" 58 #include "intel_dsi.h" 59 #include "intel_fdi.h" 60 #include "intel_fifo_underrun.h" 61 #include "intel_gmbus.h" 62 #include "intel_hdcp.h" 63 #include "intel_hdmi.h" 64 #include "intel_hotplug.h" 65 #include "intel_hti.h" 66 #include "intel_lspcon.h" 67 #include "intel_mg_phy_regs.h" 68 #include "intel_modeset_lock.h" 69 #include "intel_pps.h" 70 #include "intel_psr.h" 71 #include "intel_quirks.h" 72 #include "intel_snps_phy.h" 73 #include "intel_tc.h" 74 #include "intel_vdsc.h" 75 #include "intel_vdsc_regs.h" 76 #include "skl_scaler.h" 77 #include "skl_universal_plane.h" 78 79 static const u8 index_to_dp_signal_levels[] = { 80 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 81 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 82 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 83 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 84 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 85 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 86 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 87 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 88 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 89 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 90 }; 91 92 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 93 const struct intel_ddi_buf_trans *trans) 94 { 95 int level; 96 97 level = intel_bios_hdmi_level_shift(encoder->devdata); 98 if (level < 0) 99 level = trans->hdmi_default_entry; 100 101 return level; 102 } 103 104 static bool has_buf_trans_select(struct drm_i915_private *i915) 105 { 106 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 107 } 108 109 static bool has_iboost(struct drm_i915_private *i915) 110 { 111 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 112 } 113 114 /* 115 * Starting with Haswell, DDI port buffers must be programmed with correct 116 * values in advance. This function programs the correct values for 117 * DP/eDP/FDI use cases. 118 */ 119 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 120 const struct intel_crtc_state *crtc_state) 121 { 122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 123 u32 iboost_bit = 0; 124 int i, n_entries; 125 enum port port = encoder->port; 126 const struct intel_ddi_buf_trans *trans; 127 128 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 129 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 130 return; 131 132 /* If we're boosting the current, set bit 31 of trans1 */ 133 if (has_iboost(dev_priv) && 134 intel_bios_dp_boost_level(encoder->devdata)) 135 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 136 137 for (i = 0; i < n_entries; i++) { 138 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 139 trans->entries[i].hsw.trans1 | iboost_bit); 140 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 141 trans->entries[i].hsw.trans2); 142 } 143 } 144 145 /* 146 * Starting with Haswell, DDI port buffers must be programmed with correct 147 * values in advance. This function programs the correct values for 148 * HDMI/DVI use cases. 149 */ 150 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 151 const struct intel_crtc_state *crtc_state) 152 { 153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 154 int level = intel_ddi_level(encoder, crtc_state, 0); 155 u32 iboost_bit = 0; 156 int n_entries; 157 enum port port = encoder->port; 158 const struct intel_ddi_buf_trans *trans; 159 160 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 161 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 162 return; 163 164 /* If we're boosting the current, set bit 31 of trans1 */ 165 if (has_iboost(dev_priv) && 166 intel_bios_hdmi_boost_level(encoder->devdata)) 167 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 168 169 /* Entry 9 is for HDMI: */ 170 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 171 trans->entries[level].hsw.trans1 | iboost_bit); 172 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 173 trans->entries[level].hsw.trans2); 174 } 175 176 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 177 { 178 int ret; 179 180 /* FIXME: find out why Bspec's 100us timeout is too short */ 181 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 182 XELPDP_PORT_BUF_PHY_IDLE), 10000); 183 if (ret) 184 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 185 port_name(port)); 186 } 187 188 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 189 enum port port) 190 { 191 if (IS_BROXTON(dev_priv)) { 192 udelay(16); 193 return; 194 } 195 196 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 197 DDI_BUF_IS_IDLE), 8)) 198 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 199 port_name(port)); 200 } 201 202 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 203 enum port port) 204 { 205 enum phy phy = intel_port_to_phy(dev_priv, port); 206 int timeout_us; 207 int ret; 208 209 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 210 if (DISPLAY_VER(dev_priv) < 10) { 211 usleep_range(518, 1000); 212 return; 213 } 214 215 if (DISPLAY_VER(dev_priv) >= 14) { 216 timeout_us = 10000; 217 } else if (IS_DG2(dev_priv)) { 218 timeout_us = 1200; 219 } else if (DISPLAY_VER(dev_priv) >= 12) { 220 if (intel_phy_is_tc(dev_priv, phy)) 221 timeout_us = 3000; 222 else 223 timeout_us = 1000; 224 } else { 225 timeout_us = 500; 226 } 227 228 if (DISPLAY_VER(dev_priv) >= 14) 229 ret = _wait_for(!(intel_de_read(dev_priv, 230 XELPDP_PORT_BUF_CTL1(dev_priv, port)) & 231 XELPDP_PORT_BUF_PHY_IDLE), 232 timeout_us, 10, 10); 233 else 234 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 235 timeout_us, 10, 10); 236 237 if (ret) 238 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 239 port_name(port)); 240 } 241 242 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 243 { 244 switch (pll->info->id) { 245 case DPLL_ID_WRPLL1: 246 return PORT_CLK_SEL_WRPLL1; 247 case DPLL_ID_WRPLL2: 248 return PORT_CLK_SEL_WRPLL2; 249 case DPLL_ID_SPLL: 250 return PORT_CLK_SEL_SPLL; 251 case DPLL_ID_LCPLL_810: 252 return PORT_CLK_SEL_LCPLL_810; 253 case DPLL_ID_LCPLL_1350: 254 return PORT_CLK_SEL_LCPLL_1350; 255 case DPLL_ID_LCPLL_2700: 256 return PORT_CLK_SEL_LCPLL_2700; 257 default: 258 MISSING_CASE(pll->info->id); 259 return PORT_CLK_SEL_NONE; 260 } 261 } 262 263 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 264 const struct intel_crtc_state *crtc_state) 265 { 266 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 267 int clock = crtc_state->port_clock; 268 const enum intel_dpll_id id = pll->info->id; 269 270 switch (id) { 271 default: 272 /* 273 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 274 * here, so do warn if this get passed in 275 */ 276 MISSING_CASE(id); 277 return DDI_CLK_SEL_NONE; 278 case DPLL_ID_ICL_TBTPLL: 279 switch (clock) { 280 case 162000: 281 return DDI_CLK_SEL_TBT_162; 282 case 270000: 283 return DDI_CLK_SEL_TBT_270; 284 case 540000: 285 return DDI_CLK_SEL_TBT_540; 286 case 810000: 287 return DDI_CLK_SEL_TBT_810; 288 default: 289 MISSING_CASE(clock); 290 return DDI_CLK_SEL_NONE; 291 } 292 case DPLL_ID_ICL_MGPLL1: 293 case DPLL_ID_ICL_MGPLL2: 294 case DPLL_ID_ICL_MGPLL3: 295 case DPLL_ID_ICL_MGPLL4: 296 case DPLL_ID_TGL_MGPLL5: 297 case DPLL_ID_TGL_MGPLL6: 298 return DDI_CLK_SEL_MG; 299 } 300 } 301 302 static u32 ddi_buf_phy_link_rate(int port_clock) 303 { 304 switch (port_clock) { 305 case 162000: 306 return DDI_BUF_PHY_LINK_RATE(0); 307 case 216000: 308 return DDI_BUF_PHY_LINK_RATE(4); 309 case 243000: 310 return DDI_BUF_PHY_LINK_RATE(5); 311 case 270000: 312 return DDI_BUF_PHY_LINK_RATE(1); 313 case 324000: 314 return DDI_BUF_PHY_LINK_RATE(6); 315 case 432000: 316 return DDI_BUF_PHY_LINK_RATE(7); 317 case 540000: 318 return DDI_BUF_PHY_LINK_RATE(2); 319 case 810000: 320 return DDI_BUF_PHY_LINK_RATE(3); 321 default: 322 MISSING_CASE(port_clock); 323 return DDI_BUF_PHY_LINK_RATE(0); 324 } 325 } 326 327 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 328 const struct intel_crtc_state *crtc_state) 329 { 330 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 331 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 332 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 333 enum phy phy = intel_port_to_phy(i915, encoder->port); 334 335 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 336 intel_dp->DP = dig_port->saved_port_bits | 337 DDI_PORT_WIDTH(crtc_state->lane_count) | 338 DDI_BUF_TRANS_SELECT(0); 339 340 if (DISPLAY_VER(i915) >= 14) { 341 if (intel_dp_is_uhbr(crtc_state)) 342 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 343 else 344 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 345 } 346 347 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 348 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 349 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 350 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 351 } 352 } 353 354 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 355 enum port port) 356 { 357 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 358 359 switch (val) { 360 case DDI_CLK_SEL_NONE: 361 return 0; 362 case DDI_CLK_SEL_TBT_162: 363 return 162000; 364 case DDI_CLK_SEL_TBT_270: 365 return 270000; 366 case DDI_CLK_SEL_TBT_540: 367 return 540000; 368 case DDI_CLK_SEL_TBT_810: 369 return 810000; 370 default: 371 MISSING_CASE(val); 372 return 0; 373 } 374 } 375 376 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 377 { 378 /* CRT dotclock is determined via other means */ 379 if (pipe_config->has_pch_encoder) 380 return; 381 382 pipe_config->hw.adjusted_mode.crtc_clock = 383 intel_crtc_dotclock(pipe_config); 384 } 385 386 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 387 const struct drm_connector_state *conn_state) 388 { 389 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 390 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 391 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 392 u32 temp; 393 394 if (!intel_crtc_has_dp_encoder(crtc_state)) 395 return; 396 397 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 398 399 temp = DP_MSA_MISC_SYNC_CLOCK; 400 401 switch (crtc_state->pipe_bpp) { 402 case 18: 403 temp |= DP_MSA_MISC_6_BPC; 404 break; 405 case 24: 406 temp |= DP_MSA_MISC_8_BPC; 407 break; 408 case 30: 409 temp |= DP_MSA_MISC_10_BPC; 410 break; 411 case 36: 412 temp |= DP_MSA_MISC_12_BPC; 413 break; 414 default: 415 MISSING_CASE(crtc_state->pipe_bpp); 416 break; 417 } 418 419 /* nonsense combination */ 420 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 421 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 422 423 if (crtc_state->limited_color_range) 424 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 425 426 /* 427 * As per DP 1.2 spec section 2.3.4.3 while sending 428 * YCBCR 444 signals we should program MSA MISC1/0 fields with 429 * colorspace information. 430 */ 431 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 432 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 433 434 /* 435 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 436 * of Color Encoding Format and Content Color Gamut] while sending 437 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 438 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 439 */ 440 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 441 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 442 443 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 444 } 445 446 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 447 { 448 if (master_transcoder == TRANSCODER_EDP) 449 return 0; 450 else 451 return master_transcoder + 1; 452 } 453 454 static void 455 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 456 const struct intel_crtc_state *crtc_state) 457 { 458 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 459 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 460 u32 val = 0; 461 462 if (intel_dp_is_uhbr(crtc_state)) 463 val = TRANS_DP2_128B132B_CHANNEL_CODING; 464 465 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 466 } 467 468 /* 469 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 470 * 471 * Only intended to be used by intel_ddi_enable_transcoder_func() and 472 * intel_ddi_config_transcoder_func(). 473 */ 474 static u32 475 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 476 const struct intel_crtc_state *crtc_state) 477 { 478 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 479 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 480 enum pipe pipe = crtc->pipe; 481 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 482 enum port port = encoder->port; 483 u32 temp; 484 485 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 486 temp = TRANS_DDI_FUNC_ENABLE; 487 if (DISPLAY_VER(dev_priv) >= 12) 488 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 489 else 490 temp |= TRANS_DDI_SELECT_PORT(port); 491 492 switch (crtc_state->pipe_bpp) { 493 default: 494 MISSING_CASE(crtc_state->pipe_bpp); 495 fallthrough; 496 case 18: 497 temp |= TRANS_DDI_BPC_6; 498 break; 499 case 24: 500 temp |= TRANS_DDI_BPC_8; 501 break; 502 case 30: 503 temp |= TRANS_DDI_BPC_10; 504 break; 505 case 36: 506 temp |= TRANS_DDI_BPC_12; 507 break; 508 } 509 510 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 511 temp |= TRANS_DDI_PVSYNC; 512 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 513 temp |= TRANS_DDI_PHSYNC; 514 515 if (cpu_transcoder == TRANSCODER_EDP) { 516 switch (pipe) { 517 default: 518 MISSING_CASE(pipe); 519 fallthrough; 520 case PIPE_A: 521 /* On Haswell, can only use the always-on power well for 522 * eDP when not using the panel fitter, and when not 523 * using motion blur mitigation (which we don't 524 * support). */ 525 if (crtc_state->pch_pfit.force_thru) 526 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 527 else 528 temp |= TRANS_DDI_EDP_INPUT_A_ON; 529 break; 530 case PIPE_B: 531 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 532 break; 533 case PIPE_C: 534 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 535 break; 536 } 537 } 538 539 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 540 if (crtc_state->has_hdmi_sink) 541 temp |= TRANS_DDI_MODE_SELECT_HDMI; 542 else 543 temp |= TRANS_DDI_MODE_SELECT_DVI; 544 545 if (crtc_state->hdmi_scrambling) 546 temp |= TRANS_DDI_HDMI_SCRAMBLING; 547 if (crtc_state->hdmi_high_tmds_clock_ratio) 548 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 549 if (DISPLAY_VER(dev_priv) >= 14) 550 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 551 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 552 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 553 temp |= (crtc_state->fdi_lanes - 1) << 1; 554 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 555 if (intel_dp_is_uhbr(crtc_state)) 556 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 557 else 558 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 559 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 560 561 if (DISPLAY_VER(dev_priv) >= 12) { 562 enum transcoder master; 563 564 master = crtc_state->mst_master_transcoder; 565 drm_WARN_ON(&dev_priv->drm, 566 master == INVALID_TRANSCODER); 567 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 568 } 569 } else { 570 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 571 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 572 } 573 574 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 575 crtc_state->master_transcoder != INVALID_TRANSCODER) { 576 u8 master_select = 577 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 578 579 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 580 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 581 } 582 583 return temp; 584 } 585 586 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 587 const struct intel_crtc_state *crtc_state) 588 { 589 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 590 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 591 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 592 593 if (DISPLAY_VER(dev_priv) >= 11) { 594 enum transcoder master_transcoder = crtc_state->master_transcoder; 595 u32 ctl2 = 0; 596 597 if (master_transcoder != INVALID_TRANSCODER) { 598 u8 master_select = 599 bdw_trans_port_sync_master_select(master_transcoder); 600 601 ctl2 |= PORT_SYNC_MODE_ENABLE | 602 PORT_SYNC_MODE_MASTER_SELECT(master_select); 603 } 604 605 intel_de_write(dev_priv, 606 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 607 } 608 609 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 610 intel_ddi_transcoder_func_reg_val_get(encoder, 611 crtc_state)); 612 } 613 614 /* 615 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 616 * bit. 617 */ 618 static void 619 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 620 const struct intel_crtc_state *crtc_state) 621 { 622 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 623 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 624 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 625 u32 ctl; 626 627 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 628 ctl &= ~TRANS_DDI_FUNC_ENABLE; 629 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 630 } 631 632 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 633 { 634 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 635 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 636 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 637 u32 ctl; 638 639 if (DISPLAY_VER(dev_priv) >= 11) 640 intel_de_write(dev_priv, 641 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 642 643 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 644 645 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 646 647 ctl &= ~TRANS_DDI_FUNC_ENABLE; 648 649 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 650 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 651 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 652 653 if (DISPLAY_VER(dev_priv) >= 12) { 654 if (!intel_dp_mst_is_master_trans(crtc_state)) { 655 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 656 TRANS_DDI_MODE_SELECT_MASK); 657 } 658 } else { 659 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 660 } 661 662 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 663 664 if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) && 665 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 666 drm_dbg_kms(&dev_priv->drm, 667 "Quirk Increase DDI disabled time\n"); 668 /* Quirk time at 100ms for reliable operation */ 669 msleep(100); 670 } 671 } 672 673 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 674 enum transcoder cpu_transcoder, 675 bool enable, u32 hdcp_mask) 676 { 677 struct drm_device *dev = intel_encoder->base.dev; 678 struct drm_i915_private *dev_priv = to_i915(dev); 679 intel_wakeref_t wakeref; 680 int ret = 0; 681 682 wakeref = intel_display_power_get_if_enabled(dev_priv, 683 intel_encoder->power_domain); 684 if (drm_WARN_ON(dev, !wakeref)) 685 return -ENXIO; 686 687 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 688 hdcp_mask, enable ? hdcp_mask : 0); 689 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 690 return ret; 691 } 692 693 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 694 { 695 struct drm_device *dev = intel_connector->base.dev; 696 struct drm_i915_private *dev_priv = to_i915(dev); 697 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 698 int type = intel_connector->base.connector_type; 699 enum port port = encoder->port; 700 enum transcoder cpu_transcoder; 701 intel_wakeref_t wakeref; 702 enum pipe pipe = 0; 703 u32 tmp; 704 bool ret; 705 706 wakeref = intel_display_power_get_if_enabled(dev_priv, 707 encoder->power_domain); 708 if (!wakeref) 709 return false; 710 711 if (!encoder->get_hw_state(encoder, &pipe)) { 712 ret = false; 713 goto out; 714 } 715 716 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 717 cpu_transcoder = TRANSCODER_EDP; 718 else 719 cpu_transcoder = (enum transcoder) pipe; 720 721 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 722 723 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 724 case TRANS_DDI_MODE_SELECT_HDMI: 725 case TRANS_DDI_MODE_SELECT_DVI: 726 ret = type == DRM_MODE_CONNECTOR_HDMIA; 727 break; 728 729 case TRANS_DDI_MODE_SELECT_DP_SST: 730 ret = type == DRM_MODE_CONNECTOR_eDP || 731 type == DRM_MODE_CONNECTOR_DisplayPort; 732 break; 733 734 case TRANS_DDI_MODE_SELECT_DP_MST: 735 /* if the transcoder is in MST state then 736 * connector isn't connected */ 737 ret = false; 738 break; 739 740 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 741 if (HAS_DP20(dev_priv)) 742 /* 128b/132b */ 743 ret = false; 744 else 745 /* FDI */ 746 ret = type == DRM_MODE_CONNECTOR_VGA; 747 break; 748 749 default: 750 ret = false; 751 break; 752 } 753 754 out: 755 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 756 757 return ret; 758 } 759 760 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 761 u8 *pipe_mask, bool *is_dp_mst) 762 { 763 struct drm_device *dev = encoder->base.dev; 764 struct drm_i915_private *dev_priv = to_i915(dev); 765 enum port port = encoder->port; 766 intel_wakeref_t wakeref; 767 enum pipe p; 768 u32 tmp; 769 u8 mst_pipe_mask; 770 771 *pipe_mask = 0; 772 *is_dp_mst = false; 773 774 wakeref = intel_display_power_get_if_enabled(dev_priv, 775 encoder->power_domain); 776 if (!wakeref) 777 return; 778 779 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 780 if (!(tmp & DDI_BUF_CTL_ENABLE)) 781 goto out; 782 783 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 784 tmp = intel_de_read(dev_priv, 785 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 786 787 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 788 default: 789 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 790 fallthrough; 791 case TRANS_DDI_EDP_INPUT_A_ON: 792 case TRANS_DDI_EDP_INPUT_A_ONOFF: 793 *pipe_mask = BIT(PIPE_A); 794 break; 795 case TRANS_DDI_EDP_INPUT_B_ONOFF: 796 *pipe_mask = BIT(PIPE_B); 797 break; 798 case TRANS_DDI_EDP_INPUT_C_ONOFF: 799 *pipe_mask = BIT(PIPE_C); 800 break; 801 } 802 803 goto out; 804 } 805 806 mst_pipe_mask = 0; 807 for_each_pipe(dev_priv, p) { 808 enum transcoder cpu_transcoder = (enum transcoder)p; 809 unsigned int port_mask, ddi_select; 810 intel_wakeref_t trans_wakeref; 811 812 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 813 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 814 if (!trans_wakeref) 815 continue; 816 817 if (DISPLAY_VER(dev_priv) >= 12) { 818 port_mask = TGL_TRANS_DDI_PORT_MASK; 819 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 820 } else { 821 port_mask = TRANS_DDI_PORT_MASK; 822 ddi_select = TRANS_DDI_SELECT_PORT(port); 823 } 824 825 tmp = intel_de_read(dev_priv, 826 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 827 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 828 trans_wakeref); 829 830 if ((tmp & port_mask) != ddi_select) 831 continue; 832 833 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 834 (HAS_DP20(dev_priv) && 835 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 836 mst_pipe_mask |= BIT(p); 837 838 *pipe_mask |= BIT(p); 839 } 840 841 if (!*pipe_mask) 842 drm_dbg_kms(&dev_priv->drm, 843 "No pipe for [ENCODER:%d:%s] found\n", 844 encoder->base.base.id, encoder->base.name); 845 846 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 847 drm_dbg_kms(&dev_priv->drm, 848 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 849 encoder->base.base.id, encoder->base.name, 850 *pipe_mask); 851 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 852 } 853 854 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 855 drm_dbg_kms(&dev_priv->drm, 856 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 857 encoder->base.base.id, encoder->base.name, 858 *pipe_mask, mst_pipe_mask); 859 else 860 *is_dp_mst = mst_pipe_mask; 861 862 out: 863 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 864 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 865 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 866 BXT_PHY_LANE_POWERDOWN_ACK | 867 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 868 drm_err(&dev_priv->drm, 869 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 870 encoder->base.base.id, encoder->base.name, tmp); 871 } 872 873 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 874 } 875 876 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 877 enum pipe *pipe) 878 { 879 u8 pipe_mask; 880 bool is_mst; 881 882 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 883 884 if (is_mst || !pipe_mask) 885 return false; 886 887 *pipe = ffs(pipe_mask) - 1; 888 889 return true; 890 } 891 892 static enum intel_display_power_domain 893 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 894 const struct intel_crtc_state *crtc_state) 895 { 896 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 897 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 898 899 /* 900 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 901 * DC states enabled at the same time, while for driver initiated AUX 902 * transfers we need the same AUX IOs to be powered but with DC states 903 * disabled. Accordingly use the AUX_IO_<port> power domain here which 904 * leaves DC states enabled. 905 * 906 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 907 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 908 * well, so we can acquire a wider AUX_<port> power domain reference 909 * instead of a specific AUX_IO_<port> reference without powering up any 910 * extra wells. 911 */ 912 if (intel_encoder_can_psr(&dig_port->base)) 913 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 914 else if (DISPLAY_VER(i915) < 14 && 915 (intel_crtc_has_dp_encoder(crtc_state) || 916 intel_phy_is_tc(i915, phy))) 917 return intel_aux_power_domain(dig_port); 918 else 919 return POWER_DOMAIN_INVALID; 920 } 921 922 static void 923 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 924 const struct intel_crtc_state *crtc_state) 925 { 926 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 927 enum intel_display_power_domain domain = 928 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 929 930 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 931 932 if (domain == POWER_DOMAIN_INVALID) 933 return; 934 935 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 936 } 937 938 static void 939 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 940 const struct intel_crtc_state *crtc_state) 941 { 942 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 943 enum intel_display_power_domain domain = 944 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 945 intel_wakeref_t wf; 946 947 wf = fetch_and_zero(&dig_port->aux_wakeref); 948 if (!wf) 949 return; 950 951 intel_display_power_put(i915, domain, wf); 952 } 953 954 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 955 struct intel_crtc_state *crtc_state) 956 { 957 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 958 struct intel_digital_port *dig_port; 959 960 /* 961 * TODO: Add support for MST encoders. Atm, the following should never 962 * happen since fake-MST encoders don't set their get_power_domains() 963 * hook. 964 */ 965 if (drm_WARN_ON(&dev_priv->drm, 966 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 967 return; 968 969 dig_port = enc_to_dig_port(encoder); 970 971 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 972 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 973 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 974 dig_port->ddi_io_power_domain); 975 } 976 977 main_link_aux_power_domain_get(dig_port, crtc_state); 978 } 979 980 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 981 const struct intel_crtc_state *crtc_state) 982 { 983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 984 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 985 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 986 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 987 u32 val; 988 989 if (cpu_transcoder == TRANSCODER_EDP) 990 return; 991 992 if (DISPLAY_VER(dev_priv) >= 13) 993 val = TGL_TRANS_CLK_SEL_PORT(phy); 994 else if (DISPLAY_VER(dev_priv) >= 12) 995 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 996 else 997 val = TRANS_CLK_SEL_PORT(encoder->port); 998 999 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1000 } 1001 1002 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1003 { 1004 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1005 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1006 u32 val; 1007 1008 if (cpu_transcoder == TRANSCODER_EDP) 1009 return; 1010 1011 if (DISPLAY_VER(dev_priv) >= 12) 1012 val = TGL_TRANS_CLK_SEL_DISABLED; 1013 else 1014 val = TRANS_CLK_SEL_DISABLED; 1015 1016 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1017 } 1018 1019 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1020 enum port port, u8 iboost) 1021 { 1022 u32 tmp; 1023 1024 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1025 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1026 if (iboost) 1027 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1028 else 1029 tmp |= BALANCE_LEG_DISABLE(port); 1030 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1031 } 1032 1033 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1034 const struct intel_crtc_state *crtc_state, 1035 int level) 1036 { 1037 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1038 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1039 u8 iboost; 1040 1041 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1042 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1043 else 1044 iboost = intel_bios_dp_boost_level(encoder->devdata); 1045 1046 if (iboost == 0) { 1047 const struct intel_ddi_buf_trans *trans; 1048 int n_entries; 1049 1050 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1051 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1052 return; 1053 1054 iboost = trans->entries[level].hsw.i_boost; 1055 } 1056 1057 /* Make sure that the requested I_boost is valid */ 1058 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1059 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1060 return; 1061 } 1062 1063 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1064 1065 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1066 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1067 } 1068 1069 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1070 const struct intel_crtc_state *crtc_state) 1071 { 1072 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1073 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1074 int n_entries; 1075 1076 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1077 1078 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1079 n_entries = 1; 1080 if (drm_WARN_ON(&dev_priv->drm, 1081 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1082 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1083 1084 return index_to_dp_signal_levels[n_entries - 1] & 1085 DP_TRAIN_VOLTAGE_SWING_MASK; 1086 } 1087 1088 /* 1089 * We assume that the full set of pre-emphasis values can be 1090 * used on all DDI platforms. Should that change we need to 1091 * rethink this code. 1092 */ 1093 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1094 { 1095 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1096 } 1097 1098 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1099 int lane) 1100 { 1101 if (crtc_state->port_clock > 600000) 1102 return 0; 1103 1104 if (crtc_state->lane_count == 4) 1105 return lane >= 1 ? LOADGEN_SELECT : 0; 1106 else 1107 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1108 } 1109 1110 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1111 const struct intel_crtc_state *crtc_state) 1112 { 1113 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1114 const struct intel_ddi_buf_trans *trans; 1115 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1116 int n_entries, ln; 1117 u32 val; 1118 1119 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1120 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1121 return; 1122 1123 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1124 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1125 1126 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1127 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1128 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1129 intel_dp->hobl_active ? val : 0); 1130 } 1131 1132 /* Set PORT_TX_DW5 */ 1133 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1134 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1135 TAP2_DISABLE | TAP3_DISABLE); 1136 val |= SCALING_MODE_SEL(0x2); 1137 val |= RTERM_SELECT(0x6); 1138 val |= TAP3_DISABLE; 1139 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1140 1141 /* Program PORT_TX_DW2 */ 1142 for (ln = 0; ln < 4; ln++) { 1143 int level = intel_ddi_level(encoder, crtc_state, ln); 1144 1145 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1146 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1147 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1148 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1149 RCOMP_SCALAR(0x98)); 1150 } 1151 1152 /* Program PORT_TX_DW4 */ 1153 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1154 for (ln = 0; ln < 4; ln++) { 1155 int level = intel_ddi_level(encoder, crtc_state, ln); 1156 1157 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1158 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1159 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1160 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1161 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1162 } 1163 1164 /* Program PORT_TX_DW7 */ 1165 for (ln = 0; ln < 4; ln++) { 1166 int level = intel_ddi_level(encoder, crtc_state, ln); 1167 1168 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1169 N_SCALAR_MASK, 1170 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1171 } 1172 } 1173 1174 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1175 const struct intel_crtc_state *crtc_state) 1176 { 1177 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1178 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1179 u32 val; 1180 int ln; 1181 1182 /* 1183 * 1. If port type is eDP or DP, 1184 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1185 * else clear to 0b. 1186 */ 1187 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1188 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1189 val &= ~COMMON_KEEPER_EN; 1190 else 1191 val |= COMMON_KEEPER_EN; 1192 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1193 1194 /* 2. Program loadgen select */ 1195 /* 1196 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1197 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1198 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1199 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1200 */ 1201 for (ln = 0; ln < 4; ln++) { 1202 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1203 LOADGEN_SELECT, 1204 icl_combo_phy_loadgen_select(crtc_state, ln)); 1205 } 1206 1207 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1208 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1209 0, SUS_CLOCK_CONFIG); 1210 1211 /* 4. Clear training enable to change swing values */ 1212 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1213 val &= ~TX_TRAINING_EN; 1214 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1215 1216 /* 5. Program swing and de-emphasis */ 1217 icl_ddi_combo_vswing_program(encoder, crtc_state); 1218 1219 /* 6. Set training enable to trigger update */ 1220 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1221 val |= TX_TRAINING_EN; 1222 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1223 } 1224 1225 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1226 const struct intel_crtc_state *crtc_state) 1227 { 1228 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1229 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1230 const struct intel_ddi_buf_trans *trans; 1231 int n_entries, ln; 1232 1233 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1234 return; 1235 1236 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1237 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1238 return; 1239 1240 for (ln = 0; ln < 2; ln++) { 1241 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1242 CRI_USE_FS32, 0); 1243 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1244 CRI_USE_FS32, 0); 1245 } 1246 1247 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1248 for (ln = 0; ln < 2; ln++) { 1249 int level; 1250 1251 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1252 1253 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1254 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1255 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1256 1257 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1258 1259 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1260 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1261 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1262 } 1263 1264 /* Program MG_TX_DRVCTRL with values from vswing table */ 1265 for (ln = 0; ln < 2; ln++) { 1266 int level; 1267 1268 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1269 1270 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1271 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1272 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1273 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1274 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1275 CRI_TXDEEMPH_OVERRIDE_EN); 1276 1277 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1278 1279 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1280 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1281 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1282 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1283 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1284 CRI_TXDEEMPH_OVERRIDE_EN); 1285 1286 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1287 } 1288 1289 /* 1290 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1291 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1292 * values from table for which TX1 and TX2 enabled. 1293 */ 1294 for (ln = 0; ln < 2; ln++) { 1295 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1296 CFG_LOW_RATE_LKREN_EN, 1297 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1298 } 1299 1300 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1301 for (ln = 0; ln < 2; ln++) { 1302 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1303 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1304 CFG_AMI_CK_DIV_OVERRIDE_EN, 1305 crtc_state->port_clock > 500000 ? 1306 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1307 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1308 1309 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1310 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1311 CFG_AMI_CK_DIV_OVERRIDE_EN, 1312 crtc_state->port_clock > 500000 ? 1313 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1314 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1315 } 1316 1317 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1318 for (ln = 0; ln < 2; ln++) { 1319 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1320 0, CRI_CALCINIT); 1321 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1322 0, CRI_CALCINIT); 1323 } 1324 } 1325 1326 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1327 const struct intel_crtc_state *crtc_state) 1328 { 1329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1330 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1331 const struct intel_ddi_buf_trans *trans; 1332 int n_entries, ln; 1333 1334 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1335 return; 1336 1337 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1338 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1339 return; 1340 1341 for (ln = 0; ln < 2; ln++) { 1342 int level; 1343 1344 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1345 1346 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1347 1348 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1349 DKL_TX_PRESHOOT_COEFF_MASK | 1350 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1351 DKL_TX_VSWING_CONTROL_MASK, 1352 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1353 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1354 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1355 1356 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1357 1358 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1359 DKL_TX_PRESHOOT_COEFF_MASK | 1360 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1361 DKL_TX_VSWING_CONTROL_MASK, 1362 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1363 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1364 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1365 1366 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1367 DKL_TX_DP20BITMODE, 0); 1368 1369 if (IS_ALDERLAKE_P(dev_priv)) { 1370 u32 val; 1371 1372 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1373 if (ln == 0) { 1374 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1375 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1376 } else { 1377 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1378 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1379 } 1380 } else { 1381 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1382 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1383 } 1384 1385 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1386 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1387 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1388 val); 1389 } 1390 } 1391 } 1392 1393 static int translate_signal_level(struct intel_dp *intel_dp, 1394 u8 signal_levels) 1395 { 1396 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1397 int i; 1398 1399 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1400 if (index_to_dp_signal_levels[i] == signal_levels) 1401 return i; 1402 } 1403 1404 drm_WARN(&i915->drm, 1, 1405 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1406 signal_levels); 1407 1408 return 0; 1409 } 1410 1411 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1412 const struct intel_crtc_state *crtc_state, 1413 int lane) 1414 { 1415 u8 train_set = intel_dp->train_set[lane]; 1416 1417 if (intel_dp_is_uhbr(crtc_state)) { 1418 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1419 } else { 1420 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1421 DP_TRAIN_PRE_EMPHASIS_MASK); 1422 1423 return translate_signal_level(intel_dp, signal_levels); 1424 } 1425 } 1426 1427 int intel_ddi_level(struct intel_encoder *encoder, 1428 const struct intel_crtc_state *crtc_state, 1429 int lane) 1430 { 1431 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1432 const struct intel_ddi_buf_trans *trans; 1433 int level, n_entries; 1434 1435 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1436 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1437 return 0; 1438 1439 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1440 level = intel_ddi_hdmi_level(encoder, trans); 1441 else 1442 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1443 lane); 1444 1445 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1446 level = n_entries - 1; 1447 1448 return level; 1449 } 1450 1451 static void 1452 hsw_set_signal_levels(struct intel_encoder *encoder, 1453 const struct intel_crtc_state *crtc_state) 1454 { 1455 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1456 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1457 int level = intel_ddi_level(encoder, crtc_state, 0); 1458 enum port port = encoder->port; 1459 u32 signal_levels; 1460 1461 if (has_iboost(dev_priv)) 1462 skl_ddi_set_iboost(encoder, crtc_state, level); 1463 1464 /* HDMI ignores the rest */ 1465 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1466 return; 1467 1468 signal_levels = DDI_BUF_TRANS_SELECT(level); 1469 1470 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1471 signal_levels); 1472 1473 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1474 intel_dp->DP |= signal_levels; 1475 1476 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1477 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1478 } 1479 1480 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1481 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1482 { 1483 mutex_lock(&i915->display.dpll.lock); 1484 1485 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1486 1487 /* 1488 * "This step and the step before must be 1489 * done with separate register writes." 1490 */ 1491 intel_de_rmw(i915, reg, clk_off, 0); 1492 1493 mutex_unlock(&i915->display.dpll.lock); 1494 } 1495 1496 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1497 u32 clk_off) 1498 { 1499 mutex_lock(&i915->display.dpll.lock); 1500 1501 intel_de_rmw(i915, reg, 0, clk_off); 1502 1503 mutex_unlock(&i915->display.dpll.lock); 1504 } 1505 1506 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1507 u32 clk_off) 1508 { 1509 return !(intel_de_read(i915, reg) & clk_off); 1510 } 1511 1512 static struct intel_shared_dpll * 1513 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1514 u32 clk_sel_mask, u32 clk_sel_shift) 1515 { 1516 enum intel_dpll_id id; 1517 1518 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1519 1520 return intel_get_shared_dpll_by_id(i915, id); 1521 } 1522 1523 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1524 const struct intel_crtc_state *crtc_state) 1525 { 1526 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1527 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1528 enum phy phy = intel_port_to_phy(i915, encoder->port); 1529 1530 if (drm_WARN_ON(&i915->drm, !pll)) 1531 return; 1532 1533 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1534 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1535 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1536 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1537 } 1538 1539 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1540 { 1541 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1542 enum phy phy = intel_port_to_phy(i915, encoder->port); 1543 1544 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1545 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1546 } 1547 1548 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1549 { 1550 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1551 enum phy phy = intel_port_to_phy(i915, encoder->port); 1552 1553 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1554 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1555 } 1556 1557 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1558 { 1559 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1560 enum phy phy = intel_port_to_phy(i915, encoder->port); 1561 1562 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1563 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1564 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1565 } 1566 1567 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1568 const struct intel_crtc_state *crtc_state) 1569 { 1570 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1571 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1572 enum phy phy = intel_port_to_phy(i915, encoder->port); 1573 1574 if (drm_WARN_ON(&i915->drm, !pll)) 1575 return; 1576 1577 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1578 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1579 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1580 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1581 } 1582 1583 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1584 { 1585 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1586 enum phy phy = intel_port_to_phy(i915, encoder->port); 1587 1588 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1589 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1590 } 1591 1592 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1593 { 1594 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1595 enum phy phy = intel_port_to_phy(i915, encoder->port); 1596 1597 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1598 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1599 } 1600 1601 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1602 { 1603 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1604 enum phy phy = intel_port_to_phy(i915, encoder->port); 1605 1606 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1607 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1608 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1609 } 1610 1611 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1612 const struct intel_crtc_state *crtc_state) 1613 { 1614 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1615 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1616 enum phy phy = intel_port_to_phy(i915, encoder->port); 1617 1618 if (drm_WARN_ON(&i915->drm, !pll)) 1619 return; 1620 1621 /* 1622 * If we fail this, something went very wrong: first 2 PLLs should be 1623 * used by first 2 phys and last 2 PLLs by last phys 1624 */ 1625 if (drm_WARN_ON(&i915->drm, 1626 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1627 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1628 return; 1629 1630 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1631 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1632 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1633 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1634 } 1635 1636 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1637 { 1638 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1639 enum phy phy = intel_port_to_phy(i915, encoder->port); 1640 1641 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1642 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1643 } 1644 1645 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1646 { 1647 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1648 enum phy phy = intel_port_to_phy(i915, encoder->port); 1649 1650 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1651 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1652 } 1653 1654 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1655 { 1656 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1657 enum phy phy = intel_port_to_phy(i915, encoder->port); 1658 enum intel_dpll_id id; 1659 u32 val; 1660 1661 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1662 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1663 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1664 id = val; 1665 1666 /* 1667 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1668 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1669 * bit for phy C and D. 1670 */ 1671 if (phy >= PHY_C) 1672 id += DPLL_ID_DG1_DPLL2; 1673 1674 return intel_get_shared_dpll_by_id(i915, id); 1675 } 1676 1677 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1678 const struct intel_crtc_state *crtc_state) 1679 { 1680 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1681 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1682 enum phy phy = intel_port_to_phy(i915, encoder->port); 1683 1684 if (drm_WARN_ON(&i915->drm, !pll)) 1685 return; 1686 1687 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1688 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1689 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1690 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1691 } 1692 1693 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1694 { 1695 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1696 enum phy phy = intel_port_to_phy(i915, encoder->port); 1697 1698 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1699 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1700 } 1701 1702 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1703 { 1704 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1705 enum phy phy = intel_port_to_phy(i915, encoder->port); 1706 1707 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1708 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1709 } 1710 1711 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1712 { 1713 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1714 enum phy phy = intel_port_to_phy(i915, encoder->port); 1715 1716 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1717 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1718 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1719 } 1720 1721 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1722 const struct intel_crtc_state *crtc_state) 1723 { 1724 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1725 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1726 enum port port = encoder->port; 1727 1728 if (drm_WARN_ON(&i915->drm, !pll)) 1729 return; 1730 1731 /* 1732 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1733 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1734 */ 1735 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1736 1737 icl_ddi_combo_enable_clock(encoder, crtc_state); 1738 } 1739 1740 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1741 { 1742 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1743 enum port port = encoder->port; 1744 1745 icl_ddi_combo_disable_clock(encoder); 1746 1747 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1748 } 1749 1750 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1751 { 1752 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1753 enum port port = encoder->port; 1754 u32 tmp; 1755 1756 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1757 1758 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1759 return false; 1760 1761 return icl_ddi_combo_is_clock_enabled(encoder); 1762 } 1763 1764 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1765 const struct intel_crtc_state *crtc_state) 1766 { 1767 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1768 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1769 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1770 enum port port = encoder->port; 1771 1772 if (drm_WARN_ON(&i915->drm, !pll)) 1773 return; 1774 1775 intel_de_write(i915, DDI_CLK_SEL(port), 1776 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1777 1778 mutex_lock(&i915->display.dpll.lock); 1779 1780 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1781 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1782 1783 mutex_unlock(&i915->display.dpll.lock); 1784 } 1785 1786 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1787 { 1788 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1789 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1790 enum port port = encoder->port; 1791 1792 mutex_lock(&i915->display.dpll.lock); 1793 1794 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1795 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1796 1797 mutex_unlock(&i915->display.dpll.lock); 1798 1799 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1800 } 1801 1802 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1803 { 1804 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1805 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1806 enum port port = encoder->port; 1807 u32 tmp; 1808 1809 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1810 1811 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1812 return false; 1813 1814 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1815 1816 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1817 } 1818 1819 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1820 { 1821 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1822 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1823 enum port port = encoder->port; 1824 enum intel_dpll_id id; 1825 u32 tmp; 1826 1827 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1828 1829 switch (tmp & DDI_CLK_SEL_MASK) { 1830 case DDI_CLK_SEL_TBT_162: 1831 case DDI_CLK_SEL_TBT_270: 1832 case DDI_CLK_SEL_TBT_540: 1833 case DDI_CLK_SEL_TBT_810: 1834 id = DPLL_ID_ICL_TBTPLL; 1835 break; 1836 case DDI_CLK_SEL_MG: 1837 id = icl_tc_port_to_pll_id(tc_port); 1838 break; 1839 default: 1840 MISSING_CASE(tmp); 1841 fallthrough; 1842 case DDI_CLK_SEL_NONE: 1843 return NULL; 1844 } 1845 1846 return intel_get_shared_dpll_by_id(i915, id); 1847 } 1848 1849 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1850 { 1851 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1852 enum intel_dpll_id id; 1853 1854 switch (encoder->port) { 1855 case PORT_A: 1856 id = DPLL_ID_SKL_DPLL0; 1857 break; 1858 case PORT_B: 1859 id = DPLL_ID_SKL_DPLL1; 1860 break; 1861 case PORT_C: 1862 id = DPLL_ID_SKL_DPLL2; 1863 break; 1864 default: 1865 MISSING_CASE(encoder->port); 1866 return NULL; 1867 } 1868 1869 return intel_get_shared_dpll_by_id(i915, id); 1870 } 1871 1872 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1873 const struct intel_crtc_state *crtc_state) 1874 { 1875 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1876 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1877 enum port port = encoder->port; 1878 1879 if (drm_WARN_ON(&i915->drm, !pll)) 1880 return; 1881 1882 mutex_lock(&i915->display.dpll.lock); 1883 1884 intel_de_rmw(i915, DPLL_CTRL2, 1885 DPLL_CTRL2_DDI_CLK_OFF(port) | 1886 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1887 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1888 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1889 1890 mutex_unlock(&i915->display.dpll.lock); 1891 } 1892 1893 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1894 { 1895 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1896 enum port port = encoder->port; 1897 1898 mutex_lock(&i915->display.dpll.lock); 1899 1900 intel_de_rmw(i915, DPLL_CTRL2, 1901 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1902 1903 mutex_unlock(&i915->display.dpll.lock); 1904 } 1905 1906 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1907 { 1908 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1909 enum port port = encoder->port; 1910 1911 /* 1912 * FIXME Not sure if the override affects both 1913 * the PLL selection and the CLK_OFF bit. 1914 */ 1915 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1916 } 1917 1918 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1919 { 1920 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1921 enum port port = encoder->port; 1922 enum intel_dpll_id id; 1923 u32 tmp; 1924 1925 tmp = intel_de_read(i915, DPLL_CTRL2); 1926 1927 /* 1928 * FIXME Not sure if the override affects both 1929 * the PLL selection and the CLK_OFF bit. 1930 */ 1931 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1932 return NULL; 1933 1934 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1935 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1936 1937 return intel_get_shared_dpll_by_id(i915, id); 1938 } 1939 1940 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1941 const struct intel_crtc_state *crtc_state) 1942 { 1943 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1944 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1945 enum port port = encoder->port; 1946 1947 if (drm_WARN_ON(&i915->drm, !pll)) 1948 return; 1949 1950 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1951 } 1952 1953 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1954 { 1955 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1956 enum port port = encoder->port; 1957 1958 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1959 } 1960 1961 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1962 { 1963 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1964 enum port port = encoder->port; 1965 1966 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1967 } 1968 1969 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1970 { 1971 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1972 enum port port = encoder->port; 1973 enum intel_dpll_id id; 1974 u32 tmp; 1975 1976 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1977 1978 switch (tmp & PORT_CLK_SEL_MASK) { 1979 case PORT_CLK_SEL_WRPLL1: 1980 id = DPLL_ID_WRPLL1; 1981 break; 1982 case PORT_CLK_SEL_WRPLL2: 1983 id = DPLL_ID_WRPLL2; 1984 break; 1985 case PORT_CLK_SEL_SPLL: 1986 id = DPLL_ID_SPLL; 1987 break; 1988 case PORT_CLK_SEL_LCPLL_810: 1989 id = DPLL_ID_LCPLL_810; 1990 break; 1991 case PORT_CLK_SEL_LCPLL_1350: 1992 id = DPLL_ID_LCPLL_1350; 1993 break; 1994 case PORT_CLK_SEL_LCPLL_2700: 1995 id = DPLL_ID_LCPLL_2700; 1996 break; 1997 default: 1998 MISSING_CASE(tmp); 1999 fallthrough; 2000 case PORT_CLK_SEL_NONE: 2001 return NULL; 2002 } 2003 2004 return intel_get_shared_dpll_by_id(i915, id); 2005 } 2006 2007 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2008 const struct intel_crtc_state *crtc_state) 2009 { 2010 if (encoder->enable_clock) 2011 encoder->enable_clock(encoder, crtc_state); 2012 } 2013 2014 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2015 { 2016 if (encoder->disable_clock) 2017 encoder->disable_clock(encoder); 2018 } 2019 2020 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2021 { 2022 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2023 u32 port_mask; 2024 bool ddi_clk_needed; 2025 2026 /* 2027 * In case of DP MST, we sanitize the primary encoder only, not the 2028 * virtual ones. 2029 */ 2030 if (encoder->type == INTEL_OUTPUT_DP_MST) 2031 return; 2032 2033 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2034 u8 pipe_mask; 2035 bool is_mst; 2036 2037 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2038 /* 2039 * In the unlikely case that BIOS enables DP in MST mode, just 2040 * warn since our MST HW readout is incomplete. 2041 */ 2042 if (drm_WARN_ON(&i915->drm, is_mst)) 2043 return; 2044 } 2045 2046 port_mask = BIT(encoder->port); 2047 ddi_clk_needed = encoder->base.crtc; 2048 2049 if (encoder->type == INTEL_OUTPUT_DSI) { 2050 struct intel_encoder *other_encoder; 2051 2052 port_mask = intel_dsi_encoder_ports(encoder); 2053 /* 2054 * Sanity check that we haven't incorrectly registered another 2055 * encoder using any of the ports of this DSI encoder. 2056 */ 2057 for_each_intel_encoder(&i915->drm, other_encoder) { 2058 if (other_encoder == encoder) 2059 continue; 2060 2061 if (drm_WARN_ON(&i915->drm, 2062 port_mask & BIT(other_encoder->port))) 2063 return; 2064 } 2065 /* 2066 * For DSI we keep the ddi clocks gated 2067 * except during enable/disable sequence. 2068 */ 2069 ddi_clk_needed = false; 2070 } 2071 2072 if (ddi_clk_needed || !encoder->is_clock_enabled || 2073 !encoder->is_clock_enabled(encoder)) 2074 return; 2075 2076 drm_notice(&i915->drm, 2077 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2078 encoder->base.base.id, encoder->base.name); 2079 2080 encoder->disable_clock(encoder); 2081 } 2082 2083 static void 2084 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2085 const struct intel_crtc_state *crtc_state) 2086 { 2087 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2088 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2089 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2090 u32 ln0, ln1, pin_assignment; 2091 u8 width; 2092 2093 if (!intel_phy_is_tc(dev_priv, phy) || 2094 intel_tc_port_in_tbt_alt_mode(dig_port)) 2095 return; 2096 2097 if (DISPLAY_VER(dev_priv) >= 12) { 2098 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2099 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2100 } else { 2101 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2102 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2103 } 2104 2105 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2106 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2107 2108 /* DPPATC */ 2109 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2110 width = crtc_state->lane_count; 2111 2112 switch (pin_assignment) { 2113 case 0x0: 2114 drm_WARN_ON(&dev_priv->drm, 2115 !intel_tc_port_in_legacy_mode(dig_port)); 2116 if (width == 1) { 2117 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2118 } else { 2119 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2120 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2121 } 2122 break; 2123 case 0x1: 2124 if (width == 4) { 2125 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2126 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2127 } 2128 break; 2129 case 0x2: 2130 if (width == 2) { 2131 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2132 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2133 } 2134 break; 2135 case 0x3: 2136 case 0x5: 2137 if (width == 1) { 2138 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2139 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2140 } else { 2141 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2142 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2143 } 2144 break; 2145 case 0x4: 2146 case 0x6: 2147 if (width == 1) { 2148 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2149 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2150 } else { 2151 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2152 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2153 } 2154 break; 2155 default: 2156 MISSING_CASE(pin_assignment); 2157 } 2158 2159 if (DISPLAY_VER(dev_priv) >= 12) { 2160 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2161 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2162 } else { 2163 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2164 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2165 } 2166 } 2167 2168 static enum transcoder 2169 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2170 { 2171 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2172 return crtc_state->mst_master_transcoder; 2173 else 2174 return crtc_state->cpu_transcoder; 2175 } 2176 2177 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2178 const struct intel_crtc_state *crtc_state) 2179 { 2180 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2181 2182 if (DISPLAY_VER(dev_priv) >= 12) 2183 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2184 else 2185 return DP_TP_CTL(encoder->port); 2186 } 2187 2188 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2189 const struct intel_crtc_state *crtc_state) 2190 { 2191 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2192 2193 if (DISPLAY_VER(dev_priv) >= 12) 2194 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2195 else 2196 return DP_TP_STATUS(encoder->port); 2197 } 2198 2199 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2200 const struct intel_crtc_state *crtc_state, 2201 bool enable) 2202 { 2203 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2204 2205 if (!crtc_state->vrr.enable) 2206 return; 2207 2208 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2209 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2210 drm_dbg_kms(&i915->drm, 2211 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2212 str_enable_disable(enable)); 2213 } 2214 2215 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2216 const struct intel_crtc_state *crtc_state, 2217 bool enable) 2218 { 2219 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2220 2221 if (!crtc_state->fec_enable) 2222 return; 2223 2224 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2225 enable ? DP_FEC_READY : 0) <= 0) 2226 drm_dbg_kms(&i915->drm, "Failed to set FEC_READY to %s in the sink\n", 2227 enable ? "enabled" : "disabled"); 2228 2229 if (enable && 2230 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2231 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2232 drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n"); 2233 } 2234 2235 static int read_fec_detected_status(struct drm_dp_aux *aux) 2236 { 2237 int ret; 2238 u8 status; 2239 2240 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2241 if (ret < 0) 2242 return ret; 2243 2244 return status; 2245 } 2246 2247 static void wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2248 { 2249 struct drm_i915_private *i915 = to_i915(aux->drm_dev); 2250 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2251 int status; 2252 int err; 2253 2254 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2255 status & mask || status < 0, 2256 10000, 200000); 2257 2258 if (!err && status >= 0) 2259 return; 2260 2261 if (err == -ETIMEDOUT) 2262 drm_dbg_kms(&i915->drm, "Timeout waiting for FEC %s to get detected\n", 2263 str_enabled_disabled(enabled)); 2264 else 2265 drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status); 2266 } 2267 2268 void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2269 const struct intel_crtc_state *crtc_state, 2270 bool enabled) 2271 { 2272 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2273 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2274 int ret; 2275 2276 if (!crtc_state->fec_enable) 2277 return; 2278 2279 if (enabled) 2280 ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 2281 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2282 else 2283 ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder, crtc_state), 2284 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2285 2286 if (ret) 2287 drm_err(&i915->drm, 2288 "Timeout waiting for FEC live state to get %s\n", 2289 str_enabled_disabled(enabled)); 2290 2291 /* 2292 * At least the Synoptics MST hub doesn't set the detected flag for 2293 * FEC decoding disabling so skip waiting for that. 2294 */ 2295 if (enabled) 2296 wait_for_fec_detected(&intel_dp->aux, enabled); 2297 } 2298 2299 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2300 const struct intel_crtc_state *crtc_state) 2301 { 2302 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2303 2304 if (!crtc_state->fec_enable) 2305 return; 2306 2307 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2308 0, DP_TP_CTL_FEC_ENABLE); 2309 } 2310 2311 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2312 const struct intel_crtc_state *crtc_state) 2313 { 2314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2315 2316 if (!crtc_state->fec_enable) 2317 return; 2318 2319 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2320 DP_TP_CTL_FEC_ENABLE, 0); 2321 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2322 } 2323 2324 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2325 const struct intel_crtc_state *crtc_state) 2326 { 2327 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2328 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2329 enum phy phy = intel_port_to_phy(i915, encoder->port); 2330 2331 if (intel_phy_is_combo(i915, phy)) { 2332 bool lane_reversal = 2333 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2334 2335 intel_combo_phy_power_up_lanes(i915, phy, false, 2336 crtc_state->lane_count, 2337 lane_reversal); 2338 } 2339 } 2340 2341 /* Splitter enable for eDP MSO is limited to certain pipes. */ 2342 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2343 { 2344 if (IS_ALDERLAKE_P(i915)) 2345 return BIT(PIPE_A) | BIT(PIPE_B); 2346 else 2347 return BIT(PIPE_A); 2348 } 2349 2350 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2351 struct intel_crtc_state *pipe_config) 2352 { 2353 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2354 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2355 enum pipe pipe = crtc->pipe; 2356 u32 dss1; 2357 2358 if (!HAS_MSO(i915)) 2359 return; 2360 2361 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2362 2363 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2364 if (!pipe_config->splitter.enable) 2365 return; 2366 2367 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2368 pipe_config->splitter.enable = false; 2369 return; 2370 } 2371 2372 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2373 default: 2374 drm_WARN(&i915->drm, true, 2375 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2376 fallthrough; 2377 case SPLITTER_CONFIGURATION_2_SEGMENT: 2378 pipe_config->splitter.link_count = 2; 2379 break; 2380 case SPLITTER_CONFIGURATION_4_SEGMENT: 2381 pipe_config->splitter.link_count = 4; 2382 break; 2383 } 2384 2385 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2386 } 2387 2388 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2389 { 2390 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2391 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2392 enum pipe pipe = crtc->pipe; 2393 u32 dss1 = 0; 2394 2395 if (!HAS_MSO(i915)) 2396 return; 2397 2398 if (crtc_state->splitter.enable) { 2399 dss1 |= SPLITTER_ENABLE; 2400 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2401 if (crtc_state->splitter.link_count == 2) 2402 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2403 else 2404 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2405 } 2406 2407 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2408 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2409 OVERLAP_PIXELS_MASK, dss1); 2410 } 2411 2412 static u8 mtl_get_port_width(u8 lane_count) 2413 { 2414 switch (lane_count) { 2415 case 1: 2416 return 0; 2417 case 2: 2418 return 1; 2419 case 3: 2420 return 4; 2421 case 4: 2422 return 3; 2423 default: 2424 MISSING_CASE(lane_count); 2425 return 4; 2426 } 2427 } 2428 2429 static void 2430 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2431 { 2432 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2433 enum port port = encoder->port; 2434 i915_reg_t reg; 2435 u32 set_bits, wait_bits; 2436 2437 if (DISPLAY_VER(dev_priv) >= 20) { 2438 reg = DDI_BUF_CTL(port); 2439 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2440 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2441 } else { 2442 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2443 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2444 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2445 } 2446 2447 intel_de_rmw(dev_priv, reg, 0, set_bits); 2448 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2449 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2450 port_name(port)); 2451 } 2452 } 2453 2454 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2455 const struct intel_crtc_state *crtc_state) 2456 { 2457 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2458 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2459 enum port port = encoder->port; 2460 u32 val; 2461 2462 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)); 2463 val &= ~XELPDP_PORT_WIDTH_MASK; 2464 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2465 2466 val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK; 2467 if (intel_dp_is_uhbr(crtc_state)) 2468 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2469 else 2470 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2471 2472 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 2473 val |= XELPDP_PORT_REVERSAL; 2474 2475 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val); 2476 } 2477 2478 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2479 { 2480 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2481 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2482 u32 val; 2483 2484 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2485 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2486 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2487 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2488 } 2489 2490 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2491 struct intel_encoder *encoder, 2492 const struct intel_crtc_state *crtc_state, 2493 const struct drm_connector_state *conn_state) 2494 { 2495 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2496 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2497 2498 intel_dp_set_link_params(intel_dp, 2499 crtc_state->port_clock, 2500 crtc_state->lane_count); 2501 2502 /* 2503 * We only configure what the register value will be here. Actual 2504 * enabling happens during link training farther down. 2505 */ 2506 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2507 2508 /* 2509 * 1. Enable Power Wells 2510 * 2511 * This was handled at the beginning of intel_atomic_commit_tail(), 2512 * before we called down into this function. 2513 */ 2514 2515 /* 2. PMdemand was already set */ 2516 2517 /* 3. Select Thunderbolt */ 2518 mtl_port_buf_ctl_io_selection(encoder); 2519 2520 /* 4. Enable Panel Power if PPS is required */ 2521 intel_pps_on(intel_dp); 2522 2523 /* 5. Enable the port PLL */ 2524 intel_ddi_enable_clock(encoder, crtc_state); 2525 2526 /* 2527 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2528 * Transcoder. 2529 */ 2530 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2531 2532 /* 2533 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2534 */ 2535 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2536 2537 /* 2538 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2539 * Transport Select 2540 */ 2541 intel_ddi_config_transcoder_func(encoder, crtc_state); 2542 2543 /* 2544 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2545 */ 2546 intel_ddi_mso_configure(crtc_state); 2547 2548 if (!is_mst) 2549 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2550 2551 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2552 if (!is_mst) 2553 intel_dp_sink_enable_decompression(state, 2554 to_intel_connector(conn_state->connector), 2555 crtc_state); 2556 2557 /* 2558 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2559 * in the FEC_CONFIGURATION register to 1 before initiating link 2560 * training 2561 */ 2562 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2563 2564 intel_dp_check_frl_training(intel_dp); 2565 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2566 2567 /* 2568 * 6. The rest of the below are substeps under the bspec's "Enable and 2569 * Train Display Port" step. Note that steps that are specific to 2570 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2571 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2572 * us when active_mst_links==0, so any steps designated for "single 2573 * stream or multi-stream master transcoder" can just be performed 2574 * unconditionally here. 2575 * 2576 * mtl_ddi_prepare_link_retrain() that is called by 2577 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2578 * 6.i and 6.j 2579 * 2580 * 6.k Follow DisplayPort specification training sequence (see notes for 2581 * failure handling) 2582 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2583 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2584 * (timeout after 800 us) 2585 */ 2586 intel_dp_start_link_train(intel_dp, crtc_state); 2587 2588 /* 6.n Set DP_TP_CTL link training to Normal */ 2589 if (!is_trans_port_sync_mode(crtc_state)) 2590 intel_dp_stop_link_train(intel_dp, crtc_state); 2591 2592 /* 6.o Configure and enable FEC if needed */ 2593 intel_ddi_enable_fec(encoder, crtc_state); 2594 2595 if (!is_mst) 2596 intel_dsc_dp_pps_write(encoder, crtc_state); 2597 } 2598 2599 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2600 struct intel_encoder *encoder, 2601 const struct intel_crtc_state *crtc_state, 2602 const struct drm_connector_state *conn_state) 2603 { 2604 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2605 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2606 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2607 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2608 2609 intel_dp_set_link_params(intel_dp, 2610 crtc_state->port_clock, 2611 crtc_state->lane_count); 2612 2613 /* 2614 * We only configure what the register value will be here. Actual 2615 * enabling happens during link training farther down. 2616 */ 2617 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2618 2619 /* 2620 * 1. Enable Power Wells 2621 * 2622 * This was handled at the beginning of intel_atomic_commit_tail(), 2623 * before we called down into this function. 2624 */ 2625 2626 /* 2. Enable Panel Power if PPS is required */ 2627 intel_pps_on(intel_dp); 2628 2629 /* 2630 * 3. For non-TBT Type-C ports, set FIA lane count 2631 * (DFLEXDPSP.DPX4TXLATC) 2632 * 2633 * This was done before tgl_ddi_pre_enable_dp by 2634 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2635 */ 2636 2637 /* 2638 * 4. Enable the port PLL. 2639 * 2640 * The PLL enabling itself was already done before this function by 2641 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2642 * configure the PLL to port mapping here. 2643 */ 2644 intel_ddi_enable_clock(encoder, crtc_state); 2645 2646 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2647 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2648 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2649 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2650 dig_port->ddi_io_power_domain); 2651 } 2652 2653 /* 6. Program DP_MODE */ 2654 icl_program_mg_dp_mode(dig_port, crtc_state); 2655 2656 /* 2657 * 7. The rest of the below are substeps under the bspec's "Enable and 2658 * Train Display Port" step. Note that steps that are specific to 2659 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2660 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2661 * us when active_mst_links==0, so any steps designated for "single 2662 * stream or multi-stream master transcoder" can just be performed 2663 * unconditionally here. 2664 */ 2665 2666 /* 2667 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2668 * Transcoder. 2669 */ 2670 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2671 2672 if (HAS_DP20(dev_priv)) 2673 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2674 2675 /* 2676 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2677 * Transport Select 2678 */ 2679 intel_ddi_config_transcoder_func(encoder, crtc_state); 2680 2681 /* 2682 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2683 * selected 2684 * 2685 * This will be handled by the intel_dp_start_link_train() farther 2686 * down this function. 2687 */ 2688 2689 /* 7.e Configure voltage swing and related IO settings */ 2690 encoder->set_signal_levels(encoder, crtc_state); 2691 2692 /* 2693 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2694 * the used lanes of the DDI. 2695 */ 2696 intel_ddi_power_up_lanes(encoder, crtc_state); 2697 2698 /* 2699 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2700 */ 2701 intel_ddi_mso_configure(crtc_state); 2702 2703 if (!is_mst) 2704 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2705 2706 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2707 if (!is_mst) 2708 intel_dp_sink_enable_decompression(state, 2709 to_intel_connector(conn_state->connector), 2710 crtc_state); 2711 /* 2712 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2713 * in the FEC_CONFIGURATION register to 1 before initiating link 2714 * training 2715 */ 2716 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2717 2718 intel_dp_check_frl_training(intel_dp); 2719 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2720 2721 /* 2722 * 7.i Follow DisplayPort specification training sequence (see notes for 2723 * failure handling) 2724 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2725 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2726 * (timeout after 800 us) 2727 */ 2728 intel_dp_start_link_train(intel_dp, crtc_state); 2729 2730 /* 7.k Set DP_TP_CTL link training to Normal */ 2731 if (!is_trans_port_sync_mode(crtc_state)) 2732 intel_dp_stop_link_train(intel_dp, crtc_state); 2733 2734 /* 7.l Configure and enable FEC if needed */ 2735 intel_ddi_enable_fec(encoder, crtc_state); 2736 2737 if (!is_mst) 2738 intel_dsc_dp_pps_write(encoder, crtc_state); 2739 } 2740 2741 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2742 struct intel_encoder *encoder, 2743 const struct intel_crtc_state *crtc_state, 2744 const struct drm_connector_state *conn_state) 2745 { 2746 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2747 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2748 enum port port = encoder->port; 2749 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2750 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2751 2752 if (DISPLAY_VER(dev_priv) < 11) 2753 drm_WARN_ON(&dev_priv->drm, 2754 is_mst && (port == PORT_A || port == PORT_E)); 2755 else 2756 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2757 2758 intel_dp_set_link_params(intel_dp, 2759 crtc_state->port_clock, 2760 crtc_state->lane_count); 2761 2762 /* 2763 * We only configure what the register value will be here. Actual 2764 * enabling happens during link training farther down. 2765 */ 2766 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2767 2768 intel_pps_on(intel_dp); 2769 2770 intel_ddi_enable_clock(encoder, crtc_state); 2771 2772 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2773 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2774 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2775 dig_port->ddi_io_power_domain); 2776 } 2777 2778 icl_program_mg_dp_mode(dig_port, crtc_state); 2779 2780 if (has_buf_trans_select(dev_priv)) 2781 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2782 2783 encoder->set_signal_levels(encoder, crtc_state); 2784 2785 intel_ddi_power_up_lanes(encoder, crtc_state); 2786 2787 if (!is_mst) 2788 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2789 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2790 if (!is_mst) 2791 intel_dp_sink_enable_decompression(state, 2792 to_intel_connector(conn_state->connector), 2793 crtc_state); 2794 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2795 intel_dp_start_link_train(intel_dp, crtc_state); 2796 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2797 !is_trans_port_sync_mode(crtc_state)) 2798 intel_dp_stop_link_train(intel_dp, crtc_state); 2799 2800 intel_ddi_enable_fec(encoder, crtc_state); 2801 2802 if (!is_mst) { 2803 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2804 intel_dsc_dp_pps_write(encoder, crtc_state); 2805 } 2806 } 2807 2808 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2809 struct intel_encoder *encoder, 2810 const struct intel_crtc_state *crtc_state, 2811 const struct drm_connector_state *conn_state) 2812 { 2813 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2814 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2815 2816 if (HAS_DP20(dev_priv)) { 2817 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2818 crtc_state); 2819 if (crtc_state->has_panel_replay) 2820 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, 2821 DP_PANEL_REPLAY_ENABLE); 2822 } 2823 2824 if (DISPLAY_VER(dev_priv) >= 14) 2825 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2826 else if (DISPLAY_VER(dev_priv) >= 12) 2827 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2828 else 2829 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2830 2831 /* MST will call a setting of MSA after an allocating of Virtual Channel 2832 * from MST encoder pre_enable callback. 2833 */ 2834 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2835 intel_ddi_set_dp_msa(crtc_state, conn_state); 2836 } 2837 2838 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2839 struct intel_encoder *encoder, 2840 const struct intel_crtc_state *crtc_state, 2841 const struct drm_connector_state *conn_state) 2842 { 2843 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2844 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2845 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2846 2847 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2848 intel_ddi_enable_clock(encoder, crtc_state); 2849 2850 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2851 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2852 dig_port->ddi_io_power_domain); 2853 2854 icl_program_mg_dp_mode(dig_port, crtc_state); 2855 2856 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2857 2858 dig_port->set_infoframes(encoder, 2859 crtc_state->has_infoframe, 2860 crtc_state, conn_state); 2861 } 2862 2863 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2864 struct intel_encoder *encoder, 2865 const struct intel_crtc_state *crtc_state, 2866 const struct drm_connector_state *conn_state) 2867 { 2868 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2869 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2870 enum pipe pipe = crtc->pipe; 2871 2872 /* 2873 * When called from DP MST code: 2874 * - conn_state will be NULL 2875 * - encoder will be the main encoder (ie. mst->primary) 2876 * - the main connector associated with this port 2877 * won't be active or linked to a crtc 2878 * - crtc_state will be the state of the first stream to 2879 * be activated on this port, and it may not be the same 2880 * stream that will be deactivated last, but each stream 2881 * should have a state that is identical when it comes to 2882 * the DP link parameteres 2883 */ 2884 2885 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2886 2887 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2888 2889 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2890 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2891 conn_state); 2892 } else { 2893 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2894 2895 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2896 conn_state); 2897 2898 /* FIXME precompute everything properly */ 2899 /* FIXME how do we turn infoframes off again? */ 2900 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 2901 dig_port->set_infoframes(encoder, 2902 crtc_state->has_infoframe, 2903 crtc_state, conn_state); 2904 } 2905 } 2906 2907 static void 2908 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 2909 { 2910 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2911 enum port port = encoder->port; 2912 i915_reg_t reg; 2913 u32 clr_bits, wait_bits; 2914 2915 if (DISPLAY_VER(dev_priv) >= 20) { 2916 reg = DDI_BUF_CTL(port); 2917 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2918 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2919 } else { 2920 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2921 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2922 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2923 } 2924 2925 intel_de_rmw(dev_priv, reg, clr_bits, 0); 2926 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 2927 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 2928 port_name(port)); 2929 } 2930 2931 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 2932 const struct intel_crtc_state *crtc_state) 2933 { 2934 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2935 enum port port = encoder->port; 2936 u32 val; 2937 2938 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 2939 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2940 if (val & DDI_BUF_CTL_ENABLE) { 2941 val &= ~DDI_BUF_CTL_ENABLE; 2942 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2943 2944 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 2945 mtl_wait_ddi_buf_idle(dev_priv, port); 2946 } 2947 2948 /* 3.d Disable D2D Link */ 2949 mtl_ddi_disable_d2d_link(encoder); 2950 2951 /* 3.e Disable DP_TP_CTL */ 2952 if (intel_crtc_has_dp_encoder(crtc_state)) { 2953 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2954 DP_TP_CTL_ENABLE, 0); 2955 } 2956 } 2957 2958 static void disable_ddi_buf(struct intel_encoder *encoder, 2959 const struct intel_crtc_state *crtc_state) 2960 { 2961 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2962 enum port port = encoder->port; 2963 bool wait = false; 2964 u32 val; 2965 2966 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2967 if (val & DDI_BUF_CTL_ENABLE) { 2968 val &= ~DDI_BUF_CTL_ENABLE; 2969 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2970 wait = true; 2971 } 2972 2973 if (intel_crtc_has_dp_encoder(crtc_state)) 2974 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2975 DP_TP_CTL_ENABLE, 0); 2976 2977 intel_ddi_disable_fec(encoder, crtc_state); 2978 2979 if (wait) 2980 intel_wait_ddi_buf_idle(dev_priv, port); 2981 } 2982 2983 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2984 const struct intel_crtc_state *crtc_state) 2985 { 2986 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2987 2988 if (DISPLAY_VER(dev_priv) >= 14) { 2989 mtl_disable_ddi_buf(encoder, crtc_state); 2990 2991 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 2992 intel_ddi_disable_fec(encoder, crtc_state); 2993 } else { 2994 disable_ddi_buf(encoder, crtc_state); 2995 } 2996 2997 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2998 } 2999 3000 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3001 struct intel_encoder *encoder, 3002 const struct intel_crtc_state *old_crtc_state, 3003 const struct drm_connector_state *old_conn_state) 3004 { 3005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3006 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3007 struct intel_dp *intel_dp = &dig_port->dp; 3008 intel_wakeref_t wakeref; 3009 bool is_mst = intel_crtc_has_type(old_crtc_state, 3010 INTEL_OUTPUT_DP_MST); 3011 3012 if (!is_mst) 3013 intel_dp_set_infoframes(encoder, false, 3014 old_crtc_state, old_conn_state); 3015 3016 /* 3017 * Power down sink before disabling the port, otherwise we end 3018 * up getting interrupts from the sink on detecting link loss. 3019 */ 3020 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3021 3022 if (DISPLAY_VER(dev_priv) >= 12) { 3023 if (is_mst) { 3024 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3025 3026 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 3027 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3028 0); 3029 } 3030 } else { 3031 if (!is_mst) 3032 intel_ddi_disable_transcoder_clock(old_crtc_state); 3033 } 3034 3035 intel_disable_ddi_buf(encoder, old_crtc_state); 3036 3037 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3038 3039 /* 3040 * From TGL spec: "If single stream or multi-stream master transcoder: 3041 * Configure Transcoder Clock select to direct no clock to the 3042 * transcoder" 3043 */ 3044 if (DISPLAY_VER(dev_priv) >= 12) 3045 intel_ddi_disable_transcoder_clock(old_crtc_state); 3046 3047 intel_pps_vdd_on(intel_dp); 3048 intel_pps_off(intel_dp); 3049 3050 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3051 3052 if (wakeref) 3053 intel_display_power_put(dev_priv, 3054 dig_port->ddi_io_power_domain, 3055 wakeref); 3056 3057 intel_ddi_disable_clock(encoder); 3058 3059 /* De-select Thunderbolt */ 3060 if (DISPLAY_VER(dev_priv) >= 14) 3061 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3062 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3063 } 3064 3065 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3066 struct intel_encoder *encoder, 3067 const struct intel_crtc_state *old_crtc_state, 3068 const struct drm_connector_state *old_conn_state) 3069 { 3070 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3071 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3072 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3073 intel_wakeref_t wakeref; 3074 3075 dig_port->set_infoframes(encoder, false, 3076 old_crtc_state, old_conn_state); 3077 3078 if (DISPLAY_VER(dev_priv) < 12) 3079 intel_ddi_disable_transcoder_clock(old_crtc_state); 3080 3081 intel_disable_ddi_buf(encoder, old_crtc_state); 3082 3083 if (DISPLAY_VER(dev_priv) >= 12) 3084 intel_ddi_disable_transcoder_clock(old_crtc_state); 3085 3086 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3087 if (wakeref) 3088 intel_display_power_put(dev_priv, 3089 dig_port->ddi_io_power_domain, 3090 wakeref); 3091 3092 intel_ddi_disable_clock(encoder); 3093 3094 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3095 } 3096 3097 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3098 struct intel_encoder *encoder, 3099 const struct intel_crtc_state *old_crtc_state, 3100 const struct drm_connector_state *old_conn_state) 3101 { 3102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3103 struct intel_crtc *slave_crtc; 3104 3105 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 3106 intel_crtc_vblank_off(old_crtc_state); 3107 3108 intel_disable_transcoder(old_crtc_state); 3109 3110 intel_ddi_disable_transcoder_func(old_crtc_state); 3111 3112 intel_dsc_disable(old_crtc_state); 3113 3114 if (DISPLAY_VER(dev_priv) >= 9) 3115 skl_scaler_disable(old_crtc_state); 3116 else 3117 ilk_pfit_disable(old_crtc_state); 3118 } 3119 3120 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, 3121 intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) { 3122 const struct intel_crtc_state *old_slave_crtc_state = 3123 intel_atomic_get_old_crtc_state(state, slave_crtc); 3124 3125 intel_crtc_vblank_off(old_slave_crtc_state); 3126 3127 intel_dsc_disable(old_slave_crtc_state); 3128 skl_scaler_disable(old_slave_crtc_state); 3129 } 3130 3131 /* 3132 * When called from DP MST code: 3133 * - old_conn_state will be NULL 3134 * - encoder will be the main encoder (ie. mst->primary) 3135 * - the main connector associated with this port 3136 * won't be active or linked to a crtc 3137 * - old_crtc_state will be the state of the last stream to 3138 * be deactivated on this port, and it may not be the same 3139 * stream that was activated last, but each stream 3140 * should have a state that is identical when it comes to 3141 * the DP link parameteres 3142 */ 3143 3144 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3145 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3146 old_conn_state); 3147 else 3148 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3149 old_conn_state); 3150 } 3151 3152 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3153 struct intel_encoder *encoder, 3154 const struct intel_crtc_state *old_crtc_state, 3155 const struct drm_connector_state *old_conn_state) 3156 { 3157 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3158 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3159 enum phy phy = intel_port_to_phy(i915, encoder->port); 3160 bool is_tc_port = intel_phy_is_tc(i915, phy); 3161 3162 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3163 3164 if (is_tc_port) 3165 intel_tc_port_put_link(dig_port); 3166 } 3167 3168 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3169 struct intel_encoder *encoder, 3170 const struct intel_crtc_state *crtc_state) 3171 { 3172 const struct drm_connector_state *conn_state; 3173 struct drm_connector *conn; 3174 int i; 3175 3176 if (!crtc_state->sync_mode_slaves_mask) 3177 return; 3178 3179 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3180 struct intel_encoder *slave_encoder = 3181 to_intel_encoder(conn_state->best_encoder); 3182 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3183 const struct intel_crtc_state *slave_crtc_state; 3184 3185 if (!slave_crtc) 3186 continue; 3187 3188 slave_crtc_state = 3189 intel_atomic_get_new_crtc_state(state, slave_crtc); 3190 3191 if (slave_crtc_state->master_transcoder != 3192 crtc_state->cpu_transcoder) 3193 continue; 3194 3195 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3196 slave_crtc_state); 3197 } 3198 3199 usleep_range(200, 400); 3200 3201 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3202 crtc_state); 3203 } 3204 3205 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3206 struct intel_encoder *encoder, 3207 const struct intel_crtc_state *crtc_state, 3208 const struct drm_connector_state *conn_state) 3209 { 3210 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3211 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3212 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3213 enum port port = encoder->port; 3214 3215 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3216 intel_dp_stop_link_train(intel_dp, crtc_state); 3217 3218 drm_connector_update_privacy_screen(conn_state); 3219 intel_edp_backlight_on(crtc_state, conn_state); 3220 3221 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3222 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3223 3224 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3225 } 3226 3227 /* FIXME bad home for this function */ 3228 i915_reg_t hsw_chicken_trans_reg(struct drm_i915_private *i915, 3229 enum transcoder cpu_transcoder) 3230 { 3231 return DISPLAY_VER(i915) >= 14 ? 3232 MTL_CHICKEN_TRANS(cpu_transcoder) : 3233 CHICKEN_TRANS(cpu_transcoder); 3234 } 3235 3236 static i915_reg_t 3237 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3238 enum port port) 3239 { 3240 static const enum transcoder trans[] = { 3241 [PORT_A] = TRANSCODER_EDP, 3242 [PORT_B] = TRANSCODER_A, 3243 [PORT_C] = TRANSCODER_B, 3244 [PORT_D] = TRANSCODER_C, 3245 [PORT_E] = TRANSCODER_A, 3246 }; 3247 3248 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3249 3250 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3251 port = PORT_A; 3252 3253 return CHICKEN_TRANS(trans[port]); 3254 } 3255 3256 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3257 struct intel_encoder *encoder, 3258 const struct intel_crtc_state *crtc_state, 3259 const struct drm_connector_state *conn_state) 3260 { 3261 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3262 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3263 struct drm_connector *connector = conn_state->connector; 3264 enum port port = encoder->port; 3265 enum phy phy = intel_port_to_phy(dev_priv, port); 3266 u32 buf_ctl; 3267 3268 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3269 crtc_state->hdmi_high_tmds_clock_ratio, 3270 crtc_state->hdmi_scrambling)) 3271 drm_dbg_kms(&dev_priv->drm, 3272 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3273 connector->base.id, connector->name); 3274 3275 if (has_buf_trans_select(dev_priv)) 3276 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3277 3278 /* e. Enable D2D Link for C10/C20 Phy */ 3279 if (DISPLAY_VER(dev_priv) >= 14) 3280 mtl_ddi_enable_d2d(encoder); 3281 3282 encoder->set_signal_levels(encoder, crtc_state); 3283 3284 /* Display WA #1143: skl,kbl,cfl */ 3285 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3286 /* 3287 * For some reason these chicken bits have been 3288 * stuffed into a transcoder register, event though 3289 * the bits affect a specific DDI port rather than 3290 * a specific transcoder. 3291 */ 3292 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3293 u32 val; 3294 3295 val = intel_de_read(dev_priv, reg); 3296 3297 if (port == PORT_E) 3298 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3299 DDIE_TRAINING_OVERRIDE_VALUE; 3300 else 3301 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3302 DDI_TRAINING_OVERRIDE_VALUE; 3303 3304 intel_de_write(dev_priv, reg, val); 3305 intel_de_posting_read(dev_priv, reg); 3306 3307 udelay(1); 3308 3309 if (port == PORT_E) 3310 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3311 DDIE_TRAINING_OVERRIDE_VALUE); 3312 else 3313 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3314 DDI_TRAINING_OVERRIDE_VALUE); 3315 3316 intel_de_write(dev_priv, reg, val); 3317 } 3318 3319 intel_ddi_power_up_lanes(encoder, crtc_state); 3320 3321 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3322 * are ignored so nothing special needs to be done besides 3323 * enabling the port. 3324 * 3325 * On ADL_P the PHY link rate and lane count must be programmed but 3326 * these are both 0 for HDMI. 3327 * 3328 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3329 * is filled with lane count, already set in the crtc_state. 3330 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3331 */ 3332 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 3333 if (DISPLAY_VER(dev_priv) >= 14) { 3334 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3335 u32 port_buf = 0; 3336 3337 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3338 3339 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 3340 port_buf |= XELPDP_PORT_REVERSAL; 3341 3342 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3343 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3344 3345 buf_ctl |= DDI_PORT_WIDTH(lane_count); 3346 3347 if (DISPLAY_VER(dev_priv) >= 20) 3348 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3349 } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) { 3350 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3351 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3352 } 3353 3354 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3355 3356 intel_wait_ddi_buf_active(dev_priv, port); 3357 } 3358 3359 static void intel_enable_ddi(struct intel_atomic_state *state, 3360 struct intel_encoder *encoder, 3361 const struct intel_crtc_state *crtc_state, 3362 const struct drm_connector_state *conn_state) 3363 { 3364 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3365 3366 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 3367 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3368 3369 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3370 intel_audio_sdp_split_update(crtc_state); 3371 3372 intel_enable_transcoder(crtc_state); 3373 3374 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3375 3376 intel_crtc_vblank_on(crtc_state); 3377 3378 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3379 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3380 else 3381 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3382 3383 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3384 3385 } 3386 3387 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3388 struct intel_encoder *encoder, 3389 const struct intel_crtc_state *old_crtc_state, 3390 const struct drm_connector_state *old_conn_state) 3391 { 3392 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3393 struct intel_connector *connector = 3394 to_intel_connector(old_conn_state->connector); 3395 3396 intel_dp->link_trained = false; 3397 3398 intel_psr_disable(intel_dp, old_crtc_state); 3399 intel_edp_backlight_off(old_conn_state); 3400 /* Disable the decompression in DP Sink */ 3401 intel_dp_sink_disable_decompression(state, 3402 connector, old_crtc_state); 3403 /* Disable Ignore_MSA bit in DP Sink */ 3404 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3405 false); 3406 } 3407 3408 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3409 struct intel_encoder *encoder, 3410 const struct intel_crtc_state *old_crtc_state, 3411 const struct drm_connector_state *old_conn_state) 3412 { 3413 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3414 struct drm_connector *connector = old_conn_state->connector; 3415 3416 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3417 false, false)) 3418 drm_dbg_kms(&i915->drm, 3419 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3420 connector->base.id, connector->name); 3421 } 3422 3423 static void intel_disable_ddi(struct intel_atomic_state *state, 3424 struct intel_encoder *encoder, 3425 const struct intel_crtc_state *old_crtc_state, 3426 const struct drm_connector_state *old_conn_state) 3427 { 3428 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3429 3430 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3431 3432 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3433 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3434 old_conn_state); 3435 else 3436 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3437 old_conn_state); 3438 } 3439 3440 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3441 struct intel_encoder *encoder, 3442 const struct intel_crtc_state *crtc_state, 3443 const struct drm_connector_state *conn_state) 3444 { 3445 intel_ddi_set_dp_msa(crtc_state, conn_state); 3446 3447 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3448 3449 intel_backlight_update(state, encoder, crtc_state, conn_state); 3450 drm_connector_update_privacy_screen(conn_state); 3451 } 3452 3453 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3454 struct intel_encoder *encoder, 3455 const struct intel_crtc_state *crtc_state, 3456 const struct drm_connector_state *conn_state) 3457 { 3458 3459 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3460 !intel_encoder_is_mst(encoder)) 3461 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3462 conn_state); 3463 3464 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3465 } 3466 3467 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3468 struct intel_encoder *encoder, 3469 struct intel_crtc *crtc) 3470 { 3471 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3472 struct intel_crtc_state *crtc_state = 3473 intel_atomic_get_new_crtc_state(state, crtc); 3474 struct intel_crtc *slave_crtc; 3475 enum phy phy = intel_port_to_phy(i915, encoder->port); 3476 3477 /* FIXME: Add MTL pll_mgr */ 3478 if (DISPLAY_VER(i915) >= 14 || !intel_phy_is_tc(i915, phy)) 3479 return; 3480 3481 intel_update_active_dpll(state, crtc, encoder); 3482 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, 3483 intel_crtc_bigjoiner_slave_pipes(crtc_state)) 3484 intel_update_active_dpll(state, slave_crtc, encoder); 3485 } 3486 3487 static void 3488 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3489 struct intel_encoder *encoder, 3490 const struct intel_crtc_state *crtc_state, 3491 const struct drm_connector_state *conn_state) 3492 { 3493 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3494 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3495 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3496 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3497 3498 if (is_tc_port) { 3499 struct intel_crtc *master_crtc = 3500 to_intel_crtc(crtc_state->uapi.crtc); 3501 3502 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3503 intel_ddi_update_active_dpll(state, encoder, master_crtc); 3504 } 3505 3506 main_link_aux_power_domain_get(dig_port, crtc_state); 3507 3508 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3509 /* 3510 * Program the lane count for static/dynamic connections on 3511 * Type-C ports. Skip this step for TBT. 3512 */ 3513 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3514 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3515 bxt_ddi_phy_set_lane_optim_mask(encoder, 3516 crtc_state->lane_lat_optim_mask); 3517 } 3518 3519 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3520 { 3521 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3522 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 3523 int ln; 3524 3525 for (ln = 0; ln < 2; ln++) 3526 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3527 } 3528 3529 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3530 const struct intel_crtc_state *crtc_state) 3531 { 3532 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3533 struct intel_encoder *encoder = &dig_port->base; 3534 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3535 enum port port = encoder->port; 3536 u32 dp_tp_ctl; 3537 3538 /* 3539 * TODO: To train with only a different voltage swing entry is not 3540 * necessary disable and enable port 3541 */ 3542 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3543 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3544 mtl_disable_ddi_buf(encoder, crtc_state); 3545 3546 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3547 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3548 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3549 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3550 } else { 3551 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3552 if (crtc_state->enhanced_framing) 3553 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3554 } 3555 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3556 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3557 3558 /* 6.f Enable D2D Link */ 3559 mtl_ddi_enable_d2d(encoder); 3560 3561 /* 6.g Configure voltage swing and related IO settings */ 3562 encoder->set_signal_levels(encoder, crtc_state); 3563 3564 /* 6.h Configure PORT_BUF_CTL1 */ 3565 mtl_port_buf_ctl_program(encoder, crtc_state); 3566 3567 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3568 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3569 if (DISPLAY_VER(dev_priv) >= 20) 3570 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3571 3572 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3573 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3574 3575 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3576 intel_wait_ddi_buf_active(dev_priv, port); 3577 } 3578 3579 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3580 const struct intel_crtc_state *crtc_state) 3581 { 3582 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3583 struct intel_encoder *encoder = &dig_port->base; 3584 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3585 enum port port = encoder->port; 3586 u32 dp_tp_ctl, ddi_buf_ctl; 3587 bool wait = false; 3588 3589 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3590 3591 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3592 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3593 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3594 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3595 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3596 wait = true; 3597 } 3598 3599 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3600 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3601 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3602 3603 if (wait) 3604 intel_wait_ddi_buf_idle(dev_priv, port); 3605 } 3606 3607 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3608 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3609 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3610 } else { 3611 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3612 if (crtc_state->enhanced_framing) 3613 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3614 } 3615 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3616 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3617 3618 if (IS_ALDERLAKE_P(dev_priv) && 3619 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3620 adlp_tbt_to_dp_alt_switch_wa(encoder); 3621 3622 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3623 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3624 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3625 3626 intel_wait_ddi_buf_active(dev_priv, port); 3627 } 3628 3629 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3630 const struct intel_crtc_state *crtc_state, 3631 u8 dp_train_pat) 3632 { 3633 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3634 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3635 u32 temp; 3636 3637 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3638 3639 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3640 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3641 case DP_TRAINING_PATTERN_DISABLE: 3642 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3643 break; 3644 case DP_TRAINING_PATTERN_1: 3645 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3646 break; 3647 case DP_TRAINING_PATTERN_2: 3648 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3649 break; 3650 case DP_TRAINING_PATTERN_3: 3651 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3652 break; 3653 case DP_TRAINING_PATTERN_4: 3654 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3655 break; 3656 } 3657 3658 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3659 } 3660 3661 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3662 const struct intel_crtc_state *crtc_state) 3663 { 3664 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3665 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3666 enum port port = encoder->port; 3667 3668 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3669 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3670 3671 /* 3672 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3673 * reason we need to set idle transmission mode is to work around a HW 3674 * issue where we enable the pipe while not in idle link-training mode. 3675 * In this case there is requirement to wait for a minimum number of 3676 * idle patterns to be sent. 3677 */ 3678 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3679 return; 3680 3681 if (intel_de_wait_for_set(dev_priv, 3682 dp_tp_status_reg(encoder, crtc_state), 3683 DP_TP_STATUS_IDLE_DONE, 1)) 3684 drm_err(&dev_priv->drm, 3685 "Timed out waiting for DP idle patterns\n"); 3686 } 3687 3688 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3689 enum transcoder cpu_transcoder) 3690 { 3691 if (cpu_transcoder == TRANSCODER_EDP) 3692 return false; 3693 3694 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3695 return false; 3696 3697 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3698 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3699 } 3700 3701 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3702 { 3703 if (crtc_state->port_clock > 594000) 3704 return 2; 3705 else 3706 return 0; 3707 } 3708 3709 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3710 { 3711 if (crtc_state->port_clock > 594000) 3712 return 3; 3713 else 3714 return 0; 3715 } 3716 3717 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3718 { 3719 if (crtc_state->port_clock > 594000) 3720 return 1; 3721 else 3722 return 0; 3723 } 3724 3725 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3726 { 3727 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3728 3729 if (DISPLAY_VER(dev_priv) >= 14) 3730 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3731 else if (DISPLAY_VER(dev_priv) >= 12) 3732 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3733 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3734 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3735 else if (DISPLAY_VER(dev_priv) >= 11) 3736 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3737 } 3738 3739 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3740 enum transcoder cpu_transcoder) 3741 { 3742 u32 master_select; 3743 3744 if (DISPLAY_VER(dev_priv) >= 11) { 3745 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3746 3747 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3748 return INVALID_TRANSCODER; 3749 3750 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3751 } else { 3752 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3753 3754 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3755 return INVALID_TRANSCODER; 3756 3757 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3758 } 3759 3760 if (master_select == 0) 3761 return TRANSCODER_EDP; 3762 else 3763 return master_select - 1; 3764 } 3765 3766 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3767 { 3768 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3769 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3770 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3771 enum transcoder cpu_transcoder; 3772 3773 crtc_state->master_transcoder = 3774 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3775 3776 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3777 enum intel_display_power_domain power_domain; 3778 intel_wakeref_t trans_wakeref; 3779 3780 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3781 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3782 power_domain); 3783 3784 if (!trans_wakeref) 3785 continue; 3786 3787 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3788 crtc_state->cpu_transcoder) 3789 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3790 3791 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3792 } 3793 3794 drm_WARN_ON(&dev_priv->drm, 3795 crtc_state->master_transcoder != INVALID_TRANSCODER && 3796 crtc_state->sync_mode_slaves_mask); 3797 } 3798 3799 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3800 struct intel_crtc_state *pipe_config) 3801 { 3802 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3803 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3804 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3805 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3806 u32 temp, flags = 0; 3807 3808 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3809 if (temp & TRANS_DDI_PHSYNC) 3810 flags |= DRM_MODE_FLAG_PHSYNC; 3811 else 3812 flags |= DRM_MODE_FLAG_NHSYNC; 3813 if (temp & TRANS_DDI_PVSYNC) 3814 flags |= DRM_MODE_FLAG_PVSYNC; 3815 else 3816 flags |= DRM_MODE_FLAG_NVSYNC; 3817 3818 pipe_config->hw.adjusted_mode.flags |= flags; 3819 3820 switch (temp & TRANS_DDI_BPC_MASK) { 3821 case TRANS_DDI_BPC_6: 3822 pipe_config->pipe_bpp = 18; 3823 break; 3824 case TRANS_DDI_BPC_8: 3825 pipe_config->pipe_bpp = 24; 3826 break; 3827 case TRANS_DDI_BPC_10: 3828 pipe_config->pipe_bpp = 30; 3829 break; 3830 case TRANS_DDI_BPC_12: 3831 pipe_config->pipe_bpp = 36; 3832 break; 3833 default: 3834 break; 3835 } 3836 3837 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3838 case TRANS_DDI_MODE_SELECT_HDMI: 3839 pipe_config->has_hdmi_sink = true; 3840 3841 pipe_config->infoframes.enable |= 3842 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3843 3844 if (pipe_config->infoframes.enable) 3845 pipe_config->has_infoframe = true; 3846 3847 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3848 pipe_config->hdmi_scrambling = true; 3849 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3850 pipe_config->hdmi_high_tmds_clock_ratio = true; 3851 fallthrough; 3852 case TRANS_DDI_MODE_SELECT_DVI: 3853 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3854 if (DISPLAY_VER(dev_priv) >= 14) 3855 pipe_config->lane_count = 3856 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3857 else 3858 pipe_config->lane_count = 4; 3859 break; 3860 case TRANS_DDI_MODE_SELECT_DP_SST: 3861 if (encoder->type == INTEL_OUTPUT_EDP) 3862 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3863 else 3864 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3865 pipe_config->lane_count = 3866 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3867 3868 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3869 &pipe_config->dp_m_n); 3870 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3871 &pipe_config->dp_m2_n2); 3872 3873 pipe_config->enhanced_framing = 3874 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3875 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3876 3877 if (DISPLAY_VER(dev_priv) >= 11) 3878 pipe_config->fec_enable = 3879 intel_de_read(dev_priv, 3880 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3881 3882 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3883 pipe_config->infoframes.enable |= 3884 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3885 else 3886 pipe_config->infoframes.enable |= 3887 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3888 break; 3889 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3890 if (!HAS_DP20(dev_priv)) { 3891 /* FDI */ 3892 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3893 pipe_config->enhanced_framing = 3894 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3895 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3896 break; 3897 } 3898 fallthrough; /* 128b/132b */ 3899 case TRANS_DDI_MODE_SELECT_DP_MST: 3900 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3901 pipe_config->lane_count = 3902 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3903 3904 if (DISPLAY_VER(dev_priv) >= 12) 3905 pipe_config->mst_master_transcoder = 3906 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3907 3908 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3909 &pipe_config->dp_m_n); 3910 3911 if (DISPLAY_VER(dev_priv) >= 11) 3912 pipe_config->fec_enable = 3913 intel_de_read(dev_priv, 3914 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3915 3916 pipe_config->infoframes.enable |= 3917 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3918 break; 3919 default: 3920 break; 3921 } 3922 } 3923 3924 static void intel_ddi_get_config(struct intel_encoder *encoder, 3925 struct intel_crtc_state *pipe_config) 3926 { 3927 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3928 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3929 3930 /* XXX: DSI transcoder paranoia */ 3931 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3932 return; 3933 3934 intel_ddi_read_func_ctl(encoder, pipe_config); 3935 3936 intel_ddi_mso_get_config(encoder, pipe_config); 3937 3938 pipe_config->has_audio = 3939 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3940 3941 if (encoder->type == INTEL_OUTPUT_EDP) 3942 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3943 3944 ddi_dotclock_get(pipe_config); 3945 3946 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3947 pipe_config->lane_lat_optim_mask = 3948 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3949 3950 intel_ddi_compute_min_voltage_level(pipe_config); 3951 3952 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3953 3954 intel_read_infoframe(encoder, pipe_config, 3955 HDMI_INFOFRAME_TYPE_AVI, 3956 &pipe_config->infoframes.avi); 3957 intel_read_infoframe(encoder, pipe_config, 3958 HDMI_INFOFRAME_TYPE_SPD, 3959 &pipe_config->infoframes.spd); 3960 intel_read_infoframe(encoder, pipe_config, 3961 HDMI_INFOFRAME_TYPE_VENDOR, 3962 &pipe_config->infoframes.hdmi); 3963 intel_read_infoframe(encoder, pipe_config, 3964 HDMI_INFOFRAME_TYPE_DRM, 3965 &pipe_config->infoframes.drm); 3966 3967 if (DISPLAY_VER(dev_priv) >= 8) 3968 bdw_get_trans_port_sync_config(pipe_config); 3969 3970 intel_psr_get_config(encoder, pipe_config); 3971 3972 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3973 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3974 3975 intel_audio_codec_get_config(encoder, pipe_config); 3976 } 3977 3978 void intel_ddi_get_clock(struct intel_encoder *encoder, 3979 struct intel_crtc_state *crtc_state, 3980 struct intel_shared_dpll *pll) 3981 { 3982 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3983 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3984 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3985 bool pll_active; 3986 3987 if (drm_WARN_ON(&i915->drm, !pll)) 3988 return; 3989 3990 port_dpll->pll = pll; 3991 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3992 drm_WARN_ON(&i915->drm, !pll_active); 3993 3994 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3995 3996 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3997 &crtc_state->dpll_hw_state); 3998 } 3999 4000 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4001 struct intel_crtc_state *crtc_state) 4002 { 4003 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4004 4005 if (intel_tc_port_in_tbt_alt_mode(dig_port)) { 4006 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4007 } else { 4008 intel_cx0pll_readout_hw_state(encoder, &crtc_state->cx0pll_state); 4009 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->cx0pll_state); 4010 } 4011 4012 intel_ddi_get_config(encoder, crtc_state); 4013 } 4014 4015 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4016 struct intel_crtc_state *crtc_state) 4017 { 4018 intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); 4019 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); 4020 4021 intel_ddi_get_config(encoder, crtc_state); 4022 } 4023 4024 static void adls_ddi_get_config(struct intel_encoder *encoder, 4025 struct intel_crtc_state *crtc_state) 4026 { 4027 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4028 intel_ddi_get_config(encoder, crtc_state); 4029 } 4030 4031 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4032 struct intel_crtc_state *crtc_state) 4033 { 4034 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4035 intel_ddi_get_config(encoder, crtc_state); 4036 } 4037 4038 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4039 struct intel_crtc_state *crtc_state) 4040 { 4041 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4042 intel_ddi_get_config(encoder, crtc_state); 4043 } 4044 4045 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4046 struct intel_crtc_state *crtc_state) 4047 { 4048 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4049 intel_ddi_get_config(encoder, crtc_state); 4050 } 4051 4052 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4053 { 4054 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4055 } 4056 4057 static enum icl_port_dpll_id 4058 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4059 const struct intel_crtc_state *crtc_state) 4060 { 4061 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4062 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4063 4064 if (drm_WARN_ON(&i915->drm, !pll)) 4065 return ICL_PORT_DPLL_DEFAULT; 4066 4067 if (icl_ddi_tc_pll_is_tbt(pll)) 4068 return ICL_PORT_DPLL_DEFAULT; 4069 else 4070 return ICL_PORT_DPLL_MG_PHY; 4071 } 4072 4073 enum icl_port_dpll_id 4074 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4075 const struct intel_crtc_state *crtc_state) 4076 { 4077 if (!encoder->port_pll_type) 4078 return ICL_PORT_DPLL_DEFAULT; 4079 4080 return encoder->port_pll_type(encoder, crtc_state); 4081 } 4082 4083 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4084 struct intel_crtc_state *crtc_state, 4085 struct intel_shared_dpll *pll) 4086 { 4087 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4088 enum icl_port_dpll_id port_dpll_id; 4089 struct icl_port_dpll *port_dpll; 4090 bool pll_active; 4091 4092 if (drm_WARN_ON(&i915->drm, !pll)) 4093 return; 4094 4095 if (icl_ddi_tc_pll_is_tbt(pll)) 4096 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4097 else 4098 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4099 4100 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4101 4102 port_dpll->pll = pll; 4103 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4104 drm_WARN_ON(&i915->drm, !pll_active); 4105 4106 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4107 4108 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4109 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4110 else 4111 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4112 &crtc_state->dpll_hw_state); 4113 } 4114 4115 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4116 struct intel_crtc_state *crtc_state) 4117 { 4118 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4119 intel_ddi_get_config(encoder, crtc_state); 4120 } 4121 4122 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4123 struct intel_crtc_state *crtc_state) 4124 { 4125 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4126 intel_ddi_get_config(encoder, crtc_state); 4127 } 4128 4129 static void skl_ddi_get_config(struct intel_encoder *encoder, 4130 struct intel_crtc_state *crtc_state) 4131 { 4132 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4133 intel_ddi_get_config(encoder, crtc_state); 4134 } 4135 4136 void hsw_ddi_get_config(struct intel_encoder *encoder, 4137 struct intel_crtc_state *crtc_state) 4138 { 4139 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4140 intel_ddi_get_config(encoder, crtc_state); 4141 } 4142 4143 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4144 const struct intel_crtc_state *crtc_state) 4145 { 4146 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4147 enum phy phy = intel_port_to_phy(i915, encoder->port); 4148 4149 if (intel_phy_is_tc(i915, phy)) 4150 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4151 crtc_state); 4152 4153 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) 4154 intel_dp_sync_state(encoder, crtc_state); 4155 } 4156 4157 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4158 struct intel_crtc_state *crtc_state) 4159 { 4160 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4161 enum phy phy = intel_port_to_phy(i915, encoder->port); 4162 bool fastset = true; 4163 4164 if (intel_phy_is_tc(i915, phy)) { 4165 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4166 encoder->base.base.id, encoder->base.name); 4167 crtc_state->uapi.mode_changed = true; 4168 fastset = false; 4169 } 4170 4171 if (intel_crtc_has_dp_encoder(crtc_state) && 4172 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4173 fastset = false; 4174 4175 return fastset; 4176 } 4177 4178 static enum intel_output_type 4179 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4180 struct intel_crtc_state *crtc_state, 4181 struct drm_connector_state *conn_state) 4182 { 4183 switch (conn_state->connector->connector_type) { 4184 case DRM_MODE_CONNECTOR_HDMIA: 4185 return INTEL_OUTPUT_HDMI; 4186 case DRM_MODE_CONNECTOR_eDP: 4187 return INTEL_OUTPUT_EDP; 4188 case DRM_MODE_CONNECTOR_DisplayPort: 4189 return INTEL_OUTPUT_DP; 4190 default: 4191 MISSING_CASE(conn_state->connector->connector_type); 4192 return INTEL_OUTPUT_UNUSED; 4193 } 4194 } 4195 4196 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4197 struct intel_crtc_state *pipe_config, 4198 struct drm_connector_state *conn_state) 4199 { 4200 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4201 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4202 enum port port = encoder->port; 4203 int ret; 4204 4205 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4206 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4207 4208 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4209 pipe_config->has_hdmi_sink = 4210 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4211 4212 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4213 } else { 4214 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4215 } 4216 4217 if (ret) 4218 return ret; 4219 4220 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4221 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4222 pipe_config->pch_pfit.force_thru = 4223 pipe_config->pch_pfit.enabled || 4224 pipe_config->crc_enabled; 4225 4226 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4227 pipe_config->lane_lat_optim_mask = 4228 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4229 4230 intel_ddi_compute_min_voltage_level(pipe_config); 4231 4232 return 0; 4233 } 4234 4235 static bool mode_equal(const struct drm_display_mode *mode1, 4236 const struct drm_display_mode *mode2) 4237 { 4238 return drm_mode_match(mode1, mode2, 4239 DRM_MODE_MATCH_TIMINGS | 4240 DRM_MODE_MATCH_FLAGS | 4241 DRM_MODE_MATCH_3D_FLAGS) && 4242 mode1->clock == mode2->clock; /* we want an exact match */ 4243 } 4244 4245 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4246 const struct intel_link_m_n *m_n_2) 4247 { 4248 return m_n_1->tu == m_n_2->tu && 4249 m_n_1->data_m == m_n_2->data_m && 4250 m_n_1->data_n == m_n_2->data_n && 4251 m_n_1->link_m == m_n_2->link_m && 4252 m_n_1->link_n == m_n_2->link_n; 4253 } 4254 4255 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4256 const struct intel_crtc_state *crtc_state2) 4257 { 4258 return crtc_state1->hw.active && crtc_state2->hw.active && 4259 crtc_state1->output_types == crtc_state2->output_types && 4260 crtc_state1->output_format == crtc_state2->output_format && 4261 crtc_state1->lane_count == crtc_state2->lane_count && 4262 crtc_state1->port_clock == crtc_state2->port_clock && 4263 mode_equal(&crtc_state1->hw.adjusted_mode, 4264 &crtc_state2->hw.adjusted_mode) && 4265 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4266 } 4267 4268 static u8 4269 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4270 int tile_group_id) 4271 { 4272 struct drm_connector *connector; 4273 const struct drm_connector_state *conn_state; 4274 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4275 struct intel_atomic_state *state = 4276 to_intel_atomic_state(ref_crtc_state->uapi.state); 4277 u8 transcoders = 0; 4278 int i; 4279 4280 /* 4281 * We don't enable port sync on BDW due to missing w/as and 4282 * due to not having adjusted the modeset sequence appropriately. 4283 */ 4284 if (DISPLAY_VER(dev_priv) < 9) 4285 return 0; 4286 4287 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4288 return 0; 4289 4290 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4291 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4292 const struct intel_crtc_state *crtc_state; 4293 4294 if (!crtc) 4295 continue; 4296 4297 if (!connector->has_tile || 4298 connector->tile_group->id != 4299 tile_group_id) 4300 continue; 4301 crtc_state = intel_atomic_get_new_crtc_state(state, 4302 crtc); 4303 if (!crtcs_port_sync_compatible(ref_crtc_state, 4304 crtc_state)) 4305 continue; 4306 transcoders |= BIT(crtc_state->cpu_transcoder); 4307 } 4308 4309 return transcoders; 4310 } 4311 4312 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4313 struct intel_crtc_state *crtc_state, 4314 struct drm_connector_state *conn_state) 4315 { 4316 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4317 struct drm_connector *connector = conn_state->connector; 4318 u8 port_sync_transcoders = 0; 4319 4320 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4321 encoder->base.base.id, encoder->base.name, 4322 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4323 4324 if (connector->has_tile) 4325 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4326 connector->tile_group->id); 4327 4328 /* 4329 * EDP Transcoders cannot be ensalved 4330 * make them a master always when present 4331 */ 4332 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4333 crtc_state->master_transcoder = TRANSCODER_EDP; 4334 else 4335 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4336 4337 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4338 crtc_state->master_transcoder = INVALID_TRANSCODER; 4339 crtc_state->sync_mode_slaves_mask = 4340 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4341 } 4342 4343 return 0; 4344 } 4345 4346 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4347 { 4348 struct drm_i915_private *i915 = to_i915(encoder->dev); 4349 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4350 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 4351 4352 intel_dp_encoder_flush_work(encoder); 4353 if (intel_phy_is_tc(i915, phy)) 4354 intel_tc_port_cleanup(dig_port); 4355 intel_display_power_flush_work(i915); 4356 4357 drm_encoder_cleanup(encoder); 4358 kfree(dig_port->hdcp_port_data.streams); 4359 kfree(dig_port); 4360 } 4361 4362 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4363 { 4364 struct drm_i915_private *i915 = to_i915(encoder->dev); 4365 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4366 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4367 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 4368 4369 intel_dp->reset_link_params = true; 4370 4371 intel_pps_encoder_reset(intel_dp); 4372 4373 if (intel_phy_is_tc(i915, phy)) 4374 intel_tc_port_init_mode(dig_port); 4375 } 4376 4377 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4378 { 4379 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4380 4381 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4382 4383 return 0; 4384 } 4385 4386 static const struct drm_encoder_funcs intel_ddi_funcs = { 4387 .reset = intel_ddi_encoder_reset, 4388 .destroy = intel_ddi_encoder_destroy, 4389 .late_register = intel_ddi_encoder_late_register, 4390 }; 4391 4392 static struct intel_connector * 4393 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4394 { 4395 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4396 struct intel_connector *connector; 4397 enum port port = dig_port->base.port; 4398 4399 connector = intel_connector_alloc(); 4400 if (!connector) 4401 return NULL; 4402 4403 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4404 if (DISPLAY_VER(i915) >= 14) 4405 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4406 else 4407 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4408 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4409 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4410 4411 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4412 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4413 4414 if (!intel_dp_init_connector(dig_port, connector)) { 4415 kfree(connector); 4416 return NULL; 4417 } 4418 4419 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4420 struct drm_device *dev = dig_port->base.base.dev; 4421 struct drm_privacy_screen *privacy_screen; 4422 4423 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4424 if (!IS_ERR(privacy_screen)) { 4425 drm_connector_attach_privacy_screen_provider(&connector->base, 4426 privacy_screen); 4427 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4428 drm_warn(dev, "Error getting privacy-screen\n"); 4429 } 4430 } 4431 4432 return connector; 4433 } 4434 4435 static int modeset_pipe(struct drm_crtc *crtc, 4436 struct drm_modeset_acquire_ctx *ctx) 4437 { 4438 struct drm_atomic_state *state; 4439 struct drm_crtc_state *crtc_state; 4440 int ret; 4441 4442 state = drm_atomic_state_alloc(crtc->dev); 4443 if (!state) 4444 return -ENOMEM; 4445 4446 state->acquire_ctx = ctx; 4447 to_intel_atomic_state(state)->internal = true; 4448 4449 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4450 if (IS_ERR(crtc_state)) { 4451 ret = PTR_ERR(crtc_state); 4452 goto out; 4453 } 4454 4455 crtc_state->connectors_changed = true; 4456 4457 ret = drm_atomic_commit(state); 4458 out: 4459 drm_atomic_state_put(state); 4460 4461 return ret; 4462 } 4463 4464 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4465 struct drm_modeset_acquire_ctx *ctx) 4466 { 4467 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4468 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4469 struct intel_connector *connector = hdmi->attached_connector; 4470 struct i2c_adapter *ddc = connector->base.ddc; 4471 struct drm_connector_state *conn_state; 4472 struct intel_crtc_state *crtc_state; 4473 struct intel_crtc *crtc; 4474 u8 config; 4475 int ret; 4476 4477 if (connector->base.status != connector_status_connected) 4478 return 0; 4479 4480 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4481 ctx); 4482 if (ret) 4483 return ret; 4484 4485 conn_state = connector->base.state; 4486 4487 crtc = to_intel_crtc(conn_state->crtc); 4488 if (!crtc) 4489 return 0; 4490 4491 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4492 if (ret) 4493 return ret; 4494 4495 crtc_state = to_intel_crtc_state(crtc->base.state); 4496 4497 drm_WARN_ON(&dev_priv->drm, 4498 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4499 4500 if (!crtc_state->hw.active) 4501 return 0; 4502 4503 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4504 !crtc_state->hdmi_scrambling) 4505 return 0; 4506 4507 if (conn_state->commit && 4508 !try_wait_for_completion(&conn_state->commit->hw_done)) 4509 return 0; 4510 4511 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4512 if (ret < 0) { 4513 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4514 connector->base.base.id, connector->base.name, ret); 4515 return 0; 4516 } 4517 4518 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4519 crtc_state->hdmi_high_tmds_clock_ratio && 4520 !!(config & SCDC_SCRAMBLING_ENABLE) == 4521 crtc_state->hdmi_scrambling) 4522 return 0; 4523 4524 /* 4525 * HDMI 2.0 says that one should not send scrambled data 4526 * prior to configuring the sink scrambling, and that 4527 * TMDS clock/data transmission should be suspended when 4528 * changing the TMDS clock rate in the sink. So let's 4529 * just do a full modeset here, even though some sinks 4530 * would be perfectly happy if were to just reconfigure 4531 * the SCDC settings on the fly. 4532 */ 4533 return modeset_pipe(&crtc->base, ctx); 4534 } 4535 4536 static enum intel_hotplug_state 4537 intel_ddi_hotplug(struct intel_encoder *encoder, 4538 struct intel_connector *connector) 4539 { 4540 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4541 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4542 struct intel_dp *intel_dp = &dig_port->dp; 4543 enum phy phy = intel_port_to_phy(i915, encoder->port); 4544 bool is_tc = intel_phy_is_tc(i915, phy); 4545 struct drm_modeset_acquire_ctx ctx; 4546 enum intel_hotplug_state state; 4547 int ret; 4548 4549 if (intel_dp->compliance.test_active && 4550 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4551 intel_dp_phy_test(encoder); 4552 /* just do the PHY test and nothing else */ 4553 return INTEL_HOTPLUG_UNCHANGED; 4554 } 4555 4556 state = intel_encoder_hotplug(encoder, connector); 4557 4558 if (!intel_tc_port_link_reset(dig_port)) { 4559 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) { 4560 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4561 ret = intel_hdmi_reset_link(encoder, &ctx); 4562 else 4563 ret = intel_dp_retrain_link(encoder, &ctx); 4564 } 4565 4566 drm_WARN_ON(encoder->base.dev, ret); 4567 } 4568 4569 /* 4570 * Unpowered type-c dongles can take some time to boot and be 4571 * responsible, so here giving some time to those dongles to power up 4572 * and then retrying the probe. 4573 * 4574 * On many platforms the HDMI live state signal is known to be 4575 * unreliable, so we can't use it to detect if a sink is connected or 4576 * not. Instead we detect if it's connected based on whether we can 4577 * read the EDID or not. That in turn has a problem during disconnect, 4578 * since the HPD interrupt may be raised before the DDC lines get 4579 * disconnected (due to how the required length of DDC vs. HPD 4580 * connector pins are specified) and so we'll still be able to get a 4581 * valid EDID. To solve this schedule another detection cycle if this 4582 * time around we didn't detect any change in the sink's connection 4583 * status. 4584 * 4585 * Type-c connectors which get their HPD signal deasserted then 4586 * reasserted, without unplugging/replugging the sink from the 4587 * connector, introduce a delay until the AUX channel communication 4588 * becomes functional. Retry the detection for 5 seconds on type-c 4589 * connectors to account for this delay. 4590 */ 4591 if (state == INTEL_HOTPLUG_UNCHANGED && 4592 connector->hotplug_retries < (is_tc ? 5 : 1) && 4593 !dig_port->dp.is_mst) 4594 state = INTEL_HOTPLUG_RETRY; 4595 4596 return state; 4597 } 4598 4599 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4600 { 4601 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4602 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4603 4604 return intel_de_read(dev_priv, SDEISR) & bit; 4605 } 4606 4607 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4608 { 4609 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4610 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4611 4612 return intel_de_read(dev_priv, DEISR) & bit; 4613 } 4614 4615 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4616 { 4617 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4618 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4619 4620 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4621 } 4622 4623 static struct intel_connector * 4624 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4625 { 4626 struct intel_connector *connector; 4627 enum port port = dig_port->base.port; 4628 4629 connector = intel_connector_alloc(); 4630 if (!connector) 4631 return NULL; 4632 4633 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4634 intel_hdmi_init_connector(dig_port, connector); 4635 4636 return connector; 4637 } 4638 4639 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4640 { 4641 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4642 4643 if (dig_port->base.port != PORT_A) 4644 return false; 4645 4646 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4647 return false; 4648 4649 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4650 * supported configuration 4651 */ 4652 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4653 return true; 4654 4655 return false; 4656 } 4657 4658 static int 4659 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4660 { 4661 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4662 enum port port = dig_port->base.port; 4663 int max_lanes = 4; 4664 4665 if (DISPLAY_VER(dev_priv) >= 11) 4666 return max_lanes; 4667 4668 if (port == PORT_A || port == PORT_E) { 4669 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4670 max_lanes = port == PORT_A ? 4 : 0; 4671 else 4672 /* Both A and E share 2 lanes */ 4673 max_lanes = 2; 4674 } 4675 4676 /* 4677 * Some BIOS might fail to set this bit on port A if eDP 4678 * wasn't lit up at boot. Force this bit set when needed 4679 * so we use the proper lane count for our calculations. 4680 */ 4681 if (intel_ddi_a_force_4_lanes(dig_port)) { 4682 drm_dbg_kms(&dev_priv->drm, 4683 "Forcing DDI_A_4_LANES for port A\n"); 4684 dig_port->saved_port_bits |= DDI_A_4_LANES; 4685 max_lanes = 4; 4686 } 4687 4688 return max_lanes; 4689 } 4690 4691 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4692 enum port port) 4693 { 4694 if (port >= PORT_D_XELPD) 4695 return HPD_PORT_D + port - PORT_D_XELPD; 4696 else if (port >= PORT_TC1) 4697 return HPD_PORT_TC1 + port - PORT_TC1; 4698 else 4699 return HPD_PORT_A + port - PORT_A; 4700 } 4701 4702 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4703 enum port port) 4704 { 4705 if (port >= PORT_TC1) 4706 return HPD_PORT_C + port - PORT_TC1; 4707 else 4708 return HPD_PORT_A + port - PORT_A; 4709 } 4710 4711 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4712 enum port port) 4713 { 4714 if (port >= PORT_TC1) 4715 return HPD_PORT_TC1 + port - PORT_TC1; 4716 else 4717 return HPD_PORT_A + port - PORT_A; 4718 } 4719 4720 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4721 enum port port) 4722 { 4723 if (HAS_PCH_TGP(dev_priv)) 4724 return tgl_hpd_pin(dev_priv, port); 4725 4726 if (port >= PORT_TC1) 4727 return HPD_PORT_C + port - PORT_TC1; 4728 else 4729 return HPD_PORT_A + port - PORT_A; 4730 } 4731 4732 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4733 enum port port) 4734 { 4735 if (port >= PORT_C) 4736 return HPD_PORT_TC1 + port - PORT_C; 4737 else 4738 return HPD_PORT_A + port - PORT_A; 4739 } 4740 4741 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4742 enum port port) 4743 { 4744 if (port == PORT_D) 4745 return HPD_PORT_A; 4746 4747 if (HAS_PCH_TGP(dev_priv)) 4748 return icl_hpd_pin(dev_priv, port); 4749 4750 return HPD_PORT_A + port - PORT_A; 4751 } 4752 4753 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4754 { 4755 if (HAS_PCH_TGP(dev_priv)) 4756 return icl_hpd_pin(dev_priv, port); 4757 4758 return HPD_PORT_A + port - PORT_A; 4759 } 4760 4761 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4762 { 4763 if (DISPLAY_VER(i915) >= 12) 4764 return port >= PORT_TC1; 4765 else if (DISPLAY_VER(i915) >= 11) 4766 return port >= PORT_C; 4767 else 4768 return false; 4769 } 4770 4771 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4772 { 4773 intel_dp_encoder_suspend(encoder); 4774 } 4775 4776 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4777 { 4778 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4779 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4780 4781 intel_tc_port_suspend(dig_port); 4782 } 4783 4784 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4785 { 4786 intel_dp_encoder_shutdown(encoder); 4787 intel_hdmi_encoder_shutdown(encoder); 4788 } 4789 4790 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4791 { 4792 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4793 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4794 4795 intel_tc_port_cleanup(dig_port); 4796 } 4797 4798 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4799 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4800 4801 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 4802 { 4803 /* straps not used on skl+ */ 4804 if (DISPLAY_VER(i915) >= 9) 4805 return true; 4806 4807 switch (port) { 4808 case PORT_A: 4809 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 4810 case PORT_B: 4811 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 4812 case PORT_C: 4813 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 4814 case PORT_D: 4815 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 4816 case PORT_E: 4817 return true; /* no strap for DDI-E */ 4818 default: 4819 MISSING_CASE(port); 4820 return false; 4821 } 4822 } 4823 4824 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 4825 { 4826 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4827 enum phy phy = intel_port_to_phy(i915, encoder->port); 4828 4829 return init_dp || intel_phy_is_tc(i915, phy); 4830 } 4831 4832 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 4833 { 4834 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 4835 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 4836 "Platform does not support DSI\n"); 4837 } 4838 4839 static bool port_in_use(struct drm_i915_private *i915, enum port port) 4840 { 4841 struct intel_encoder *encoder; 4842 4843 for_each_intel_encoder(&i915->drm, encoder) { 4844 /* FIXME what about second port for dual link DSI? */ 4845 if (encoder->port == port) 4846 return true; 4847 } 4848 4849 return false; 4850 } 4851 4852 void intel_ddi_init(struct drm_i915_private *dev_priv, 4853 const struct intel_bios_encoder_data *devdata) 4854 { 4855 struct intel_digital_port *dig_port; 4856 struct intel_encoder *encoder; 4857 bool init_hdmi, init_dp; 4858 enum port port; 4859 enum phy phy; 4860 4861 port = intel_bios_encoder_port(devdata); 4862 if (port == PORT_NONE) 4863 return; 4864 4865 if (!port_strap_detected(dev_priv, port)) { 4866 drm_dbg_kms(&dev_priv->drm, 4867 "Port %c strap not detected\n", port_name(port)); 4868 return; 4869 } 4870 4871 if (!assert_port_valid(dev_priv, port)) 4872 return; 4873 4874 if (port_in_use(dev_priv, port)) { 4875 drm_dbg_kms(&dev_priv->drm, 4876 "Port %c already claimed\n", port_name(port)); 4877 return; 4878 } 4879 4880 if (intel_bios_encoder_supports_dsi(devdata)) { 4881 /* BXT/GLK handled elsewhere, for now at least */ 4882 if (!assert_has_icl_dsi(dev_priv)) 4883 return; 4884 4885 icl_dsi_init(dev_priv, devdata); 4886 return; 4887 } 4888 4889 phy = intel_port_to_phy(dev_priv, port); 4890 4891 /* 4892 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4893 * have taken over some of the PHYs and made them unavailable to the 4894 * driver. In that case we should skip initializing the corresponding 4895 * outputs. 4896 */ 4897 if (intel_hti_uses_phy(dev_priv, phy)) { 4898 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4899 port_name(port), phy_name(phy)); 4900 return; 4901 } 4902 4903 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4904 intel_bios_encoder_supports_hdmi(devdata); 4905 init_dp = intel_bios_encoder_supports_dp(devdata); 4906 4907 if (intel_bios_encoder_is_lspcon(devdata)) { 4908 /* 4909 * Lspcon device needs to be driven with DP connector 4910 * with special detection sequence. So make sure DP 4911 * is initialized before lspcon. 4912 */ 4913 init_dp = true; 4914 init_hdmi = false; 4915 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4916 port_name(port)); 4917 } 4918 4919 if (!init_dp && !init_hdmi) { 4920 drm_dbg_kms(&dev_priv->drm, 4921 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4922 port_name(port)); 4923 return; 4924 } 4925 4926 if (intel_phy_is_snps(dev_priv, phy) && 4927 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4928 drm_dbg_kms(&dev_priv->drm, 4929 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4930 phy_name(phy)); 4931 } 4932 4933 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4934 if (!dig_port) 4935 return; 4936 4937 dig_port->aux_ch = AUX_CH_NONE; 4938 4939 encoder = &dig_port->base; 4940 encoder->devdata = devdata; 4941 4942 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4943 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4944 DRM_MODE_ENCODER_TMDS, 4945 "DDI %c/PHY %c", 4946 port_name(port - PORT_D_XELPD + PORT_D), 4947 phy_name(phy)); 4948 } else if (DISPLAY_VER(dev_priv) >= 12) { 4949 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4950 4951 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4952 DRM_MODE_ENCODER_TMDS, 4953 "DDI %s%c/PHY %s%c", 4954 port >= PORT_TC1 ? "TC" : "", 4955 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4956 tc_port != TC_PORT_NONE ? "TC" : "", 4957 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4958 } else if (DISPLAY_VER(dev_priv) >= 11) { 4959 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4960 4961 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4962 DRM_MODE_ENCODER_TMDS, 4963 "DDI %c%s/PHY %s%c", 4964 port_name(port), 4965 port >= PORT_C ? " (TC)" : "", 4966 tc_port != TC_PORT_NONE ? "TC" : "", 4967 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4968 } else { 4969 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4970 DRM_MODE_ENCODER_TMDS, 4971 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4972 } 4973 4974 mutex_init(&dig_port->hdcp_mutex); 4975 dig_port->num_hdcp_streams = 0; 4976 4977 encoder->hotplug = intel_ddi_hotplug; 4978 encoder->compute_output_type = intel_ddi_compute_output_type; 4979 encoder->compute_config = intel_ddi_compute_config; 4980 encoder->compute_config_late = intel_ddi_compute_config_late; 4981 encoder->enable = intel_enable_ddi; 4982 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4983 encoder->pre_enable = intel_ddi_pre_enable; 4984 encoder->disable = intel_disable_ddi; 4985 encoder->post_pll_disable = intel_ddi_post_pll_disable; 4986 encoder->post_disable = intel_ddi_post_disable; 4987 encoder->update_pipe = intel_ddi_update_pipe; 4988 encoder->audio_enable = intel_audio_codec_enable; 4989 encoder->audio_disable = intel_audio_codec_disable; 4990 encoder->get_hw_state = intel_ddi_get_hw_state; 4991 encoder->sync_state = intel_ddi_sync_state; 4992 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4993 encoder->suspend = intel_ddi_encoder_suspend; 4994 encoder->shutdown = intel_ddi_encoder_shutdown; 4995 encoder->get_power_domains = intel_ddi_get_power_domains; 4996 4997 encoder->type = INTEL_OUTPUT_DDI; 4998 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 4999 encoder->port = port; 5000 encoder->cloneable = 0; 5001 encoder->pipe_mask = ~0; 5002 5003 if (DISPLAY_VER(dev_priv) >= 14) { 5004 encoder->enable_clock = intel_mtl_pll_enable; 5005 encoder->disable_clock = intel_mtl_pll_disable; 5006 encoder->port_pll_type = intel_mtl_port_pll_type; 5007 encoder->get_config = mtl_ddi_get_config; 5008 } else if (IS_DG2(dev_priv)) { 5009 encoder->enable_clock = intel_mpllb_enable; 5010 encoder->disable_clock = intel_mpllb_disable; 5011 encoder->get_config = dg2_ddi_get_config; 5012 } else if (IS_ALDERLAKE_S(dev_priv)) { 5013 encoder->enable_clock = adls_ddi_enable_clock; 5014 encoder->disable_clock = adls_ddi_disable_clock; 5015 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5016 encoder->get_config = adls_ddi_get_config; 5017 } else if (IS_ROCKETLAKE(dev_priv)) { 5018 encoder->enable_clock = rkl_ddi_enable_clock; 5019 encoder->disable_clock = rkl_ddi_disable_clock; 5020 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5021 encoder->get_config = rkl_ddi_get_config; 5022 } else if (IS_DG1(dev_priv)) { 5023 encoder->enable_clock = dg1_ddi_enable_clock; 5024 encoder->disable_clock = dg1_ddi_disable_clock; 5025 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5026 encoder->get_config = dg1_ddi_get_config; 5027 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5028 if (intel_ddi_is_tc(dev_priv, port)) { 5029 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5030 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5031 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5032 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5033 encoder->get_config = icl_ddi_combo_get_config; 5034 } else { 5035 encoder->enable_clock = icl_ddi_combo_enable_clock; 5036 encoder->disable_clock = icl_ddi_combo_disable_clock; 5037 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5038 encoder->get_config = icl_ddi_combo_get_config; 5039 } 5040 } else if (DISPLAY_VER(dev_priv) >= 11) { 5041 if (intel_ddi_is_tc(dev_priv, port)) { 5042 encoder->enable_clock = icl_ddi_tc_enable_clock; 5043 encoder->disable_clock = icl_ddi_tc_disable_clock; 5044 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5045 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5046 encoder->get_config = icl_ddi_tc_get_config; 5047 } else { 5048 encoder->enable_clock = icl_ddi_combo_enable_clock; 5049 encoder->disable_clock = icl_ddi_combo_disable_clock; 5050 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5051 encoder->get_config = icl_ddi_combo_get_config; 5052 } 5053 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5054 /* BXT/GLK have fixed PLL->port mapping */ 5055 encoder->get_config = bxt_ddi_get_config; 5056 } else if (DISPLAY_VER(dev_priv) == 9) { 5057 encoder->enable_clock = skl_ddi_enable_clock; 5058 encoder->disable_clock = skl_ddi_disable_clock; 5059 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5060 encoder->get_config = skl_ddi_get_config; 5061 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5062 encoder->enable_clock = hsw_ddi_enable_clock; 5063 encoder->disable_clock = hsw_ddi_disable_clock; 5064 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5065 encoder->get_config = hsw_ddi_get_config; 5066 } 5067 5068 if (DISPLAY_VER(dev_priv) >= 14) { 5069 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5070 } else if (IS_DG2(dev_priv)) { 5071 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5072 } else if (DISPLAY_VER(dev_priv) >= 12) { 5073 if (intel_phy_is_combo(dev_priv, phy)) 5074 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5075 else 5076 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5077 } else if (DISPLAY_VER(dev_priv) >= 11) { 5078 if (intel_phy_is_combo(dev_priv, phy)) 5079 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5080 else 5081 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5082 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5083 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; 5084 } else { 5085 encoder->set_signal_levels = hsw_set_signal_levels; 5086 } 5087 5088 intel_ddi_buf_trans_init(encoder); 5089 5090 if (DISPLAY_VER(dev_priv) >= 13) 5091 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5092 else if (IS_DG1(dev_priv)) 5093 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5094 else if (IS_ROCKETLAKE(dev_priv)) 5095 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5096 else if (DISPLAY_VER(dev_priv) >= 12) 5097 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5098 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5099 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5100 else if (DISPLAY_VER(dev_priv) == 11) 5101 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5102 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5103 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5104 else 5105 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5106 5107 if (DISPLAY_VER(dev_priv) >= 11) 5108 dig_port->saved_port_bits = 5109 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5110 & DDI_BUF_PORT_REVERSAL; 5111 else 5112 dig_port->saved_port_bits = 5113 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5114 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5115 5116 if (intel_bios_encoder_lane_reversal(devdata)) 5117 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 5118 5119 dig_port->dp.output_reg = INVALID_MMIO_REG; 5120 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5121 5122 if (need_aux_ch(encoder, init_dp)) { 5123 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5124 if (dig_port->aux_ch == AUX_CH_NONE) 5125 goto err; 5126 } 5127 5128 if (intel_phy_is_tc(dev_priv, phy)) { 5129 bool is_legacy = 5130 !intel_bios_encoder_supports_typec_usb(devdata) && 5131 !intel_bios_encoder_supports_tbt(devdata); 5132 5133 if (!is_legacy && init_hdmi) { 5134 is_legacy = !init_dp; 5135 5136 drm_dbg_kms(&dev_priv->drm, 5137 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5138 port_name(port), 5139 str_yes_no(init_dp), 5140 is_legacy ? "legacy" : "non-legacy"); 5141 } 5142 5143 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5144 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5145 5146 dig_port->lock = intel_tc_port_lock; 5147 dig_port->unlock = intel_tc_port_unlock; 5148 5149 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5150 goto err; 5151 } 5152 5153 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5154 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5155 5156 if (DISPLAY_VER(dev_priv) >= 11) { 5157 if (intel_phy_is_tc(dev_priv, phy)) 5158 dig_port->connected = intel_tc_port_connected; 5159 else 5160 dig_port->connected = lpt_digital_port_connected; 5161 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5162 dig_port->connected = bdw_digital_port_connected; 5163 } else if (DISPLAY_VER(dev_priv) == 9) { 5164 dig_port->connected = lpt_digital_port_connected; 5165 } else if (IS_BROADWELL(dev_priv)) { 5166 if (port == PORT_A) 5167 dig_port->connected = bdw_digital_port_connected; 5168 else 5169 dig_port->connected = lpt_digital_port_connected; 5170 } else if (IS_HASWELL(dev_priv)) { 5171 if (port == PORT_A) 5172 dig_port->connected = hsw_digital_port_connected; 5173 else 5174 dig_port->connected = lpt_digital_port_connected; 5175 } 5176 5177 intel_infoframe_init(dig_port); 5178 5179 if (init_dp) { 5180 if (!intel_ddi_init_dp_connector(dig_port)) 5181 goto err; 5182 5183 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5184 5185 if (dig_port->dp.mso_link_count) 5186 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5187 } 5188 5189 /* 5190 * In theory we don't need the encoder->type check, 5191 * but leave it just in case we have some really bad VBTs... 5192 */ 5193 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5194 if (!intel_ddi_init_hdmi_connector(dig_port)) 5195 goto err; 5196 } 5197 5198 return; 5199 5200 err: 5201 drm_encoder_cleanup(&encoder->base); 5202 kfree(dig_port); 5203 } 5204