1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include <drm/drm_debugfs.h> 9 #include <drm/drm_fourcc.h> 10 11 #include "i915_debugfs.h" 12 #include "intel_de.h" 13 #include "intel_display_debugfs.h" 14 #include "intel_display_power.h" 15 #include "intel_display_power_well.h" 16 #include "intel_display_types.h" 17 #include "intel_dmc.h" 18 #include "intel_dp.h" 19 #include "intel_dp_mst.h" 20 #include "intel_drrs.h" 21 #include "intel_fbc.h" 22 #include "intel_fbdev.h" 23 #include "intel_hdcp.h" 24 #include "intel_hdmi.h" 25 #include "intel_panel.h" 26 #include "intel_pm.h" 27 #include "intel_psr.h" 28 #include "intel_sprite.h" 29 #include "skl_watermark.h" 30 31 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 32 { 33 return to_i915(node->minor->dev); 34 } 35 36 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) 37 { 38 struct drm_i915_private *dev_priv = node_to_i915(m->private); 39 40 seq_printf(m, "FB tracking busy bits: 0x%08x\n", 41 dev_priv->display.fb_tracking.busy_bits); 42 43 seq_printf(m, "FB tracking flip bits: 0x%08x\n", 44 dev_priv->display.fb_tracking.flip_bits); 45 46 return 0; 47 } 48 49 static int i915_ips_status(struct seq_file *m, void *unused) 50 { 51 struct drm_i915_private *dev_priv = node_to_i915(m->private); 52 intel_wakeref_t wakeref; 53 54 if (!HAS_IPS(dev_priv)) 55 return -ENODEV; 56 57 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 58 59 seq_printf(m, "Enabled by kernel parameter: %s\n", 60 str_yes_no(dev_priv->params.enable_ips)); 61 62 if (DISPLAY_VER(dev_priv) >= 8) { 63 seq_puts(m, "Currently: unknown\n"); 64 } else { 65 if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE) 66 seq_puts(m, "Currently: enabled\n"); 67 else 68 seq_puts(m, "Currently: disabled\n"); 69 } 70 71 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 72 73 return 0; 74 } 75 76 static int i915_sr_status(struct seq_file *m, void *unused) 77 { 78 struct drm_i915_private *dev_priv = node_to_i915(m->private); 79 intel_wakeref_t wakeref; 80 bool sr_enabled = false; 81 82 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 83 84 if (DISPLAY_VER(dev_priv) >= 9) 85 /* no global SR status; inspect per-plane WM */; 86 else if (HAS_PCH_SPLIT(dev_priv)) 87 sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE; 88 else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || 89 IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 90 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN; 91 else if (IS_I915GM(dev_priv)) 92 sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN; 93 else if (IS_PINEVIEW(dev_priv)) 94 sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN; 95 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 96 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 97 98 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 99 100 seq_printf(m, "self-refresh: %s\n", str_enabled_disabled(sr_enabled)); 101 102 return 0; 103 } 104 105 static int i915_opregion(struct seq_file *m, void *unused) 106 { 107 struct drm_i915_private *i915 = node_to_i915(m->private); 108 struct intel_opregion *opregion = &i915->display.opregion; 109 110 if (opregion->header) 111 seq_write(m, opregion->header, OPREGION_SIZE); 112 113 return 0; 114 } 115 116 static int i915_vbt(struct seq_file *m, void *unused) 117 { 118 struct drm_i915_private *i915 = node_to_i915(m->private); 119 struct intel_opregion *opregion = &i915->display.opregion; 120 121 if (opregion->vbt) 122 seq_write(m, opregion->vbt, opregion->vbt_size); 123 124 return 0; 125 } 126 127 static int i915_gem_framebuffer_info(struct seq_file *m, void *data) 128 { 129 struct drm_i915_private *dev_priv = node_to_i915(m->private); 130 struct drm_device *dev = &dev_priv->drm; 131 struct intel_framebuffer *fbdev_fb = NULL; 132 struct drm_framebuffer *drm_fb; 133 134 #ifdef CONFIG_DRM_FBDEV_EMULATION 135 fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev); 136 if (fbdev_fb) { 137 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 138 fbdev_fb->base.width, 139 fbdev_fb->base.height, 140 fbdev_fb->base.format->depth, 141 fbdev_fb->base.format->cpp[0] * 8, 142 fbdev_fb->base.modifier, 143 drm_framebuffer_read_refcount(&fbdev_fb->base)); 144 i915_debugfs_describe_obj(m, intel_fb_obj(&fbdev_fb->base)); 145 seq_putc(m, '\n'); 146 } 147 #endif 148 149 mutex_lock(&dev->mode_config.fb_lock); 150 drm_for_each_fb(drm_fb, dev) { 151 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); 152 if (fb == fbdev_fb) 153 continue; 154 155 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 156 fb->base.width, 157 fb->base.height, 158 fb->base.format->depth, 159 fb->base.format->cpp[0] * 8, 160 fb->base.modifier, 161 drm_framebuffer_read_refcount(&fb->base)); 162 i915_debugfs_describe_obj(m, intel_fb_obj(&fb->base)); 163 seq_putc(m, '\n'); 164 } 165 mutex_unlock(&dev->mode_config.fb_lock); 166 167 return 0; 168 } 169 170 static int i915_psr_sink_status_show(struct seq_file *m, void *data) 171 { 172 u8 val; 173 static const char * const sink_status[] = { 174 "inactive", 175 "transition to active, capture and display", 176 "active, display from RFB", 177 "active, capture and display on sink device timings", 178 "transition to inactive, capture and display, timing re-sync", 179 "reserved", 180 "reserved", 181 "sink internal error", 182 }; 183 struct drm_connector *connector = m->private; 184 struct intel_dp *intel_dp = 185 intel_attached_dp(to_intel_connector(connector)); 186 int ret; 187 188 if (!CAN_PSR(intel_dp)) { 189 seq_puts(m, "PSR Unsupported\n"); 190 return -ENODEV; 191 } 192 193 if (connector->status != connector_status_connected) 194 return -ENODEV; 195 196 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val); 197 198 if (ret == 1) { 199 const char *str = "unknown"; 200 201 val &= DP_PSR_SINK_STATE_MASK; 202 if (val < ARRAY_SIZE(sink_status)) 203 str = sink_status[val]; 204 seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str); 205 } else { 206 return ret; 207 } 208 209 return 0; 210 } 211 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status); 212 213 static void 214 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) 215 { 216 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 217 const char *status = "unknown"; 218 u32 val, status_val; 219 220 if (intel_dp->psr.psr2_enabled) { 221 static const char * const live_status[] = { 222 "IDLE", 223 "CAPTURE", 224 "CAPTURE_FS", 225 "SLEEP", 226 "BUFON_FW", 227 "ML_UP", 228 "SU_STANDBY", 229 "FAST_SLEEP", 230 "DEEP_SLEEP", 231 "BUF_ON", 232 "TG_ON" 233 }; 234 val = intel_de_read(dev_priv, 235 EDP_PSR2_STATUS(intel_dp->psr.transcoder)); 236 status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val); 237 if (status_val < ARRAY_SIZE(live_status)) 238 status = live_status[status_val]; 239 } else { 240 static const char * const live_status[] = { 241 "IDLE", 242 "SRDONACK", 243 "SRDENT", 244 "BUFOFF", 245 "BUFON", 246 "AUXACK", 247 "SRDOFFACK", 248 "SRDENT_ON", 249 }; 250 val = intel_de_read(dev_priv, 251 EDP_PSR_STATUS(intel_dp->psr.transcoder)); 252 status_val = (val & EDP_PSR_STATUS_STATE_MASK) >> 253 EDP_PSR_STATUS_STATE_SHIFT; 254 if (status_val < ARRAY_SIZE(live_status)) 255 status = live_status[status_val]; 256 } 257 258 seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val); 259 } 260 261 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) 262 { 263 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 264 struct intel_psr *psr = &intel_dp->psr; 265 intel_wakeref_t wakeref; 266 const char *status; 267 bool enabled; 268 u32 val; 269 270 seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support)); 271 if (psr->sink_support) 272 seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); 273 seq_puts(m, "\n"); 274 275 if (!psr->sink_support) 276 return 0; 277 278 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 279 mutex_lock(&psr->lock); 280 281 if (psr->enabled) 282 status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled"; 283 else 284 status = "disabled"; 285 seq_printf(m, "PSR mode: %s\n", status); 286 287 if (!psr->enabled) { 288 seq_printf(m, "PSR sink not reliable: %s\n", 289 str_yes_no(psr->sink_not_reliable)); 290 291 goto unlock; 292 } 293 294 if (psr->psr2_enabled) { 295 val = intel_de_read(dev_priv, 296 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 297 enabled = val & EDP_PSR2_ENABLE; 298 } else { 299 val = intel_de_read(dev_priv, 300 EDP_PSR_CTL(intel_dp->psr.transcoder)); 301 enabled = val & EDP_PSR_ENABLE; 302 } 303 seq_printf(m, "Source PSR ctl: %s [0x%08x]\n", 304 str_enabled_disabled(enabled), val); 305 psr_source_status(intel_dp, m); 306 seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", 307 psr->busy_frontbuffer_bits); 308 309 /* 310 * SKL+ Perf counter is reset to 0 everytime DC state is entered 311 */ 312 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 313 val = intel_de_read(dev_priv, 314 EDP_PSR_PERF_CNT(intel_dp->psr.transcoder)); 315 val &= EDP_PSR_PERF_CNT_MASK; 316 seq_printf(m, "Performance counter: %u\n", val); 317 } 318 319 if (psr->debug & I915_PSR_DEBUG_IRQ) { 320 seq_printf(m, "Last attempted entry at: %lld\n", 321 psr->last_entry_attempt); 322 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); 323 } 324 325 if (psr->psr2_enabled) { 326 u32 su_frames_val[3]; 327 int frame; 328 329 /* 330 * Reading all 3 registers before hand to minimize crossing a 331 * frame boundary between register reads 332 */ 333 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { 334 val = intel_de_read(dev_priv, 335 PSR2_SU_STATUS(intel_dp->psr.transcoder, frame)); 336 su_frames_val[frame / 3] = val; 337 } 338 339 seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); 340 341 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { 342 u32 su_blocks; 343 344 su_blocks = su_frames_val[frame / 3] & 345 PSR2_SU_STATUS_MASK(frame); 346 su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); 347 seq_printf(m, "%d\t%d\n", frame, su_blocks); 348 } 349 350 seq_printf(m, "PSR2 selective fetch: %s\n", 351 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); 352 } 353 354 unlock: 355 mutex_unlock(&psr->lock); 356 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 357 358 return 0; 359 } 360 361 static int i915_edp_psr_status(struct seq_file *m, void *data) 362 { 363 struct drm_i915_private *dev_priv = node_to_i915(m->private); 364 struct intel_dp *intel_dp = NULL; 365 struct intel_encoder *encoder; 366 367 if (!HAS_PSR(dev_priv)) 368 return -ENODEV; 369 370 /* Find the first EDP which supports PSR */ 371 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 372 intel_dp = enc_to_intel_dp(encoder); 373 break; 374 } 375 376 if (!intel_dp) 377 return -ENODEV; 378 379 return intel_psr_status(m, intel_dp); 380 } 381 382 static int 383 i915_edp_psr_debug_set(void *data, u64 val) 384 { 385 struct drm_i915_private *dev_priv = data; 386 struct intel_encoder *encoder; 387 intel_wakeref_t wakeref; 388 int ret = -ENODEV; 389 390 if (!HAS_PSR(dev_priv)) 391 return ret; 392 393 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 394 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 395 396 drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val); 397 398 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 399 400 // TODO: split to each transcoder's PSR debug state 401 ret = intel_psr_debug_set(intel_dp, val); 402 403 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 404 } 405 406 return ret; 407 } 408 409 static int 410 i915_edp_psr_debug_get(void *data, u64 *val) 411 { 412 struct drm_i915_private *dev_priv = data; 413 struct intel_encoder *encoder; 414 415 if (!HAS_PSR(dev_priv)) 416 return -ENODEV; 417 418 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 419 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 420 421 // TODO: split to each transcoder's PSR debug state 422 *val = READ_ONCE(intel_dp->psr.debug); 423 return 0; 424 } 425 426 return -ENODEV; 427 } 428 429 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops, 430 i915_edp_psr_debug_get, i915_edp_psr_debug_set, 431 "%llu\n"); 432 433 static int i915_power_domain_info(struct seq_file *m, void *unused) 434 { 435 struct drm_i915_private *i915 = node_to_i915(m->private); 436 437 intel_display_power_debug(i915, m); 438 439 return 0; 440 } 441 442 static void intel_seq_print_mode(struct seq_file *m, int tabs, 443 const struct drm_display_mode *mode) 444 { 445 int i; 446 447 for (i = 0; i < tabs; i++) 448 seq_putc(m, '\t'); 449 450 seq_printf(m, DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); 451 } 452 453 static void intel_encoder_info(struct seq_file *m, 454 struct intel_crtc *crtc, 455 struct intel_encoder *encoder) 456 { 457 struct drm_i915_private *dev_priv = node_to_i915(m->private); 458 struct drm_connector_list_iter conn_iter; 459 struct drm_connector *connector; 460 461 seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n", 462 encoder->base.base.id, encoder->base.name); 463 464 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 465 drm_for_each_connector_iter(connector, &conn_iter) { 466 const struct drm_connector_state *conn_state = 467 connector->state; 468 469 if (conn_state->best_encoder != &encoder->base) 470 continue; 471 472 seq_printf(m, "\t\t[CONNECTOR:%d:%s]\n", 473 connector->base.id, connector->name); 474 } 475 drm_connector_list_iter_end(&conn_iter); 476 } 477 478 static void intel_panel_info(struct seq_file *m, 479 struct intel_connector *connector) 480 { 481 const struct drm_display_mode *fixed_mode; 482 483 if (list_empty(&connector->panel.fixed_modes)) 484 return; 485 486 seq_puts(m, "\tfixed modes:\n"); 487 488 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) 489 intel_seq_print_mode(m, 2, fixed_mode); 490 } 491 492 static void intel_hdcp_info(struct seq_file *m, 493 struct intel_connector *intel_connector) 494 { 495 bool hdcp_cap, hdcp2_cap; 496 497 if (!intel_connector->hdcp.shim) { 498 seq_puts(m, "No Connector Support"); 499 goto out; 500 } 501 502 hdcp_cap = intel_hdcp_capable(intel_connector); 503 hdcp2_cap = intel_hdcp2_capable(intel_connector); 504 505 if (hdcp_cap) 506 seq_puts(m, "HDCP1.4 "); 507 if (hdcp2_cap) 508 seq_puts(m, "HDCP2.2 "); 509 510 if (!hdcp_cap && !hdcp2_cap) 511 seq_puts(m, "None"); 512 513 out: 514 seq_puts(m, "\n"); 515 } 516 517 static void intel_dp_info(struct seq_file *m, 518 struct intel_connector *intel_connector) 519 { 520 struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); 521 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 522 const struct drm_property_blob *edid = intel_connector->base.edid_blob_ptr; 523 524 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); 525 seq_printf(m, "\taudio support: %s\n", 526 str_yes_no(intel_dp->has_audio)); 527 528 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, 529 edid ? edid->data : NULL, &intel_dp->aux); 530 } 531 532 static void intel_dp_mst_info(struct seq_file *m, 533 struct intel_connector *intel_connector) 534 { 535 bool has_audio = intel_connector->port->has_audio; 536 537 seq_printf(m, "\taudio support: %s\n", str_yes_no(has_audio)); 538 } 539 540 static void intel_hdmi_info(struct seq_file *m, 541 struct intel_connector *intel_connector) 542 { 543 struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); 544 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(intel_encoder); 545 546 seq_printf(m, "\taudio support: %s\n", 547 str_yes_no(intel_hdmi->has_audio)); 548 } 549 550 static void intel_connector_info(struct seq_file *m, 551 struct drm_connector *connector) 552 { 553 struct intel_connector *intel_connector = to_intel_connector(connector); 554 const struct drm_connector_state *conn_state = connector->state; 555 struct intel_encoder *encoder = 556 to_intel_encoder(conn_state->best_encoder); 557 const struct drm_display_mode *mode; 558 559 seq_printf(m, "[CONNECTOR:%d:%s]: status: %s\n", 560 connector->base.id, connector->name, 561 drm_get_connector_status_name(connector->status)); 562 563 if (connector->status == connector_status_disconnected) 564 return; 565 566 seq_printf(m, "\tphysical dimensions: %dx%dmm\n", 567 connector->display_info.width_mm, 568 connector->display_info.height_mm); 569 seq_printf(m, "\tsubpixel order: %s\n", 570 drm_get_subpixel_order_name(connector->display_info.subpixel_order)); 571 seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev); 572 573 if (!encoder) 574 return; 575 576 switch (connector->connector_type) { 577 case DRM_MODE_CONNECTOR_DisplayPort: 578 case DRM_MODE_CONNECTOR_eDP: 579 if (encoder->type == INTEL_OUTPUT_DP_MST) 580 intel_dp_mst_info(m, intel_connector); 581 else 582 intel_dp_info(m, intel_connector); 583 break; 584 case DRM_MODE_CONNECTOR_HDMIA: 585 if (encoder->type == INTEL_OUTPUT_HDMI || 586 encoder->type == INTEL_OUTPUT_DDI) 587 intel_hdmi_info(m, intel_connector); 588 break; 589 default: 590 break; 591 } 592 593 seq_puts(m, "\tHDCP version: "); 594 intel_hdcp_info(m, intel_connector); 595 596 seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc); 597 598 intel_panel_info(m, intel_connector); 599 600 seq_printf(m, "\tmodes:\n"); 601 list_for_each_entry(mode, &connector->modes, head) 602 intel_seq_print_mode(m, 2, mode); 603 } 604 605 static const char *plane_type(enum drm_plane_type type) 606 { 607 switch (type) { 608 case DRM_PLANE_TYPE_OVERLAY: 609 return "OVL"; 610 case DRM_PLANE_TYPE_PRIMARY: 611 return "PRI"; 612 case DRM_PLANE_TYPE_CURSOR: 613 return "CUR"; 614 /* 615 * Deliberately omitting default: to generate compiler warnings 616 * when a new drm_plane_type gets added. 617 */ 618 } 619 620 return "unknown"; 621 } 622 623 static void plane_rotation(char *buf, size_t bufsize, unsigned int rotation) 624 { 625 /* 626 * According to doc only one DRM_MODE_ROTATE_ is allowed but this 627 * will print them all to visualize if the values are misused 628 */ 629 snprintf(buf, bufsize, 630 "%s%s%s%s%s%s(0x%08x)", 631 (rotation & DRM_MODE_ROTATE_0) ? "0 " : "", 632 (rotation & DRM_MODE_ROTATE_90) ? "90 " : "", 633 (rotation & DRM_MODE_ROTATE_180) ? "180 " : "", 634 (rotation & DRM_MODE_ROTATE_270) ? "270 " : "", 635 (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "", 636 (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "", 637 rotation); 638 } 639 640 static const char *plane_visibility(const struct intel_plane_state *plane_state) 641 { 642 if (plane_state->uapi.visible) 643 return "visible"; 644 645 if (plane_state->planar_slave) 646 return "planar-slave"; 647 648 return "hidden"; 649 } 650 651 static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane) 652 { 653 const struct intel_plane_state *plane_state = 654 to_intel_plane_state(plane->base.state); 655 const struct drm_framebuffer *fb = plane_state->uapi.fb; 656 struct drm_rect src, dst; 657 char rot_str[48]; 658 659 src = drm_plane_state_src(&plane_state->uapi); 660 dst = drm_plane_state_dest(&plane_state->uapi); 661 662 plane_rotation(rot_str, sizeof(rot_str), 663 plane_state->uapi.rotation); 664 665 seq_puts(m, "\t\tuapi: [FB:"); 666 if (fb) 667 seq_printf(m, "%d] %p4cc,0x%llx,%dx%d", fb->base.id, 668 &fb->format->format, fb->modifier, fb->width, 669 fb->height); 670 else 671 seq_puts(m, "0] n/a,0x0,0x0,"); 672 seq_printf(m, ", visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT 673 ", rotation=%s\n", plane_visibility(plane_state), 674 DRM_RECT_FP_ARG(&src), DRM_RECT_ARG(&dst), rot_str); 675 676 if (plane_state->planar_linked_plane) 677 seq_printf(m, "\t\tplanar: Linked to [PLANE:%d:%s] as a %s\n", 678 plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name, 679 plane_state->planar_slave ? "slave" : "master"); 680 } 681 682 static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane) 683 { 684 const struct intel_plane_state *plane_state = 685 to_intel_plane_state(plane->base.state); 686 const struct drm_framebuffer *fb = plane_state->hw.fb; 687 char rot_str[48]; 688 689 if (!fb) 690 return; 691 692 plane_rotation(rot_str, sizeof(rot_str), 693 plane_state->hw.rotation); 694 695 seq_printf(m, "\t\thw: [FB:%d] %p4cc,0x%llx,%dx%d, visible=%s, src=" 696 DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", 697 fb->base.id, &fb->format->format, 698 fb->modifier, fb->width, fb->height, 699 str_yes_no(plane_state->uapi.visible), 700 DRM_RECT_FP_ARG(&plane_state->uapi.src), 701 DRM_RECT_ARG(&plane_state->uapi.dst), 702 rot_str); 703 } 704 705 static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc) 706 { 707 struct drm_i915_private *dev_priv = node_to_i915(m->private); 708 struct intel_plane *plane; 709 710 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { 711 seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n", 712 plane->base.base.id, plane->base.name, 713 plane_type(plane->base.type)); 714 intel_plane_uapi_info(m, plane); 715 intel_plane_hw_info(m, plane); 716 } 717 } 718 719 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc) 720 { 721 const struct intel_crtc_state *crtc_state = 722 to_intel_crtc_state(crtc->base.state); 723 int num_scalers = crtc->num_scalers; 724 int i; 725 726 /* Not all platformas have a scaler */ 727 if (num_scalers) { 728 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d scaling_filter=%d", 729 num_scalers, 730 crtc_state->scaler_state.scaler_users, 731 crtc_state->scaler_state.scaler_id, 732 crtc_state->hw.scaling_filter); 733 734 for (i = 0; i < num_scalers; i++) { 735 const struct intel_scaler *sc = 736 &crtc_state->scaler_state.scalers[i]; 737 738 seq_printf(m, ", scalers[%d]: use=%s, mode=%x", 739 i, str_yes_no(sc->in_use), sc->mode); 740 } 741 seq_puts(m, "\n"); 742 } else { 743 seq_puts(m, "\tNo scalers available on this platform\n"); 744 } 745 } 746 747 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE) 748 static void crtc_updates_info(struct seq_file *m, 749 struct intel_crtc *crtc, 750 const char *hdr) 751 { 752 u64 count; 753 int row; 754 755 count = 0; 756 for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) 757 count += crtc->debug.vbl.times[row]; 758 seq_printf(m, "%sUpdates: %llu\n", hdr, count); 759 if (!count) 760 return; 761 762 for (row = 0; row < ARRAY_SIZE(crtc->debug.vbl.times); row++) { 763 char columns[80] = " |"; 764 unsigned int x; 765 766 if (row & 1) { 767 const char *units; 768 769 if (row > 10) { 770 x = 1000000; 771 units = "ms"; 772 } else { 773 x = 1000; 774 units = "us"; 775 } 776 777 snprintf(columns, sizeof(columns), "%4ld%s |", 778 DIV_ROUND_CLOSEST(BIT(row + 9), x), units); 779 } 780 781 if (crtc->debug.vbl.times[row]) { 782 x = ilog2(crtc->debug.vbl.times[row]); 783 memset(columns + 8, '*', x); 784 columns[8 + x] = '\0'; 785 } 786 787 seq_printf(m, "%s%s\n", hdr, columns); 788 } 789 790 seq_printf(m, "%sMin update: %lluns\n", 791 hdr, crtc->debug.vbl.min); 792 seq_printf(m, "%sMax update: %lluns\n", 793 hdr, crtc->debug.vbl.max); 794 seq_printf(m, "%sAverage update: %lluns\n", 795 hdr, div64_u64(crtc->debug.vbl.sum, count)); 796 seq_printf(m, "%sOverruns > %uus: %u\n", 797 hdr, VBLANK_EVASION_TIME_US, crtc->debug.vbl.over); 798 } 799 800 static int crtc_updates_show(struct seq_file *m, void *data) 801 { 802 crtc_updates_info(m, m->private, ""); 803 return 0; 804 } 805 806 static int crtc_updates_open(struct inode *inode, struct file *file) 807 { 808 return single_open(file, crtc_updates_show, inode->i_private); 809 } 810 811 static ssize_t crtc_updates_write(struct file *file, 812 const char __user *ubuf, 813 size_t len, loff_t *offp) 814 { 815 struct seq_file *m = file->private_data; 816 struct intel_crtc *crtc = m->private; 817 818 /* May race with an update. Meh. */ 819 memset(&crtc->debug.vbl, 0, sizeof(crtc->debug.vbl)); 820 821 return len; 822 } 823 824 static const struct file_operations crtc_updates_fops = { 825 .owner = THIS_MODULE, 826 .open = crtc_updates_open, 827 .read = seq_read, 828 .llseek = seq_lseek, 829 .release = single_release, 830 .write = crtc_updates_write 831 }; 832 833 static void crtc_updates_add(struct drm_crtc *crtc) 834 { 835 debugfs_create_file("i915_update_info", 0644, crtc->debugfs_entry, 836 to_intel_crtc(crtc), &crtc_updates_fops); 837 } 838 839 #else 840 static void crtc_updates_info(struct seq_file *m, 841 struct intel_crtc *crtc, 842 const char *hdr) 843 { 844 } 845 846 static void crtc_updates_add(struct drm_crtc *crtc) 847 { 848 } 849 #endif 850 851 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) 852 { 853 struct drm_i915_private *dev_priv = node_to_i915(m->private); 854 const struct intel_crtc_state *crtc_state = 855 to_intel_crtc_state(crtc->base.state); 856 struct intel_encoder *encoder; 857 858 seq_printf(m, "[CRTC:%d:%s]:\n", 859 crtc->base.base.id, crtc->base.name); 860 861 seq_printf(m, "\tuapi: enable=%s, active=%s, mode=" DRM_MODE_FMT "\n", 862 str_yes_no(crtc_state->uapi.enable), 863 str_yes_no(crtc_state->uapi.active), 864 DRM_MODE_ARG(&crtc_state->uapi.mode)); 865 866 seq_printf(m, "\thw: enable=%s, active=%s\n", 867 str_yes_no(crtc_state->hw.enable), str_yes_no(crtc_state->hw.active)); 868 seq_printf(m, "\tadjusted_mode=" DRM_MODE_FMT "\n", 869 DRM_MODE_ARG(&crtc_state->hw.adjusted_mode)); 870 seq_printf(m, "\tpipe__mode=" DRM_MODE_FMT "\n", 871 DRM_MODE_ARG(&crtc_state->hw.pipe_mode)); 872 873 seq_printf(m, "\tpipe src=" DRM_RECT_FMT ", dither=%s, bpp=%d\n", 874 DRM_RECT_ARG(&crtc_state->pipe_src), 875 str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); 876 877 intel_scaler_info(m, crtc); 878 879 if (crtc_state->bigjoiner_pipes) 880 seq_printf(m, "\tLinked to 0x%x pipes as a %s\n", 881 crtc_state->bigjoiner_pipes, 882 intel_crtc_is_bigjoiner_slave(crtc_state) ? "slave" : "master"); 883 884 for_each_intel_encoder_mask(&dev_priv->drm, encoder, 885 crtc_state->uapi.encoder_mask) 886 intel_encoder_info(m, crtc, encoder); 887 888 intel_plane_info(m, crtc); 889 890 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s\n", 891 str_yes_no(!crtc->cpu_fifo_underrun_disabled), 892 str_yes_no(!crtc->pch_fifo_underrun_disabled)); 893 894 crtc_updates_info(m, crtc, "\t"); 895 } 896 897 static int i915_display_info(struct seq_file *m, void *unused) 898 { 899 struct drm_i915_private *dev_priv = node_to_i915(m->private); 900 struct drm_device *dev = &dev_priv->drm; 901 struct intel_crtc *crtc; 902 struct drm_connector *connector; 903 struct drm_connector_list_iter conn_iter; 904 intel_wakeref_t wakeref; 905 906 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 907 908 drm_modeset_lock_all(dev); 909 910 seq_printf(m, "CRTC info\n"); 911 seq_printf(m, "---------\n"); 912 for_each_intel_crtc(dev, crtc) 913 intel_crtc_info(m, crtc); 914 915 seq_printf(m, "\n"); 916 seq_printf(m, "Connector info\n"); 917 seq_printf(m, "--------------\n"); 918 drm_connector_list_iter_begin(dev, &conn_iter); 919 drm_for_each_connector_iter(connector, &conn_iter) 920 intel_connector_info(m, connector); 921 drm_connector_list_iter_end(&conn_iter); 922 923 drm_modeset_unlock_all(dev); 924 925 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 926 927 return 0; 928 } 929 930 static int i915_shared_dplls_info(struct seq_file *m, void *unused) 931 { 932 struct drm_i915_private *dev_priv = node_to_i915(m->private); 933 struct drm_device *dev = &dev_priv->drm; 934 int i; 935 936 drm_modeset_lock_all(dev); 937 938 seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n", 939 dev_priv->display.dpll.ref_clks.nssc, 940 dev_priv->display.dpll.ref_clks.ssc); 941 942 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { 943 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; 944 945 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name, 946 pll->info->id); 947 seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n", 948 pll->state.pipe_mask, pll->active_mask, 949 str_yes_no(pll->on)); 950 seq_printf(m, " tracked hardware state:\n"); 951 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); 952 seq_printf(m, " dpll_md: 0x%08x\n", 953 pll->state.hw_state.dpll_md); 954 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); 955 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); 956 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); 957 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); 958 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); 959 seq_printf(m, " div0: 0x%08x\n", pll->state.hw_state.div0); 960 seq_printf(m, " mg_refclkin_ctl: 0x%08x\n", 961 pll->state.hw_state.mg_refclkin_ctl); 962 seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n", 963 pll->state.hw_state.mg_clktop2_coreclkctl1); 964 seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n", 965 pll->state.hw_state.mg_clktop2_hsclkctl); 966 seq_printf(m, " mg_pll_div0: 0x%08x\n", 967 pll->state.hw_state.mg_pll_div0); 968 seq_printf(m, " mg_pll_div1: 0x%08x\n", 969 pll->state.hw_state.mg_pll_div1); 970 seq_printf(m, " mg_pll_lf: 0x%08x\n", 971 pll->state.hw_state.mg_pll_lf); 972 seq_printf(m, " mg_pll_frac_lock: 0x%08x\n", 973 pll->state.hw_state.mg_pll_frac_lock); 974 seq_printf(m, " mg_pll_ssc: 0x%08x\n", 975 pll->state.hw_state.mg_pll_ssc); 976 seq_printf(m, " mg_pll_bias: 0x%08x\n", 977 pll->state.hw_state.mg_pll_bias); 978 seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n", 979 pll->state.hw_state.mg_pll_tdc_coldst_bias); 980 } 981 drm_modeset_unlock_all(dev); 982 983 return 0; 984 } 985 986 static int i915_ddb_info(struct seq_file *m, void *unused) 987 { 988 struct drm_i915_private *dev_priv = node_to_i915(m->private); 989 struct drm_device *dev = &dev_priv->drm; 990 struct skl_ddb_entry *entry; 991 struct intel_crtc *crtc; 992 993 if (DISPLAY_VER(dev_priv) < 9) 994 return -ENODEV; 995 996 drm_modeset_lock_all(dev); 997 998 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); 999 1000 for_each_intel_crtc(&dev_priv->drm, crtc) { 1001 struct intel_crtc_state *crtc_state = 1002 to_intel_crtc_state(crtc->base.state); 1003 enum pipe pipe = crtc->pipe; 1004 enum plane_id plane_id; 1005 1006 seq_printf(m, "Pipe %c\n", pipe_name(pipe)); 1007 1008 for_each_plane_id_on_crtc(crtc, plane_id) { 1009 entry = &crtc_state->wm.skl.plane_ddb[plane_id]; 1010 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1, 1011 entry->start, entry->end, 1012 skl_ddb_entry_size(entry)); 1013 } 1014 1015 entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 1016 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, 1017 entry->end, skl_ddb_entry_size(entry)); 1018 } 1019 1020 drm_modeset_unlock_all(dev); 1021 1022 return 0; 1023 } 1024 1025 static int i915_drrs_status(struct seq_file *m, void *unused) 1026 { 1027 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1028 struct drm_connector_list_iter conn_iter; 1029 struct intel_connector *connector; 1030 struct intel_crtc *crtc; 1031 1032 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 1033 for_each_intel_connector_iter(connector, &conn_iter) { 1034 seq_printf(m, "[CONNECTOR:%d:%s] DRRS type: %s\n", 1035 connector->base.base.id, connector->base.name, 1036 intel_drrs_type_str(intel_panel_drrs_type(connector))); 1037 } 1038 drm_connector_list_iter_end(&conn_iter); 1039 1040 seq_puts(m, "\n"); 1041 1042 for_each_intel_crtc(&dev_priv->drm, crtc) { 1043 const struct intel_crtc_state *crtc_state = 1044 to_intel_crtc_state(crtc->base.state); 1045 1046 seq_printf(m, "[CRTC:%d:%s]:\n", 1047 crtc->base.base.id, crtc->base.name); 1048 1049 mutex_lock(&crtc->drrs.mutex); 1050 1051 /* DRRS Supported */ 1052 seq_printf(m, "\tDRRS Enabled: %s\n", 1053 str_yes_no(crtc_state->has_drrs)); 1054 1055 seq_printf(m, "\tDRRS Active: %s\n", 1056 str_yes_no(intel_drrs_is_active(crtc))); 1057 1058 seq_printf(m, "\tBusy_frontbuffer_bits: 0x%X\n", 1059 crtc->drrs.busy_frontbuffer_bits); 1060 1061 seq_printf(m, "\tDRRS refresh rate: %s\n", 1062 crtc->drrs.refresh_rate == DRRS_REFRESH_RATE_LOW ? 1063 "low" : "high"); 1064 1065 mutex_unlock(&crtc->drrs.mutex); 1066 } 1067 1068 return 0; 1069 } 1070 1071 static bool 1072 intel_lpsp_power_well_enabled(struct drm_i915_private *i915, 1073 enum i915_power_well_id power_well_id) 1074 { 1075 intel_wakeref_t wakeref; 1076 bool is_enabled; 1077 1078 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1079 is_enabled = intel_display_power_well_is_enabled(i915, 1080 power_well_id); 1081 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1082 1083 return is_enabled; 1084 } 1085 1086 static int i915_lpsp_status(struct seq_file *m, void *unused) 1087 { 1088 struct drm_i915_private *i915 = node_to_i915(m->private); 1089 bool lpsp_enabled = false; 1090 1091 if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) { 1092 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2); 1093 } else if (IS_DISPLAY_VER(i915, 11, 12)) { 1094 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3); 1095 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 1096 lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL); 1097 } else { 1098 seq_puts(m, "LPSP: not supported\n"); 1099 return 0; 1100 } 1101 1102 seq_printf(m, "LPSP: %s\n", str_enabled_disabled(lpsp_enabled)); 1103 1104 return 0; 1105 } 1106 1107 static int i915_dp_mst_info(struct seq_file *m, void *unused) 1108 { 1109 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1110 struct drm_device *dev = &dev_priv->drm; 1111 struct intel_encoder *intel_encoder; 1112 struct intel_digital_port *dig_port; 1113 struct drm_connector *connector; 1114 struct drm_connector_list_iter conn_iter; 1115 1116 drm_connector_list_iter_begin(dev, &conn_iter); 1117 drm_for_each_connector_iter(connector, &conn_iter) { 1118 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 1119 continue; 1120 1121 intel_encoder = intel_attached_encoder(to_intel_connector(connector)); 1122 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) 1123 continue; 1124 1125 dig_port = enc_to_dig_port(intel_encoder); 1126 if (!intel_dp_mst_source_support(&dig_port->dp)) 1127 continue; 1128 1129 seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n", 1130 dig_port->base.base.base.id, 1131 dig_port->base.base.name); 1132 drm_dp_mst_dump_topology(m, &dig_port->dp.mst_mgr); 1133 } 1134 drm_connector_list_iter_end(&conn_iter); 1135 1136 return 0; 1137 } 1138 1139 static ssize_t i915_displayport_test_active_write(struct file *file, 1140 const char __user *ubuf, 1141 size_t len, loff_t *offp) 1142 { 1143 char *input_buffer; 1144 int status = 0; 1145 struct drm_device *dev; 1146 struct drm_connector *connector; 1147 struct drm_connector_list_iter conn_iter; 1148 struct intel_dp *intel_dp; 1149 int val = 0; 1150 1151 dev = ((struct seq_file *)file->private_data)->private; 1152 1153 if (len == 0) 1154 return 0; 1155 1156 input_buffer = memdup_user_nul(ubuf, len); 1157 if (IS_ERR(input_buffer)) 1158 return PTR_ERR(input_buffer); 1159 1160 drm_dbg(&to_i915(dev)->drm, 1161 "Copied %d bytes from user\n", (unsigned int)len); 1162 1163 drm_connector_list_iter_begin(dev, &conn_iter); 1164 drm_for_each_connector_iter(connector, &conn_iter) { 1165 struct intel_encoder *encoder; 1166 1167 if (connector->connector_type != 1168 DRM_MODE_CONNECTOR_DisplayPort) 1169 continue; 1170 1171 encoder = to_intel_encoder(connector->encoder); 1172 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 1173 continue; 1174 1175 if (encoder && connector->status == connector_status_connected) { 1176 intel_dp = enc_to_intel_dp(encoder); 1177 status = kstrtoint(input_buffer, 10, &val); 1178 if (status < 0) 1179 break; 1180 drm_dbg(&to_i915(dev)->drm, 1181 "Got %d for test active\n", val); 1182 /* To prevent erroneous activation of the compliance 1183 * testing code, only accept an actual value of 1 here 1184 */ 1185 if (val == 1) 1186 intel_dp->compliance.test_active = true; 1187 else 1188 intel_dp->compliance.test_active = false; 1189 } 1190 } 1191 drm_connector_list_iter_end(&conn_iter); 1192 kfree(input_buffer); 1193 if (status < 0) 1194 return status; 1195 1196 *offp += len; 1197 return len; 1198 } 1199 1200 static int i915_displayport_test_active_show(struct seq_file *m, void *data) 1201 { 1202 struct drm_i915_private *dev_priv = m->private; 1203 struct drm_device *dev = &dev_priv->drm; 1204 struct drm_connector *connector; 1205 struct drm_connector_list_iter conn_iter; 1206 struct intel_dp *intel_dp; 1207 1208 drm_connector_list_iter_begin(dev, &conn_iter); 1209 drm_for_each_connector_iter(connector, &conn_iter) { 1210 struct intel_encoder *encoder; 1211 1212 if (connector->connector_type != 1213 DRM_MODE_CONNECTOR_DisplayPort) 1214 continue; 1215 1216 encoder = to_intel_encoder(connector->encoder); 1217 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 1218 continue; 1219 1220 if (encoder && connector->status == connector_status_connected) { 1221 intel_dp = enc_to_intel_dp(encoder); 1222 if (intel_dp->compliance.test_active) 1223 seq_puts(m, "1"); 1224 else 1225 seq_puts(m, "0"); 1226 } else 1227 seq_puts(m, "0"); 1228 } 1229 drm_connector_list_iter_end(&conn_iter); 1230 1231 return 0; 1232 } 1233 1234 static int i915_displayport_test_active_open(struct inode *inode, 1235 struct file *file) 1236 { 1237 return single_open(file, i915_displayport_test_active_show, 1238 inode->i_private); 1239 } 1240 1241 static const struct file_operations i915_displayport_test_active_fops = { 1242 .owner = THIS_MODULE, 1243 .open = i915_displayport_test_active_open, 1244 .read = seq_read, 1245 .llseek = seq_lseek, 1246 .release = single_release, 1247 .write = i915_displayport_test_active_write 1248 }; 1249 1250 static int i915_displayport_test_data_show(struct seq_file *m, void *data) 1251 { 1252 struct drm_i915_private *dev_priv = m->private; 1253 struct drm_device *dev = &dev_priv->drm; 1254 struct drm_connector *connector; 1255 struct drm_connector_list_iter conn_iter; 1256 struct intel_dp *intel_dp; 1257 1258 drm_connector_list_iter_begin(dev, &conn_iter); 1259 drm_for_each_connector_iter(connector, &conn_iter) { 1260 struct intel_encoder *encoder; 1261 1262 if (connector->connector_type != 1263 DRM_MODE_CONNECTOR_DisplayPort) 1264 continue; 1265 1266 encoder = to_intel_encoder(connector->encoder); 1267 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 1268 continue; 1269 1270 if (encoder && connector->status == connector_status_connected) { 1271 intel_dp = enc_to_intel_dp(encoder); 1272 if (intel_dp->compliance.test_type == 1273 DP_TEST_LINK_EDID_READ) 1274 seq_printf(m, "%lx", 1275 intel_dp->compliance.test_data.edid); 1276 else if (intel_dp->compliance.test_type == 1277 DP_TEST_LINK_VIDEO_PATTERN) { 1278 seq_printf(m, "hdisplay: %d\n", 1279 intel_dp->compliance.test_data.hdisplay); 1280 seq_printf(m, "vdisplay: %d\n", 1281 intel_dp->compliance.test_data.vdisplay); 1282 seq_printf(m, "bpc: %u\n", 1283 intel_dp->compliance.test_data.bpc); 1284 } else if (intel_dp->compliance.test_type == 1285 DP_TEST_LINK_PHY_TEST_PATTERN) { 1286 seq_printf(m, "pattern: %d\n", 1287 intel_dp->compliance.test_data.phytest.phy_pattern); 1288 seq_printf(m, "Number of lanes: %d\n", 1289 intel_dp->compliance.test_data.phytest.num_lanes); 1290 seq_printf(m, "Link Rate: %d\n", 1291 intel_dp->compliance.test_data.phytest.link_rate); 1292 seq_printf(m, "level: %02x\n", 1293 intel_dp->train_set[0]); 1294 } 1295 } else 1296 seq_puts(m, "0"); 1297 } 1298 drm_connector_list_iter_end(&conn_iter); 1299 1300 return 0; 1301 } 1302 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data); 1303 1304 static int i915_displayport_test_type_show(struct seq_file *m, void *data) 1305 { 1306 struct drm_i915_private *dev_priv = m->private; 1307 struct drm_device *dev = &dev_priv->drm; 1308 struct drm_connector *connector; 1309 struct drm_connector_list_iter conn_iter; 1310 struct intel_dp *intel_dp; 1311 1312 drm_connector_list_iter_begin(dev, &conn_iter); 1313 drm_for_each_connector_iter(connector, &conn_iter) { 1314 struct intel_encoder *encoder; 1315 1316 if (connector->connector_type != 1317 DRM_MODE_CONNECTOR_DisplayPort) 1318 continue; 1319 1320 encoder = to_intel_encoder(connector->encoder); 1321 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) 1322 continue; 1323 1324 if (encoder && connector->status == connector_status_connected) { 1325 intel_dp = enc_to_intel_dp(encoder); 1326 seq_printf(m, "%02lx\n", intel_dp->compliance.test_type); 1327 } else 1328 seq_puts(m, "0"); 1329 } 1330 drm_connector_list_iter_end(&conn_iter); 1331 1332 return 0; 1333 } 1334 DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type); 1335 1336 static void wm_latency_show(struct seq_file *m, const u16 wm[8]) 1337 { 1338 struct drm_i915_private *dev_priv = m->private; 1339 struct drm_device *dev = &dev_priv->drm; 1340 int level; 1341 int num_levels; 1342 1343 if (IS_CHERRYVIEW(dev_priv)) 1344 num_levels = 3; 1345 else if (IS_VALLEYVIEW(dev_priv)) 1346 num_levels = 1; 1347 else if (IS_G4X(dev_priv)) 1348 num_levels = 3; 1349 else 1350 num_levels = ilk_wm_max_level(dev_priv) + 1; 1351 1352 drm_modeset_lock_all(dev); 1353 1354 for (level = 0; level < num_levels; level++) { 1355 unsigned int latency = wm[level]; 1356 1357 /* 1358 * - WM1+ latency values in 0.5us units 1359 * - latencies are in us on gen9/vlv/chv 1360 */ 1361 if (DISPLAY_VER(dev_priv) >= 9 || 1362 IS_VALLEYVIEW(dev_priv) || 1363 IS_CHERRYVIEW(dev_priv) || 1364 IS_G4X(dev_priv)) 1365 latency *= 10; 1366 else if (level > 0) 1367 latency *= 5; 1368 1369 seq_printf(m, "WM%d %u (%u.%u usec)\n", 1370 level, wm[level], latency / 10, latency % 10); 1371 } 1372 1373 drm_modeset_unlock_all(dev); 1374 } 1375 1376 static int pri_wm_latency_show(struct seq_file *m, void *data) 1377 { 1378 struct drm_i915_private *dev_priv = m->private; 1379 const u16 *latencies; 1380 1381 if (DISPLAY_VER(dev_priv) >= 9) 1382 latencies = dev_priv->display.wm.skl_latency; 1383 else 1384 latencies = dev_priv->display.wm.pri_latency; 1385 1386 wm_latency_show(m, latencies); 1387 1388 return 0; 1389 } 1390 1391 static int spr_wm_latency_show(struct seq_file *m, void *data) 1392 { 1393 struct drm_i915_private *dev_priv = m->private; 1394 const u16 *latencies; 1395 1396 if (DISPLAY_VER(dev_priv) >= 9) 1397 latencies = dev_priv->display.wm.skl_latency; 1398 else 1399 latencies = dev_priv->display.wm.spr_latency; 1400 1401 wm_latency_show(m, latencies); 1402 1403 return 0; 1404 } 1405 1406 static int cur_wm_latency_show(struct seq_file *m, void *data) 1407 { 1408 struct drm_i915_private *dev_priv = m->private; 1409 const u16 *latencies; 1410 1411 if (DISPLAY_VER(dev_priv) >= 9) 1412 latencies = dev_priv->display.wm.skl_latency; 1413 else 1414 latencies = dev_priv->display.wm.cur_latency; 1415 1416 wm_latency_show(m, latencies); 1417 1418 return 0; 1419 } 1420 1421 static int pri_wm_latency_open(struct inode *inode, struct file *file) 1422 { 1423 struct drm_i915_private *dev_priv = inode->i_private; 1424 1425 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) 1426 return -ENODEV; 1427 1428 return single_open(file, pri_wm_latency_show, dev_priv); 1429 } 1430 1431 static int spr_wm_latency_open(struct inode *inode, struct file *file) 1432 { 1433 struct drm_i915_private *dev_priv = inode->i_private; 1434 1435 if (HAS_GMCH(dev_priv)) 1436 return -ENODEV; 1437 1438 return single_open(file, spr_wm_latency_show, dev_priv); 1439 } 1440 1441 static int cur_wm_latency_open(struct inode *inode, struct file *file) 1442 { 1443 struct drm_i915_private *dev_priv = inode->i_private; 1444 1445 if (HAS_GMCH(dev_priv)) 1446 return -ENODEV; 1447 1448 return single_open(file, cur_wm_latency_show, dev_priv); 1449 } 1450 1451 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, 1452 size_t len, loff_t *offp, u16 wm[8]) 1453 { 1454 struct seq_file *m = file->private_data; 1455 struct drm_i915_private *dev_priv = m->private; 1456 struct drm_device *dev = &dev_priv->drm; 1457 u16 new[8] = { 0 }; 1458 int num_levels; 1459 int level; 1460 int ret; 1461 char tmp[32]; 1462 1463 if (IS_CHERRYVIEW(dev_priv)) 1464 num_levels = 3; 1465 else if (IS_VALLEYVIEW(dev_priv)) 1466 num_levels = 1; 1467 else if (IS_G4X(dev_priv)) 1468 num_levels = 3; 1469 else 1470 num_levels = ilk_wm_max_level(dev_priv) + 1; 1471 1472 if (len >= sizeof(tmp)) 1473 return -EINVAL; 1474 1475 if (copy_from_user(tmp, ubuf, len)) 1476 return -EFAULT; 1477 1478 tmp[len] = '\0'; 1479 1480 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", 1481 &new[0], &new[1], &new[2], &new[3], 1482 &new[4], &new[5], &new[6], &new[7]); 1483 if (ret != num_levels) 1484 return -EINVAL; 1485 1486 drm_modeset_lock_all(dev); 1487 1488 for (level = 0; level < num_levels; level++) 1489 wm[level] = new[level]; 1490 1491 drm_modeset_unlock_all(dev); 1492 1493 return len; 1494 } 1495 1496 1497 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, 1498 size_t len, loff_t *offp) 1499 { 1500 struct seq_file *m = file->private_data; 1501 struct drm_i915_private *dev_priv = m->private; 1502 u16 *latencies; 1503 1504 if (DISPLAY_VER(dev_priv) >= 9) 1505 latencies = dev_priv->display.wm.skl_latency; 1506 else 1507 latencies = dev_priv->display.wm.pri_latency; 1508 1509 return wm_latency_write(file, ubuf, len, offp, latencies); 1510 } 1511 1512 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, 1513 size_t len, loff_t *offp) 1514 { 1515 struct seq_file *m = file->private_data; 1516 struct drm_i915_private *dev_priv = m->private; 1517 u16 *latencies; 1518 1519 if (DISPLAY_VER(dev_priv) >= 9) 1520 latencies = dev_priv->display.wm.skl_latency; 1521 else 1522 latencies = dev_priv->display.wm.spr_latency; 1523 1524 return wm_latency_write(file, ubuf, len, offp, latencies); 1525 } 1526 1527 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, 1528 size_t len, loff_t *offp) 1529 { 1530 struct seq_file *m = file->private_data; 1531 struct drm_i915_private *dev_priv = m->private; 1532 u16 *latencies; 1533 1534 if (DISPLAY_VER(dev_priv) >= 9) 1535 latencies = dev_priv->display.wm.skl_latency; 1536 else 1537 latencies = dev_priv->display.wm.cur_latency; 1538 1539 return wm_latency_write(file, ubuf, len, offp, latencies); 1540 } 1541 1542 static const struct file_operations i915_pri_wm_latency_fops = { 1543 .owner = THIS_MODULE, 1544 .open = pri_wm_latency_open, 1545 .read = seq_read, 1546 .llseek = seq_lseek, 1547 .release = single_release, 1548 .write = pri_wm_latency_write 1549 }; 1550 1551 static const struct file_operations i915_spr_wm_latency_fops = { 1552 .owner = THIS_MODULE, 1553 .open = spr_wm_latency_open, 1554 .read = seq_read, 1555 .llseek = seq_lseek, 1556 .release = single_release, 1557 .write = spr_wm_latency_write 1558 }; 1559 1560 static const struct file_operations i915_cur_wm_latency_fops = { 1561 .owner = THIS_MODULE, 1562 .open = cur_wm_latency_open, 1563 .read = seq_read, 1564 .llseek = seq_lseek, 1565 .release = single_release, 1566 .write = cur_wm_latency_write 1567 }; 1568 1569 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) 1570 { 1571 struct drm_i915_private *dev_priv = m->private; 1572 struct intel_hotplug *hotplug = &dev_priv->display.hotplug; 1573 1574 /* Synchronize with everything first in case there's been an HPD 1575 * storm, but we haven't finished handling it in the kernel yet 1576 */ 1577 intel_synchronize_irq(dev_priv); 1578 flush_work(&dev_priv->display.hotplug.dig_port_work); 1579 flush_delayed_work(&dev_priv->display.hotplug.hotplug_work); 1580 1581 seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); 1582 seq_printf(m, "Detected: %s\n", 1583 str_yes_no(delayed_work_pending(&hotplug->reenable_work))); 1584 1585 return 0; 1586 } 1587 1588 static ssize_t i915_hpd_storm_ctl_write(struct file *file, 1589 const char __user *ubuf, size_t len, 1590 loff_t *offp) 1591 { 1592 struct seq_file *m = file->private_data; 1593 struct drm_i915_private *dev_priv = m->private; 1594 struct intel_hotplug *hotplug = &dev_priv->display.hotplug; 1595 unsigned int new_threshold; 1596 int i; 1597 char *newline; 1598 char tmp[16]; 1599 1600 if (len >= sizeof(tmp)) 1601 return -EINVAL; 1602 1603 if (copy_from_user(tmp, ubuf, len)) 1604 return -EFAULT; 1605 1606 tmp[len] = '\0'; 1607 1608 /* Strip newline, if any */ 1609 newline = strchr(tmp, '\n'); 1610 if (newline) 1611 *newline = '\0'; 1612 1613 if (strcmp(tmp, "reset") == 0) 1614 new_threshold = HPD_STORM_DEFAULT_THRESHOLD; 1615 else if (kstrtouint(tmp, 10, &new_threshold) != 0) 1616 return -EINVAL; 1617 1618 if (new_threshold > 0) 1619 drm_dbg_kms(&dev_priv->drm, 1620 "Setting HPD storm detection threshold to %d\n", 1621 new_threshold); 1622 else 1623 drm_dbg_kms(&dev_priv->drm, "Disabling HPD storm detection\n"); 1624 1625 spin_lock_irq(&dev_priv->irq_lock); 1626 hotplug->hpd_storm_threshold = new_threshold; 1627 /* Reset the HPD storm stats so we don't accidentally trigger a storm */ 1628 for_each_hpd_pin(i) 1629 hotplug->stats[i].count = 0; 1630 spin_unlock_irq(&dev_priv->irq_lock); 1631 1632 /* Re-enable hpd immediately if we were in an irq storm */ 1633 flush_delayed_work(&dev_priv->display.hotplug.reenable_work); 1634 1635 return len; 1636 } 1637 1638 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) 1639 { 1640 return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); 1641 } 1642 1643 static const struct file_operations i915_hpd_storm_ctl_fops = { 1644 .owner = THIS_MODULE, 1645 .open = i915_hpd_storm_ctl_open, 1646 .read = seq_read, 1647 .llseek = seq_lseek, 1648 .release = single_release, 1649 .write = i915_hpd_storm_ctl_write 1650 }; 1651 1652 static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data) 1653 { 1654 struct drm_i915_private *dev_priv = m->private; 1655 1656 seq_printf(m, "Enabled: %s\n", 1657 str_yes_no(dev_priv->display.hotplug.hpd_short_storm_enabled)); 1658 1659 return 0; 1660 } 1661 1662 static int 1663 i915_hpd_short_storm_ctl_open(struct inode *inode, struct file *file) 1664 { 1665 return single_open(file, i915_hpd_short_storm_ctl_show, 1666 inode->i_private); 1667 } 1668 1669 static ssize_t i915_hpd_short_storm_ctl_write(struct file *file, 1670 const char __user *ubuf, 1671 size_t len, loff_t *offp) 1672 { 1673 struct seq_file *m = file->private_data; 1674 struct drm_i915_private *dev_priv = m->private; 1675 struct intel_hotplug *hotplug = &dev_priv->display.hotplug; 1676 char *newline; 1677 char tmp[16]; 1678 int i; 1679 bool new_state; 1680 1681 if (len >= sizeof(tmp)) 1682 return -EINVAL; 1683 1684 if (copy_from_user(tmp, ubuf, len)) 1685 return -EFAULT; 1686 1687 tmp[len] = '\0'; 1688 1689 /* Strip newline, if any */ 1690 newline = strchr(tmp, '\n'); 1691 if (newline) 1692 *newline = '\0'; 1693 1694 /* Reset to the "default" state for this system */ 1695 if (strcmp(tmp, "reset") == 0) 1696 new_state = !HAS_DP_MST(dev_priv); 1697 else if (kstrtobool(tmp, &new_state) != 0) 1698 return -EINVAL; 1699 1700 drm_dbg_kms(&dev_priv->drm, "%sabling HPD short storm detection\n", 1701 new_state ? "En" : "Dis"); 1702 1703 spin_lock_irq(&dev_priv->irq_lock); 1704 hotplug->hpd_short_storm_enabled = new_state; 1705 /* Reset the HPD storm stats so we don't accidentally trigger a storm */ 1706 for_each_hpd_pin(i) 1707 hotplug->stats[i].count = 0; 1708 spin_unlock_irq(&dev_priv->irq_lock); 1709 1710 /* Re-enable hpd immediately if we were in an irq storm */ 1711 flush_delayed_work(&dev_priv->display.hotplug.reenable_work); 1712 1713 return len; 1714 } 1715 1716 static const struct file_operations i915_hpd_short_storm_ctl_fops = { 1717 .owner = THIS_MODULE, 1718 .open = i915_hpd_short_storm_ctl_open, 1719 .read = seq_read, 1720 .llseek = seq_lseek, 1721 .release = single_release, 1722 .write = i915_hpd_short_storm_ctl_write, 1723 }; 1724 1725 static int i915_drrs_ctl_set(void *data, u64 val) 1726 { 1727 struct drm_i915_private *dev_priv = data; 1728 struct drm_device *dev = &dev_priv->drm; 1729 struct intel_crtc *crtc; 1730 1731 for_each_intel_crtc(dev, crtc) { 1732 struct intel_crtc_state *crtc_state; 1733 struct drm_crtc_commit *commit; 1734 int ret; 1735 1736 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); 1737 if (ret) 1738 return ret; 1739 1740 crtc_state = to_intel_crtc_state(crtc->base.state); 1741 1742 if (!crtc_state->hw.active || 1743 !crtc_state->has_drrs) 1744 goto out; 1745 1746 commit = crtc_state->uapi.commit; 1747 if (commit) { 1748 ret = wait_for_completion_interruptible(&commit->hw_done); 1749 if (ret) 1750 goto out; 1751 } 1752 1753 drm_dbg(&dev_priv->drm, 1754 "Manually %sactivating DRRS\n", val ? "" : "de"); 1755 1756 if (val) 1757 intel_drrs_activate(crtc_state); 1758 else 1759 intel_drrs_deactivate(crtc_state); 1760 1761 out: 1762 drm_modeset_unlock(&crtc->base.mutex); 1763 if (ret) 1764 return ret; 1765 } 1766 1767 return 0; 1768 } 1769 1770 DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n"); 1771 1772 static ssize_t 1773 i915_fifo_underrun_reset_write(struct file *filp, 1774 const char __user *ubuf, 1775 size_t cnt, loff_t *ppos) 1776 { 1777 struct drm_i915_private *dev_priv = filp->private_data; 1778 struct intel_crtc *crtc; 1779 struct drm_device *dev = &dev_priv->drm; 1780 int ret; 1781 bool reset; 1782 1783 ret = kstrtobool_from_user(ubuf, cnt, &reset); 1784 if (ret) 1785 return ret; 1786 1787 if (!reset) 1788 return cnt; 1789 1790 for_each_intel_crtc(dev, crtc) { 1791 struct drm_crtc_commit *commit; 1792 struct intel_crtc_state *crtc_state; 1793 1794 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); 1795 if (ret) 1796 return ret; 1797 1798 crtc_state = to_intel_crtc_state(crtc->base.state); 1799 commit = crtc_state->uapi.commit; 1800 if (commit) { 1801 ret = wait_for_completion_interruptible(&commit->hw_done); 1802 if (!ret) 1803 ret = wait_for_completion_interruptible(&commit->flip_done); 1804 } 1805 1806 if (!ret && crtc_state->hw.active) { 1807 drm_dbg_kms(&dev_priv->drm, 1808 "Re-arming FIFO underruns on pipe %c\n", 1809 pipe_name(crtc->pipe)); 1810 1811 intel_crtc_arm_fifo_underrun(crtc, crtc_state); 1812 } 1813 1814 drm_modeset_unlock(&crtc->base.mutex); 1815 1816 if (ret) 1817 return ret; 1818 } 1819 1820 intel_fbc_reset_underrun(dev_priv); 1821 1822 return cnt; 1823 } 1824 1825 static const struct file_operations i915_fifo_underrun_reset_ops = { 1826 .owner = THIS_MODULE, 1827 .open = simple_open, 1828 .write = i915_fifo_underrun_reset_write, 1829 .llseek = default_llseek, 1830 }; 1831 1832 static const struct drm_info_list intel_display_debugfs_list[] = { 1833 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, 1834 {"i915_ips_status", i915_ips_status, 0}, 1835 {"i915_sr_status", i915_sr_status, 0}, 1836 {"i915_opregion", i915_opregion, 0}, 1837 {"i915_vbt", i915_vbt, 0}, 1838 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, 1839 {"i915_edp_psr_status", i915_edp_psr_status, 0}, 1840 {"i915_power_domain_info", i915_power_domain_info, 0}, 1841 {"i915_display_info", i915_display_info, 0}, 1842 {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, 1843 {"i915_dp_mst_info", i915_dp_mst_info, 0}, 1844 {"i915_ddb_info", i915_ddb_info, 0}, 1845 {"i915_drrs_status", i915_drrs_status, 0}, 1846 {"i915_lpsp_status", i915_lpsp_status, 0}, 1847 }; 1848 1849 static const struct { 1850 const char *name; 1851 const struct file_operations *fops; 1852 } intel_display_debugfs_files[] = { 1853 {"i915_fifo_underrun_reset", &i915_fifo_underrun_reset_ops}, 1854 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, 1855 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, 1856 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, 1857 {"i915_dp_test_data", &i915_displayport_test_data_fops}, 1858 {"i915_dp_test_type", &i915_displayport_test_type_fops}, 1859 {"i915_dp_test_active", &i915_displayport_test_active_fops}, 1860 {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}, 1861 {"i915_hpd_short_storm_ctl", &i915_hpd_short_storm_ctl_fops}, 1862 {"i915_drrs_ctl", &i915_drrs_ctl_fops}, 1863 {"i915_edp_psr_debug", &i915_edp_psr_debug_fops}, 1864 }; 1865 1866 void intel_display_debugfs_register(struct drm_i915_private *i915) 1867 { 1868 struct drm_minor *minor = i915->drm.primary; 1869 int i; 1870 1871 for (i = 0; i < ARRAY_SIZE(intel_display_debugfs_files); i++) { 1872 debugfs_create_file(intel_display_debugfs_files[i].name, 1873 S_IRUGO | S_IWUSR, 1874 minor->debugfs_root, 1875 to_i915(minor->dev), 1876 intel_display_debugfs_files[i].fops); 1877 } 1878 1879 drm_debugfs_create_files(intel_display_debugfs_list, 1880 ARRAY_SIZE(intel_display_debugfs_list), 1881 minor->debugfs_root, minor); 1882 1883 intel_dmc_debugfs_register(i915); 1884 intel_fbc_debugfs_register(i915); 1885 skl_watermark_ipc_debugfs_register(i915); 1886 } 1887 1888 static int i915_panel_show(struct seq_file *m, void *data) 1889 { 1890 struct drm_connector *connector = m->private; 1891 struct intel_dp *intel_dp = 1892 intel_attached_dp(to_intel_connector(connector)); 1893 1894 if (connector->status != connector_status_connected) 1895 return -ENODEV; 1896 1897 seq_printf(m, "Panel power up delay: %d\n", 1898 intel_dp->pps.panel_power_up_delay); 1899 seq_printf(m, "Panel power down delay: %d\n", 1900 intel_dp->pps.panel_power_down_delay); 1901 seq_printf(m, "Backlight on delay: %d\n", 1902 intel_dp->pps.backlight_on_delay); 1903 seq_printf(m, "Backlight off delay: %d\n", 1904 intel_dp->pps.backlight_off_delay); 1905 1906 return 0; 1907 } 1908 DEFINE_SHOW_ATTRIBUTE(i915_panel); 1909 1910 static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data) 1911 { 1912 struct drm_connector *connector = m->private; 1913 struct drm_i915_private *i915 = to_i915(connector->dev); 1914 struct intel_connector *intel_connector = to_intel_connector(connector); 1915 int ret; 1916 1917 ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1918 if (ret) 1919 return ret; 1920 1921 if (!connector->encoder || connector->status != connector_status_connected) { 1922 ret = -ENODEV; 1923 goto out; 1924 } 1925 1926 seq_printf(m, "%s:%d HDCP version: ", connector->name, 1927 connector->base.id); 1928 intel_hdcp_info(m, intel_connector); 1929 1930 out: 1931 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1932 1933 return ret; 1934 } 1935 DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability); 1936 1937 static int i915_psr_status_show(struct seq_file *m, void *data) 1938 { 1939 struct drm_connector *connector = m->private; 1940 struct intel_dp *intel_dp = 1941 intel_attached_dp(to_intel_connector(connector)); 1942 1943 return intel_psr_status(m, intel_dp); 1944 } 1945 DEFINE_SHOW_ATTRIBUTE(i915_psr_status); 1946 1947 static int i915_lpsp_capability_show(struct seq_file *m, void *data) 1948 { 1949 struct drm_connector *connector = m->private; 1950 struct drm_i915_private *i915 = to_i915(connector->dev); 1951 struct intel_encoder *encoder; 1952 bool lpsp_capable = false; 1953 1954 encoder = intel_attached_encoder(to_intel_connector(connector)); 1955 if (!encoder) 1956 return -ENODEV; 1957 1958 if (connector->status != connector_status_connected) 1959 return -ENODEV; 1960 1961 if (DISPLAY_VER(i915) >= 13) 1962 lpsp_capable = encoder->port <= PORT_B; 1963 else if (DISPLAY_VER(i915) >= 12) 1964 /* 1965 * Actually TGL can drive LPSP on port till DDI_C 1966 * but there is no physical connected DDI_C on TGL sku's, 1967 * even driver is not initilizing DDI_C port for gen12. 1968 */ 1969 lpsp_capable = encoder->port <= PORT_B; 1970 else if (DISPLAY_VER(i915) == 11) 1971 lpsp_capable = (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 1972 connector->connector_type == DRM_MODE_CONNECTOR_eDP); 1973 else if (IS_DISPLAY_VER(i915, 9, 10)) 1974 lpsp_capable = (encoder->port == PORT_A && 1975 (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 1976 connector->connector_type == DRM_MODE_CONNECTOR_eDP || 1977 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)); 1978 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 1979 lpsp_capable = connector->connector_type == DRM_MODE_CONNECTOR_eDP; 1980 1981 seq_printf(m, "LPSP: %s\n", lpsp_capable ? "capable" : "incapable"); 1982 1983 return 0; 1984 } 1985 DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability); 1986 1987 static int i915_dsc_fec_support_show(struct seq_file *m, void *data) 1988 { 1989 struct drm_connector *connector = m->private; 1990 struct drm_device *dev = connector->dev; 1991 struct drm_crtc *crtc; 1992 struct intel_dp *intel_dp; 1993 struct drm_modeset_acquire_ctx ctx; 1994 struct intel_crtc_state *crtc_state = NULL; 1995 int ret = 0; 1996 bool try_again = false; 1997 1998 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1999 2000 do { 2001 try_again = false; 2002 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, 2003 &ctx); 2004 if (ret) { 2005 if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) { 2006 try_again = true; 2007 continue; 2008 } 2009 break; 2010 } 2011 crtc = connector->state->crtc; 2012 if (connector->status != connector_status_connected || !crtc) { 2013 ret = -ENODEV; 2014 break; 2015 } 2016 ret = drm_modeset_lock(&crtc->mutex, &ctx); 2017 if (ret == -EDEADLK) { 2018 ret = drm_modeset_backoff(&ctx); 2019 if (!ret) { 2020 try_again = true; 2021 continue; 2022 } 2023 break; 2024 } else if (ret) { 2025 break; 2026 } 2027 intel_dp = intel_attached_dp(to_intel_connector(connector)); 2028 crtc_state = to_intel_crtc_state(crtc->state); 2029 seq_printf(m, "DSC_Enabled: %s\n", 2030 str_yes_no(crtc_state->dsc.compression_enable)); 2031 seq_printf(m, "DSC_Sink_Support: %s\n", 2032 str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))); 2033 seq_printf(m, "Force_DSC_Enable: %s\n", 2034 str_yes_no(intel_dp->force_dsc_en)); 2035 if (!intel_dp_is_edp(intel_dp)) 2036 seq_printf(m, "FEC_Sink_Support: %s\n", 2037 str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable))); 2038 } while (try_again); 2039 2040 drm_modeset_drop_locks(&ctx); 2041 drm_modeset_acquire_fini(&ctx); 2042 2043 return ret; 2044 } 2045 2046 static ssize_t i915_dsc_fec_support_write(struct file *file, 2047 const char __user *ubuf, 2048 size_t len, loff_t *offp) 2049 { 2050 bool dsc_enable = false; 2051 int ret; 2052 struct drm_connector *connector = 2053 ((struct seq_file *)file->private_data)->private; 2054 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 2055 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2056 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2057 2058 if (len == 0) 2059 return 0; 2060 2061 drm_dbg(&i915->drm, 2062 "Copied %zu bytes from user to force DSC\n", len); 2063 2064 ret = kstrtobool_from_user(ubuf, len, &dsc_enable); 2065 if (ret < 0) 2066 return ret; 2067 2068 drm_dbg(&i915->drm, "Got %s for DSC Enable\n", 2069 (dsc_enable) ? "true" : "false"); 2070 intel_dp->force_dsc_en = dsc_enable; 2071 2072 *offp += len; 2073 return len; 2074 } 2075 2076 static int i915_dsc_fec_support_open(struct inode *inode, 2077 struct file *file) 2078 { 2079 return single_open(file, i915_dsc_fec_support_show, 2080 inode->i_private); 2081 } 2082 2083 static const struct file_operations i915_dsc_fec_support_fops = { 2084 .owner = THIS_MODULE, 2085 .open = i915_dsc_fec_support_open, 2086 .read = seq_read, 2087 .llseek = seq_lseek, 2088 .release = single_release, 2089 .write = i915_dsc_fec_support_write 2090 }; 2091 2092 static int i915_dsc_bpc_show(struct seq_file *m, void *data) 2093 { 2094 struct drm_connector *connector = m->private; 2095 struct drm_device *dev = connector->dev; 2096 struct drm_crtc *crtc; 2097 struct intel_crtc_state *crtc_state; 2098 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 2099 int ret; 2100 2101 if (!encoder) 2102 return -ENODEV; 2103 2104 ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex); 2105 if (ret) 2106 return ret; 2107 2108 crtc = connector->state->crtc; 2109 if (connector->status != connector_status_connected || !crtc) { 2110 ret = -ENODEV; 2111 goto out; 2112 } 2113 2114 crtc_state = to_intel_crtc_state(crtc->state); 2115 seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component); 2116 2117 out: drm_modeset_unlock(&dev->mode_config.connection_mutex); 2118 2119 return ret; 2120 } 2121 2122 static ssize_t i915_dsc_bpc_write(struct file *file, 2123 const char __user *ubuf, 2124 size_t len, loff_t *offp) 2125 { 2126 struct drm_connector *connector = 2127 ((struct seq_file *)file->private_data)->private; 2128 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 2129 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2130 int dsc_bpc = 0; 2131 int ret; 2132 2133 ret = kstrtoint_from_user(ubuf, len, 0, &dsc_bpc); 2134 if (ret < 0) 2135 return ret; 2136 2137 intel_dp->force_dsc_bpc = dsc_bpc; 2138 *offp += len; 2139 2140 return len; 2141 } 2142 2143 static int i915_dsc_bpc_open(struct inode *inode, 2144 struct file *file) 2145 { 2146 return single_open(file, i915_dsc_bpc_show, inode->i_private); 2147 } 2148 2149 static const struct file_operations i915_dsc_bpc_fops = { 2150 .owner = THIS_MODULE, 2151 .open = i915_dsc_bpc_open, 2152 .read = seq_read, 2153 .llseek = seq_lseek, 2154 .release = single_release, 2155 .write = i915_dsc_bpc_write 2156 }; 2157 2158 /* 2159 * Returns the Current CRTC's bpc. 2160 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc 2161 */ 2162 static int i915_current_bpc_show(struct seq_file *m, void *data) 2163 { 2164 struct intel_crtc *crtc = to_intel_crtc(m->private); 2165 struct intel_crtc_state *crtc_state; 2166 int ret; 2167 2168 ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); 2169 if (ret) 2170 return ret; 2171 2172 crtc_state = to_intel_crtc_state(crtc->base.state); 2173 seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3); 2174 2175 drm_modeset_unlock(&crtc->base.mutex); 2176 2177 return ret; 2178 } 2179 DEFINE_SHOW_ATTRIBUTE(i915_current_bpc); 2180 2181 /** 2182 * intel_connector_debugfs_add - add i915 specific connector debugfs files 2183 * @connector: pointer to a registered drm_connector 2184 * 2185 * Cleanup will be done by drm_connector_unregister() through a call to 2186 * drm_debugfs_connector_remove(). 2187 */ 2188 void intel_connector_debugfs_add(struct intel_connector *intel_connector) 2189 { 2190 struct drm_connector *connector = &intel_connector->base; 2191 struct dentry *root = connector->debugfs_entry; 2192 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2193 2194 /* The connector must have been registered beforehands. */ 2195 if (!root) 2196 return; 2197 2198 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 2199 debugfs_create_file("i915_panel_timings", S_IRUGO, root, 2200 connector, &i915_panel_fops); 2201 debugfs_create_file("i915_psr_sink_status", S_IRUGO, root, 2202 connector, &i915_psr_sink_status_fops); 2203 } 2204 2205 if (HAS_PSR(dev_priv) && 2206 connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 2207 debugfs_create_file("i915_psr_status", 0444, root, 2208 connector, &i915_psr_status_fops); 2209 } 2210 2211 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2212 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 2213 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) { 2214 debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root, 2215 connector, &i915_hdcp_sink_capability_fops); 2216 } 2217 2218 if (DISPLAY_VER(dev_priv) >= 11 && 2219 ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && 2220 !to_intel_connector(connector)->mst_port) || 2221 connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 2222 debugfs_create_file("i915_dsc_fec_support", 0644, root, 2223 connector, &i915_dsc_fec_support_fops); 2224 2225 debugfs_create_file("i915_dsc_bpc", 0644, root, 2226 connector, &i915_dsc_bpc_fops); 2227 } 2228 2229 if (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 2230 connector->connector_type == DRM_MODE_CONNECTOR_eDP || 2231 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2232 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 2233 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 2234 debugfs_create_file("i915_lpsp_capability", 0444, root, 2235 connector, &i915_lpsp_capability_fops); 2236 } 2237 2238 /** 2239 * intel_crtc_debugfs_add - add i915 specific crtc debugfs files 2240 * @crtc: pointer to a drm_crtc 2241 * 2242 * Failure to add debugfs entries should generally be ignored. 2243 */ 2244 void intel_crtc_debugfs_add(struct drm_crtc *crtc) 2245 { 2246 if (!crtc->debugfs_entry) 2247 return; 2248 2249 crtc_updates_add(crtc); 2250 intel_fbc_crtc_debugfs_add(to_intel_crtc(crtc)); 2251 2252 debugfs_create_file("i915_current_bpc", 0444, crtc->debugfs_entry, crtc, 2253 &i915_current_bpc_fops); 2254 } 2255