1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 26 #ifndef __INTEL_DISPLAY_TYPES_H__ 27 #define __INTEL_DISPLAY_TYPES_H__ 28 29 #include <linux/i2c.h> 30 #include <linux/pm_qos.h> 31 #include <linux/pwm.h> 32 #include <linux/sched/clock.h> 33 34 #include <drm/display/drm_dp_dual_mode_helper.h> 35 #include <drm/display/drm_dp_mst_helper.h> 36 #include <drm/display/drm_dsc.h> 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_encoder.h> 40 #include <drm/drm_fourcc.h> 41 #include <drm/drm_framebuffer.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_rect.h> 44 #include <drm/drm_vblank.h> 45 #include <drm/drm_vblank_work.h> 46 #include <drm/i915_hdcp_interface.h> 47 #include <media/cec-notifier.h> 48 49 #include "i915_vma.h" 50 #include "i915_vma_types.h" 51 #include "intel_bios.h" 52 #include "intel_display.h" 53 #include "intel_display_limits.h" 54 #include "intel_display_power.h" 55 #include "intel_dpll_mgr.h" 56 #include "intel_wm_types.h" 57 58 struct drm_printer; 59 struct __intel_global_objs_state; 60 struct intel_ddi_buf_trans; 61 struct intel_fbc; 62 struct intel_connector; 63 struct intel_tc_port; 64 65 /* 66 * Display related stuff 67 */ 68 69 /* these are outputs from the chip - integrated only 70 external chips are via DVO or SDVO output */ 71 enum intel_output_type { 72 INTEL_OUTPUT_UNUSED = 0, 73 INTEL_OUTPUT_ANALOG = 1, 74 INTEL_OUTPUT_DVO = 2, 75 INTEL_OUTPUT_SDVO = 3, 76 INTEL_OUTPUT_LVDS = 4, 77 INTEL_OUTPUT_TVOUT = 5, 78 INTEL_OUTPUT_HDMI = 6, 79 INTEL_OUTPUT_DP = 7, 80 INTEL_OUTPUT_EDP = 8, 81 INTEL_OUTPUT_DSI = 9, 82 INTEL_OUTPUT_DDI = 10, 83 INTEL_OUTPUT_DP_MST = 11, 84 }; 85 86 enum hdmi_force_audio { 87 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 88 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 89 HDMI_AUDIO_AUTO, /* trust EDID */ 90 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 91 }; 92 93 /* "Broadcast RGB" property */ 94 enum intel_broadcast_rgb { 95 INTEL_BROADCAST_RGB_AUTO, 96 INTEL_BROADCAST_RGB_FULL, 97 INTEL_BROADCAST_RGB_LIMITED, 98 }; 99 100 struct intel_fb_view { 101 /* 102 * The remap information used in the remapped and rotated views to 103 * create the DMA scatter-gather list for each FB color plane. This sg 104 * list is created along with the view type (gtt.type) specific 105 * i915_vma object and contains the list of FB object pages (reordered 106 * in the rotated view) that are visible in the view. 107 * In the normal view the FB object's backing store sg list is used 108 * directly and hence the remap information here is not used. 109 */ 110 struct i915_gtt_view gtt; 111 112 /* 113 * The GTT view (gtt.type) specific information for each FB color 114 * plane. In the normal GTT view all formats (up to 4 color planes), 115 * in the rotated and remapped GTT view all no-CCS formats (up to 2 116 * color planes) are supported. 117 * 118 * The view information shared by all FB color planes in the FB, 119 * like dst x/y and src/dst width, is stored separately in 120 * intel_plane_state. 121 */ 122 struct i915_color_plane_view { 123 u32 offset; 124 unsigned int x, y; 125 /* 126 * Plane stride in: 127 * bytes for 0/180 degree rotation 128 * pixels for 90/270 degree rotation 129 */ 130 unsigned int mapping_stride; 131 unsigned int scanout_stride; 132 } color_plane[4]; 133 }; 134 135 struct intel_framebuffer { 136 struct drm_framebuffer base; 137 struct intel_frontbuffer *frontbuffer; 138 139 /* Params to remap the FB pages and program the plane registers in each view. */ 140 struct intel_fb_view normal_view; 141 union { 142 struct intel_fb_view rotated_view; 143 struct intel_fb_view remapped_view; 144 }; 145 146 struct i915_address_space *dpt_vm; 147 }; 148 149 enum intel_hotplug_state { 150 INTEL_HOTPLUG_UNCHANGED, 151 INTEL_HOTPLUG_CHANGED, 152 INTEL_HOTPLUG_RETRY, 153 }; 154 155 struct intel_encoder { 156 struct drm_encoder base; 157 158 enum intel_output_type type; 159 enum port port; 160 u16 cloneable; 161 u8 pipe_mask; 162 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder, 163 struct intel_connector *connector); 164 enum intel_output_type (*compute_output_type)(struct intel_encoder *, 165 struct intel_crtc_state *, 166 struct drm_connector_state *); 167 int (*compute_config)(struct intel_encoder *, 168 struct intel_crtc_state *, 169 struct drm_connector_state *); 170 int (*compute_config_late)(struct intel_encoder *, 171 struct intel_crtc_state *, 172 struct drm_connector_state *); 173 void (*pre_pll_enable)(struct intel_atomic_state *, 174 struct intel_encoder *, 175 const struct intel_crtc_state *, 176 const struct drm_connector_state *); 177 void (*pre_enable)(struct intel_atomic_state *, 178 struct intel_encoder *, 179 const struct intel_crtc_state *, 180 const struct drm_connector_state *); 181 void (*enable)(struct intel_atomic_state *, 182 struct intel_encoder *, 183 const struct intel_crtc_state *, 184 const struct drm_connector_state *); 185 void (*disable)(struct intel_atomic_state *, 186 struct intel_encoder *, 187 const struct intel_crtc_state *, 188 const struct drm_connector_state *); 189 void (*post_disable)(struct intel_atomic_state *, 190 struct intel_encoder *, 191 const struct intel_crtc_state *, 192 const struct drm_connector_state *); 193 void (*post_pll_disable)(struct intel_atomic_state *, 194 struct intel_encoder *, 195 const struct intel_crtc_state *, 196 const struct drm_connector_state *); 197 void (*update_pipe)(struct intel_atomic_state *, 198 struct intel_encoder *, 199 const struct intel_crtc_state *, 200 const struct drm_connector_state *); 201 /* Read out the current hw state of this connector, returning true if 202 * the encoder is active. If the encoder is enabled it also set the pipe 203 * it is connected to in the pipe parameter. */ 204 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); 205 /* Reconstructs the equivalent mode flags for the current hardware 206 * state. This must be called _after_ display->get_pipe_config has 207 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 208 * be set correctly before calling this function. */ 209 void (*get_config)(struct intel_encoder *, 210 struct intel_crtc_state *pipe_config); 211 212 /* 213 * Optional hook called during init/resume to sync any state 214 * stored in the encoder (eg. DP link parameters) wrt. the HW state. 215 */ 216 void (*sync_state)(struct intel_encoder *encoder, 217 const struct intel_crtc_state *crtc_state); 218 219 /* 220 * Optional hook, returning true if this encoder allows a fastset 221 * during the initial commit, false otherwise. 222 */ 223 bool (*initial_fastset_check)(struct intel_encoder *encoder, 224 struct intel_crtc_state *crtc_state); 225 226 /* 227 * Acquires the power domains needed for an active encoder during 228 * hardware state readout. 229 */ 230 void (*get_power_domains)(struct intel_encoder *encoder, 231 struct intel_crtc_state *crtc_state); 232 /* 233 * Called during system suspend after all pending requests for the 234 * encoder are flushed (for example for DP AUX transactions) and 235 * device interrupts are disabled. 236 * All modeset locks are held while the hook is called. 237 */ 238 void (*suspend)(struct intel_encoder *); 239 /* 240 * Called without the modeset locks held after the suspend() hook for 241 * all encoders have been called. 242 */ 243 void (*suspend_complete)(struct intel_encoder *encoder); 244 /* 245 * Called during system reboot/shutdown after all the 246 * encoders have been disabled and suspended. 247 * All modeset locks are held while the hook is called. 248 */ 249 void (*shutdown)(struct intel_encoder *encoder); 250 /* 251 * Called without the modeset locks held after the shutdown() hook for 252 * all encoders have been called. 253 */ 254 void (*shutdown_complete)(struct intel_encoder *encoder); 255 /* 256 * Enable/disable the clock to the port. 257 */ 258 void (*enable_clock)(struct intel_encoder *encoder, 259 const struct intel_crtc_state *crtc_state); 260 void (*disable_clock)(struct intel_encoder *encoder); 261 /* 262 * Returns whether the port clock is enabled or not. 263 */ 264 bool (*is_clock_enabled)(struct intel_encoder *encoder); 265 /* 266 * Returns the PLL type the port uses. 267 */ 268 enum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *encoder, 269 const struct intel_crtc_state *crtc_state); 270 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder, 271 const struct intel_crtc_state *crtc_state, 272 int *n_entries); 273 void (*set_signal_levels)(struct intel_encoder *encoder, 274 const struct intel_crtc_state *crtc_state); 275 276 enum hpd_pin hpd_pin; 277 enum intel_display_power_domain power_domain; 278 279 /* VBT information for this encoder (may be NULL for older platforms) */ 280 const struct intel_bios_encoder_data *devdata; 281 }; 282 283 struct intel_panel_bl_funcs { 284 /* Connector and platform specific backlight functions */ 285 int (*setup)(struct intel_connector *connector, enum pipe pipe); 286 u32 (*get)(struct intel_connector *connector, enum pipe pipe); 287 void (*set)(const struct drm_connector_state *conn_state, u32 level); 288 void (*disable)(const struct drm_connector_state *conn_state, u32 level); 289 void (*enable)(const struct intel_crtc_state *crtc_state, 290 const struct drm_connector_state *conn_state, u32 level); 291 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz); 292 }; 293 294 enum drrs_type { 295 DRRS_TYPE_NONE, 296 DRRS_TYPE_STATIC, 297 DRRS_TYPE_SEAMLESS, 298 }; 299 300 struct intel_vbt_panel_data { 301 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 302 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 303 304 /* Feature bits */ 305 int panel_type; 306 unsigned int lvds_dither:1; 307 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 308 309 bool vrr; 310 311 u8 seamless_drrs_min_refresh_rate; 312 enum drrs_type drrs_type; 313 314 struct { 315 int max_link_rate; 316 int rate; 317 int lanes; 318 int preemphasis; 319 int vswing; 320 int bpp; 321 struct edp_power_seq pps; 322 u8 drrs_msa_timing_delay; 323 bool low_vswing; 324 bool initialized; 325 bool hobl; 326 } edp; 327 328 struct { 329 bool enable; 330 bool full_link; 331 bool require_aux_wakeup; 332 int idle_frames; 333 int tp1_wakeup_time_us; 334 int tp2_tp3_wakeup_time_us; 335 int psr2_tp2_tp3_wakeup_time_us; 336 } psr; 337 338 struct { 339 u16 pwm_freq_hz; 340 u16 brightness_precision_bits; 341 u16 hdr_dpcd_refresh_timeout; 342 bool present; 343 bool active_low_pwm; 344 u8 min_brightness; /* min_brightness/255 of max */ 345 s8 controller; /* brightness controller number */ 346 enum intel_backlight_type type; 347 } backlight; 348 349 /* MIPI DSI */ 350 struct { 351 u16 panel_id; 352 struct mipi_config *config; 353 struct mipi_pps_data *pps; 354 u16 bl_ports; 355 u16 cabc_ports; 356 u8 seq_version; 357 u32 size; 358 u8 *data; 359 const u8 *sequence[MIPI_SEQ_MAX]; 360 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 361 enum drm_panel_orientation orientation; 362 } dsi; 363 }; 364 365 struct intel_panel { 366 /* Fixed EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 367 const struct drm_edid *fixed_edid; 368 369 struct list_head fixed_modes; 370 371 /* backlight */ 372 struct { 373 bool present; 374 u32 level; 375 u32 min; 376 u32 max; 377 bool enabled; 378 bool combination_mode; /* gen 2/4 only */ 379 bool active_low_pwm; 380 bool alternate_pwm_increment; /* lpt+ */ 381 382 /* PWM chip */ 383 u32 pwm_level_min; 384 u32 pwm_level_max; 385 bool pwm_enabled; 386 bool util_pin_active_low; /* bxt+ */ 387 u8 controller; /* bxt+ only */ 388 struct pwm_device *pwm; 389 struct pwm_state pwm_state; 390 391 /* DPCD backlight */ 392 union { 393 struct { 394 struct drm_edp_backlight_info info; 395 } vesa; 396 struct { 397 bool sdr_uses_aux; 398 } intel; 399 } edp; 400 401 struct backlight_device *device; 402 403 const struct intel_panel_bl_funcs *funcs; 404 const struct intel_panel_bl_funcs *pwm_funcs; 405 void (*power)(struct intel_connector *, bool enable); 406 } backlight; 407 408 struct intel_vbt_panel_data vbt; 409 }; 410 411 struct intel_digital_port; 412 413 enum check_link_response { 414 HDCP_LINK_PROTECTED = 0, 415 HDCP_TOPOLOGY_CHANGE, 416 HDCP_LINK_INTEGRITY_FAILURE, 417 HDCP_REAUTH_REQUEST 418 }; 419 420 /* 421 * This structure serves as a translation layer between the generic HDCP code 422 * and the bus-specific code. What that means is that HDCP over HDMI differs 423 * from HDCP over DP, so to account for these differences, we need to 424 * communicate with the receiver through this shim. 425 * 426 * For completeness, the 2 buses differ in the following ways: 427 * - DP AUX vs. DDC 428 * HDCP registers on the receiver are set via DP AUX for DP, and 429 * they are set via DDC for HDMI. 430 * - Receiver register offsets 431 * The offsets of the registers are different for DP vs. HDMI 432 * - Receiver register masks/offsets 433 * For instance, the ready bit for the KSV fifo is in a different 434 * place on DP vs HDMI 435 * - Receiver register names 436 * Seriously. In the DP spec, the 16-bit register containing 437 * downstream information is called BINFO, on HDMI it's called 438 * BSTATUS. To confuse matters further, DP has a BSTATUS register 439 * with a completely different definition. 440 * - KSV FIFO 441 * On HDMI, the ksv fifo is read all at once, whereas on DP it must 442 * be read 3 keys at a time 443 * - Aksv output 444 * Since Aksv is hidden in hardware, there's different procedures 445 * to send it over DP AUX vs DDC 446 */ 447 struct intel_hdcp_shim { 448 /* Outputs the transmitter's An and Aksv values to the receiver. */ 449 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an); 450 451 /* Reads the receiver's key selection vector */ 452 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv); 453 454 /* 455 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The 456 * definitions are the same in the respective specs, but the names are 457 * different. Call it BSTATUS since that's the name the HDMI spec 458 * uses and it was there first. 459 */ 460 int (*read_bstatus)(struct intel_digital_port *dig_port, 461 u8 *bstatus); 462 463 /* Determines whether a repeater is present downstream */ 464 int (*repeater_present)(struct intel_digital_port *dig_port, 465 bool *repeater_present); 466 467 /* Reads the receiver's Ri' value */ 468 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri); 469 470 /* Determines if the receiver's KSV FIFO is ready for consumption */ 471 int (*read_ksv_ready)(struct intel_digital_port *dig_port, 472 bool *ksv_ready); 473 474 /* Reads the ksv fifo for num_downstream devices */ 475 int (*read_ksv_fifo)(struct intel_digital_port *dig_port, 476 int num_downstream, u8 *ksv_fifo); 477 478 /* Reads a 32-bit part of V' from the receiver */ 479 int (*read_v_prime_part)(struct intel_digital_port *dig_port, 480 int i, u32 *part); 481 482 /* Enables HDCP signalling on the port */ 483 int (*toggle_signalling)(struct intel_digital_port *dig_port, 484 enum transcoder cpu_transcoder, 485 bool enable); 486 487 /* Enable/Disable stream encryption on DP MST Transport Link */ 488 int (*stream_encryption)(struct intel_connector *connector, 489 bool enable); 490 491 /* Ensures the link is still protected */ 492 bool (*check_link)(struct intel_digital_port *dig_port, 493 struct intel_connector *connector); 494 495 /* Detects panel's hdcp capability. This is optional for HDMI. */ 496 int (*hdcp_capable)(struct intel_digital_port *dig_port, 497 bool *hdcp_capable); 498 499 /* HDCP adaptation(DP/HDMI) required on the port */ 500 enum hdcp_wired_protocol protocol; 501 502 /* Detects whether sink is HDCP2.2 capable */ 503 int (*hdcp_2_2_capable)(struct intel_connector *connector, 504 bool *capable); 505 506 /* Write HDCP2.2 messages */ 507 int (*write_2_2_msg)(struct intel_connector *connector, 508 void *buf, size_t size); 509 510 /* Read HDCP2.2 messages */ 511 int (*read_2_2_msg)(struct intel_connector *connector, 512 u8 msg_id, void *buf, size_t size); 513 514 /* 515 * Implementation of DP HDCP2.2 Errata for the communication of stream 516 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to 517 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. 518 */ 519 int (*config_stream_type)(struct intel_connector *connector, 520 bool is_repeater, u8 type); 521 522 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */ 523 int (*stream_2_2_encryption)(struct intel_connector *connector, 524 bool enable); 525 526 /* HDCP2.2 Link Integrity Check */ 527 int (*check_2_2_link)(struct intel_digital_port *dig_port, 528 struct intel_connector *connector); 529 }; 530 531 struct intel_hdcp { 532 const struct intel_hdcp_shim *shim; 533 /* Mutex for hdcp state of the connector */ 534 struct mutex mutex; 535 u64 value; 536 struct delayed_work check_work; 537 struct work_struct prop_work; 538 539 /* HDCP1.4 Encryption status */ 540 bool hdcp_encrypted; 541 542 /* HDCP2.2 related definitions */ 543 /* Flag indicates whether this connector supports HDCP2.2 or not. */ 544 bool hdcp2_supported; 545 546 /* HDCP2.2 Encryption status */ 547 bool hdcp2_encrypted; 548 549 /* 550 * Content Stream Type defined by content owner. TYPE0(0x0) content can 551 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1) 552 * content can flow only through a link protected by HDCP2.2. 553 */ 554 u8 content_type; 555 556 bool is_paired; 557 bool is_repeater; 558 559 /* 560 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT. 561 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List. 562 * When it rolls over re-auth has to be triggered. 563 */ 564 u32 seq_num_v; 565 566 /* 567 * Count of RepeaterAuth_Stream_Manage msg propagated. 568 * Initialized to 0 on AKE_INIT. Incremented after every successful 569 * transmission of RepeaterAuth_Stream_Manage message. When it rolls 570 * over re-Auth has to be triggered. 571 */ 572 u32 seq_num_m; 573 574 /* 575 * Work queue to signal the CP_IRQ. Used for the waiters to read the 576 * available information from HDCP DP sink. 577 */ 578 wait_queue_head_t cp_irq_queue; 579 atomic_t cp_irq_count; 580 int cp_irq_count_cached; 581 582 /* 583 * HDCP register access for gen12+ need the transcoder associated. 584 * Transcoder attached to the connector could be changed at modeset. 585 * Hence caching the transcoder here. 586 */ 587 enum transcoder cpu_transcoder; 588 /* Only used for DP MST stream encryption */ 589 enum transcoder stream_transcoder; 590 }; 591 592 struct intel_connector { 593 struct drm_connector base; 594 /* 595 * The fixed encoder this connector is connected to. 596 */ 597 struct intel_encoder *encoder; 598 599 /* ACPI device id for ACPI and driver cooperation */ 600 u32 acpi_device_id; 601 602 /* Reads out the current hw, returning true if the connector is enabled 603 * and active (i.e. dpms ON state). */ 604 bool (*get_hw_state)(struct intel_connector *); 605 606 /* Panel info for eDP and LVDS */ 607 struct intel_panel panel; 608 609 /* Cached EDID for detect. */ 610 const struct drm_edid *detect_edid; 611 612 /* Number of times hotplug detection was tried after an HPD interrupt */ 613 int hotplug_retries; 614 615 /* since POLL and HPD connectors may use the same HPD line keep the native 616 state of connector->polled in case hotplug storm detection changes it */ 617 u8 polled; 618 619 struct drm_dp_mst_port *port; 620 621 struct intel_dp *mst_port; 622 623 struct { 624 struct drm_dp_aux *dsc_decompression_aux; 625 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; 626 u8 fec_capability; 627 } dp; 628 629 /* Work struct to schedule a uevent on link train failure */ 630 struct work_struct modeset_retry_work; 631 632 struct intel_hdcp hdcp; 633 }; 634 635 struct intel_digital_connector_state { 636 struct drm_connector_state base; 637 638 enum hdmi_force_audio force_audio; 639 int broadcast_rgb; 640 }; 641 642 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base) 643 644 struct dpll { 645 /* given values */ 646 int n; 647 int m1, m2; 648 int p1, p2; 649 /* derived values */ 650 int dot; 651 int vco; 652 int m; 653 int p; 654 }; 655 656 struct intel_atomic_state { 657 struct drm_atomic_state base; 658 659 intel_wakeref_t wakeref; 660 661 struct __intel_global_objs_state *global_objs; 662 int num_global_objs; 663 664 /* Internal commit, as opposed to userspace/client initiated one */ 665 bool internal; 666 667 bool dpll_set, modeset; 668 669 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; 670 671 /* 672 * Current watermarks can't be trusted during hardware readout, so 673 * don't bother calculating intermediate watermarks. 674 */ 675 bool skip_intermediate_wm; 676 677 bool rps_interactive; 678 679 struct i915_sw_fence commit_ready; 680 681 struct llist_node freed; 682 }; 683 684 struct intel_plane_state { 685 struct drm_plane_state uapi; 686 687 /* 688 * actual hardware state, the state we program to the hardware. 689 * The following members are used to verify the hardware state: 690 * During initial hw readout, they need to be copied from uapi. 691 */ 692 struct { 693 struct drm_crtc *crtc; 694 struct drm_framebuffer *fb; 695 696 u16 alpha; 697 u16 pixel_blend_mode; 698 unsigned int rotation; 699 enum drm_color_encoding color_encoding; 700 enum drm_color_range color_range; 701 enum drm_scaling_filter scaling_filter; 702 } hw; 703 704 struct i915_vma *ggtt_vma; 705 struct i915_vma *dpt_vma; 706 unsigned long flags; 707 #define PLANE_HAS_FENCE BIT(0) 708 709 struct intel_fb_view view; 710 711 /* Plane pxp decryption state */ 712 bool decrypt; 713 714 /* Plane state to display black pixels when pxp is borked */ 715 bool force_black; 716 717 /* plane control register */ 718 u32 ctl; 719 720 /* plane color control register */ 721 u32 color_ctl; 722 723 /* chroma upsampler control register */ 724 u32 cus_ctl; 725 726 /* 727 * scaler_id 728 * = -1 : not using a scaler 729 * >= 0 : using a scalers 730 * 731 * plane requiring a scaler: 732 * - During check_plane, its bit is set in 733 * crtc_state->scaler_state.scaler_users by calling helper function 734 * update_scaler_plane. 735 * - scaler_id indicates the scaler it got assigned. 736 * 737 * plane doesn't require a scaler: 738 * - this can happen when scaling is no more required or plane simply 739 * got disabled. 740 * - During check_plane, corresponding bit is reset in 741 * crtc_state->scaler_state.scaler_users by calling helper function 742 * update_scaler_plane. 743 */ 744 int scaler_id; 745 746 /* 747 * planar_linked_plane: 748 * 749 * ICL planar formats require 2 planes that are updated as pairs. 750 * This member is used to make sure the other plane is also updated 751 * when required, and for update_slave() to find the correct 752 * plane_state to pass as argument. 753 */ 754 struct intel_plane *planar_linked_plane; 755 756 /* 757 * planar_slave: 758 * If set don't update use the linked plane's state for updating 759 * this plane during atomic commit with the update_slave() callback. 760 * 761 * It's also used by the watermark code to ignore wm calculations on 762 * this plane. They're calculated by the linked plane's wm code. 763 */ 764 u32 planar_slave; 765 766 struct drm_intel_sprite_colorkey ckey; 767 768 struct drm_rect psr2_sel_fetch_area; 769 770 /* Clear Color Value */ 771 u64 ccval; 772 773 const char *no_fbc_reason; 774 }; 775 776 struct intel_initial_plane_config { 777 struct intel_framebuffer *fb; 778 struct i915_vma *vma; 779 unsigned int tiling; 780 int size; 781 u32 base; 782 u8 rotation; 783 }; 784 785 struct intel_scaler { 786 int in_use; 787 u32 mode; 788 }; 789 790 struct intel_crtc_scaler_state { 791 #define SKL_NUM_SCALERS 2 792 struct intel_scaler scalers[SKL_NUM_SCALERS]; 793 794 /* 795 * scaler_users: keeps track of users requesting scalers on this crtc. 796 * 797 * If a bit is set, a user is using a scaler. 798 * Here user can be a plane or crtc as defined below: 799 * bits 0-30 - plane (bit position is index from drm_plane_index) 800 * bit 31 - crtc 801 * 802 * Instead of creating a new index to cover planes and crtc, using 803 * existing drm_plane_index for planes which is well less than 31 804 * planes and bit 31 for crtc. This should be fine to cover all 805 * our platforms. 806 * 807 * intel_atomic_setup_scalers will setup available scalers to users 808 * requesting scalers. It will gracefully fail if request exceeds 809 * avilability. 810 */ 811 #define SKL_CRTC_INDEX 31 812 unsigned scaler_users; 813 814 /* scaler used by crtc for panel fitting purpose */ 815 int scaler_id; 816 }; 817 818 /* {crtc,crtc_state}->mode_flags */ 819 /* Flag to get scanline using frame time stamps */ 820 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1) 821 /* Flag to use the scanline counter instead of the pixel counter */ 822 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2) 823 /* 824 * TE0 or TE1 flag is set if the crtc has a DSI encoder which 825 * is operating in command mode. 826 * Flag to use TE from DSI0 instead of VBI in command mode 827 */ 828 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3) 829 /* Flag to use TE from DSI1 instead of VBI in command mode */ 830 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4) 831 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */ 832 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5) 833 /* Do tricks to make vblank timestamps sane with VRR? */ 834 #define I915_MODE_FLAG_VRR (1<<6) 835 836 struct intel_wm_level { 837 bool enable; 838 u32 pri_val; 839 u32 spr_val; 840 u32 cur_val; 841 u32 fbc_val; 842 }; 843 844 struct intel_pipe_wm { 845 struct intel_wm_level wm[5]; 846 bool fbc_wm_enabled; 847 bool pipe_enabled; 848 bool sprites_enabled; 849 bool sprites_scaled; 850 }; 851 852 struct skl_wm_level { 853 u16 min_ddb_alloc; 854 u16 blocks; 855 u8 lines; 856 bool enable; 857 bool ignore_lines; 858 bool can_sagv; 859 }; 860 861 struct skl_plane_wm { 862 struct skl_wm_level wm[8]; 863 struct skl_wm_level uv_wm[8]; 864 struct skl_wm_level trans_wm; 865 struct { 866 struct skl_wm_level wm0; 867 struct skl_wm_level trans_wm; 868 } sagv; 869 bool is_planar; 870 }; 871 872 struct skl_pipe_wm { 873 struct skl_plane_wm planes[I915_MAX_PLANES]; 874 bool use_sagv_wm; 875 }; 876 877 enum vlv_wm_level { 878 VLV_WM_LEVEL_PM2, 879 VLV_WM_LEVEL_PM5, 880 VLV_WM_LEVEL_DDR_DVFS, 881 NUM_VLV_WM_LEVELS, 882 }; 883 884 struct vlv_wm_state { 885 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; 886 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS]; 887 u8 num_levels; 888 bool cxsr; 889 }; 890 891 struct vlv_fifo_state { 892 u16 plane[I915_MAX_PLANES]; 893 }; 894 895 enum g4x_wm_level { 896 G4X_WM_LEVEL_NORMAL, 897 G4X_WM_LEVEL_SR, 898 G4X_WM_LEVEL_HPLL, 899 NUM_G4X_WM_LEVELS, 900 }; 901 902 struct g4x_wm_state { 903 struct g4x_pipe_wm wm; 904 struct g4x_sr_wm sr; 905 struct g4x_sr_wm hpll; 906 bool cxsr; 907 bool hpll_en; 908 bool fbc_en; 909 }; 910 911 struct intel_crtc_wm_state { 912 union { 913 /* 914 * raw: 915 * The "raw" watermark values produced by the formula 916 * given the plane's current state. They do not consider 917 * how much FIFO is actually allocated for each plane. 918 * 919 * optimal: 920 * The "optimal" watermark values given the current 921 * state of the planes and the amount of FIFO 922 * allocated to each, ignoring any previous state 923 * of the planes. 924 * 925 * intermediate: 926 * The "intermediate" watermark values when transitioning 927 * between the old and new "optimal" values. Used when 928 * the watermark registers are single buffered and hence 929 * their state changes asynchronously with regards to the 930 * actual plane registers. These are essentially the 931 * worst case combination of the old and new "optimal" 932 * watermarks, which are therefore safe to use when the 933 * plane is in either its old or new state. 934 */ 935 struct { 936 struct intel_pipe_wm intermediate; 937 struct intel_pipe_wm optimal; 938 } ilk; 939 940 struct { 941 struct skl_pipe_wm raw; 942 /* gen9+ only needs 1-step wm programming */ 943 struct skl_pipe_wm optimal; 944 struct skl_ddb_entry ddb; 945 /* 946 * pre-icl: for packed/planar CbCr 947 * icl+: for everything 948 */ 949 struct skl_ddb_entry plane_ddb[I915_MAX_PLANES]; 950 /* pre-icl: for planar Y */ 951 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; 952 } skl; 953 954 struct { 955 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */ 956 struct vlv_wm_state intermediate; /* inverted */ 957 struct vlv_wm_state optimal; /* inverted */ 958 struct vlv_fifo_state fifo_state; 959 } vlv; 960 961 struct { 962 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS]; 963 struct g4x_wm_state intermediate; 964 struct g4x_wm_state optimal; 965 } g4x; 966 }; 967 968 /* 969 * Platforms with two-step watermark programming will need to 970 * update watermark programming post-vblank to switch from the 971 * safe intermediate watermarks to the optimal final 972 * watermarks. 973 */ 974 bool need_postvbl_update; 975 }; 976 977 enum intel_output_format { 978 INTEL_OUTPUT_FORMAT_RGB, 979 INTEL_OUTPUT_FORMAT_YCBCR420, 980 INTEL_OUTPUT_FORMAT_YCBCR444, 981 }; 982 983 struct intel_mpllb_state { 984 u32 clock; /* in KHz */ 985 u32 ref_control; 986 u32 mpllb_cp; 987 u32 mpllb_div; 988 u32 mpllb_div2; 989 u32 mpllb_fracn1; 990 u32 mpllb_fracn2; 991 u32 mpllb_sscen; 992 u32 mpllb_sscstep; 993 }; 994 995 /* Used by dp and fdi links */ 996 struct intel_link_m_n { 997 u32 tu; 998 u32 data_m; 999 u32 data_n; 1000 u32 link_m; 1001 u32 link_n; 1002 }; 1003 1004 struct intel_csc_matrix { 1005 u16 coeff[9]; 1006 u16 preoff[3]; 1007 u16 postoff[3]; 1008 }; 1009 1010 struct intel_c10pll_state { 1011 u32 clock; /* in KHz */ 1012 u8 tx; 1013 u8 cmn; 1014 u8 pll[20]; 1015 }; 1016 1017 struct intel_c20pll_state { 1018 u32 link_bit_rate; 1019 u32 clock; /* in kHz */ 1020 u16 tx[3]; 1021 u16 cmn[4]; 1022 union { 1023 u16 mplla[10]; 1024 u16 mpllb[11]; 1025 }; 1026 }; 1027 1028 struct intel_cx0pll_state { 1029 union { 1030 struct intel_c10pll_state c10; 1031 struct intel_c20pll_state c20; 1032 }; 1033 bool ssc_enabled; 1034 }; 1035 1036 struct intel_crtc_state { 1037 /* 1038 * uapi (drm) state. This is the software state shown to userspace. 1039 * In particular, the following members are used for bookkeeping: 1040 * - crtc 1041 * - state 1042 * - *_changed 1043 * - event 1044 * - commit 1045 * - mode_blob 1046 */ 1047 struct drm_crtc_state uapi; 1048 1049 /* 1050 * actual hardware state, the state we program to the hardware. 1051 * The following members are used to verify the hardware state: 1052 * - enable 1053 * - active 1054 * - mode / pipe_mode / adjusted_mode 1055 * - color property blobs. 1056 * 1057 * During initial hw readout, they need to be copied to uapi. 1058 * 1059 * Bigjoiner will allow a transcoder mode that spans 2 pipes; 1060 * Use the pipe_mode for calculations like watermarks, pipe 1061 * scaler, and bandwidth. 1062 * 1063 * Use adjusted_mode for things that need to know the full 1064 * mode on the transcoder, which spans all pipes. 1065 */ 1066 struct { 1067 bool active, enable; 1068 /* logical state of LUTs */ 1069 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; 1070 struct drm_display_mode mode, pipe_mode, adjusted_mode; 1071 enum drm_scaling_filter scaling_filter; 1072 } hw; 1073 1074 /* actual state of LUTs */ 1075 struct drm_property_blob *pre_csc_lut, *post_csc_lut; 1076 1077 struct intel_csc_matrix csc, output_csc; 1078 1079 /** 1080 * quirks - bitfield with hw state readout quirks 1081 * 1082 * For various reasons the hw state readout code might not be able to 1083 * completely faithfully read out the current state. These cases are 1084 * tracked with quirk flags so that fastboot and state checker can act 1085 * accordingly. 1086 */ 1087 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ 1088 unsigned long quirks; 1089 1090 unsigned fb_bits; /* framebuffers to flip */ 1091 bool update_pipe; /* can a fast modeset be performed? */ 1092 bool update_m_n; /* update M/N seamlessly during fastset? */ 1093 bool update_lrr; /* update TRANS_VTOTAL/etc. during fastset? */ 1094 bool disable_cxsr; 1095 bool update_wm_pre, update_wm_post; /* watermarks are updated */ 1096 bool fifo_changed; /* FIFO split is changed */ 1097 bool preload_luts; 1098 bool inherited; /* state inherited from BIOS? */ 1099 1100 /* Ask the hardware to actually async flip? */ 1101 bool do_async_flip; 1102 1103 /* Pipe source size (ie. panel fitter input size) 1104 * All planes will be positioned inside this space, 1105 * and get clipped at the edges. */ 1106 struct drm_rect pipe_src; 1107 1108 /* 1109 * Pipe pixel rate, adjusted for 1110 * panel fitter/pipe scaler downscaling. 1111 */ 1112 unsigned int pixel_rate; 1113 1114 /* Whether to set up the PCH/FDI. Note that we never allow sharing 1115 * between pch encoders and cpu encoders. */ 1116 bool has_pch_encoder; 1117 1118 /* Are we sending infoframes on the attached port */ 1119 bool has_infoframe; 1120 1121 /* CPU Transcoder for the pipe. Currently this can only differ from the 1122 * pipe on Haswell and later (where we have a special eDP transcoder) 1123 * and Broxton (where we have special DSI transcoders). */ 1124 enum transcoder cpu_transcoder; 1125 1126 /* 1127 * Use reduced/limited/broadcast rbg range, compressing from the full 1128 * range fed into the crtcs. 1129 */ 1130 bool limited_color_range; 1131 1132 /* Bitmask of encoder types (enum intel_output_type) 1133 * driven by the pipe. 1134 */ 1135 unsigned int output_types; 1136 1137 /* Whether we should send NULL infoframes. Required for audio. */ 1138 bool has_hdmi_sink; 1139 1140 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or 1141 * has_dp_encoder is set. */ 1142 bool has_audio; 1143 1144 /* 1145 * Enable dithering, used when the selected pipe bpp doesn't match the 1146 * plane bpp. 1147 */ 1148 bool dither; 1149 1150 /* 1151 * Dither gets enabled for 18bpp which causes CRC mismatch errors for 1152 * compliance video pattern tests. 1153 * Disable dither only if it is a compliance test request for 1154 * 18bpp. 1155 */ 1156 bool dither_force_disable; 1157 1158 /* Controls for the clock computation, to override various stages. */ 1159 bool clock_set; 1160 1161 /* SDVO TV has a bunch of special case. To make multifunction encoders 1162 * work correctly, we need to track this at runtime.*/ 1163 bool sdvo_tv_clock; 1164 1165 /* 1166 * crtc bandwidth limit, don't increase pipe bpp or clock if not really 1167 * required. This is set in the 2nd loop of calling encoder's 1168 * ->compute_config if the first pick doesn't work out. 1169 */ 1170 bool bw_constrained; 1171 1172 /* Settings for the intel dpll used on pretty much everything but 1173 * haswell. */ 1174 struct dpll dpll; 1175 1176 /* Selected dpll when shared or NULL. */ 1177 struct intel_shared_dpll *shared_dpll; 1178 1179 /* Actual register state of the dpll, for shared dpll cross-checking. */ 1180 union { 1181 struct intel_dpll_hw_state dpll_hw_state; 1182 struct intel_mpllb_state mpllb_state; 1183 struct intel_cx0pll_state cx0pll_state; 1184 }; 1185 1186 /* 1187 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by 1188 * setting shared_dpll and dpll_hw_state to one of these reserved ones. 1189 */ 1190 struct icl_port_dpll { 1191 struct intel_shared_dpll *pll; 1192 struct intel_dpll_hw_state hw_state; 1193 } icl_port_dplls[ICL_PORT_DPLL_COUNT]; 1194 1195 /* DSI PLL registers */ 1196 struct { 1197 u32 ctrl, div; 1198 } dsi_pll; 1199 1200 int max_link_bpp_x16; /* in 1/16 bpp units */ 1201 int pipe_bpp; /* in 1 bpp units */ 1202 struct intel_link_m_n dp_m_n; 1203 1204 /* m2_n2 for eDP downclock */ 1205 struct intel_link_m_n dp_m2_n2; 1206 bool has_drrs; 1207 1208 /* PSR is supported but might not be enabled due the lack of enabled planes */ 1209 bool has_psr; 1210 bool has_psr2; 1211 bool enable_psr2_sel_fetch; 1212 bool req_psr2_sdp_prior_scanline; 1213 bool wm_level_disabled; 1214 u32 dc3co_exitline; 1215 u16 su_y_granularity; 1216 struct drm_dp_vsc_sdp psr_vsc; 1217 1218 /* 1219 * Frequence the dpll for the port should run at. Differs from the 1220 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also 1221 * already multiplied by pixel_multiplier. 1222 */ 1223 int port_clock; 1224 1225 /* Used by SDVO (and if we ever fix it, HDMI). */ 1226 unsigned pixel_multiplier; 1227 1228 /* I915_MODE_FLAG_* */ 1229 u8 mode_flags; 1230 1231 u8 lane_count; 1232 1233 /* 1234 * Used by platforms having DP/HDMI PHY with programmable lane 1235 * latency optimization. 1236 */ 1237 u8 lane_lat_optim_mask; 1238 1239 /* minimum acceptable voltage level */ 1240 u8 min_voltage_level; 1241 1242 /* Panel fitter controls for gen2-gen4 + VLV */ 1243 struct { 1244 u32 control; 1245 u32 pgm_ratios; 1246 u32 lvds_border_bits; 1247 } gmch_pfit; 1248 1249 /* Panel fitter placement and size for Ironlake+ */ 1250 struct { 1251 struct drm_rect dst; 1252 bool enabled; 1253 bool force_thru; 1254 } pch_pfit; 1255 1256 /* FDI configuration, only valid if has_pch_encoder is set. */ 1257 int fdi_lanes; 1258 struct intel_link_m_n fdi_m_n; 1259 1260 bool ips_enabled; 1261 1262 bool crc_enabled; 1263 1264 bool double_wide; 1265 1266 int pbn; 1267 1268 struct intel_crtc_scaler_state scaler_state; 1269 1270 /* w/a for waiting 2 vblanks during crtc enable */ 1271 enum pipe hsw_workaround_pipe; 1272 1273 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ 1274 bool disable_lp_wm; 1275 1276 struct intel_crtc_wm_state wm; 1277 1278 int min_cdclk[I915_MAX_PLANES]; 1279 1280 /* for packed/planar CbCr */ 1281 u32 data_rate[I915_MAX_PLANES]; 1282 /* for planar Y */ 1283 u32 data_rate_y[I915_MAX_PLANES]; 1284 1285 /* FIXME unify with data_rate[]? */ 1286 u64 rel_data_rate[I915_MAX_PLANES]; 1287 u64 rel_data_rate_y[I915_MAX_PLANES]; 1288 1289 /* Gamma mode programmed on the pipe */ 1290 u32 gamma_mode; 1291 1292 union { 1293 /* CSC mode programmed on the pipe */ 1294 u32 csc_mode; 1295 1296 /* CHV CGM mode */ 1297 u32 cgm_mode; 1298 }; 1299 1300 /* bitmask of logically enabled planes (enum plane_id) */ 1301 u8 enabled_planes; 1302 1303 /* bitmask of actually visible planes (enum plane_id) */ 1304 u8 active_planes; 1305 u8 scaled_planes; 1306 u8 nv12_planes; 1307 u8 c8_planes; 1308 1309 /* bitmask of planes that will be updated during the commit */ 1310 u8 update_planes; 1311 1312 /* bitmask of planes with async flip active */ 1313 u8 async_flip_planes; 1314 1315 u8 framestart_delay; /* 1-4 */ 1316 u8 msa_timing_delay; /* 0-3 */ 1317 1318 struct { 1319 u32 enable; 1320 u32 gcp; 1321 union hdmi_infoframe avi; 1322 union hdmi_infoframe spd; 1323 union hdmi_infoframe hdmi; 1324 union hdmi_infoframe drm; 1325 struct drm_dp_vsc_sdp vsc; 1326 } infoframes; 1327 1328 u8 eld[MAX_ELD_BYTES]; 1329 1330 /* HDMI scrambling status */ 1331 bool hdmi_scrambling; 1332 1333 /* HDMI High TMDS char rate ratio */ 1334 bool hdmi_high_tmds_clock_ratio; 1335 1336 /* 1337 * Output format RGB/YCBCR etc., that is coming out 1338 * at the end of the pipe. 1339 */ 1340 enum intel_output_format output_format; 1341 1342 /* 1343 * Sink output format RGB/YCBCR etc., that is going 1344 * into the sink. 1345 */ 1346 enum intel_output_format sink_format; 1347 1348 /* enable pipe gamma? */ 1349 bool gamma_enable; 1350 1351 /* enable pipe csc? */ 1352 bool csc_enable; 1353 1354 /* enable vlv/chv wgc csc? */ 1355 bool wgc_enable; 1356 1357 /* big joiner pipe bitmask */ 1358 u8 bigjoiner_pipes; 1359 1360 /* Display Stream compression state */ 1361 struct { 1362 bool compression_enable; 1363 bool dsc_split; 1364 u16 compressed_bpp; 1365 u8 slice_count; 1366 struct drm_dsc_config config; 1367 } dsc; 1368 1369 /* HSW+ linetime watermarks */ 1370 u16 linetime; 1371 u16 ips_linetime; 1372 1373 bool enhanced_framing; 1374 1375 /* 1376 * Forward Error Correction. 1377 * 1378 * Note: This will be false for 128b/132b, which will always have FEC 1379 * enabled automatically. 1380 */ 1381 bool fec_enable; 1382 1383 bool sdp_split_enable; 1384 1385 /* Pointer to master transcoder in case of tiled displays */ 1386 enum transcoder master_transcoder; 1387 1388 /* Bitmask to indicate slaves attached */ 1389 u8 sync_mode_slaves_mask; 1390 1391 /* Only valid on TGL+ */ 1392 enum transcoder mst_master_transcoder; 1393 1394 /* For DSB related info */ 1395 struct intel_dsb *dsb; 1396 1397 u32 psr2_man_track_ctl; 1398 1399 /* Variable Refresh Rate state */ 1400 struct { 1401 bool enable, in_range; 1402 u8 pipeline_full; 1403 u16 flipline, vmin, vmax, guardband; 1404 } vrr; 1405 1406 /* Stream Splitter for eDP MSO */ 1407 struct { 1408 bool enable; 1409 u8 link_count; 1410 u8 pixel_overlap; 1411 } splitter; 1412 1413 /* for loading single buffered registers during vblank */ 1414 struct drm_vblank_work vblank_work; 1415 }; 1416 1417 enum intel_pipe_crc_source { 1418 INTEL_PIPE_CRC_SOURCE_NONE, 1419 INTEL_PIPE_CRC_SOURCE_PLANE1, 1420 INTEL_PIPE_CRC_SOURCE_PLANE2, 1421 INTEL_PIPE_CRC_SOURCE_PLANE3, 1422 INTEL_PIPE_CRC_SOURCE_PLANE4, 1423 INTEL_PIPE_CRC_SOURCE_PLANE5, 1424 INTEL_PIPE_CRC_SOURCE_PLANE6, 1425 INTEL_PIPE_CRC_SOURCE_PLANE7, 1426 INTEL_PIPE_CRC_SOURCE_PIPE, 1427 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1428 INTEL_PIPE_CRC_SOURCE_TV, 1429 INTEL_PIPE_CRC_SOURCE_DP_B, 1430 INTEL_PIPE_CRC_SOURCE_DP_C, 1431 INTEL_PIPE_CRC_SOURCE_DP_D, 1432 INTEL_PIPE_CRC_SOURCE_AUTO, 1433 INTEL_PIPE_CRC_SOURCE_MAX, 1434 }; 1435 1436 enum drrs_refresh_rate { 1437 DRRS_REFRESH_RATE_HIGH, 1438 DRRS_REFRESH_RATE_LOW, 1439 }; 1440 1441 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1442 struct intel_pipe_crc { 1443 spinlock_t lock; 1444 int skipped; 1445 enum intel_pipe_crc_source source; 1446 }; 1447 1448 struct intel_crtc { 1449 struct drm_crtc base; 1450 enum pipe pipe; 1451 /* 1452 * Whether the crtc and the connected output pipeline is active. Implies 1453 * that crtc->enabled is set, i.e. the current mode configuration has 1454 * some outputs connected to this crtc. 1455 */ 1456 bool active; 1457 u8 plane_ids_mask; 1458 1459 /* I915_MODE_FLAG_* */ 1460 u8 mode_flags; 1461 1462 u16 vmax_vblank_start; 1463 1464 struct intel_display_power_domain_set enabled_power_domains; 1465 struct intel_display_power_domain_set hw_readout_power_domains; 1466 struct intel_overlay *overlay; 1467 1468 struct intel_crtc_state *config; 1469 1470 /* Access to these should be protected by dev_priv->irq_lock. */ 1471 bool cpu_fifo_underrun_disabled; 1472 bool pch_fifo_underrun_disabled; 1473 1474 /* per-pipe watermark state */ 1475 struct { 1476 /* watermarks currently being used */ 1477 union { 1478 struct intel_pipe_wm ilk; 1479 struct vlv_wm_state vlv; 1480 struct g4x_wm_state g4x; 1481 } active; 1482 } wm; 1483 1484 struct { 1485 struct mutex mutex; 1486 struct delayed_work work; 1487 enum drrs_refresh_rate refresh_rate; 1488 unsigned int frontbuffer_bits; 1489 unsigned int busy_frontbuffer_bits; 1490 enum transcoder cpu_transcoder; 1491 struct intel_link_m_n m_n, m2_n2; 1492 } drrs; 1493 1494 int scanline_offset; 1495 1496 struct { 1497 unsigned start_vbl_count; 1498 ktime_t start_vbl_time; 1499 int min_vbl, max_vbl; 1500 int scanline_start; 1501 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE 1502 struct { 1503 u64 min; 1504 u64 max; 1505 u64 sum; 1506 unsigned int over; 1507 unsigned int times[17]; /* [1us, 16ms] */ 1508 } vbl; 1509 #endif 1510 } debug; 1511 1512 /* scalers available on this crtc */ 1513 int num_scalers; 1514 1515 /* for loading single buffered registers during vblank */ 1516 struct pm_qos_request vblank_pm_qos; 1517 1518 #ifdef CONFIG_DEBUG_FS 1519 struct intel_pipe_crc pipe_crc; 1520 #endif 1521 }; 1522 1523 struct intel_plane { 1524 struct drm_plane base; 1525 enum i9xx_plane_id i9xx_plane; 1526 enum plane_id id; 1527 enum pipe pipe; 1528 bool need_async_flip_disable_wa; 1529 u32 frontbuffer_bit; 1530 1531 struct { 1532 u32 base, cntl, size; 1533 } cursor; 1534 1535 struct intel_fbc *fbc; 1536 1537 /* 1538 * NOTE: Do not place new plane state fields here (e.g., when adding 1539 * new plane properties). New runtime state should now be placed in 1540 * the intel_plane_state structure and accessed via plane_state. 1541 */ 1542 1543 int (*min_width)(const struct drm_framebuffer *fb, 1544 int color_plane, 1545 unsigned int rotation); 1546 int (*max_width)(const struct drm_framebuffer *fb, 1547 int color_plane, 1548 unsigned int rotation); 1549 int (*max_height)(const struct drm_framebuffer *fb, 1550 int color_plane, 1551 unsigned int rotation); 1552 unsigned int (*max_stride)(struct intel_plane *plane, 1553 u32 pixel_format, u64 modifier, 1554 unsigned int rotation); 1555 /* Write all non-self arming plane registers */ 1556 void (*update_noarm)(struct intel_plane *plane, 1557 const struct intel_crtc_state *crtc_state, 1558 const struct intel_plane_state *plane_state); 1559 /* Write all self-arming plane registers */ 1560 void (*update_arm)(struct intel_plane *plane, 1561 const struct intel_crtc_state *crtc_state, 1562 const struct intel_plane_state *plane_state); 1563 /* Disable the plane, must arm */ 1564 void (*disable_arm)(struct intel_plane *plane, 1565 const struct intel_crtc_state *crtc_state); 1566 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); 1567 int (*check_plane)(struct intel_crtc_state *crtc_state, 1568 struct intel_plane_state *plane_state); 1569 int (*min_cdclk)(const struct intel_crtc_state *crtc_state, 1570 const struct intel_plane_state *plane_state); 1571 void (*async_flip)(struct intel_plane *plane, 1572 const struct intel_crtc_state *crtc_state, 1573 const struct intel_plane_state *plane_state, 1574 bool async_flip); 1575 void (*enable_flip_done)(struct intel_plane *plane); 1576 void (*disable_flip_done)(struct intel_plane *plane); 1577 }; 1578 1579 struct intel_watermark_params { 1580 u16 fifo_size; 1581 u16 max_wm; 1582 u8 default_wm; 1583 u8 guard_size; 1584 u8 cacheline_size; 1585 }; 1586 1587 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) 1588 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 1589 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi) 1590 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 1591 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 1592 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 1593 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 1594 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi) 1595 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL) 1596 1597 struct intel_hdmi { 1598 i915_reg_t hdmi_reg; 1599 struct { 1600 enum drm_dp_dual_mode_type type; 1601 int max_tmds_clock; 1602 } dp_dual_mode; 1603 struct intel_connector *attached_connector; 1604 struct cec_notifier *cec_notifier; 1605 }; 1606 1607 struct intel_dp_mst_encoder; 1608 1609 struct intel_dp_compliance_data { 1610 unsigned long edid; 1611 u8 video_pattern; 1612 u16 hdisplay, vdisplay; 1613 u8 bpc; 1614 struct drm_dp_phy_test_params phytest; 1615 }; 1616 1617 struct intel_dp_compliance { 1618 unsigned long test_type; 1619 struct intel_dp_compliance_data test_data; 1620 bool test_active; 1621 int test_link_rate; 1622 u8 test_lane_count; 1623 }; 1624 1625 struct intel_dp_pcon_frl { 1626 bool is_trained; 1627 int trained_rate_gbps; 1628 }; 1629 1630 struct intel_pps { 1631 int panel_power_up_delay; 1632 int panel_power_down_delay; 1633 int panel_power_cycle_delay; 1634 int backlight_on_delay; 1635 int backlight_off_delay; 1636 struct delayed_work panel_vdd_work; 1637 bool want_panel_vdd; 1638 bool initializing; 1639 unsigned long last_power_on; 1640 unsigned long last_backlight_off; 1641 ktime_t panel_power_off_time; 1642 intel_wakeref_t vdd_wakeref; 1643 1644 union { 1645 /* 1646 * Pipe whose power sequencer is currently locked into 1647 * this port. Only relevant on VLV/CHV. 1648 */ 1649 enum pipe pps_pipe; 1650 1651 /* 1652 * Power sequencer index. Only relevant on BXT+. 1653 */ 1654 int pps_idx; 1655 }; 1656 1657 /* 1658 * Pipe currently driving the port. Used for preventing 1659 * the use of the PPS for any pipe currentrly driving 1660 * external DP as that will mess things up on VLV. 1661 */ 1662 enum pipe active_pipe; 1663 /* 1664 * Set if the sequencer may be reset due to a power transition, 1665 * requiring a reinitialization. Only relevant on BXT+. 1666 */ 1667 bool pps_reset; 1668 struct edp_power_seq pps_delays; 1669 struct edp_power_seq bios_pps_delays; 1670 }; 1671 1672 struct intel_psr { 1673 /* Mutex for PSR state of the transcoder */ 1674 struct mutex lock; 1675 1676 #define I915_PSR_DEBUG_MODE_MASK 0x0f 1677 #define I915_PSR_DEBUG_DEFAULT 0x00 1678 #define I915_PSR_DEBUG_DISABLE 0x01 1679 #define I915_PSR_DEBUG_ENABLE 0x02 1680 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 1681 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4 1682 #define I915_PSR_DEBUG_IRQ 0x10 1683 1684 u32 debug; 1685 bool sink_support; 1686 bool source_support; 1687 bool enabled; 1688 bool paused; 1689 enum pipe pipe; 1690 enum transcoder transcoder; 1691 bool active; 1692 struct work_struct work; 1693 unsigned int busy_frontbuffer_bits; 1694 bool sink_psr2_support; 1695 bool link_standby; 1696 bool colorimetry_support; 1697 bool psr2_enabled; 1698 bool psr2_sel_fetch_enabled; 1699 bool psr2_sel_fetch_cff_enabled; 1700 bool req_psr2_sdp_prior_scanline; 1701 u8 sink_sync_latency; 1702 u8 io_wake_lines; 1703 u8 fast_wake_lines; 1704 ktime_t last_entry_attempt; 1705 ktime_t last_exit; 1706 bool sink_not_reliable; 1707 bool irq_aux_error; 1708 u16 su_w_granularity; 1709 u16 su_y_granularity; 1710 u32 dc3co_exitline; 1711 u32 dc3co_exit_delay; 1712 struct delayed_work dc3co_work; 1713 }; 1714 1715 struct intel_dp { 1716 i915_reg_t output_reg; 1717 u32 DP; 1718 int link_rate; 1719 u8 lane_count; 1720 u8 sink_count; 1721 bool link_trained; 1722 bool reset_link_params; 1723 bool use_max_params; 1724 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 1725 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 1726 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 1727 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 1728 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; 1729 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; 1730 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; 1731 /* source rates */ 1732 int num_source_rates; 1733 const int *source_rates; 1734 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ 1735 int num_sink_rates; 1736 int sink_rates[DP_MAX_SUPPORTED_RATES]; 1737 bool use_rate_select; 1738 /* Max sink lane count as reported by DP_MAX_LANE_COUNT */ 1739 int max_sink_lane_count; 1740 /* intersection of source and sink rates */ 1741 int num_common_rates; 1742 int common_rates[DP_MAX_SUPPORTED_RATES]; 1743 /* Max lane count for the current link */ 1744 int max_link_lane_count; 1745 /* Max rate for the current link */ 1746 int max_link_rate; 1747 int mso_link_count; 1748 int mso_pixel_overlap; 1749 /* sink or branch descriptor */ 1750 struct drm_dp_desc desc; 1751 struct drm_dp_aux aux; 1752 u32 aux_busy_last_status; 1753 u8 train_set[4]; 1754 1755 struct intel_pps pps; 1756 1757 bool is_mst; 1758 int active_mst_links; 1759 1760 /* connector directly attached - won't be use for modeset in mst world */ 1761 struct intel_connector *attached_connector; 1762 1763 /* mst connector list */ 1764 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; 1765 struct drm_dp_mst_topology_mgr mst_mgr; 1766 1767 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index); 1768 /* 1769 * This function returns the value we have to program the AUX_CTL 1770 * register with to kick off an AUX transaction. 1771 */ 1772 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes, 1773 u32 aux_clock_divider); 1774 1775 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); 1776 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); 1777 1778 /* This is called before a link training is starterd */ 1779 void (*prepare_link_retrain)(struct intel_dp *intel_dp, 1780 const struct intel_crtc_state *crtc_state); 1781 void (*set_link_train)(struct intel_dp *intel_dp, 1782 const struct intel_crtc_state *crtc_state, 1783 u8 dp_train_pat); 1784 void (*set_idle_link_train)(struct intel_dp *intel_dp, 1785 const struct intel_crtc_state *crtc_state); 1786 1787 u8 (*preemph_max)(struct intel_dp *intel_dp); 1788 u8 (*voltage_max)(struct intel_dp *intel_dp, 1789 const struct intel_crtc_state *crtc_state); 1790 1791 /* Displayport compliance testing */ 1792 struct intel_dp_compliance compliance; 1793 1794 /* Downstream facing port caps */ 1795 struct { 1796 int min_tmds_clock, max_tmds_clock; 1797 int max_dotclock; 1798 int pcon_max_frl_bw; 1799 u8 max_bpc; 1800 bool ycbcr_444_to_420; 1801 bool ycbcr420_passthrough; 1802 bool rgb_to_ycbcr; 1803 } dfp; 1804 1805 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1806 struct pm_qos_request pm_qos; 1807 1808 /* Display stream compression testing */ 1809 bool force_dsc_en; 1810 int force_dsc_output_format; 1811 int force_dsc_bpc; 1812 1813 bool hobl_failed; 1814 bool hobl_active; 1815 1816 struct intel_dp_pcon_frl frl; 1817 1818 struct intel_psr psr; 1819 1820 /* When we last wrote the OUI for eDP */ 1821 unsigned long last_oui_write; 1822 }; 1823 1824 enum lspcon_vendor { 1825 LSPCON_VENDOR_MCA, 1826 LSPCON_VENDOR_PARADE 1827 }; 1828 1829 struct intel_lspcon { 1830 bool active; 1831 bool hdr_supported; 1832 enum drm_lspcon_mode mode; 1833 enum lspcon_vendor vendor; 1834 }; 1835 1836 struct intel_digital_port { 1837 struct intel_encoder base; 1838 u32 saved_port_bits; 1839 struct intel_dp dp; 1840 struct intel_hdmi hdmi; 1841 struct intel_lspcon lspcon; 1842 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); 1843 bool release_cl2_override; 1844 u8 max_lanes; 1845 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ 1846 enum aux_ch aux_ch; 1847 enum intel_display_power_domain ddi_io_power_domain; 1848 intel_wakeref_t ddi_io_wakeref; 1849 intel_wakeref_t aux_wakeref; 1850 1851 struct intel_tc_port *tc; 1852 1853 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */ 1854 struct mutex hdcp_mutex; 1855 /* the number of pipes using HDCP signalling out of this port */ 1856 unsigned int num_hdcp_streams; 1857 /* port HDCP auth status */ 1858 bool hdcp_auth_status; 1859 /* HDCP port data need to pass to security f/w */ 1860 struct hdcp_port_data hdcp_port_data; 1861 /* Whether the MST topology supports HDCP Type 1 Content */ 1862 bool hdcp_mst_type1_capable; 1863 1864 void (*write_infoframe)(struct intel_encoder *encoder, 1865 const struct intel_crtc_state *crtc_state, 1866 unsigned int type, 1867 const void *frame, ssize_t len); 1868 void (*read_infoframe)(struct intel_encoder *encoder, 1869 const struct intel_crtc_state *crtc_state, 1870 unsigned int type, 1871 void *frame, ssize_t len); 1872 void (*set_infoframes)(struct intel_encoder *encoder, 1873 bool enable, 1874 const struct intel_crtc_state *crtc_state, 1875 const struct drm_connector_state *conn_state); 1876 u32 (*infoframes_enabled)(struct intel_encoder *encoder, 1877 const struct intel_crtc_state *pipe_config); 1878 bool (*connected)(struct intel_encoder *encoder); 1879 }; 1880 1881 struct intel_dp_mst_encoder { 1882 struct intel_encoder base; 1883 enum pipe pipe; 1884 struct intel_digital_port *primary; 1885 struct intel_connector *connector; 1886 }; 1887 1888 static inline struct intel_encoder * 1889 intel_attached_encoder(struct intel_connector *connector) 1890 { 1891 return connector->encoder; 1892 } 1893 1894 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) 1895 { 1896 switch (encoder->type) { 1897 case INTEL_OUTPUT_DDI: 1898 case INTEL_OUTPUT_DP: 1899 case INTEL_OUTPUT_EDP: 1900 case INTEL_OUTPUT_HDMI: 1901 return true; 1902 default: 1903 return false; 1904 } 1905 } 1906 1907 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder) 1908 { 1909 return encoder->type == INTEL_OUTPUT_DP_MST; 1910 } 1911 1912 static inline struct intel_dp_mst_encoder * 1913 enc_to_mst(struct intel_encoder *encoder) 1914 { 1915 return container_of(&encoder->base, struct intel_dp_mst_encoder, 1916 base.base); 1917 } 1918 1919 static inline struct intel_digital_port * 1920 enc_to_dig_port(struct intel_encoder *encoder) 1921 { 1922 struct intel_encoder *intel_encoder = encoder; 1923 1924 if (intel_encoder_is_dig_port(intel_encoder)) 1925 return container_of(&encoder->base, struct intel_digital_port, 1926 base.base); 1927 else if (intel_encoder_is_mst(intel_encoder)) 1928 return enc_to_mst(encoder)->primary; 1929 else 1930 return NULL; 1931 } 1932 1933 static inline struct intel_digital_port * 1934 intel_attached_dig_port(struct intel_connector *connector) 1935 { 1936 return enc_to_dig_port(intel_attached_encoder(connector)); 1937 } 1938 1939 static inline struct intel_hdmi * 1940 enc_to_intel_hdmi(struct intel_encoder *encoder) 1941 { 1942 return &enc_to_dig_port(encoder)->hdmi; 1943 } 1944 1945 static inline struct intel_hdmi * 1946 intel_attached_hdmi(struct intel_connector *connector) 1947 { 1948 return enc_to_intel_hdmi(intel_attached_encoder(connector)); 1949 } 1950 1951 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder) 1952 { 1953 return &enc_to_dig_port(encoder)->dp; 1954 } 1955 1956 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector) 1957 { 1958 return enc_to_intel_dp(intel_attached_encoder(connector)); 1959 } 1960 1961 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) 1962 { 1963 switch (encoder->type) { 1964 case INTEL_OUTPUT_DP: 1965 case INTEL_OUTPUT_EDP: 1966 return true; 1967 case INTEL_OUTPUT_DDI: 1968 /* Skip pure HDMI/DVI DDI encoders */ 1969 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg); 1970 default: 1971 return false; 1972 } 1973 } 1974 1975 static inline struct intel_lspcon * 1976 enc_to_intel_lspcon(struct intel_encoder *encoder) 1977 { 1978 return &enc_to_dig_port(encoder)->lspcon; 1979 } 1980 1981 static inline struct intel_digital_port * 1982 dp_to_dig_port(struct intel_dp *intel_dp) 1983 { 1984 return container_of(intel_dp, struct intel_digital_port, dp); 1985 } 1986 1987 static inline struct intel_lspcon * 1988 dp_to_lspcon(struct intel_dp *intel_dp) 1989 { 1990 return &dp_to_dig_port(intel_dp)->lspcon; 1991 } 1992 1993 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev) 1994 1995 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ 1996 (intel_dp)->psr.source_support) 1997 1998 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) 1999 { 2000 if (!intel_encoder_is_dp(encoder)) 2001 return false; 2002 2003 return CAN_PSR(enc_to_intel_dp(encoder)); 2004 } 2005 2006 static inline struct intel_digital_port * 2007 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 2008 { 2009 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 2010 } 2011 2012 static inline struct intel_plane_state * 2013 intel_atomic_get_plane_state(struct intel_atomic_state *state, 2014 struct intel_plane *plane) 2015 { 2016 struct drm_plane_state *ret = 2017 drm_atomic_get_plane_state(&state->base, &plane->base); 2018 2019 if (IS_ERR(ret)) 2020 return ERR_CAST(ret); 2021 2022 return to_intel_plane_state(ret); 2023 } 2024 2025 static inline struct intel_plane_state * 2026 intel_atomic_get_old_plane_state(struct intel_atomic_state *state, 2027 struct intel_plane *plane) 2028 { 2029 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base, 2030 &plane->base)); 2031 } 2032 2033 static inline struct intel_plane_state * 2034 intel_atomic_get_new_plane_state(struct intel_atomic_state *state, 2035 struct intel_plane *plane) 2036 { 2037 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base, 2038 &plane->base)); 2039 } 2040 2041 static inline struct intel_crtc_state * 2042 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state, 2043 struct intel_crtc *crtc) 2044 { 2045 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base, 2046 &crtc->base)); 2047 } 2048 2049 static inline struct intel_crtc_state * 2050 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state, 2051 struct intel_crtc *crtc) 2052 { 2053 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base, 2054 &crtc->base)); 2055 } 2056 2057 static inline struct intel_digital_connector_state * 2058 intel_atomic_get_new_connector_state(struct intel_atomic_state *state, 2059 struct intel_connector *connector) 2060 { 2061 return to_intel_digital_connector_state( 2062 drm_atomic_get_new_connector_state(&state->base, 2063 &connector->base)); 2064 } 2065 2066 static inline struct intel_digital_connector_state * 2067 intel_atomic_get_old_connector_state(struct intel_atomic_state *state, 2068 struct intel_connector *connector) 2069 { 2070 return to_intel_digital_connector_state( 2071 drm_atomic_get_old_connector_state(&state->base, 2072 &connector->base)); 2073 } 2074 2075 /* intel_display.c */ 2076 static inline bool 2077 intel_crtc_has_type(const struct intel_crtc_state *crtc_state, 2078 enum intel_output_type type) 2079 { 2080 return crtc_state->output_types & BIT(type); 2081 } 2082 2083 static inline bool 2084 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) 2085 { 2086 return crtc_state->output_types & 2087 (BIT(INTEL_OUTPUT_DP) | 2088 BIT(INTEL_OUTPUT_DP_MST) | 2089 BIT(INTEL_OUTPUT_EDP)); 2090 } 2091 2092 static inline bool 2093 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state) 2094 { 2095 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi); 2096 } 2097 2098 static inline bool 2099 intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state) 2100 { 2101 return crtc_state->update_pipe; 2102 } 2103 2104 static inline bool 2105 intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state) 2106 { 2107 return crtc_state->uapi.color_mgmt_changed || 2108 intel_crtc_needs_fastset(crtc_state) || 2109 intel_crtc_needs_modeset(crtc_state); 2110 } 2111 2112 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state) 2113 { 2114 return i915_ggtt_offset(plane_state->ggtt_vma); 2115 } 2116 2117 static inline struct intel_frontbuffer * 2118 to_intel_frontbuffer(struct drm_framebuffer *fb) 2119 { 2120 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; 2121 } 2122 2123 static inline int to_bpp_int(int bpp_x16) 2124 { 2125 return bpp_x16 >> 4; 2126 } 2127 2128 static inline int to_bpp_frac(int bpp_x16) 2129 { 2130 return bpp_x16 & 0xf; 2131 } 2132 2133 #define BPP_X16_FMT "%d.%04d" 2134 #define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625) 2135 2136 static inline int to_bpp_int_roundup(int bpp_x16) 2137 { 2138 return (bpp_x16 + 0xf) >> 4; 2139 } 2140 2141 static inline int to_bpp_x16(int bpp) 2142 { 2143 return bpp << 4; 2144 } 2145 2146 #endif /* __INTEL_DISPLAY_TYPES_H__ */ 2147