1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/export.h> 29 #include <linux/i2c.h> 30 #include <linux/notifier.h> 31 #include <linux/slab.h> 32 #include <linux/string_helpers.h> 33 #include <linux/timekeeping.h> 34 #include <linux/types.h> 35 36 #include <asm/byteorder.h> 37 38 #include <drm/display/drm_dp_helper.h> 39 #include <drm/display/drm_dsc_helper.h> 40 #include <drm/display/drm_hdmi_helper.h> 41 #include <drm/drm_atomic_helper.h> 42 #include <drm/drm_crtc.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_probe_helper.h> 45 46 #include "g4x_dp.h" 47 #include "i915_drv.h" 48 #include "i915_irq.h" 49 #include "i915_reg.h" 50 #include "intel_atomic.h" 51 #include "intel_audio.h" 52 #include "intel_backlight.h" 53 #include "intel_combo_phy_regs.h" 54 #include "intel_connector.h" 55 #include "intel_crtc.h" 56 #include "intel_cx0_phy.h" 57 #include "intel_ddi.h" 58 #include "intel_de.h" 59 #include "intel_display_types.h" 60 #include "intel_dp.h" 61 #include "intel_dp_aux.h" 62 #include "intel_dp_hdcp.h" 63 #include "intel_dp_link_training.h" 64 #include "intel_dp_mst.h" 65 #include "intel_dpio_phy.h" 66 #include "intel_dpll.h" 67 #include "intel_fifo_underrun.h" 68 #include "intel_hdcp.h" 69 #include "intel_hdmi.h" 70 #include "intel_hotplug.h" 71 #include "intel_hotplug_irq.h" 72 #include "intel_lspcon.h" 73 #include "intel_lvds.h" 74 #include "intel_panel.h" 75 #include "intel_pch_display.h" 76 #include "intel_pps.h" 77 #include "intel_psr.h" 78 #include "intel_tc.h" 79 #include "intel_vdsc.h" 80 #include "intel_vrr.h" 81 #include "intel_crtc_state_dump.h" 82 83 /* DP DSC throughput values used for slice count calculations KPixels/s */ 84 #define DP_DSC_PEAK_PIXEL_RATE 2720000 85 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 86 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 87 88 /* DP DSC FEC Overhead factor = 1/(0.972261) */ 89 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261 90 91 /* Compliance test status bits */ 92 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 93 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) 94 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) 95 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) 96 97 98 /* Constants for DP DSC configurations */ 99 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; 100 101 /* With Single pipe configuration, HW is capable of supporting maximum 102 * of 4 slices per line. 103 */ 104 static const u8 valid_dsc_slicecount[] = {1, 2, 4}; 105 106 /** 107 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 108 * @intel_dp: DP struct 109 * 110 * If a CPU or PCH DP output is attached to an eDP panel, this function 111 * will return true, and false otherwise. 112 * 113 * This function is not safe to use prior to encoder type being set. 114 */ 115 bool intel_dp_is_edp(struct intel_dp *intel_dp) 116 { 117 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 118 119 return dig_port->base.type == INTEL_OUTPUT_EDP; 120 } 121 122 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 123 124 /* Is link rate UHBR and thus 128b/132b? */ 125 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) 126 { 127 return crtc_state->port_clock >= 1000000; 128 } 129 130 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) 131 { 132 intel_dp->sink_rates[0] = 162000; 133 intel_dp->num_sink_rates = 1; 134 } 135 136 /* update sink rates from dpcd */ 137 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) 138 { 139 static const int dp_rates[] = { 140 162000, 270000, 540000, 810000 141 }; 142 int i, max_rate; 143 int max_lttpr_rate; 144 145 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { 146 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ 147 static const int quirk_rates[] = { 162000, 270000, 324000 }; 148 149 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); 150 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); 151 152 return; 153 } 154 155 /* 156 * Sink rates for 8b/10b. 157 */ 158 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); 159 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); 160 if (max_lttpr_rate) 161 max_rate = min(max_rate, max_lttpr_rate); 162 163 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { 164 if (dp_rates[i] > max_rate) 165 break; 166 intel_dp->sink_rates[i] = dp_rates[i]; 167 } 168 169 /* 170 * Sink rates for 128b/132b. If set, sink should support all 8b/10b 171 * rates and 10 Gbps. 172 */ 173 if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) { 174 u8 uhbr_rates = 0; 175 176 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); 177 178 drm_dp_dpcd_readb(&intel_dp->aux, 179 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates); 180 181 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) { 182 /* We have a repeater */ 183 if (intel_dp->lttpr_common_caps[0] >= 0x20 && 184 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 185 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] & 186 DP_PHY_REPEATER_128B132B_SUPPORTED) { 187 /* Repeater supports 128b/132b, valid UHBR rates */ 188 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES - 189 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 190 } else { 191 /* Does not support 128b/132b */ 192 uhbr_rates = 0; 193 } 194 } 195 196 if (uhbr_rates & DP_UHBR10) 197 intel_dp->sink_rates[i++] = 1000000; 198 if (uhbr_rates & DP_UHBR13_5) 199 intel_dp->sink_rates[i++] = 1350000; 200 if (uhbr_rates & DP_UHBR20) 201 intel_dp->sink_rates[i++] = 2000000; 202 } 203 204 intel_dp->num_sink_rates = i; 205 } 206 207 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) 208 { 209 struct intel_connector *connector = intel_dp->attached_connector; 210 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 211 struct intel_encoder *encoder = &intel_dig_port->base; 212 213 intel_dp_set_dpcd_sink_rates(intel_dp); 214 215 if (intel_dp->num_sink_rates) 216 return; 217 218 drm_err(&dp_to_i915(intel_dp)->drm, 219 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n", 220 connector->base.base.id, connector->base.name, 221 encoder->base.base.id, encoder->base.name); 222 223 intel_dp_set_default_sink_rates(intel_dp); 224 } 225 226 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp) 227 { 228 intel_dp->max_sink_lane_count = 1; 229 } 230 231 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp) 232 { 233 struct intel_connector *connector = intel_dp->attached_connector; 234 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 235 struct intel_encoder *encoder = &intel_dig_port->base; 236 237 intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 238 239 switch (intel_dp->max_sink_lane_count) { 240 case 1: 241 case 2: 242 case 4: 243 return; 244 } 245 246 drm_err(&dp_to_i915(intel_dp)->drm, 247 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n", 248 connector->base.base.id, connector->base.name, 249 encoder->base.base.id, encoder->base.name, 250 intel_dp->max_sink_lane_count); 251 252 intel_dp_set_default_max_sink_lane_count(intel_dp); 253 } 254 255 /* Get length of rates array potentially limited by max_rate. */ 256 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) 257 { 258 int i; 259 260 /* Limit results by potentially reduced max rate */ 261 for (i = 0; i < len; i++) { 262 if (rates[len - i - 1] <= max_rate) 263 return len - i; 264 } 265 266 return 0; 267 } 268 269 /* Get length of common rates array potentially limited by max_rate. */ 270 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, 271 int max_rate) 272 { 273 return intel_dp_rate_limit_len(intel_dp->common_rates, 274 intel_dp->num_common_rates, max_rate); 275 } 276 277 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index) 278 { 279 if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm, 280 index < 0 || index >= intel_dp->num_common_rates)) 281 return 162000; 282 283 return intel_dp->common_rates[index]; 284 } 285 286 /* Theoretical max between source and sink */ 287 static int intel_dp_max_common_rate(struct intel_dp *intel_dp) 288 { 289 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); 290 } 291 292 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) 293 { 294 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); 295 int max_lanes = dig_port->max_lanes; 296 297 if (vbt_max_lanes) 298 max_lanes = min(max_lanes, vbt_max_lanes); 299 300 return max_lanes; 301 } 302 303 /* Theoretical max between source and sink */ 304 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) 305 { 306 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 307 int source_max = intel_dp_max_source_lane_count(dig_port); 308 int sink_max = intel_dp->max_sink_lane_count; 309 int lane_max = intel_tc_port_max_lane_count(dig_port); 310 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); 311 312 if (lttpr_max) 313 sink_max = min(sink_max, lttpr_max); 314 315 return min3(source_max, sink_max, lane_max); 316 } 317 318 int intel_dp_max_lane_count(struct intel_dp *intel_dp) 319 { 320 switch (intel_dp->max_link_lane_count) { 321 case 1: 322 case 2: 323 case 4: 324 return intel_dp->max_link_lane_count; 325 default: 326 MISSING_CASE(intel_dp->max_link_lane_count); 327 return 1; 328 } 329 } 330 331 /* 332 * The required data bandwidth for a mode with given pixel clock and bpp. This 333 * is the required net bandwidth independent of the data bandwidth efficiency. 334 */ 335 int 336 intel_dp_link_required(int pixel_clock, int bpp) 337 { 338 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 339 return DIV_ROUND_UP(pixel_clock * bpp, 8); 340 } 341 342 /* 343 * Given a link rate and lanes, get the data bandwidth. 344 * 345 * Data bandwidth is the actual payload rate, which depends on the data 346 * bandwidth efficiency and the link rate. 347 * 348 * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency 349 * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) = 350 * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by 351 * coincidence, the port clock in kHz matches the data bandwidth in kBps, and 352 * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no 353 * longer holds for data bandwidth as soon as FEC or MST is taken into account!) 354 * 355 * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For 356 * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875 357 * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000 358 * does not match the symbol clock, the port clock (not even if you think in 359 * terms of a byte clock), nor the data bandwidth. It only matches the link bit 360 * rate in units of 10000 bps. 361 */ 362 int 363 intel_dp_max_data_rate(int max_link_rate, int max_lanes) 364 { 365 if (max_link_rate >= 1000000) { 366 /* 367 * UHBR rates always use 128b/132b channel encoding, and have 368 * 97.71% data bandwidth efficiency. Consider max_link_rate the 369 * link bit rate in units of 10000 bps. 370 */ 371 int max_link_rate_kbps = max_link_rate * 10; 372 373 max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000); 374 max_link_rate = max_link_rate_kbps / 8; 375 } 376 377 /* 378 * Lower than UHBR rates always use 8b/10b channel encoding, and have 379 * 80% data bandwidth efficiency for SST non-FEC. However, this turns 380 * out to be a nop by coincidence, and can be skipped: 381 * 382 * int max_link_rate_kbps = max_link_rate * 10; 383 * max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10); 384 * max_link_rate = max_link_rate_kbps / 8; 385 */ 386 387 return max_link_rate * max_lanes; 388 } 389 390 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp) 391 { 392 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 393 struct intel_encoder *encoder = &intel_dig_port->base; 394 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 395 396 return DISPLAY_VER(dev_priv) >= 12 || 397 (DISPLAY_VER(dev_priv) == 11 && 398 encoder->port != PORT_A); 399 } 400 401 static int dg2_max_source_rate(struct intel_dp *intel_dp) 402 { 403 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000; 404 } 405 406 static int icl_max_source_rate(struct intel_dp *intel_dp) 407 { 408 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 409 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 410 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 411 412 if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp)) 413 return 540000; 414 415 return 810000; 416 } 417 418 static int ehl_max_source_rate(struct intel_dp *intel_dp) 419 { 420 if (intel_dp_is_edp(intel_dp)) 421 return 540000; 422 423 return 810000; 424 } 425 426 static int mtl_max_source_rate(struct intel_dp *intel_dp) 427 { 428 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 429 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 430 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 431 432 if (intel_is_c10phy(i915, phy)) 433 return 810000; 434 435 return 2000000; 436 } 437 438 static int vbt_max_link_rate(struct intel_dp *intel_dp) 439 { 440 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 441 int max_rate; 442 443 max_rate = intel_bios_dp_max_link_rate(encoder->devdata); 444 445 if (intel_dp_is_edp(intel_dp)) { 446 struct intel_connector *connector = intel_dp->attached_connector; 447 int edp_max_rate = connector->panel.vbt.edp.max_link_rate; 448 449 if (max_rate && edp_max_rate) 450 max_rate = min(max_rate, edp_max_rate); 451 else if (edp_max_rate) 452 max_rate = edp_max_rate; 453 } 454 455 return max_rate; 456 } 457 458 static void 459 intel_dp_set_source_rates(struct intel_dp *intel_dp) 460 { 461 /* The values must be in increasing order */ 462 static const int mtl_rates[] = { 463 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 464 810000, 1000000, 1350000, 2000000, 465 }; 466 static const int icl_rates[] = { 467 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000, 468 1000000, 1350000, 469 }; 470 static const int bxt_rates[] = { 471 162000, 216000, 243000, 270000, 324000, 432000, 540000 472 }; 473 static const int skl_rates[] = { 474 162000, 216000, 270000, 324000, 432000, 540000 475 }; 476 static const int hsw_rates[] = { 477 162000, 270000, 540000 478 }; 479 static const int g4x_rates[] = { 480 162000, 270000 481 }; 482 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 483 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 484 const int *source_rates; 485 int size, max_rate = 0, vbt_max_rate; 486 487 /* This should only be done once */ 488 drm_WARN_ON(&dev_priv->drm, 489 intel_dp->source_rates || intel_dp->num_source_rates); 490 491 if (DISPLAY_VER(dev_priv) >= 14) { 492 source_rates = mtl_rates; 493 size = ARRAY_SIZE(mtl_rates); 494 max_rate = mtl_max_source_rate(intel_dp); 495 } else if (DISPLAY_VER(dev_priv) >= 11) { 496 source_rates = icl_rates; 497 size = ARRAY_SIZE(icl_rates); 498 if (IS_DG2(dev_priv)) 499 max_rate = dg2_max_source_rate(intel_dp); 500 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) || 501 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 502 max_rate = 810000; 503 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 504 max_rate = ehl_max_source_rate(intel_dp); 505 else 506 max_rate = icl_max_source_rate(intel_dp); 507 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 508 source_rates = bxt_rates; 509 size = ARRAY_SIZE(bxt_rates); 510 } else if (DISPLAY_VER(dev_priv) == 9) { 511 source_rates = skl_rates; 512 size = ARRAY_SIZE(skl_rates); 513 } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) || 514 IS_BROADWELL(dev_priv)) { 515 source_rates = hsw_rates; 516 size = ARRAY_SIZE(hsw_rates); 517 } else { 518 source_rates = g4x_rates; 519 size = ARRAY_SIZE(g4x_rates); 520 } 521 522 vbt_max_rate = vbt_max_link_rate(intel_dp); 523 if (max_rate && vbt_max_rate) 524 max_rate = min(max_rate, vbt_max_rate); 525 else if (vbt_max_rate) 526 max_rate = vbt_max_rate; 527 528 if (max_rate) 529 size = intel_dp_rate_limit_len(source_rates, size, max_rate); 530 531 intel_dp->source_rates = source_rates; 532 intel_dp->num_source_rates = size; 533 } 534 535 static int intersect_rates(const int *source_rates, int source_len, 536 const int *sink_rates, int sink_len, 537 int *common_rates) 538 { 539 int i = 0, j = 0, k = 0; 540 541 while (i < source_len && j < sink_len) { 542 if (source_rates[i] == sink_rates[j]) { 543 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 544 return k; 545 common_rates[k] = source_rates[i]; 546 ++k; 547 ++i; 548 ++j; 549 } else if (source_rates[i] < sink_rates[j]) { 550 ++i; 551 } else { 552 ++j; 553 } 554 } 555 return k; 556 } 557 558 /* return index of rate in rates array, or -1 if not found */ 559 static int intel_dp_rate_index(const int *rates, int len, int rate) 560 { 561 int i; 562 563 for (i = 0; i < len; i++) 564 if (rate == rates[i]) 565 return i; 566 567 return -1; 568 } 569 570 static void intel_dp_set_common_rates(struct intel_dp *intel_dp) 571 { 572 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 573 574 drm_WARN_ON(&i915->drm, 575 !intel_dp->num_source_rates || !intel_dp->num_sink_rates); 576 577 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, 578 intel_dp->num_source_rates, 579 intel_dp->sink_rates, 580 intel_dp->num_sink_rates, 581 intel_dp->common_rates); 582 583 /* Paranoia, there should always be something in common. */ 584 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) { 585 intel_dp->common_rates[0] = 162000; 586 intel_dp->num_common_rates = 1; 587 } 588 } 589 590 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, 591 u8 lane_count) 592 { 593 /* 594 * FIXME: we need to synchronize the current link parameters with 595 * hardware readout. Currently fast link training doesn't work on 596 * boot-up. 597 */ 598 if (link_rate == 0 || 599 link_rate > intel_dp->max_link_rate) 600 return false; 601 602 if (lane_count == 0 || 603 lane_count > intel_dp_max_lane_count(intel_dp)) 604 return false; 605 606 return true; 607 } 608 609 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, 610 int link_rate, 611 u8 lane_count) 612 { 613 /* FIXME figure out what we actually want here */ 614 const struct drm_display_mode *fixed_mode = 615 intel_panel_preferred_fixed_mode(intel_dp->attached_connector); 616 int mode_rate, max_rate; 617 618 mode_rate = intel_dp_link_required(fixed_mode->clock, 18); 619 max_rate = intel_dp_max_data_rate(link_rate, lane_count); 620 if (mode_rate > max_rate) 621 return false; 622 623 return true; 624 } 625 626 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 627 int link_rate, u8 lane_count) 628 { 629 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 630 int index; 631 632 /* 633 * TODO: Enable fallback on MST links once MST link compute can handle 634 * the fallback params. 635 */ 636 if (intel_dp->is_mst) { 637 drm_err(&i915->drm, "Link Training Unsuccessful\n"); 638 return -1; 639 } 640 641 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { 642 drm_dbg_kms(&i915->drm, 643 "Retrying Link training for eDP with max parameters\n"); 644 intel_dp->use_max_params = true; 645 return 0; 646 } 647 648 index = intel_dp_rate_index(intel_dp->common_rates, 649 intel_dp->num_common_rates, 650 link_rate); 651 if (index > 0) { 652 if (intel_dp_is_edp(intel_dp) && 653 !intel_dp_can_link_train_fallback_for_edp(intel_dp, 654 intel_dp_common_rate(intel_dp, index - 1), 655 lane_count)) { 656 drm_dbg_kms(&i915->drm, 657 "Retrying Link training for eDP with same parameters\n"); 658 return 0; 659 } 660 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1); 661 intel_dp->max_link_lane_count = lane_count; 662 } else if (lane_count > 1) { 663 if (intel_dp_is_edp(intel_dp) && 664 !intel_dp_can_link_train_fallback_for_edp(intel_dp, 665 intel_dp_max_common_rate(intel_dp), 666 lane_count >> 1)) { 667 drm_dbg_kms(&i915->drm, 668 "Retrying Link training for eDP with same parameters\n"); 669 return 0; 670 } 671 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); 672 intel_dp->max_link_lane_count = lane_count >> 1; 673 } else { 674 drm_err(&i915->drm, "Link Training Unsuccessful\n"); 675 return -1; 676 } 677 678 return 0; 679 } 680 681 u32 intel_dp_mode_to_fec_clock(u32 mode_clock) 682 { 683 return div_u64(mul_u32_u32(mode_clock, 1000000U), 684 DP_DSC_FEC_OVERHEAD_FACTOR); 685 } 686 687 static int 688 small_joiner_ram_size_bits(struct drm_i915_private *i915) 689 { 690 if (DISPLAY_VER(i915) >= 13) 691 return 17280 * 8; 692 else if (DISPLAY_VER(i915) >= 11) 693 return 7680 * 8; 694 else 695 return 6144 * 8; 696 } 697 698 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp) 699 { 700 u32 bits_per_pixel = bpp; 701 int i; 702 703 /* Error out if the max bpp is less than smallest allowed valid bpp */ 704 if (bits_per_pixel < valid_dsc_bpp[0]) { 705 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n", 706 bits_per_pixel, valid_dsc_bpp[0]); 707 return 0; 708 } 709 710 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */ 711 if (DISPLAY_VER(i915) >= 13) { 712 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); 713 714 /* 715 * According to BSpec, 27 is the max DSC output bpp, 716 * 8 is the min DSC output bpp. 717 * While we can still clamp higher bpp values to 27, saving bandwidth, 718 * if it is required to oompress up to bpp < 8, means we can't do 719 * that and probably means we can't fit the required mode, even with 720 * DSC enabled. 721 */ 722 if (bits_per_pixel < 8) { 723 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n", 724 bits_per_pixel); 725 return 0; 726 } 727 bits_per_pixel = min_t(u32, bits_per_pixel, 27); 728 } else { 729 /* Find the nearest match in the array of known BPPs from VESA */ 730 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { 731 if (bits_per_pixel < valid_dsc_bpp[i + 1]) 732 break; 733 } 734 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n", 735 bits_per_pixel, valid_dsc_bpp[i]); 736 737 bits_per_pixel = valid_dsc_bpp[i]; 738 } 739 740 return bits_per_pixel; 741 } 742 743 static 744 u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915, 745 u32 mode_clock, u32 mode_hdisplay, 746 bool bigjoiner) 747 { 748 u32 max_bpp_small_joiner_ram; 749 750 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ 751 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay; 752 753 if (bigjoiner) { 754 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; 755 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ 756 int ppc = 2; 757 u32 max_bpp_bigjoiner = 758 i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits / 759 intel_dp_mode_to_fec_clock(mode_clock); 760 761 max_bpp_small_joiner_ram *= 2; 762 763 return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner); 764 } 765 766 return max_bpp_small_joiner_ram; 767 } 768 769 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, 770 u32 link_clock, u32 lane_count, 771 u32 mode_clock, u32 mode_hdisplay, 772 bool bigjoiner, 773 enum intel_output_format output_format, 774 u32 pipe_bpp, 775 u32 timeslots) 776 { 777 u32 bits_per_pixel, joiner_max_bpp; 778 779 /* 780 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* 781 * (LinkSymbolClock)* 8 * (TimeSlots / 64) 782 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available) 783 * for MST -> TimeSlots has to be calculated, based on mode requirements 784 * 785 * Due to FEC overhead, the available bw is reduced to 97.2261%. 786 * To support the given mode: 787 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead 788 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead 789 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock 790 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) / 791 * (ModeClock / FEC Overhead) 792 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) / 793 * (ModeClock / FEC Overhead * 8) 794 */ 795 bits_per_pixel = ((link_clock * lane_count) * timeslots) / 796 (intel_dp_mode_to_fec_clock(mode_clock) * 8); 797 798 /* Bandwidth required for 420 is half, that of 444 format */ 799 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 800 bits_per_pixel *= 2; 801 802 /* 803 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum 804 * supported PPS value can be 63.9375 and with the further 805 * mention that for 420, 422 formats, bpp should be programmed double 806 * the target bpp restricting our target bpp to be 31.9375 at max. 807 */ 808 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 809 bits_per_pixel = min_t(u32, bits_per_pixel, 31); 810 811 drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots " 812 "total bw %u pixel clock %u\n", 813 bits_per_pixel, timeslots, 814 (link_clock * lane_count * 8), 815 intel_dp_mode_to_fec_clock(mode_clock)); 816 817 joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock, 818 mode_hdisplay, bigjoiner); 819 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp); 820 821 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp); 822 823 return bits_per_pixel; 824 } 825 826 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, 827 int mode_clock, int mode_hdisplay, 828 bool bigjoiner) 829 { 830 struct drm_i915_private *i915 = to_i915(connector->base.dev); 831 u8 min_slice_count, i; 832 int max_slice_width; 833 834 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) 835 min_slice_count = DIV_ROUND_UP(mode_clock, 836 DP_DSC_MAX_ENC_THROUGHPUT_0); 837 else 838 min_slice_count = DIV_ROUND_UP(mode_clock, 839 DP_DSC_MAX_ENC_THROUGHPUT_1); 840 841 /* 842 * Due to some DSC engine BW limitations, we need to enable second 843 * slice and VDSC engine, whenever we approach close enough to max CDCLK 844 */ 845 if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100)) 846 min_slice_count = max_t(u8, min_slice_count, 2); 847 848 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd); 849 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { 850 drm_dbg_kms(&i915->drm, 851 "Unsupported slice width %d by DP DSC Sink device\n", 852 max_slice_width); 853 return 0; 854 } 855 /* Also take into account max slice width */ 856 min_slice_count = max_t(u8, min_slice_count, 857 DIV_ROUND_UP(mode_hdisplay, 858 max_slice_width)); 859 860 /* Find the closest match to the valid slice count values */ 861 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { 862 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner; 863 864 if (test_slice_count > 865 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) 866 break; 867 868 /* big joiner needs small joiner to be enabled */ 869 if (bigjoiner && test_slice_count < 4) 870 continue; 871 872 if (min_slice_count <= test_slice_count) 873 return test_slice_count; 874 } 875 876 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n", 877 min_slice_count); 878 return 0; 879 } 880 881 static bool source_can_output(struct intel_dp *intel_dp, 882 enum intel_output_format format) 883 { 884 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 885 886 switch (format) { 887 case INTEL_OUTPUT_FORMAT_RGB: 888 return true; 889 890 case INTEL_OUTPUT_FORMAT_YCBCR444: 891 /* 892 * No YCbCr output support on gmch platforms. 893 * Also, ILK doesn't seem capable of DP YCbCr output. 894 * The displayed image is severly corrupted. SNB+ is fine. 895 */ 896 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915); 897 898 case INTEL_OUTPUT_FORMAT_YCBCR420: 899 /* Platform < Gen 11 cannot output YCbCr420 format */ 900 return DISPLAY_VER(i915) >= 11; 901 902 default: 903 MISSING_CASE(format); 904 return false; 905 } 906 } 907 908 static bool 909 dfp_can_convert_from_rgb(struct intel_dp *intel_dp, 910 enum intel_output_format sink_format) 911 { 912 if (!drm_dp_is_branch(intel_dp->dpcd)) 913 return false; 914 915 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) 916 return intel_dp->dfp.rgb_to_ycbcr; 917 918 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 919 return intel_dp->dfp.rgb_to_ycbcr && 920 intel_dp->dfp.ycbcr_444_to_420; 921 922 return false; 923 } 924 925 static bool 926 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp, 927 enum intel_output_format sink_format) 928 { 929 if (!drm_dp_is_branch(intel_dp->dpcd)) 930 return false; 931 932 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 933 return intel_dp->dfp.ycbcr_444_to_420; 934 935 return false; 936 } 937 938 static bool 939 dfp_can_convert(struct intel_dp *intel_dp, 940 enum intel_output_format output_format, 941 enum intel_output_format sink_format) 942 { 943 switch (output_format) { 944 case INTEL_OUTPUT_FORMAT_RGB: 945 return dfp_can_convert_from_rgb(intel_dp, sink_format); 946 case INTEL_OUTPUT_FORMAT_YCBCR444: 947 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format); 948 default: 949 MISSING_CASE(output_format); 950 return false; 951 } 952 953 return false; 954 } 955 956 static enum intel_output_format 957 intel_dp_output_format(struct intel_connector *connector, 958 enum intel_output_format sink_format) 959 { 960 struct intel_dp *intel_dp = intel_attached_dp(connector); 961 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 962 enum intel_output_format force_dsc_output_format = 963 intel_dp->force_dsc_output_format; 964 enum intel_output_format output_format; 965 if (force_dsc_output_format) { 966 if (source_can_output(intel_dp, force_dsc_output_format) && 967 (!drm_dp_is_branch(intel_dp->dpcd) || 968 sink_format != force_dsc_output_format || 969 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format))) 970 return force_dsc_output_format; 971 972 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n"); 973 } 974 975 if (sink_format == INTEL_OUTPUT_FORMAT_RGB || 976 dfp_can_convert_from_rgb(intel_dp, sink_format)) 977 output_format = INTEL_OUTPUT_FORMAT_RGB; 978 979 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 980 dfp_can_convert_from_ycbcr444(intel_dp, sink_format)) 981 output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 982 983 else 984 output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 985 986 drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format)); 987 988 return output_format; 989 } 990 991 int intel_dp_min_bpp(enum intel_output_format output_format) 992 { 993 if (output_format == INTEL_OUTPUT_FORMAT_RGB) 994 return 6 * 3; 995 else 996 return 8 * 3; 997 } 998 999 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) 1000 { 1001 /* 1002 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output 1003 * format of the number of bytes per pixel will be half the number 1004 * of bytes of RGB pixel. 1005 */ 1006 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1007 bpp /= 2; 1008 1009 return bpp; 1010 } 1011 1012 static enum intel_output_format 1013 intel_dp_sink_format(struct intel_connector *connector, 1014 const struct drm_display_mode *mode) 1015 { 1016 const struct drm_display_info *info = &connector->base.display_info; 1017 1018 if (drm_mode_is_420_only(info, mode)) 1019 return INTEL_OUTPUT_FORMAT_YCBCR420; 1020 1021 return INTEL_OUTPUT_FORMAT_RGB; 1022 } 1023 1024 static int 1025 intel_dp_mode_min_output_bpp(struct intel_connector *connector, 1026 const struct drm_display_mode *mode) 1027 { 1028 enum intel_output_format output_format, sink_format; 1029 1030 sink_format = intel_dp_sink_format(connector, mode); 1031 1032 output_format = intel_dp_output_format(connector, sink_format); 1033 1034 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); 1035 } 1036 1037 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv, 1038 int hdisplay) 1039 { 1040 /* 1041 * Older platforms don't like hdisplay==4096 with DP. 1042 * 1043 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline 1044 * and frame counter increment), but we don't get vblank interrupts, 1045 * and the pipe underruns immediately. The link also doesn't seem 1046 * to get trained properly. 1047 * 1048 * On CHV the vblank interrupts don't seem to disappear but 1049 * otherwise the symptoms are similar. 1050 * 1051 * TODO: confirm the behaviour on HSW+ 1052 */ 1053 return hdisplay == 4096 && !HAS_DDI(dev_priv); 1054 } 1055 1056 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp) 1057 { 1058 struct intel_connector *connector = intel_dp->attached_connector; 1059 const struct drm_display_info *info = &connector->base.display_info; 1060 int max_tmds_clock = intel_dp->dfp.max_tmds_clock; 1061 1062 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */ 1063 if (max_tmds_clock && info->max_tmds_clock) 1064 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); 1065 1066 return max_tmds_clock; 1067 } 1068 1069 static enum drm_mode_status 1070 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, 1071 int clock, int bpc, 1072 enum intel_output_format sink_format, 1073 bool respect_downstream_limits) 1074 { 1075 int tmds_clock, min_tmds_clock, max_tmds_clock; 1076 1077 if (!respect_downstream_limits) 1078 return MODE_OK; 1079 1080 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1081 1082 min_tmds_clock = intel_dp->dfp.min_tmds_clock; 1083 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp); 1084 1085 if (min_tmds_clock && tmds_clock < min_tmds_clock) 1086 return MODE_CLOCK_LOW; 1087 1088 if (max_tmds_clock && tmds_clock > max_tmds_clock) 1089 return MODE_CLOCK_HIGH; 1090 1091 return MODE_OK; 1092 } 1093 1094 static enum drm_mode_status 1095 intel_dp_mode_valid_downstream(struct intel_connector *connector, 1096 const struct drm_display_mode *mode, 1097 int target_clock) 1098 { 1099 struct intel_dp *intel_dp = intel_attached_dp(connector); 1100 const struct drm_display_info *info = &connector->base.display_info; 1101 enum drm_mode_status status; 1102 enum intel_output_format sink_format; 1103 1104 /* If PCON supports FRL MODE, check FRL bandwidth constraints */ 1105 if (intel_dp->dfp.pcon_max_frl_bw) { 1106 int target_bw; 1107 int max_frl_bw; 1108 int bpp = intel_dp_mode_min_output_bpp(connector, mode); 1109 1110 target_bw = bpp * target_clock; 1111 1112 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 1113 1114 /* converting bw from Gbps to Kbps*/ 1115 max_frl_bw = max_frl_bw * 1000000; 1116 1117 if (target_bw > max_frl_bw) 1118 return MODE_CLOCK_HIGH; 1119 1120 return MODE_OK; 1121 } 1122 1123 if (intel_dp->dfp.max_dotclock && 1124 target_clock > intel_dp->dfp.max_dotclock) 1125 return MODE_CLOCK_HIGH; 1126 1127 sink_format = intel_dp_sink_format(connector, mode); 1128 1129 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ 1130 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1131 8, sink_format, true); 1132 1133 if (status != MODE_OK) { 1134 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 1135 !connector->base.ycbcr_420_allowed || 1136 !drm_mode_is_420_also(info, mode)) 1137 return status; 1138 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1139 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1140 8, sink_format, true); 1141 if (status != MODE_OK) 1142 return status; 1143 } 1144 1145 return MODE_OK; 1146 } 1147 1148 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, 1149 int hdisplay, int clock) 1150 { 1151 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1152 1153 if (!intel_dp_can_bigjoiner(intel_dp)) 1154 return false; 1155 1156 return clock > i915->max_dotclk_freq || hdisplay > 5120; 1157 } 1158 1159 static enum drm_mode_status 1160 intel_dp_mode_valid(struct drm_connector *_connector, 1161 struct drm_display_mode *mode) 1162 { 1163 struct intel_connector *connector = to_intel_connector(_connector); 1164 struct intel_dp *intel_dp = intel_attached_dp(connector); 1165 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1166 const struct drm_display_mode *fixed_mode; 1167 int target_clock = mode->clock; 1168 int max_rate, mode_rate, max_lanes, max_link_clock; 1169 int max_dotclk = dev_priv->max_dotclk_freq; 1170 u16 dsc_max_compressed_bpp = 0; 1171 u8 dsc_slice_count = 0; 1172 enum drm_mode_status status; 1173 bool dsc = false, bigjoiner = false; 1174 1175 status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 1176 if (status != MODE_OK) 1177 return status; 1178 1179 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1180 return MODE_H_ILLEGAL; 1181 1182 fixed_mode = intel_panel_fixed_mode(connector, mode); 1183 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 1184 status = intel_panel_mode_valid(connector, mode); 1185 if (status != MODE_OK) 1186 return status; 1187 1188 target_clock = fixed_mode->clock; 1189 } 1190 1191 if (mode->clock < 10000) 1192 return MODE_CLOCK_LOW; 1193 1194 if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) { 1195 bigjoiner = true; 1196 max_dotclk *= 2; 1197 } 1198 if (target_clock > max_dotclk) 1199 return MODE_CLOCK_HIGH; 1200 1201 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) 1202 return MODE_H_ILLEGAL; 1203 1204 max_link_clock = intel_dp_max_link_rate(intel_dp); 1205 max_lanes = intel_dp_max_lane_count(intel_dp); 1206 1207 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 1208 mode_rate = intel_dp_link_required(target_clock, 1209 intel_dp_mode_min_output_bpp(connector, mode)); 1210 1211 if (HAS_DSC(dev_priv) && 1212 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) { 1213 enum intel_output_format sink_format, output_format; 1214 int pipe_bpp; 1215 1216 sink_format = intel_dp_sink_format(connector, mode); 1217 output_format = intel_dp_output_format(connector, sink_format); 1218 /* 1219 * TBD pass the connector BPC, 1220 * for now U8_MAX so that max BPC on that platform would be picked 1221 */ 1222 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); 1223 1224 /* 1225 * Output bpp is stored in 6.4 format so right shift by 4 to get the 1226 * integer value since we support only integer values of bpp. 1227 */ 1228 if (intel_dp_is_edp(intel_dp)) { 1229 dsc_max_compressed_bpp = 1230 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; 1231 dsc_slice_count = 1232 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 1233 true); 1234 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { 1235 dsc_max_compressed_bpp = 1236 intel_dp_dsc_get_max_compressed_bpp(dev_priv, 1237 max_link_clock, 1238 max_lanes, 1239 target_clock, 1240 mode->hdisplay, 1241 bigjoiner, 1242 output_format, 1243 pipe_bpp, 64); 1244 dsc_slice_count = 1245 intel_dp_dsc_get_slice_count(connector, 1246 target_clock, 1247 mode->hdisplay, 1248 bigjoiner); 1249 } 1250 1251 dsc = dsc_max_compressed_bpp && dsc_slice_count; 1252 } 1253 1254 /* 1255 * Big joiner configuration needs DSC for TGL which is not true for 1256 * XE_LPD where uncompressed joiner is supported. 1257 */ 1258 if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) 1259 return MODE_CLOCK_HIGH; 1260 1261 if (mode_rate > max_rate && !dsc) 1262 return MODE_CLOCK_HIGH; 1263 1264 status = intel_dp_mode_valid_downstream(connector, mode, target_clock); 1265 if (status != MODE_OK) 1266 return status; 1267 1268 return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner); 1269 } 1270 1271 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915) 1272 { 1273 return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915); 1274 } 1275 1276 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915) 1277 { 1278 return DISPLAY_VER(i915) >= 10; 1279 } 1280 1281 static void snprintf_int_array(char *str, size_t len, 1282 const int *array, int nelem) 1283 { 1284 int i; 1285 1286 str[0] = '\0'; 1287 1288 for (i = 0; i < nelem; i++) { 1289 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); 1290 if (r >= len) 1291 return; 1292 str += r; 1293 len -= r; 1294 } 1295 } 1296 1297 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1298 { 1299 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1300 char str[128]; /* FIXME: too big for stack? */ 1301 1302 if (!drm_debug_enabled(DRM_UT_KMS)) 1303 return; 1304 1305 snprintf_int_array(str, sizeof(str), 1306 intel_dp->source_rates, intel_dp->num_source_rates); 1307 drm_dbg_kms(&i915->drm, "source rates: %s\n", str); 1308 1309 snprintf_int_array(str, sizeof(str), 1310 intel_dp->sink_rates, intel_dp->num_sink_rates); 1311 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str); 1312 1313 snprintf_int_array(str, sizeof(str), 1314 intel_dp->common_rates, intel_dp->num_common_rates); 1315 drm_dbg_kms(&i915->drm, "common rates: %s\n", str); 1316 } 1317 1318 int 1319 intel_dp_max_link_rate(struct intel_dp *intel_dp) 1320 { 1321 int len; 1322 1323 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); 1324 1325 return intel_dp_common_rate(intel_dp, len - 1); 1326 } 1327 1328 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1329 { 1330 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1331 int i = intel_dp_rate_index(intel_dp->sink_rates, 1332 intel_dp->num_sink_rates, rate); 1333 1334 if (drm_WARN_ON(&i915->drm, i < 0)) 1335 i = 0; 1336 1337 return i; 1338 } 1339 1340 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1341 u8 *link_bw, u8 *rate_select) 1342 { 1343 /* eDP 1.4 rate select method. */ 1344 if (intel_dp->use_rate_select) { 1345 *link_bw = 0; 1346 *rate_select = 1347 intel_dp_rate_select(intel_dp, port_clock); 1348 } else { 1349 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1350 *rate_select = 0; 1351 } 1352 } 1353 1354 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp) 1355 { 1356 struct intel_connector *connector = intel_dp->attached_connector; 1357 1358 return connector->base.display_info.is_hdmi; 1359 } 1360 1361 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, 1362 const struct intel_crtc_state *pipe_config) 1363 { 1364 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1365 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1366 1367 if (DISPLAY_VER(dev_priv) >= 12) 1368 return true; 1369 1370 if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A) 1371 return true; 1372 1373 return false; 1374 } 1375 1376 static bool intel_dp_supports_fec(struct intel_dp *intel_dp, 1377 const struct intel_connector *connector, 1378 const struct intel_crtc_state *pipe_config) 1379 { 1380 return intel_dp_source_supports_fec(intel_dp, pipe_config) && 1381 drm_dp_sink_supports_fec(connector->dp.fec_capability); 1382 } 1383 1384 static bool intel_dp_supports_dsc(const struct intel_connector *connector, 1385 const struct intel_crtc_state *crtc_state) 1386 { 1387 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable) 1388 return false; 1389 1390 return intel_dsc_source_support(crtc_state) && 1391 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd); 1392 } 1393 1394 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, 1395 const struct intel_crtc_state *crtc_state, 1396 int bpc, bool respect_downstream_limits) 1397 { 1398 int clock = crtc_state->hw.adjusted_mode.crtc_clock; 1399 1400 /* 1401 * Current bpc could already be below 8bpc due to 1402 * FDI bandwidth constraints or other limits. 1403 * HDMI minimum is 8bpc however. 1404 */ 1405 bpc = max(bpc, 8); 1406 1407 /* 1408 * We will never exceed downstream TMDS clock limits while 1409 * attempting deep color. If the user insists on forcing an 1410 * out of spec mode they will have to be satisfied with 8bpc. 1411 */ 1412 if (!respect_downstream_limits) 1413 bpc = 8; 1414 1415 for (; bpc >= 8; bpc -= 2) { 1416 if (intel_hdmi_bpc_possible(crtc_state, bpc, 1417 intel_dp_has_hdmi_sink(intel_dp)) && 1418 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, 1419 respect_downstream_limits) == MODE_OK) 1420 return bpc; 1421 } 1422 1423 return -EINVAL; 1424 } 1425 1426 static int intel_dp_max_bpp(struct intel_dp *intel_dp, 1427 const struct intel_crtc_state *crtc_state, 1428 bool respect_downstream_limits) 1429 { 1430 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1431 struct intel_connector *intel_connector = intel_dp->attached_connector; 1432 int bpp, bpc; 1433 1434 bpc = crtc_state->pipe_bpp / 3; 1435 1436 if (intel_dp->dfp.max_bpc) 1437 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); 1438 1439 if (intel_dp->dfp.min_tmds_clock) { 1440 int max_hdmi_bpc; 1441 1442 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc, 1443 respect_downstream_limits); 1444 if (max_hdmi_bpc < 0) 1445 return 0; 1446 1447 bpc = min(bpc, max_hdmi_bpc); 1448 } 1449 1450 bpp = bpc * 3; 1451 if (intel_dp_is_edp(intel_dp)) { 1452 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1453 if (intel_connector->base.display_info.bpc == 0 && 1454 intel_connector->panel.vbt.edp.bpp && 1455 intel_connector->panel.vbt.edp.bpp < bpp) { 1456 drm_dbg_kms(&dev_priv->drm, 1457 "clamping bpp for eDP panel to BIOS-provided %i\n", 1458 intel_connector->panel.vbt.edp.bpp); 1459 bpp = intel_connector->panel.vbt.edp.bpp; 1460 } 1461 } 1462 1463 return bpp; 1464 } 1465 1466 /* Adjust link config limits based on compliance test requests. */ 1467 void 1468 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, 1469 struct intel_crtc_state *pipe_config, 1470 struct link_config_limits *limits) 1471 { 1472 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1473 1474 /* For DP Compliance we override the computed bpp for the pipe */ 1475 if (intel_dp->compliance.test_data.bpc != 0) { 1476 int bpp = 3 * intel_dp->compliance.test_data.bpc; 1477 1478 limits->pipe.min_bpp = limits->pipe.max_bpp = bpp; 1479 pipe_config->dither_force_disable = bpp == 6 * 3; 1480 1481 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp); 1482 } 1483 1484 /* Use values requested by Compliance Test Request */ 1485 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { 1486 int index; 1487 1488 /* Validate the compliance test data since max values 1489 * might have changed due to link train fallback. 1490 */ 1491 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, 1492 intel_dp->compliance.test_lane_count)) { 1493 index = intel_dp_rate_index(intel_dp->common_rates, 1494 intel_dp->num_common_rates, 1495 intel_dp->compliance.test_link_rate); 1496 if (index >= 0) 1497 limits->min_rate = limits->max_rate = 1498 intel_dp->compliance.test_link_rate; 1499 limits->min_lane_count = limits->max_lane_count = 1500 intel_dp->compliance.test_lane_count; 1501 } 1502 } 1503 } 1504 1505 static bool has_seamless_m_n(struct intel_connector *connector) 1506 { 1507 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1508 1509 /* 1510 * Seamless M/N reprogramming only implemented 1511 * for BDW+ double buffered M/N registers so far. 1512 */ 1513 return HAS_DOUBLE_BUFFERED_M_N(i915) && 1514 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 1515 } 1516 1517 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state, 1518 const struct drm_connector_state *conn_state) 1519 { 1520 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1521 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1522 1523 /* FIXME a bit of a mess wrt clock vs. crtc_clock */ 1524 if (has_seamless_m_n(connector)) 1525 return intel_panel_highest_mode(connector, adjusted_mode)->clock; 1526 else 1527 return adjusted_mode->crtc_clock; 1528 } 1529 1530 /* Optimize link config in order: max bpp, min clock, min lanes */ 1531 static int 1532 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 1533 struct intel_crtc_state *pipe_config, 1534 const struct drm_connector_state *conn_state, 1535 const struct link_config_limits *limits) 1536 { 1537 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); 1538 int mode_rate, link_rate, link_avail; 1539 1540 for (bpp = to_bpp_int(limits->link.max_bpp_x16); 1541 bpp >= to_bpp_int(limits->link.min_bpp_x16); 1542 bpp -= 2 * 3) { 1543 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); 1544 1545 mode_rate = intel_dp_link_required(clock, link_bpp); 1546 1547 for (i = 0; i < intel_dp->num_common_rates; i++) { 1548 link_rate = intel_dp_common_rate(intel_dp, i); 1549 if (link_rate < limits->min_rate || 1550 link_rate > limits->max_rate) 1551 continue; 1552 1553 for (lane_count = limits->min_lane_count; 1554 lane_count <= limits->max_lane_count; 1555 lane_count <<= 1) { 1556 link_avail = intel_dp_max_data_rate(link_rate, 1557 lane_count); 1558 1559 if (mode_rate <= link_avail) { 1560 pipe_config->lane_count = lane_count; 1561 pipe_config->pipe_bpp = bpp; 1562 pipe_config->port_clock = link_rate; 1563 1564 return 0; 1565 } 1566 } 1567 } 1568 } 1569 1570 return -EINVAL; 1571 } 1572 1573 static 1574 u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) 1575 { 1576 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ 1577 if (DISPLAY_VER(i915) >= 12) 1578 return 12; 1579 if (DISPLAY_VER(i915) == 11) 1580 return 10; 1581 1582 return 0; 1583 } 1584 1585 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, 1586 u8 max_req_bpc) 1587 { 1588 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1589 int i, num_bpc; 1590 u8 dsc_bpc[3] = {}; 1591 u8 dsc_max_bpc; 1592 1593 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915); 1594 1595 if (!dsc_max_bpc) 1596 return dsc_max_bpc; 1597 1598 dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); 1599 1600 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, 1601 dsc_bpc); 1602 for (i = 0; i < num_bpc; i++) { 1603 if (dsc_max_bpc >= dsc_bpc[i]) 1604 return dsc_bpc[i] * 3; 1605 } 1606 1607 return 0; 1608 } 1609 1610 static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915) 1611 { 1612 return DISPLAY_VER(i915) >= 14 ? 2 : 1; 1613 } 1614 1615 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 1616 { 1617 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> 1618 DP_DSC_MINOR_SHIFT; 1619 } 1620 1621 static int intel_dp_get_slice_height(int vactive) 1622 { 1623 int slice_height; 1624 1625 /* 1626 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108 1627 * lines is an optimal slice height, but any size can be used as long as 1628 * vertical active integer multiple and maximum vertical slice count 1629 * requirements are met. 1630 */ 1631 for (slice_height = 108; slice_height <= vactive; slice_height += 2) 1632 if (vactive % slice_height == 0) 1633 return slice_height; 1634 1635 /* 1636 * Highly unlikely we reach here as most of the resolutions will end up 1637 * finding appropriate slice_height in above loop but returning 1638 * slice_height as 2 here as it should work with all resolutions. 1639 */ 1640 return 2; 1641 } 1642 1643 static int intel_dp_dsc_compute_params(const struct intel_connector *connector, 1644 struct intel_crtc_state *crtc_state) 1645 { 1646 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1647 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1648 u8 line_buf_depth; 1649 int ret; 1650 1651 /* 1652 * RC_MODEL_SIZE is currently a constant across all configurations. 1653 * 1654 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and 1655 * DP_DSC_RC_BUF_SIZE for this. 1656 */ 1657 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1658 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1659 1660 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); 1661 1662 ret = intel_dsc_compute_params(crtc_state); 1663 if (ret) 1664 return ret; 1665 1666 vdsc_cfg->dsc_version_major = 1667 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 1668 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; 1669 vdsc_cfg->dsc_version_minor = 1670 min(intel_dp_source_dsc_version_minor(i915), 1671 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)); 1672 if (vdsc_cfg->convert_rgb) 1673 vdsc_cfg->convert_rgb = 1674 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & 1675 DP_DSC_RGB; 1676 1677 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd); 1678 if (!line_buf_depth) { 1679 drm_dbg_kms(&i915->drm, 1680 "DSC Sink Line Buffer Depth invalid\n"); 1681 return -EINVAL; 1682 } 1683 1684 if (vdsc_cfg->dsc_version_minor == 2) 1685 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? 1686 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; 1687 else 1688 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? 1689 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; 1690 1691 vdsc_cfg->block_pred_enable = 1692 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & 1693 DP_DSC_BLK_PREDICTION_IS_SUPPORTED; 1694 1695 return drm_dsc_compute_rc_parameters(vdsc_cfg); 1696 } 1697 1698 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector, 1699 enum intel_output_format output_format) 1700 { 1701 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1702 u8 sink_dsc_format; 1703 1704 switch (output_format) { 1705 case INTEL_OUTPUT_FORMAT_RGB: 1706 sink_dsc_format = DP_DSC_RGB; 1707 break; 1708 case INTEL_OUTPUT_FORMAT_YCBCR444: 1709 sink_dsc_format = DP_DSC_YCbCr444; 1710 break; 1711 case INTEL_OUTPUT_FORMAT_YCBCR420: 1712 if (min(intel_dp_source_dsc_version_minor(i915), 1713 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2) 1714 return false; 1715 sink_dsc_format = DP_DSC_YCbCr420_Native; 1716 break; 1717 default: 1718 return false; 1719 } 1720 1721 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); 1722 } 1723 1724 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock, 1725 u32 lane_count, u32 mode_clock, 1726 enum intel_output_format output_format, 1727 int timeslots) 1728 { 1729 u32 available_bw, required_bw; 1730 1731 available_bw = (link_clock * lane_count * timeslots) / 8; 1732 required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock)); 1733 1734 return available_bw > required_bw; 1735 } 1736 1737 static int dsc_compute_link_config(struct intel_dp *intel_dp, 1738 struct intel_crtc_state *pipe_config, 1739 struct link_config_limits *limits, 1740 u16 compressed_bpp, 1741 int timeslots) 1742 { 1743 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1744 int link_rate, lane_count; 1745 int i; 1746 1747 for (i = 0; i < intel_dp->num_common_rates; i++) { 1748 link_rate = intel_dp_common_rate(intel_dp, i); 1749 if (link_rate < limits->min_rate || link_rate > limits->max_rate) 1750 continue; 1751 1752 for (lane_count = limits->min_lane_count; 1753 lane_count <= limits->max_lane_count; 1754 lane_count <<= 1) { 1755 if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count, 1756 adjusted_mode->clock, 1757 pipe_config->output_format, 1758 timeslots)) 1759 continue; 1760 1761 pipe_config->lane_count = lane_count; 1762 pipe_config->port_clock = link_rate; 1763 1764 return 0; 1765 } 1766 } 1767 1768 return -EINVAL; 1769 } 1770 1771 static 1772 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, 1773 struct intel_crtc_state *pipe_config, 1774 int bpc) 1775 { 1776 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd); 1777 1778 if (max_bppx16) 1779 return max_bppx16; 1780 /* 1781 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate 1782 * values as given in spec Table 2-157 DP v2.0 1783 */ 1784 switch (pipe_config->output_format) { 1785 case INTEL_OUTPUT_FORMAT_RGB: 1786 case INTEL_OUTPUT_FORMAT_YCBCR444: 1787 return (3 * bpc) << 4; 1788 case INTEL_OUTPUT_FORMAT_YCBCR420: 1789 return (3 * (bpc / 2)) << 4; 1790 default: 1791 MISSING_CASE(pipe_config->output_format); 1792 break; 1793 } 1794 1795 return 0; 1796 } 1797 1798 static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) 1799 { 1800 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ 1801 switch (pipe_config->output_format) { 1802 case INTEL_OUTPUT_FORMAT_RGB: 1803 case INTEL_OUTPUT_FORMAT_YCBCR444: 1804 return 8; 1805 case INTEL_OUTPUT_FORMAT_YCBCR420: 1806 return 6; 1807 default: 1808 MISSING_CASE(pipe_config->output_format); 1809 break; 1810 } 1811 1812 return 0; 1813 } 1814 1815 static int dsc_sink_max_compressed_bpp(const struct intel_connector *connector, 1816 struct intel_crtc_state *pipe_config, 1817 int bpc) 1818 { 1819 return intel_dp_dsc_max_sink_compressed_bppx16(connector, 1820 pipe_config, bpc) >> 4; 1821 } 1822 1823 static int dsc_src_min_compressed_bpp(void) 1824 { 1825 /* Min Compressed bpp supported by source is 8 */ 1826 return 8; 1827 } 1828 1829 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) 1830 { 1831 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1832 1833 /* 1834 * Max Compressed bpp for Gen 13+ is 27bpp. 1835 * For earlier platform is 23bpp. (Bspec:49259). 1836 */ 1837 if (DISPLAY_VER(i915) <= 12) 1838 return 23; 1839 else 1840 return 27; 1841 } 1842 1843 /* 1844 * From a list of valid compressed bpps try different compressed bpp and find a 1845 * suitable link configuration that can support it. 1846 */ 1847 static int 1848 icl_dsc_compute_link_config(struct intel_dp *intel_dp, 1849 struct intel_crtc_state *pipe_config, 1850 struct link_config_limits *limits, 1851 int dsc_max_bpp, 1852 int dsc_min_bpp, 1853 int pipe_bpp, 1854 int timeslots) 1855 { 1856 int i, ret; 1857 1858 /* Compressed BPP should be less than the Input DSC bpp */ 1859 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); 1860 1861 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { 1862 if (valid_dsc_bpp[i] < dsc_min_bpp || 1863 valid_dsc_bpp[i] > dsc_max_bpp) 1864 break; 1865 1866 ret = dsc_compute_link_config(intel_dp, 1867 pipe_config, 1868 limits, 1869 valid_dsc_bpp[i], 1870 timeslots); 1871 if (ret == 0) { 1872 pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i]; 1873 return 0; 1874 } 1875 } 1876 1877 return -EINVAL; 1878 } 1879 1880 /* 1881 * From XE_LPD onwards we supports compression bpps in steps of 1 up to 1882 * uncompressed bpp-1. So we start from max compressed bpp and see if any 1883 * link configuration is able to support that compressed bpp, if not we 1884 * step down and check for lower compressed bpp. 1885 */ 1886 static int 1887 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, 1888 struct intel_crtc_state *pipe_config, 1889 struct link_config_limits *limits, 1890 int dsc_max_bpp, 1891 int dsc_min_bpp, 1892 int pipe_bpp, 1893 int timeslots) 1894 { 1895 u16 compressed_bpp; 1896 int ret; 1897 1898 /* Compressed BPP should be less than the Input DSC bpp */ 1899 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); 1900 1901 for (compressed_bpp = dsc_max_bpp; 1902 compressed_bpp >= dsc_min_bpp; 1903 compressed_bpp--) { 1904 ret = dsc_compute_link_config(intel_dp, 1905 pipe_config, 1906 limits, 1907 compressed_bpp, 1908 timeslots); 1909 if (ret == 0) { 1910 pipe_config->dsc.compressed_bpp = compressed_bpp; 1911 return 0; 1912 } 1913 } 1914 return -EINVAL; 1915 } 1916 1917 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, 1918 const struct intel_connector *connector, 1919 struct intel_crtc_state *pipe_config, 1920 struct link_config_limits *limits, 1921 int pipe_bpp, 1922 int timeslots) 1923 { 1924 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1925 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1926 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; 1927 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; 1928 int dsc_joiner_max_bpp; 1929 1930 dsc_src_min_bpp = dsc_src_min_compressed_bpp(); 1931 dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config); 1932 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); 1933 dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16)); 1934 1935 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 1936 dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(connector, pipe_config, pipe_bpp / 3); 1937 dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; 1938 1939 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock, 1940 adjusted_mode->hdisplay, 1941 pipe_config->bigjoiner_pipes); 1942 dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp); 1943 dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16)); 1944 1945 if (DISPLAY_VER(i915) >= 13) 1946 return xelpd_dsc_compute_link_config(intel_dp, pipe_config, limits, 1947 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); 1948 return icl_dsc_compute_link_config(intel_dp, pipe_config, limits, 1949 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); 1950 } 1951 1952 static 1953 u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) 1954 { 1955 /* Min DSC Input BPC for ICL+ is 8 */ 1956 return HAS_DSC(i915) ? 8 : 0; 1957 } 1958 1959 static 1960 bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, 1961 struct drm_connector_state *conn_state, 1962 struct link_config_limits *limits, 1963 int pipe_bpp) 1964 { 1965 u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp; 1966 1967 dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc); 1968 dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915); 1969 1970 dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp); 1971 dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp); 1972 1973 return pipe_bpp >= dsc_min_pipe_bpp && 1974 pipe_bpp <= dsc_max_pipe_bpp; 1975 } 1976 1977 static 1978 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, 1979 struct drm_connector_state *conn_state, 1980 struct link_config_limits *limits) 1981 { 1982 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1983 int forced_bpp; 1984 1985 if (!intel_dp->force_dsc_bpc) 1986 return 0; 1987 1988 forced_bpp = intel_dp->force_dsc_bpc * 3; 1989 1990 if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) { 1991 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc); 1992 return forced_bpp; 1993 } 1994 1995 drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n", 1996 intel_dp->force_dsc_bpc); 1997 1998 return 0; 1999 } 2000 2001 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2002 struct intel_crtc_state *pipe_config, 2003 struct drm_connector_state *conn_state, 2004 struct link_config_limits *limits, 2005 int timeslots) 2006 { 2007 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2008 const struct intel_connector *connector = 2009 to_intel_connector(conn_state->connector); 2010 u8 max_req_bpc = conn_state->max_requested_bpc; 2011 u8 dsc_max_bpc, dsc_max_bpp; 2012 u8 dsc_min_bpc, dsc_min_bpp; 2013 u8 dsc_bpc[3] = {}; 2014 int forced_bpp, pipe_bpp; 2015 int num_bpc, i, ret; 2016 2017 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits); 2018 2019 if (forced_bpp) { 2020 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, 2021 limits, forced_bpp, timeslots); 2022 if (ret == 0) { 2023 pipe_config->pipe_bpp = forced_bpp; 2024 return 0; 2025 } 2026 } 2027 2028 dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915); 2029 if (!dsc_max_bpc) 2030 return -EINVAL; 2031 2032 dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); 2033 dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp); 2034 2035 dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915); 2036 dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp); 2037 2038 /* 2039 * Get the maximum DSC bpc that will be supported by any valid 2040 * link configuration and compressed bpp. 2041 */ 2042 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); 2043 for (i = 0; i < num_bpc; i++) { 2044 pipe_bpp = dsc_bpc[i] * 3; 2045 if (pipe_bpp < dsc_min_bpp) 2046 break; 2047 if (pipe_bpp > dsc_max_bpp) 2048 continue; 2049 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, 2050 limits, pipe_bpp, timeslots); 2051 if (ret == 0) { 2052 pipe_config->pipe_bpp = pipe_bpp; 2053 return 0; 2054 } 2055 } 2056 2057 return -EINVAL; 2058 } 2059 2060 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2061 struct intel_crtc_state *pipe_config, 2062 struct drm_connector_state *conn_state, 2063 struct link_config_limits *limits) 2064 { 2065 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2066 struct intel_connector *connector = 2067 to_intel_connector(conn_state->connector); 2068 int pipe_bpp, forced_bpp; 2069 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; 2070 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; 2071 2072 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits); 2073 2074 if (forced_bpp) { 2075 pipe_bpp = forced_bpp; 2076 } else { 2077 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc); 2078 2079 /* For eDP use max bpp that can be supported with DSC. */ 2080 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); 2081 if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) { 2082 drm_dbg_kms(&i915->drm, 2083 "Computed BPC is not in DSC BPC limits\n"); 2084 return -EINVAL; 2085 } 2086 } 2087 pipe_config->port_clock = limits->max_rate; 2088 pipe_config->lane_count = limits->max_lane_count; 2089 2090 dsc_src_min_bpp = dsc_src_min_compressed_bpp(); 2091 dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config); 2092 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); 2093 dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16)); 2094 2095 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 2096 dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(connector, pipe_config, pipe_bpp / 3); 2097 dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; 2098 dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16)); 2099 2100 /* Compressed BPP should be less than the Input DSC bpp */ 2101 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); 2102 2103 pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp); 2104 2105 pipe_config->pipe_bpp = pipe_bpp; 2106 2107 return 0; 2108 } 2109 2110 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 2111 struct intel_crtc_state *pipe_config, 2112 struct drm_connector_state *conn_state, 2113 struct link_config_limits *limits, 2114 int timeslots, 2115 bool compute_pipe_bpp) 2116 { 2117 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2118 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2119 const struct intel_connector *connector = 2120 to_intel_connector(conn_state->connector); 2121 const struct drm_display_mode *adjusted_mode = 2122 &pipe_config->hw.adjusted_mode; 2123 int ret; 2124 2125 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && 2126 intel_dp_supports_fec(intel_dp, connector, pipe_config); 2127 2128 if (!intel_dp_supports_dsc(connector, pipe_config)) 2129 return -EINVAL; 2130 2131 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format)) 2132 return -EINVAL; 2133 2134 /* 2135 * compute pipe bpp is set to false for DP MST DSC case 2136 * and compressed_bpp is calculated same time once 2137 * vpci timeslots are allocated, because overall bpp 2138 * calculation procedure is bit different for MST case. 2139 */ 2140 if (compute_pipe_bpp) { 2141 if (intel_dp_is_edp(intel_dp)) 2142 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2143 conn_state, limits); 2144 else 2145 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2146 conn_state, limits, timeslots); 2147 if (ret) { 2148 drm_dbg_kms(&dev_priv->drm, 2149 "No Valid pipe bpp for given mode ret = %d\n", ret); 2150 return ret; 2151 } 2152 } 2153 2154 /* Calculate Slice count */ 2155 if (intel_dp_is_edp(intel_dp)) { 2156 pipe_config->dsc.slice_count = 2157 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 2158 true); 2159 if (!pipe_config->dsc.slice_count) { 2160 drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n", 2161 pipe_config->dsc.slice_count); 2162 return -EINVAL; 2163 } 2164 } else { 2165 u8 dsc_dp_slice_count; 2166 2167 dsc_dp_slice_count = 2168 intel_dp_dsc_get_slice_count(connector, 2169 adjusted_mode->crtc_clock, 2170 adjusted_mode->crtc_hdisplay, 2171 pipe_config->bigjoiner_pipes); 2172 if (!dsc_dp_slice_count) { 2173 drm_dbg_kms(&dev_priv->drm, 2174 "Compressed Slice Count not supported\n"); 2175 return -EINVAL; 2176 } 2177 2178 pipe_config->dsc.slice_count = dsc_dp_slice_count; 2179 } 2180 /* 2181 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate 2182 * is greater than the maximum Cdclock and if slice count is even 2183 * then we need to use 2 VDSC instances. 2184 */ 2185 if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1) 2186 pipe_config->dsc.dsc_split = true; 2187 2188 ret = intel_dp_dsc_compute_params(connector, pipe_config); 2189 if (ret < 0) { 2190 drm_dbg_kms(&dev_priv->drm, 2191 "Cannot compute valid DSC parameters for Input Bpp = %d " 2192 "Compressed BPP = %d\n", 2193 pipe_config->pipe_bpp, 2194 pipe_config->dsc.compressed_bpp); 2195 return ret; 2196 } 2197 2198 pipe_config->dsc.compression_enable = true; 2199 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " 2200 "Compressed Bpp = %d Slice Count = %d\n", 2201 pipe_config->pipe_bpp, 2202 pipe_config->dsc.compressed_bpp, 2203 pipe_config->dsc.slice_count); 2204 2205 return 0; 2206 } 2207 2208 /** 2209 * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits 2210 * @intel_dp: intel DP 2211 * @crtc_state: crtc state 2212 * @dsc: DSC compression mode 2213 * @limits: link configuration limits 2214 * 2215 * Calculates the output link min, max bpp values in @limits based on the 2216 * pipe bpp range, @crtc_state and @dsc mode. 2217 * 2218 * Returns %true in case of success. 2219 */ 2220 bool 2221 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, 2222 const struct intel_crtc_state *crtc_state, 2223 bool dsc, 2224 struct link_config_limits *limits) 2225 { 2226 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2227 const struct drm_display_mode *adjusted_mode = 2228 &crtc_state->hw.adjusted_mode; 2229 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2230 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2231 int max_link_bpp_x16; 2232 2233 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, 2234 to_bpp_x16(limits->pipe.max_bpp)); 2235 2236 if (!dsc) { 2237 max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3)); 2238 2239 if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp)) 2240 return false; 2241 2242 limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp); 2243 } else { 2244 /* 2245 * TODO: set the DSC link limits already here, atm these are 2246 * initialized only later in intel_edp_dsc_compute_pipe_bpp() / 2247 * intel_dp_dsc_compute_pipe_bpp() 2248 */ 2249 limits->link.min_bpp_x16 = 0; 2250 } 2251 2252 limits->link.max_bpp_x16 = max_link_bpp_x16; 2253 2254 drm_dbg_kms(&i915->drm, 2255 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n", 2256 encoder->base.base.id, encoder->base.name, 2257 crtc->base.base.id, crtc->base.name, 2258 adjusted_mode->crtc_clock, 2259 dsc ? "on" : "off", 2260 limits->max_lane_count, 2261 limits->max_rate, 2262 limits->pipe.max_bpp, 2263 BPP_X16_ARGS(limits->link.max_bpp_x16)); 2264 2265 return true; 2266 } 2267 2268 static bool 2269 intel_dp_compute_config_limits(struct intel_dp *intel_dp, 2270 struct intel_crtc_state *crtc_state, 2271 bool respect_downstream_limits, 2272 bool dsc, 2273 struct link_config_limits *limits) 2274 { 2275 limits->min_rate = intel_dp_common_rate(intel_dp, 0); 2276 limits->max_rate = intel_dp_max_link_rate(intel_dp); 2277 2278 limits->min_lane_count = 1; 2279 limits->max_lane_count = intel_dp_max_lane_count(intel_dp); 2280 2281 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); 2282 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, 2283 respect_downstream_limits); 2284 2285 if (intel_dp->use_max_params) { 2286 /* 2287 * Use the maximum clock and number of lanes the eDP panel 2288 * advertizes being capable of in case the initial fast 2289 * optimal params failed us. The panels are generally 2290 * designed to support only a single clock and lane 2291 * configuration, and typically on older panels these 2292 * values correspond to the native resolution of the panel. 2293 */ 2294 limits->min_lane_count = limits->max_lane_count; 2295 limits->min_rate = limits->max_rate; 2296 } 2297 2298 intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits); 2299 2300 return intel_dp_compute_config_link_bpp_limits(intel_dp, 2301 crtc_state, 2302 dsc, 2303 limits); 2304 } 2305 2306 static int 2307 intel_dp_compute_link_config(struct intel_encoder *encoder, 2308 struct intel_crtc_state *pipe_config, 2309 struct drm_connector_state *conn_state, 2310 bool respect_downstream_limits) 2311 { 2312 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2313 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2314 const struct drm_display_mode *adjusted_mode = 2315 &pipe_config->hw.adjusted_mode; 2316 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2317 struct link_config_limits limits; 2318 bool joiner_needs_dsc = false; 2319 bool dsc_needed; 2320 int ret = 0; 2321 2322 if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay, 2323 adjusted_mode->crtc_clock)) 2324 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe); 2325 2326 /* 2327 * Pipe joiner needs compression up to display 12 due to bandwidth 2328 * limitation. DG2 onwards pipe joiner can be enabled without 2329 * compression. 2330 */ 2331 joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes; 2332 2333 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || 2334 !intel_dp_compute_config_limits(intel_dp, pipe_config, 2335 respect_downstream_limits, 2336 false, 2337 &limits); 2338 2339 if (!dsc_needed) { 2340 /* 2341 * Optimize for slow and wide for everything, because there are some 2342 * eDP 1.3 and 1.4 panels don't work well with fast and narrow. 2343 */ 2344 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, 2345 conn_state, &limits); 2346 if (ret) 2347 dsc_needed = true; 2348 } 2349 2350 if (dsc_needed) { 2351 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n", 2352 str_yes_no(ret), str_yes_no(joiner_needs_dsc), 2353 str_yes_no(intel_dp->force_dsc_en)); 2354 2355 if (!intel_dp_compute_config_limits(intel_dp, pipe_config, 2356 respect_downstream_limits, 2357 true, 2358 &limits)) 2359 return -EINVAL; 2360 2361 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, 2362 conn_state, &limits, 64, true); 2363 if (ret < 0) 2364 return ret; 2365 } 2366 2367 if (pipe_config->dsc.compression_enable) { 2368 drm_dbg_kms(&i915->drm, 2369 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", 2370 pipe_config->lane_count, pipe_config->port_clock, 2371 pipe_config->pipe_bpp, 2372 pipe_config->dsc.compressed_bpp); 2373 2374 drm_dbg_kms(&i915->drm, 2375 "DP link rate required %i available %i\n", 2376 intel_dp_link_required(adjusted_mode->crtc_clock, 2377 pipe_config->dsc.compressed_bpp), 2378 intel_dp_max_data_rate(pipe_config->port_clock, 2379 pipe_config->lane_count)); 2380 } else { 2381 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n", 2382 pipe_config->lane_count, pipe_config->port_clock, 2383 pipe_config->pipe_bpp); 2384 2385 drm_dbg_kms(&i915->drm, 2386 "DP link rate required %i available %i\n", 2387 intel_dp_link_required(adjusted_mode->crtc_clock, 2388 pipe_config->pipe_bpp), 2389 intel_dp_max_data_rate(pipe_config->port_clock, 2390 pipe_config->lane_count)); 2391 } 2392 return 0; 2393 } 2394 2395 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 2396 const struct drm_connector_state *conn_state) 2397 { 2398 const struct intel_digital_connector_state *intel_conn_state = 2399 to_intel_digital_connector_state(conn_state); 2400 const struct drm_display_mode *adjusted_mode = 2401 &crtc_state->hw.adjusted_mode; 2402 2403 /* 2404 * Our YCbCr output is always limited range. 2405 * crtc_state->limited_color_range only applies to RGB, 2406 * and it must never be set for YCbCr or we risk setting 2407 * some conflicting bits in TRANSCONF which will mess up 2408 * the colors on the monitor. 2409 */ 2410 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2411 return false; 2412 2413 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2414 /* 2415 * See: 2416 * CEA-861-E - 5.1 Default Encoding Parameters 2417 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 2418 */ 2419 return crtc_state->pipe_bpp != 18 && 2420 drm_default_rgb_quant_range(adjusted_mode) == 2421 HDMI_QUANTIZATION_RANGE_LIMITED; 2422 } else { 2423 return intel_conn_state->broadcast_rgb == 2424 INTEL_BROADCAST_RGB_LIMITED; 2425 } 2426 } 2427 2428 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv, 2429 enum port port) 2430 { 2431 if (IS_G4X(dev_priv)) 2432 return false; 2433 if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A) 2434 return false; 2435 2436 return true; 2437 } 2438 2439 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, 2440 const struct drm_connector_state *conn_state, 2441 struct drm_dp_vsc_sdp *vsc) 2442 { 2443 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2444 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2445 2446 /* 2447 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2448 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ 2449 * Colorimetry Format indication. 2450 */ 2451 vsc->revision = 0x5; 2452 vsc->length = 0x13; 2453 2454 /* DP 1.4a spec, Table 2-120 */ 2455 switch (crtc_state->output_format) { 2456 case INTEL_OUTPUT_FORMAT_YCBCR444: 2457 vsc->pixelformat = DP_PIXELFORMAT_YUV444; 2458 break; 2459 case INTEL_OUTPUT_FORMAT_YCBCR420: 2460 vsc->pixelformat = DP_PIXELFORMAT_YUV420; 2461 break; 2462 case INTEL_OUTPUT_FORMAT_RGB: 2463 default: 2464 vsc->pixelformat = DP_PIXELFORMAT_RGB; 2465 } 2466 2467 switch (conn_state->colorspace) { 2468 case DRM_MODE_COLORIMETRY_BT709_YCC: 2469 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2470 break; 2471 case DRM_MODE_COLORIMETRY_XVYCC_601: 2472 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; 2473 break; 2474 case DRM_MODE_COLORIMETRY_XVYCC_709: 2475 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; 2476 break; 2477 case DRM_MODE_COLORIMETRY_SYCC_601: 2478 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; 2479 break; 2480 case DRM_MODE_COLORIMETRY_OPYCC_601: 2481 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; 2482 break; 2483 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 2484 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; 2485 break; 2486 case DRM_MODE_COLORIMETRY_BT2020_RGB: 2487 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; 2488 break; 2489 case DRM_MODE_COLORIMETRY_BT2020_YCC: 2490 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; 2491 break; 2492 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 2493 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 2494 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; 2495 break; 2496 default: 2497 /* 2498 * RGB->YCBCR color conversion uses the BT.709 2499 * color space. 2500 */ 2501 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2502 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2503 else 2504 vsc->colorimetry = DP_COLORIMETRY_DEFAULT; 2505 break; 2506 } 2507 2508 vsc->bpc = crtc_state->pipe_bpp / 3; 2509 2510 /* only RGB pixelformat supports 6 bpc */ 2511 drm_WARN_ON(&dev_priv->drm, 2512 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); 2513 2514 /* all YCbCr are always limited range */ 2515 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; 2516 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; 2517 } 2518 2519 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, 2520 struct intel_crtc_state *crtc_state, 2521 const struct drm_connector_state *conn_state) 2522 { 2523 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc; 2524 2525 /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */ 2526 if (crtc_state->has_psr) 2527 return; 2528 2529 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 2530 return; 2531 2532 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 2533 vsc->sdp_type = DP_SDP_VSC; 2534 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 2535 &crtc_state->infoframes.vsc); 2536 } 2537 2538 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, 2539 const struct intel_crtc_state *crtc_state, 2540 const struct drm_connector_state *conn_state, 2541 struct drm_dp_vsc_sdp *vsc) 2542 { 2543 vsc->sdp_type = DP_SDP_VSC; 2544 2545 if (crtc_state->has_psr2) { 2546 if (intel_dp->psr.colorimetry_support && 2547 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { 2548 /* [PSR2, +Colorimetry] */ 2549 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 2550 vsc); 2551 } else { 2552 /* 2553 * [PSR2, -Colorimetry] 2554 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 2555 * 3D stereo + PSR/PSR2 + Y-coordinate. 2556 */ 2557 vsc->revision = 0x4; 2558 vsc->length = 0xe; 2559 } 2560 } else { 2561 /* 2562 * [PSR1] 2563 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2564 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or 2565 * higher). 2566 */ 2567 vsc->revision = 0x2; 2568 vsc->length = 0x8; 2569 } 2570 } 2571 2572 static void 2573 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, 2574 struct intel_crtc_state *crtc_state, 2575 const struct drm_connector_state *conn_state) 2576 { 2577 int ret; 2578 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2579 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; 2580 2581 if (!conn_state->hdr_output_metadata) 2582 return; 2583 2584 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); 2585 2586 if (ret) { 2587 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n"); 2588 return; 2589 } 2590 2591 crtc_state->infoframes.enable |= 2592 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 2593 } 2594 2595 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915, 2596 enum transcoder cpu_transcoder) 2597 { 2598 if (HAS_DOUBLE_BUFFERED_M_N(i915)) 2599 return true; 2600 2601 return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder); 2602 } 2603 2604 static bool can_enable_drrs(struct intel_connector *connector, 2605 const struct intel_crtc_state *pipe_config, 2606 const struct drm_display_mode *downclock_mode) 2607 { 2608 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2609 2610 if (pipe_config->vrr.enable) 2611 return false; 2612 2613 /* 2614 * DRRS and PSR can't be enable together, so giving preference to PSR 2615 * as it allows more power-savings by complete shutting down display, 2616 * so to guarantee this, intel_drrs_compute_config() must be called 2617 * after intel_psr_compute_config(). 2618 */ 2619 if (pipe_config->has_psr) 2620 return false; 2621 2622 /* FIXME missing FDI M2/N2 etc. */ 2623 if (pipe_config->has_pch_encoder) 2624 return false; 2625 2626 if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder)) 2627 return false; 2628 2629 return downclock_mode && 2630 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 2631 } 2632 2633 static void 2634 intel_dp_drrs_compute_config(struct intel_connector *connector, 2635 struct intel_crtc_state *pipe_config, 2636 int link_bpp) 2637 { 2638 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2639 const struct drm_display_mode *downclock_mode = 2640 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 2641 int pixel_clock; 2642 2643 if (has_seamless_m_n(connector)) 2644 pipe_config->update_m_n = true; 2645 2646 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { 2647 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) 2648 intel_zero_m_n(&pipe_config->dp_m2_n2); 2649 return; 2650 } 2651 2652 if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) 2653 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; 2654 2655 pipe_config->has_drrs = true; 2656 2657 pixel_clock = downclock_mode->clock; 2658 if (pipe_config->splitter.enable) 2659 pixel_clock /= pipe_config->splitter.link_count; 2660 2661 intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock, 2662 pipe_config->port_clock, &pipe_config->dp_m2_n2, 2663 pipe_config->fec_enable); 2664 2665 /* FIXME: abstract this better */ 2666 if (pipe_config->splitter.enable) 2667 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 2668 } 2669 2670 static bool intel_dp_has_audio(struct intel_encoder *encoder, 2671 struct intel_crtc_state *crtc_state, 2672 const struct drm_connector_state *conn_state) 2673 { 2674 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2675 const struct intel_digital_connector_state *intel_conn_state = 2676 to_intel_digital_connector_state(conn_state); 2677 struct intel_connector *connector = 2678 to_intel_connector(conn_state->connector); 2679 2680 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 2681 !intel_dp_port_has_audio(i915, encoder->port)) 2682 return false; 2683 2684 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2685 return connector->base.display_info.has_audio; 2686 else 2687 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2688 } 2689 2690 static int 2691 intel_dp_compute_output_format(struct intel_encoder *encoder, 2692 struct intel_crtc_state *crtc_state, 2693 struct drm_connector_state *conn_state, 2694 bool respect_downstream_limits) 2695 { 2696 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2697 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2698 struct intel_connector *connector = intel_dp->attached_connector; 2699 const struct drm_display_info *info = &connector->base.display_info; 2700 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2701 bool ycbcr_420_only; 2702 int ret; 2703 2704 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2705 2706 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) { 2707 drm_dbg_kms(&i915->drm, 2708 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2709 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 2710 } else { 2711 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode); 2712 } 2713 2714 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); 2715 2716 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 2717 respect_downstream_limits); 2718 if (ret) { 2719 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2720 !connector->base.ycbcr_420_allowed || 2721 !drm_mode_is_420_also(info, adjusted_mode)) 2722 return ret; 2723 2724 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2725 crtc_state->output_format = intel_dp_output_format(connector, 2726 crtc_state->sink_format); 2727 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 2728 respect_downstream_limits); 2729 } 2730 2731 return ret; 2732 } 2733 2734 void 2735 intel_dp_audio_compute_config(struct intel_encoder *encoder, 2736 struct intel_crtc_state *pipe_config, 2737 struct drm_connector_state *conn_state) 2738 { 2739 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2740 struct drm_connector *connector = conn_state->connector; 2741 2742 pipe_config->has_audio = 2743 intel_dp_has_audio(encoder, pipe_config, conn_state) && 2744 intel_audio_compute_config(encoder, pipe_config, conn_state); 2745 2746 pipe_config->sdp_split_enable = pipe_config->has_audio && 2747 intel_dp_is_uhbr(pipe_config); 2748 2749 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n", 2750 connector->base.id, connector->name, 2751 str_yes_no(pipe_config->sdp_split_enable)); 2752 } 2753 2754 int 2755 intel_dp_compute_config(struct intel_encoder *encoder, 2756 struct intel_crtc_state *pipe_config, 2757 struct drm_connector_state *conn_state) 2758 { 2759 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2760 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2761 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2762 const struct drm_display_mode *fixed_mode; 2763 struct intel_connector *connector = intel_dp->attached_connector; 2764 int ret = 0, link_bpp; 2765 2766 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A) 2767 pipe_config->has_pch_encoder = true; 2768 2769 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode); 2770 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 2771 ret = intel_panel_compute_config(connector, adjusted_mode); 2772 if (ret) 2773 return ret; 2774 } 2775 2776 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2777 return -EINVAL; 2778 2779 if (!connector->base.interlace_allowed && 2780 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2781 return -EINVAL; 2782 2783 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2784 return -EINVAL; 2785 2786 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay)) 2787 return -EINVAL; 2788 2789 /* 2790 * Try to respect downstream TMDS clock limits first, if 2791 * that fails assume the user might know something we don't. 2792 */ 2793 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true); 2794 if (ret) 2795 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false); 2796 if (ret) 2797 return ret; 2798 2799 if ((intel_dp_is_edp(intel_dp) && fixed_mode) || 2800 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 2801 ret = intel_panel_fitting(pipe_config, conn_state); 2802 if (ret) 2803 return ret; 2804 } 2805 2806 pipe_config->limited_color_range = 2807 intel_dp_limited_color_range(pipe_config, conn_state); 2808 2809 pipe_config->enhanced_framing = 2810 drm_dp_enhanced_frame_cap(intel_dp->dpcd); 2811 2812 if (pipe_config->dsc.compression_enable) 2813 link_bpp = pipe_config->dsc.compressed_bpp; 2814 else 2815 link_bpp = intel_dp_output_bpp(pipe_config->output_format, 2816 pipe_config->pipe_bpp); 2817 2818 if (intel_dp->mso_link_count) { 2819 int n = intel_dp->mso_link_count; 2820 int overlap = intel_dp->mso_pixel_overlap; 2821 2822 pipe_config->splitter.enable = true; 2823 pipe_config->splitter.link_count = n; 2824 pipe_config->splitter.pixel_overlap = overlap; 2825 2826 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n", 2827 n, overlap); 2828 2829 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap; 2830 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap; 2831 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap; 2832 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap; 2833 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap; 2834 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap; 2835 adjusted_mode->crtc_clock /= n; 2836 } 2837 2838 intel_dp_audio_compute_config(encoder, pipe_config, conn_state); 2839 2840 intel_link_compute_m_n(link_bpp, 2841 pipe_config->lane_count, 2842 adjusted_mode->crtc_clock, 2843 pipe_config->port_clock, 2844 &pipe_config->dp_m_n, 2845 pipe_config->fec_enable); 2846 2847 /* FIXME: abstract this better */ 2848 if (pipe_config->splitter.enable) 2849 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; 2850 2851 if (!HAS_DDI(dev_priv)) 2852 g4x_dp_set_clock(encoder, pipe_config); 2853 2854 intel_vrr_compute_config(pipe_config, conn_state); 2855 intel_psr_compute_config(intel_dp, pipe_config, conn_state); 2856 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp); 2857 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); 2858 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); 2859 2860 return 0; 2861 } 2862 2863 void intel_dp_set_link_params(struct intel_dp *intel_dp, 2864 int link_rate, int lane_count) 2865 { 2866 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 2867 intel_dp->link_trained = false; 2868 intel_dp->link_rate = link_rate; 2869 intel_dp->lane_count = lane_count; 2870 } 2871 2872 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp) 2873 { 2874 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); 2875 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); 2876 } 2877 2878 /* Enable backlight PWM and backlight PP control. */ 2879 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 2880 const struct drm_connector_state *conn_state) 2881 { 2882 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); 2883 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2884 2885 if (!intel_dp_is_edp(intel_dp)) 2886 return; 2887 2888 drm_dbg_kms(&i915->drm, "\n"); 2889 2890 intel_backlight_enable(crtc_state, conn_state); 2891 intel_pps_backlight_on(intel_dp); 2892 } 2893 2894 /* Disable backlight PP control and backlight PWM. */ 2895 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) 2896 { 2897 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); 2898 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2899 2900 if (!intel_dp_is_edp(intel_dp)) 2901 return; 2902 2903 drm_dbg_kms(&i915->drm, "\n"); 2904 2905 intel_pps_backlight_off(intel_dp); 2906 intel_backlight_disable(old_conn_state); 2907 } 2908 2909 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) 2910 { 2911 /* 2912 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus 2913 * be capable of signalling downstream hpd with a long pulse. 2914 * Whether or not that means D3 is safe to use is not clear, 2915 * but let's assume so until proven otherwise. 2916 * 2917 * FIXME should really check all downstream ports... 2918 */ 2919 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && 2920 drm_dp_is_branch(intel_dp->dpcd) && 2921 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; 2922 } 2923 2924 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, 2925 const struct intel_crtc_state *crtc_state, 2926 bool enable) 2927 { 2928 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2929 int ret; 2930 2931 if (!crtc_state->dsc.compression_enable) 2932 return; 2933 2934 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, 2935 enable ? DP_DECOMPRESSION_EN : 0); 2936 if (ret < 0) 2937 drm_dbg_kms(&i915->drm, 2938 "Failed to %s sink decompression state\n", 2939 str_enable_disable(enable)); 2940 } 2941 2942 static void 2943 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful) 2944 { 2945 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2946 u8 oui[] = { 0x00, 0xaa, 0x01 }; 2947 u8 buf[3] = {}; 2948 2949 /* 2950 * During driver init, we want to be careful and avoid changing the source OUI if it's 2951 * already set to what we want, so as to avoid clearing any state by accident 2952 */ 2953 if (careful) { 2954 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) 2955 drm_err(&i915->drm, "Failed to read source OUI\n"); 2956 2957 if (memcmp(oui, buf, sizeof(oui)) == 0) 2958 return; 2959 } 2960 2961 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) 2962 drm_err(&i915->drm, "Failed to write source OUI\n"); 2963 2964 intel_dp->last_oui_write = jiffies; 2965 } 2966 2967 void intel_dp_wait_source_oui(struct intel_dp *intel_dp) 2968 { 2969 struct intel_connector *connector = intel_dp->attached_connector; 2970 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2971 2972 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n", 2973 connector->base.base.id, connector->base.name, 2974 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 2975 2976 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 2977 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 2978 } 2979 2980 /* If the device supports it, try to set the power state appropriately */ 2981 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) 2982 { 2983 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2984 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2985 int ret, i; 2986 2987 /* Should have a valid DPCD by this point */ 2988 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 2989 return; 2990 2991 if (mode != DP_SET_POWER_D0) { 2992 if (downstream_hpd_needs_d0(intel_dp)) 2993 return; 2994 2995 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 2996 } else { 2997 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); 2998 2999 lspcon_resume(dp_to_dig_port(intel_dp)); 3000 3001 /* Write the source OUI as early as possible */ 3002 if (intel_dp_is_edp(intel_dp)) 3003 intel_edp_init_source_oui(intel_dp, false); 3004 3005 /* 3006 * When turning on, we need to retry for 1ms to give the sink 3007 * time to wake up. 3008 */ 3009 for (i = 0; i < 3; i++) { 3010 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3011 if (ret == 1) 3012 break; 3013 msleep(1); 3014 } 3015 3016 if (ret == 1 && lspcon->active) 3017 lspcon_wait_pcon_mode(lspcon); 3018 } 3019 3020 if (ret != 1) 3021 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n", 3022 encoder->base.base.id, encoder->base.name, 3023 mode == DP_SET_POWER_D0 ? "D0" : "D3"); 3024 } 3025 3026 static bool 3027 intel_dp_get_dpcd(struct intel_dp *intel_dp); 3028 3029 /** 3030 * intel_dp_sync_state - sync the encoder state during init/resume 3031 * @encoder: intel encoder to sync 3032 * @crtc_state: state for the CRTC connected to the encoder 3033 * 3034 * Sync any state stored in the encoder wrt. HW state during driver init 3035 * and system resume. 3036 */ 3037 void intel_dp_sync_state(struct intel_encoder *encoder, 3038 const struct intel_crtc_state *crtc_state) 3039 { 3040 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3041 3042 if (!crtc_state) 3043 return; 3044 3045 /* 3046 * Don't clobber DPCD if it's been already read out during output 3047 * setup (eDP) or detect. 3048 */ 3049 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 3050 intel_dp_get_dpcd(intel_dp); 3051 3052 intel_dp_reset_max_link_params(intel_dp); 3053 } 3054 3055 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 3056 struct intel_crtc_state *crtc_state) 3057 { 3058 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3059 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3060 bool fastset = true; 3061 3062 /* 3063 * If BIOS has set an unsupported or non-standard link rate for some 3064 * reason force an encoder recompute and full modeset. 3065 */ 3066 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, 3067 crtc_state->port_clock) < 0) { 3068 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n", 3069 encoder->base.base.id, encoder->base.name); 3070 crtc_state->uapi.connectors_changed = true; 3071 fastset = false; 3072 } 3073 3074 /* 3075 * FIXME hack to force full modeset when DSC is being used. 3076 * 3077 * As long as we do not have full state readout and config comparison 3078 * of crtc_state->dsc, we have no way to ensure reliable fastset. 3079 * Remove once we have readout for DSC. 3080 */ 3081 if (crtc_state->dsc.compression_enable) { 3082 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n", 3083 encoder->base.base.id, encoder->base.name); 3084 crtc_state->uapi.mode_changed = true; 3085 fastset = false; 3086 } 3087 3088 if (CAN_PSR(intel_dp)) { 3089 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n", 3090 encoder->base.base.id, encoder->base.name); 3091 crtc_state->uapi.mode_changed = true; 3092 fastset = false; 3093 } 3094 3095 return fastset; 3096 } 3097 3098 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) 3099 { 3100 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3101 3102 /* Clear the cached register set to avoid using stale values */ 3103 3104 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); 3105 3106 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, 3107 intel_dp->pcon_dsc_dpcd, 3108 sizeof(intel_dp->pcon_dsc_dpcd)) < 0) 3109 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n", 3110 DP_PCON_DSC_ENCODER); 3111 3112 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n", 3113 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); 3114 } 3115 3116 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) 3117 { 3118 int bw_gbps[] = {9, 18, 24, 32, 40, 48}; 3119 int i; 3120 3121 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { 3122 if (frl_bw_mask & (1 << i)) 3123 return bw_gbps[i]; 3124 } 3125 return 0; 3126 } 3127 3128 static int intel_dp_pcon_set_frl_mask(int max_frl) 3129 { 3130 switch (max_frl) { 3131 case 48: 3132 return DP_PCON_FRL_BW_MASK_48GBPS; 3133 case 40: 3134 return DP_PCON_FRL_BW_MASK_40GBPS; 3135 case 32: 3136 return DP_PCON_FRL_BW_MASK_32GBPS; 3137 case 24: 3138 return DP_PCON_FRL_BW_MASK_24GBPS; 3139 case 18: 3140 return DP_PCON_FRL_BW_MASK_18GBPS; 3141 case 9: 3142 return DP_PCON_FRL_BW_MASK_9GBPS; 3143 } 3144 3145 return 0; 3146 } 3147 3148 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) 3149 { 3150 struct intel_connector *intel_connector = intel_dp->attached_connector; 3151 struct drm_connector *connector = &intel_connector->base; 3152 int max_frl_rate; 3153 int max_lanes, rate_per_lane; 3154 int max_dsc_lanes, dsc_rate_per_lane; 3155 3156 max_lanes = connector->display_info.hdmi.max_lanes; 3157 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane; 3158 max_frl_rate = max_lanes * rate_per_lane; 3159 3160 if (connector->display_info.hdmi.dsc_cap.v_1p2) { 3161 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes; 3162 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane; 3163 if (max_dsc_lanes && dsc_rate_per_lane) 3164 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane); 3165 } 3166 3167 return max_frl_rate; 3168 } 3169 3170 static bool 3171 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp, 3172 u8 max_frl_bw_mask, u8 *frl_trained_mask) 3173 { 3174 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) && 3175 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL && 3176 *frl_trained_mask >= max_frl_bw_mask) 3177 return true; 3178 3179 return false; 3180 } 3181 3182 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) 3183 { 3184 #define TIMEOUT_FRL_READY_MS 500 3185 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 3186 3187 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3188 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret; 3189 u8 max_frl_bw_mask = 0, frl_trained_mask; 3190 bool is_active; 3191 3192 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 3193 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw); 3194 3195 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp); 3196 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw); 3197 3198 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw); 3199 3200 if (max_frl_bw <= 0) 3201 return -EINVAL; 3202 3203 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); 3204 drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask); 3205 3206 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask)) 3207 goto frl_trained; 3208 3209 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false); 3210 if (ret < 0) 3211 return ret; 3212 /* Wait for PCON to be FRL Ready */ 3213 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS); 3214 3215 if (!is_active) 3216 return -ETIMEDOUT; 3217 3218 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, 3219 DP_PCON_ENABLE_SEQUENTIAL_LINK); 3220 if (ret < 0) 3221 return ret; 3222 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, 3223 DP_PCON_FRL_LINK_TRAIN_NORMAL); 3224 if (ret < 0) 3225 return ret; 3226 ret = drm_dp_pcon_frl_enable(&intel_dp->aux); 3227 if (ret < 0) 3228 return ret; 3229 /* 3230 * Wait for FRL to be completed 3231 * Check if the HDMI Link is up and active. 3232 */ 3233 wait_for(is_active = 3234 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask), 3235 TIMEOUT_HDMI_LINK_ACTIVE_MS); 3236 3237 if (!is_active) 3238 return -ETIMEDOUT; 3239 3240 frl_trained: 3241 drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask); 3242 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask); 3243 intel_dp->frl.is_trained = true; 3244 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps); 3245 3246 return 0; 3247 } 3248 3249 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) 3250 { 3251 if (drm_dp_is_branch(intel_dp->dpcd) && 3252 intel_dp_has_hdmi_sink(intel_dp) && 3253 intel_dp_hdmi_sink_max_frl(intel_dp) > 0) 3254 return true; 3255 3256 return false; 3257 } 3258 3259 static 3260 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp) 3261 { 3262 int ret; 3263 u8 buf = 0; 3264 3265 /* Set PCON source control mode */ 3266 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE; 3267 3268 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3269 if (ret < 0) 3270 return ret; 3271 3272 /* Set HDMI LINK ENABLE */ 3273 buf |= DP_PCON_ENABLE_HDMI_LINK; 3274 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3275 if (ret < 0) 3276 return ret; 3277 3278 return 0; 3279 } 3280 3281 void intel_dp_check_frl_training(struct intel_dp *intel_dp) 3282 { 3283 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3284 3285 /* 3286 * Always go for FRL training if: 3287 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) 3288 * -sink is HDMI2.1 3289 */ 3290 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) || 3291 !intel_dp_is_hdmi_2_1_sink(intel_dp) || 3292 intel_dp->frl.is_trained) 3293 return; 3294 3295 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) { 3296 int ret, mode; 3297 3298 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n"); 3299 ret = intel_dp_pcon_set_tmds_mode(intel_dp); 3300 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL); 3301 3302 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS) 3303 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n"); 3304 } else { 3305 drm_dbg(&dev_priv->drm, "FRL training Completed\n"); 3306 } 3307 } 3308 3309 static int 3310 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state) 3311 { 3312 int vactive = crtc_state->hw.adjusted_mode.vdisplay; 3313 3314 return intel_hdmi_dsc_get_slice_height(vactive); 3315 } 3316 3317 static int 3318 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, 3319 const struct intel_crtc_state *crtc_state) 3320 { 3321 struct intel_connector *intel_connector = intel_dp->attached_connector; 3322 struct drm_connector *connector = &intel_connector->base; 3323 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice; 3324 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices; 3325 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd); 3326 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); 3327 3328 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices, 3329 pcon_max_slice_width, 3330 hdmi_max_slices, hdmi_throughput); 3331 } 3332 3333 static int 3334 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, 3335 const struct intel_crtc_state *crtc_state, 3336 int num_slices, int slice_width) 3337 { 3338 struct intel_connector *intel_connector = intel_dp->attached_connector; 3339 struct drm_connector *connector = &intel_connector->base; 3340 int output_format = crtc_state->output_format; 3341 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp; 3342 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd); 3343 int hdmi_max_chunk_bytes = 3344 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024; 3345 3346 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, 3347 num_slices, output_format, hdmi_all_bpp, 3348 hdmi_max_chunk_bytes); 3349 } 3350 3351 void 3352 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 3353 const struct intel_crtc_state *crtc_state) 3354 { 3355 u8 pps_param[6]; 3356 int slice_height; 3357 int slice_width; 3358 int num_slices; 3359 int bits_per_pixel; 3360 int ret; 3361 struct intel_connector *intel_connector = intel_dp->attached_connector; 3362 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3363 struct drm_connector *connector; 3364 bool hdmi_is_dsc_1_2; 3365 3366 if (!intel_dp_is_hdmi_2_1_sink(intel_dp)) 3367 return; 3368 3369 if (!intel_connector) 3370 return; 3371 connector = &intel_connector->base; 3372 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2; 3373 3374 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || 3375 !hdmi_is_dsc_1_2) 3376 return; 3377 3378 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); 3379 if (!slice_height) 3380 return; 3381 3382 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state); 3383 if (!num_slices) 3384 return; 3385 3386 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, 3387 num_slices); 3388 3389 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state, 3390 num_slices, slice_width); 3391 if (!bits_per_pixel) 3392 return; 3393 3394 pps_param[0] = slice_height & 0xFF; 3395 pps_param[1] = slice_height >> 8; 3396 pps_param[2] = slice_width & 0xFF; 3397 pps_param[3] = slice_width >> 8; 3398 pps_param[4] = bits_per_pixel & 0xFF; 3399 pps_param[5] = (bits_per_pixel >> 8) & 0x3; 3400 3401 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); 3402 if (ret < 0) 3403 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n"); 3404 } 3405 3406 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 3407 const struct intel_crtc_state *crtc_state) 3408 { 3409 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3410 bool ycbcr444_to_420 = false; 3411 bool rgb_to_ycbcr = false; 3412 u8 tmp; 3413 3414 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) 3415 return; 3416 3417 if (!drm_dp_is_branch(intel_dp->dpcd)) 3418 return; 3419 3420 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0; 3421 3422 if (drm_dp_dpcd_writeb(&intel_dp->aux, 3423 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) 3424 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n", 3425 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp))); 3426 3427 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3428 switch (crtc_state->output_format) { 3429 case INTEL_OUTPUT_FORMAT_YCBCR420: 3430 break; 3431 case INTEL_OUTPUT_FORMAT_YCBCR444: 3432 ycbcr444_to_420 = true; 3433 break; 3434 case INTEL_OUTPUT_FORMAT_RGB: 3435 rgb_to_ycbcr = true; 3436 ycbcr444_to_420 = true; 3437 break; 3438 default: 3439 MISSING_CASE(crtc_state->output_format); 3440 break; 3441 } 3442 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) { 3443 switch (crtc_state->output_format) { 3444 case INTEL_OUTPUT_FORMAT_YCBCR444: 3445 break; 3446 case INTEL_OUTPUT_FORMAT_RGB: 3447 rgb_to_ycbcr = true; 3448 break; 3449 default: 3450 MISSING_CASE(crtc_state->output_format); 3451 break; 3452 } 3453 } 3454 3455 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; 3456 3457 if (drm_dp_dpcd_writeb(&intel_dp->aux, 3458 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) 3459 drm_dbg_kms(&i915->drm, 3460 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", 3461 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); 3462 3463 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; 3464 3465 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) 3466 drm_dbg_kms(&i915->drm, 3467 "Failed to %s protocol converter RGB->YCbCr conversion mode\n", 3468 str_enable_disable(tmp)); 3469 } 3470 3471 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) 3472 { 3473 u8 dprx = 0; 3474 3475 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 3476 &dprx) != 1) 3477 return false; 3478 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; 3479 } 3480 3481 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, 3482 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 3483 { 3484 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd, 3485 DP_DSC_RECEIVER_CAP_SIZE) < 0) { 3486 drm_err(aux->drm_dev, 3487 "Failed to read DPCD register 0x%x\n", 3488 DP_DSC_SUPPORT); 3489 return; 3490 } 3491 3492 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", 3493 DP_DSC_RECEIVER_CAP_SIZE, 3494 dsc_dpcd); 3495 } 3496 3497 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector) 3498 { 3499 struct drm_i915_private *i915 = to_i915(connector->base.dev); 3500 3501 /* 3502 * Clear the cached register set to avoid using stale values 3503 * for the sinks that do not support DSC. 3504 */ 3505 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 3506 3507 /* Clear fec_capable to avoid using stale values */ 3508 connector->dp.fec_capability = 0; 3509 3510 if (dpcd_rev < DP_DPCD_REV_14) 3511 return; 3512 3513 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, 3514 connector->dp.dsc_dpcd); 3515 3516 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, 3517 &connector->dp.fec_capability) < 0) { 3518 drm_err(&i915->drm, "Failed to read FEC DPCD register\n"); 3519 return; 3520 } 3521 3522 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", 3523 connector->dp.fec_capability); 3524 } 3525 3526 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) 3527 { 3528 if (edp_dpcd_rev < DP_EDP_14) 3529 return; 3530 3531 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); 3532 } 3533 3534 static void intel_edp_mso_mode_fixup(struct intel_connector *connector, 3535 struct drm_display_mode *mode) 3536 { 3537 struct intel_dp *intel_dp = intel_attached_dp(connector); 3538 struct drm_i915_private *i915 = to_i915(connector->base.dev); 3539 int n = intel_dp->mso_link_count; 3540 int overlap = intel_dp->mso_pixel_overlap; 3541 3542 if (!mode || !n) 3543 return; 3544 3545 mode->hdisplay = (mode->hdisplay - overlap) * n; 3546 mode->hsync_start = (mode->hsync_start - overlap) * n; 3547 mode->hsync_end = (mode->hsync_end - overlap) * n; 3548 mode->htotal = (mode->htotal - overlap) * n; 3549 mode->clock *= n; 3550 3551 drm_mode_set_name(mode); 3552 3553 drm_dbg_kms(&i915->drm, 3554 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n", 3555 connector->base.base.id, connector->base.name, 3556 DRM_MODE_ARG(mode)); 3557 } 3558 3559 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp) 3560 { 3561 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3562 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3563 struct intel_connector *connector = intel_dp->attached_connector; 3564 3565 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { 3566 /* 3567 * This is a big fat ugly hack. 3568 * 3569 * Some machines in UEFI boot mode provide us a VBT that has 18 3570 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3571 * unknown we fail to light up. Yet the same BIOS boots up with 3572 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3573 * max, not what it tells us to use. 3574 * 3575 * Note: This will still be broken if the eDP panel is not lit 3576 * up by the BIOS, and thus we can't get the mode at module 3577 * load. 3578 */ 3579 drm_dbg_kms(&dev_priv->drm, 3580 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3581 pipe_bpp, connector->panel.vbt.edp.bpp); 3582 connector->panel.vbt.edp.bpp = pipe_bpp; 3583 } 3584 } 3585 3586 static void intel_edp_mso_init(struct intel_dp *intel_dp) 3587 { 3588 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3589 struct intel_connector *connector = intel_dp->attached_connector; 3590 struct drm_display_info *info = &connector->base.display_info; 3591 u8 mso; 3592 3593 if (intel_dp->edp_dpcd[0] < DP_EDP_14) 3594 return; 3595 3596 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { 3597 drm_err(&i915->drm, "Failed to read MSO cap\n"); 3598 return; 3599 } 3600 3601 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */ 3602 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK; 3603 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { 3604 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso); 3605 mso = 0; 3606 } 3607 3608 if (mso) { 3609 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n", 3610 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, 3611 info->mso_pixel_overlap); 3612 if (!HAS_MSO(i915)) { 3613 drm_err(&i915->drm, "No source MSO support, disabling\n"); 3614 mso = 0; 3615 } 3616 } 3617 3618 intel_dp->mso_link_count = mso; 3619 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; 3620 } 3621 3622 static bool 3623 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 3624 { 3625 struct drm_i915_private *dev_priv = 3626 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 3627 3628 /* this function is meant to be called only once */ 3629 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); 3630 3631 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) 3632 return false; 3633 3634 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 3635 drm_dp_is_branch(intel_dp->dpcd)); 3636 3637 /* 3638 * Read the eDP display control registers. 3639 * 3640 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in 3641 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it 3642 * set, but require eDP 1.4+ detection (e.g. for supported link rates 3643 * method). The display control registers should read zero if they're 3644 * not supported anyway. 3645 */ 3646 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 3647 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 3648 sizeof(intel_dp->edp_dpcd)) { 3649 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n", 3650 (int)sizeof(intel_dp->edp_dpcd), 3651 intel_dp->edp_dpcd); 3652 3653 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; 3654 } 3655 3656 /* 3657 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks 3658 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] 3659 */ 3660 intel_psr_init_dpcd(intel_dp); 3661 3662 /* Clear the default sink rates */ 3663 intel_dp->num_sink_rates = 0; 3664 3665 /* Read the eDP 1.4+ supported link rates. */ 3666 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { 3667 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 3668 int i; 3669 3670 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 3671 sink_rates, sizeof(sink_rates)); 3672 3673 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 3674 int val = le16_to_cpu(sink_rates[i]); 3675 3676 if (val == 0) 3677 break; 3678 3679 /* Value read multiplied by 200kHz gives the per-lane 3680 * link rate in kHz. The source rates are, however, 3681 * stored in terms of LS_Clk kHz. The full conversion 3682 * back to symbols is 3683 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) 3684 */ 3685 intel_dp->sink_rates[i] = (val * 200) / 10; 3686 } 3687 intel_dp->num_sink_rates = i; 3688 } 3689 3690 /* 3691 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, 3692 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. 3693 */ 3694 if (intel_dp->num_sink_rates) 3695 intel_dp->use_rate_select = true; 3696 else 3697 intel_dp_set_sink_rates(intel_dp); 3698 intel_dp_set_max_sink_lane_count(intel_dp); 3699 3700 /* Read the eDP DSC DPCD registers */ 3701 if (HAS_DSC(dev_priv)) 3702 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], 3703 connector); 3704 3705 /* 3706 * If needed, program our source OUI so we can make various Intel-specific AUX services 3707 * available (such as HDR backlight controls) 3708 */ 3709 intel_edp_init_source_oui(intel_dp, true); 3710 3711 return true; 3712 } 3713 3714 static bool 3715 intel_dp_has_sink_count(struct intel_dp *intel_dp) 3716 { 3717 if (!intel_dp->attached_connector) 3718 return false; 3719 3720 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, 3721 intel_dp->dpcd, 3722 &intel_dp->desc); 3723 } 3724 3725 static bool 3726 intel_dp_get_dpcd(struct intel_dp *intel_dp) 3727 { 3728 int ret; 3729 3730 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) 3731 return false; 3732 3733 /* 3734 * Don't clobber cached eDP rates. Also skip re-reading 3735 * the OUI/ID since we know it won't change. 3736 */ 3737 if (!intel_dp_is_edp(intel_dp)) { 3738 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 3739 drm_dp_is_branch(intel_dp->dpcd)); 3740 3741 intel_dp_set_sink_rates(intel_dp); 3742 intel_dp_set_max_sink_lane_count(intel_dp); 3743 intel_dp_set_common_rates(intel_dp); 3744 } 3745 3746 if (intel_dp_has_sink_count(intel_dp)) { 3747 ret = drm_dp_read_sink_count(&intel_dp->aux); 3748 if (ret < 0) 3749 return false; 3750 3751 /* 3752 * Sink count can change between short pulse hpd hence 3753 * a member variable in intel_dp will track any changes 3754 * between short pulse interrupts. 3755 */ 3756 intel_dp->sink_count = ret; 3757 3758 /* 3759 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 3760 * a dongle is present but no display. Unless we require to know 3761 * if a dongle is present or not, we don't need to update 3762 * downstream port information. So, an early return here saves 3763 * time from performing other operations which are not required. 3764 */ 3765 if (!intel_dp->sink_count) 3766 return false; 3767 } 3768 3769 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, 3770 intel_dp->downstream_ports) == 0; 3771 } 3772 3773 static bool 3774 intel_dp_can_mst(struct intel_dp *intel_dp) 3775 { 3776 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3777 3778 return i915->params.enable_dp_mst && 3779 intel_dp_mst_source_support(intel_dp) && 3780 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 3781 } 3782 3783 static void 3784 intel_dp_configure_mst(struct intel_dp *intel_dp) 3785 { 3786 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3787 struct intel_encoder *encoder = 3788 &dp_to_dig_port(intel_dp)->base; 3789 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 3790 3791 drm_dbg_kms(&i915->drm, 3792 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n", 3793 encoder->base.base.id, encoder->base.name, 3794 str_yes_no(intel_dp_mst_source_support(intel_dp)), 3795 str_yes_no(sink_can_mst), 3796 str_yes_no(i915->params.enable_dp_mst)); 3797 3798 if (!intel_dp_mst_source_support(intel_dp)) 3799 return; 3800 3801 intel_dp->is_mst = sink_can_mst && 3802 i915->params.enable_dp_mst; 3803 3804 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 3805 intel_dp->is_mst); 3806 } 3807 3808 static bool 3809 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi) 3810 { 3811 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4; 3812 } 3813 3814 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4]) 3815 { 3816 int retry; 3817 3818 for (retry = 0; retry < 3; retry++) { 3819 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1, 3820 &esi[1], 3) == 3) 3821 return true; 3822 } 3823 3824 return false; 3825 } 3826 3827 bool 3828 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 3829 const struct drm_connector_state *conn_state) 3830 { 3831 /* 3832 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 3833 * of Color Encoding Format and Content Color Gamut], in order to 3834 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. 3835 */ 3836 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3837 return true; 3838 3839 switch (conn_state->colorspace) { 3840 case DRM_MODE_COLORIMETRY_SYCC_601: 3841 case DRM_MODE_COLORIMETRY_OPYCC_601: 3842 case DRM_MODE_COLORIMETRY_BT2020_YCC: 3843 case DRM_MODE_COLORIMETRY_BT2020_RGB: 3844 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 3845 return true; 3846 default: 3847 break; 3848 } 3849 3850 return false; 3851 } 3852 3853 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 3854 struct dp_sdp *sdp, size_t size) 3855 { 3856 size_t length = sizeof(struct dp_sdp); 3857 3858 if (size < length) 3859 return -ENOSPC; 3860 3861 memset(sdp, 0, size); 3862 3863 /* 3864 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 3865 * VSC SDP Header Bytes 3866 */ 3867 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ 3868 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ 3869 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ 3870 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ 3871 3872 /* 3873 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as 3874 * per DP 1.4a spec. 3875 */ 3876 if (vsc->revision != 0x5) 3877 goto out; 3878 3879 /* VSC SDP Payload for DB16 through DB18 */ 3880 /* Pixel Encoding and Colorimetry Formats */ 3881 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ 3882 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ 3883 3884 switch (vsc->bpc) { 3885 case 6: 3886 /* 6bpc: 0x0 */ 3887 break; 3888 case 8: 3889 sdp->db[17] = 0x1; /* DB17[3:0] */ 3890 break; 3891 case 10: 3892 sdp->db[17] = 0x2; 3893 break; 3894 case 12: 3895 sdp->db[17] = 0x3; 3896 break; 3897 case 16: 3898 sdp->db[17] = 0x4; 3899 break; 3900 default: 3901 MISSING_CASE(vsc->bpc); 3902 break; 3903 } 3904 /* Dynamic Range and Component Bit Depth */ 3905 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 3906 sdp->db[17] |= 0x80; /* DB17[7] */ 3907 3908 /* Content Type */ 3909 sdp->db[18] = vsc->content_type & 0x7; 3910 3911 out: 3912 return length; 3913 } 3914 3915 static ssize_t 3916 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915, 3917 const struct hdmi_drm_infoframe *drm_infoframe, 3918 struct dp_sdp *sdp, 3919 size_t size) 3920 { 3921 size_t length = sizeof(struct dp_sdp); 3922 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; 3923 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; 3924 ssize_t len; 3925 3926 if (size < length) 3927 return -ENOSPC; 3928 3929 memset(sdp, 0, size); 3930 3931 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); 3932 if (len < 0) { 3933 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n"); 3934 return -ENOSPC; 3935 } 3936 3937 if (len != infoframe_size) { 3938 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n"); 3939 return -ENOSPC; 3940 } 3941 3942 /* 3943 * Set up the infoframe sdp packet for HDR static metadata. 3944 * Prepare VSC Header for SU as per DP 1.4a spec, 3945 * Table 2-100 and Table 2-101 3946 */ 3947 3948 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ 3949 sdp->sdp_header.HB0 = 0; 3950 /* 3951 * Packet Type 80h + Non-audio INFOFRAME Type value 3952 * HDMI_INFOFRAME_TYPE_DRM: 0x87 3953 * - 80h + Non-audio INFOFRAME Type value 3954 * - InfoFrame Type: 0x07 3955 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] 3956 */ 3957 sdp->sdp_header.HB1 = drm_infoframe->type; 3958 /* 3959 * Least Significant Eight Bits of (Data Byte Count – 1) 3960 * infoframe_size - 1 3961 */ 3962 sdp->sdp_header.HB2 = 0x1D; 3963 /* INFOFRAME SDP Version Number */ 3964 sdp->sdp_header.HB3 = (0x13 << 2); 3965 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 3966 sdp->db[0] = drm_infoframe->version; 3967 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 3968 sdp->db[1] = drm_infoframe->length; 3969 /* 3970 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after 3971 * HDMI_INFOFRAME_HEADER_SIZE 3972 */ 3973 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); 3974 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], 3975 HDMI_DRM_INFOFRAME_SIZE); 3976 3977 /* 3978 * Size of DP infoframe sdp packet for HDR static metadata consists of 3979 * - DP SDP Header(struct dp_sdp_header): 4 bytes 3980 * - Two Data Blocks: 2 bytes 3981 * CTA Header Byte2 (INFOFRAME Version Number) 3982 * CTA Header Byte3 (Length of INFOFRAME) 3983 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes 3984 * 3985 * Prior to GEN11's GMP register size is identical to DP HDR static metadata 3986 * infoframe size. But GEN11+ has larger than that size, write_infoframe 3987 * will pad rest of the size. 3988 */ 3989 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; 3990 } 3991 3992 static void intel_write_dp_sdp(struct intel_encoder *encoder, 3993 const struct intel_crtc_state *crtc_state, 3994 unsigned int type) 3995 { 3996 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3997 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3998 struct dp_sdp sdp = {}; 3999 ssize_t len; 4000 4001 if ((crtc_state->infoframes.enable & 4002 intel_hdmi_infoframe_enable(type)) == 0) 4003 return; 4004 4005 switch (type) { 4006 case DP_SDP_VSC: 4007 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp, 4008 sizeof(sdp)); 4009 break; 4010 case HDMI_PACKET_TYPE_GAMUT_METADATA: 4011 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv, 4012 &crtc_state->infoframes.drm.drm, 4013 &sdp, sizeof(sdp)); 4014 break; 4015 default: 4016 MISSING_CASE(type); 4017 return; 4018 } 4019 4020 if (drm_WARN_ON(&dev_priv->drm, len < 0)) 4021 return; 4022 4023 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); 4024 } 4025 4026 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, 4027 const struct intel_crtc_state *crtc_state, 4028 const struct drm_dp_vsc_sdp *vsc) 4029 { 4030 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4031 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4032 struct dp_sdp sdp = {}; 4033 ssize_t len; 4034 4035 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp)); 4036 4037 if (drm_WARN_ON(&dev_priv->drm, len < 0)) 4038 return; 4039 4040 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC, 4041 &sdp, len); 4042 } 4043 4044 void intel_dp_set_infoframes(struct intel_encoder *encoder, 4045 bool enable, 4046 const struct intel_crtc_state *crtc_state, 4047 const struct drm_connector_state *conn_state) 4048 { 4049 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4050 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 4051 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 4052 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | 4053 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; 4054 u32 val = intel_de_read(dev_priv, reg) & ~dip_enable; 4055 4056 /* TODO: Add DSC case (DIP_ENABLE_PPS) */ 4057 /* When PSR is enabled, this routine doesn't disable VSC DIP */ 4058 if (!crtc_state->has_psr) 4059 val &= ~VIDEO_DIP_ENABLE_VSC_HSW; 4060 4061 intel_de_write(dev_priv, reg, val); 4062 intel_de_posting_read(dev_priv, reg); 4063 4064 if (!enable) 4065 return; 4066 4067 /* When PSR is enabled, VSC SDP is handled by PSR routine */ 4068 if (!crtc_state->has_psr) 4069 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); 4070 4071 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); 4072 } 4073 4074 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, 4075 const void *buffer, size_t size) 4076 { 4077 const struct dp_sdp *sdp = buffer; 4078 4079 if (size < sizeof(struct dp_sdp)) 4080 return -EINVAL; 4081 4082 memset(vsc, 0, sizeof(*vsc)); 4083 4084 if (sdp->sdp_header.HB0 != 0) 4085 return -EINVAL; 4086 4087 if (sdp->sdp_header.HB1 != DP_SDP_VSC) 4088 return -EINVAL; 4089 4090 vsc->sdp_type = sdp->sdp_header.HB1; 4091 vsc->revision = sdp->sdp_header.HB2; 4092 vsc->length = sdp->sdp_header.HB3; 4093 4094 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || 4095 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) { 4096 /* 4097 * - HB2 = 0x2, HB3 = 0x8 4098 * VSC SDP supporting 3D stereo + PSR 4099 * - HB2 = 0x4, HB3 = 0xe 4100 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of 4101 * first scan line of the SU region (applies to eDP v1.4b 4102 * and higher). 4103 */ 4104 return 0; 4105 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { 4106 /* 4107 * - HB2 = 0x5, HB3 = 0x13 4108 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry 4109 * Format. 4110 */ 4111 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; 4112 vsc->colorimetry = sdp->db[16] & 0xf; 4113 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; 4114 4115 switch (sdp->db[17] & 0x7) { 4116 case 0x0: 4117 vsc->bpc = 6; 4118 break; 4119 case 0x1: 4120 vsc->bpc = 8; 4121 break; 4122 case 0x2: 4123 vsc->bpc = 10; 4124 break; 4125 case 0x3: 4126 vsc->bpc = 12; 4127 break; 4128 case 0x4: 4129 vsc->bpc = 16; 4130 break; 4131 default: 4132 MISSING_CASE(sdp->db[17] & 0x7); 4133 return -EINVAL; 4134 } 4135 4136 vsc->content_type = sdp->db[18] & 0x7; 4137 } else { 4138 return -EINVAL; 4139 } 4140 4141 return 0; 4142 } 4143 4144 static int 4145 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, 4146 const void *buffer, size_t size) 4147 { 4148 int ret; 4149 4150 const struct dp_sdp *sdp = buffer; 4151 4152 if (size < sizeof(struct dp_sdp)) 4153 return -EINVAL; 4154 4155 if (sdp->sdp_header.HB0 != 0) 4156 return -EINVAL; 4157 4158 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) 4159 return -EINVAL; 4160 4161 /* 4162 * Least Significant Eight Bits of (Data Byte Count – 1) 4163 * 1Dh (i.e., Data Byte Count = 30 bytes). 4164 */ 4165 if (sdp->sdp_header.HB2 != 0x1D) 4166 return -EINVAL; 4167 4168 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ 4169 if ((sdp->sdp_header.HB3 & 0x3) != 0) 4170 return -EINVAL; 4171 4172 /* INFOFRAME SDP Version Number */ 4173 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) 4174 return -EINVAL; 4175 4176 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 4177 if (sdp->db[0] != 1) 4178 return -EINVAL; 4179 4180 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 4181 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) 4182 return -EINVAL; 4183 4184 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], 4185 HDMI_DRM_INFOFRAME_SIZE); 4186 4187 return ret; 4188 } 4189 4190 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, 4191 struct intel_crtc_state *crtc_state, 4192 struct drm_dp_vsc_sdp *vsc) 4193 { 4194 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4195 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4196 unsigned int type = DP_SDP_VSC; 4197 struct dp_sdp sdp = {}; 4198 int ret; 4199 4200 /* When PSR is enabled, VSC SDP is handled by PSR routine */ 4201 if (crtc_state->has_psr) 4202 return; 4203 4204 if ((crtc_state->infoframes.enable & 4205 intel_hdmi_infoframe_enable(type)) == 0) 4206 return; 4207 4208 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); 4209 4210 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); 4211 4212 if (ret) 4213 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n"); 4214 } 4215 4216 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, 4217 struct intel_crtc_state *crtc_state, 4218 struct hdmi_drm_infoframe *drm_infoframe) 4219 { 4220 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4222 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; 4223 struct dp_sdp sdp = {}; 4224 int ret; 4225 4226 if ((crtc_state->infoframes.enable & 4227 intel_hdmi_infoframe_enable(type)) == 0) 4228 return; 4229 4230 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 4231 sizeof(sdp)); 4232 4233 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, 4234 sizeof(sdp)); 4235 4236 if (ret) 4237 drm_dbg_kms(&dev_priv->drm, 4238 "Failed to unpack DP HDR Metadata Infoframe SDP\n"); 4239 } 4240 4241 void intel_read_dp_sdp(struct intel_encoder *encoder, 4242 struct intel_crtc_state *crtc_state, 4243 unsigned int type) 4244 { 4245 switch (type) { 4246 case DP_SDP_VSC: 4247 intel_read_dp_vsc_sdp(encoder, crtc_state, 4248 &crtc_state->infoframes.vsc); 4249 break; 4250 case HDMI_PACKET_TYPE_GAMUT_METADATA: 4251 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, 4252 &crtc_state->infoframes.drm.drm); 4253 break; 4254 default: 4255 MISSING_CASE(type); 4256 break; 4257 } 4258 } 4259 4260 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) 4261 { 4262 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4263 int status = 0; 4264 int test_link_rate; 4265 u8 test_lane_count, test_link_bw; 4266 /* (DP CTS 1.2) 4267 * 4.3.1.11 4268 */ 4269 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ 4270 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, 4271 &test_lane_count); 4272 4273 if (status <= 0) { 4274 drm_dbg_kms(&i915->drm, "Lane count read failed\n"); 4275 return DP_TEST_NAK; 4276 } 4277 test_lane_count &= DP_MAX_LANE_COUNT_MASK; 4278 4279 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, 4280 &test_link_bw); 4281 if (status <= 0) { 4282 drm_dbg_kms(&i915->drm, "Link Rate read failed\n"); 4283 return DP_TEST_NAK; 4284 } 4285 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); 4286 4287 /* Validate the requested link rate and lane count */ 4288 if (!intel_dp_link_params_valid(intel_dp, test_link_rate, 4289 test_lane_count)) 4290 return DP_TEST_NAK; 4291 4292 intel_dp->compliance.test_lane_count = test_lane_count; 4293 intel_dp->compliance.test_link_rate = test_link_rate; 4294 4295 return DP_TEST_ACK; 4296 } 4297 4298 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) 4299 { 4300 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4301 u8 test_pattern; 4302 u8 test_misc; 4303 __be16 h_width, v_height; 4304 int status = 0; 4305 4306 /* Read the TEST_PATTERN (DP CTS 3.1.5) */ 4307 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, 4308 &test_pattern); 4309 if (status <= 0) { 4310 drm_dbg_kms(&i915->drm, "Test pattern read failed\n"); 4311 return DP_TEST_NAK; 4312 } 4313 if (test_pattern != DP_COLOR_RAMP) 4314 return DP_TEST_NAK; 4315 4316 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, 4317 &h_width, 2); 4318 if (status <= 0) { 4319 drm_dbg_kms(&i915->drm, "H Width read failed\n"); 4320 return DP_TEST_NAK; 4321 } 4322 4323 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, 4324 &v_height, 2); 4325 if (status <= 0) { 4326 drm_dbg_kms(&i915->drm, "V Height read failed\n"); 4327 return DP_TEST_NAK; 4328 } 4329 4330 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, 4331 &test_misc); 4332 if (status <= 0) { 4333 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n"); 4334 return DP_TEST_NAK; 4335 } 4336 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) 4337 return DP_TEST_NAK; 4338 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) 4339 return DP_TEST_NAK; 4340 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { 4341 case DP_TEST_BIT_DEPTH_6: 4342 intel_dp->compliance.test_data.bpc = 6; 4343 break; 4344 case DP_TEST_BIT_DEPTH_8: 4345 intel_dp->compliance.test_data.bpc = 8; 4346 break; 4347 default: 4348 return DP_TEST_NAK; 4349 } 4350 4351 intel_dp->compliance.test_data.video_pattern = test_pattern; 4352 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); 4353 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); 4354 /* Set test active flag here so userspace doesn't interrupt things */ 4355 intel_dp->compliance.test_active = true; 4356 4357 return DP_TEST_ACK; 4358 } 4359 4360 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) 4361 { 4362 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4363 u8 test_result = DP_TEST_ACK; 4364 struct intel_connector *intel_connector = intel_dp->attached_connector; 4365 struct drm_connector *connector = &intel_connector->base; 4366 4367 if (intel_connector->detect_edid == NULL || 4368 connector->edid_corrupt || 4369 intel_dp->aux.i2c_defer_count > 6) { 4370 /* Check EDID read for NACKs, DEFERs and corruption 4371 * (DP CTS 1.2 Core r1.1) 4372 * 4.2.2.4 : Failed EDID read, I2C_NAK 4373 * 4.2.2.5 : Failed EDID read, I2C_DEFER 4374 * 4.2.2.6 : EDID corruption detected 4375 * Use failsafe mode for all cases 4376 */ 4377 if (intel_dp->aux.i2c_nack_count > 0 || 4378 intel_dp->aux.i2c_defer_count > 0) 4379 drm_dbg_kms(&i915->drm, 4380 "EDID read had %d NACKs, %d DEFERs\n", 4381 intel_dp->aux.i2c_nack_count, 4382 intel_dp->aux.i2c_defer_count); 4383 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; 4384 } else { 4385 /* FIXME: Get rid of drm_edid_raw() */ 4386 const struct edid *block = drm_edid_raw(intel_connector->detect_edid); 4387 4388 /* We have to write the checksum of the last block read */ 4389 block += block->extensions; 4390 4391 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, 4392 block->checksum) <= 0) 4393 drm_dbg_kms(&i915->drm, 4394 "Failed to write EDID checksum\n"); 4395 4396 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; 4397 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; 4398 } 4399 4400 /* Set test active flag here so userspace doesn't interrupt things */ 4401 intel_dp->compliance.test_active = true; 4402 4403 return test_result; 4404 } 4405 4406 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, 4407 const struct intel_crtc_state *crtc_state) 4408 { 4409 struct drm_i915_private *dev_priv = 4410 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 4411 struct drm_dp_phy_test_params *data = 4412 &intel_dp->compliance.test_data.phytest; 4413 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4414 enum pipe pipe = crtc->pipe; 4415 u32 pattern_val; 4416 4417 switch (data->phy_pattern) { 4418 case DP_PHY_TEST_PATTERN_NONE: 4419 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n"); 4420 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); 4421 break; 4422 case DP_PHY_TEST_PATTERN_D10_2: 4423 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n"); 4424 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4425 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); 4426 break; 4427 case DP_PHY_TEST_PATTERN_ERROR_COUNT: 4428 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n"); 4429 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4430 DDI_DP_COMP_CTL_ENABLE | 4431 DDI_DP_COMP_CTL_SCRAMBLED_0); 4432 break; 4433 case DP_PHY_TEST_PATTERN_PRBS7: 4434 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n"); 4435 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4436 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); 4437 break; 4438 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: 4439 /* 4440 * FIXME: Ideally pattern should come from DPCD 0x250. As 4441 * current firmware of DPR-100 could not set it, so hardcoding 4442 * now for complaince test. 4443 */ 4444 drm_dbg_kms(&dev_priv->drm, 4445 "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); 4446 pattern_val = 0x3e0f83e0; 4447 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); 4448 pattern_val = 0x0f83e0f8; 4449 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); 4450 pattern_val = 0x0000f83e; 4451 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); 4452 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4453 DDI_DP_COMP_CTL_ENABLE | 4454 DDI_DP_COMP_CTL_CUSTOM80); 4455 break; 4456 case DP_PHY_TEST_PATTERN_CP2520: 4457 /* 4458 * FIXME: Ideally pattern should come from DPCD 0x24A. As 4459 * current firmware of DPR-100 could not set it, so hardcoding 4460 * now for complaince test. 4461 */ 4462 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n"); 4463 pattern_val = 0xFB; 4464 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4465 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | 4466 pattern_val); 4467 break; 4468 default: 4469 WARN(1, "Invalid Phy Test Pattern\n"); 4470 } 4471 } 4472 4473 static void intel_dp_process_phy_request(struct intel_dp *intel_dp, 4474 const struct intel_crtc_state *crtc_state) 4475 { 4476 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4477 struct drm_dp_phy_test_params *data = 4478 &intel_dp->compliance.test_data.phytest; 4479 u8 link_status[DP_LINK_STATUS_SIZE]; 4480 4481 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 4482 link_status) < 0) { 4483 drm_dbg_kms(&i915->drm, "failed to get link status\n"); 4484 return; 4485 } 4486 4487 /* retrieve vswing & pre-emphasis setting */ 4488 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, 4489 link_status); 4490 4491 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX); 4492 4493 intel_dp_phy_pattern_update(intel_dp, crtc_state); 4494 4495 drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 4496 intel_dp->train_set, crtc_state->lane_count); 4497 4498 drm_dp_set_phy_test_pattern(&intel_dp->aux, data, 4499 link_status[DP_DPCD_REV]); 4500 } 4501 4502 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) 4503 { 4504 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4505 struct drm_dp_phy_test_params *data = 4506 &intel_dp->compliance.test_data.phytest; 4507 4508 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) { 4509 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n"); 4510 return DP_TEST_NAK; 4511 } 4512 4513 /* Set test active flag here so userspace doesn't interrupt things */ 4514 intel_dp->compliance.test_active = true; 4515 4516 return DP_TEST_ACK; 4517 } 4518 4519 static void intel_dp_handle_test_request(struct intel_dp *intel_dp) 4520 { 4521 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4522 u8 response = DP_TEST_NAK; 4523 u8 request = 0; 4524 int status; 4525 4526 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); 4527 if (status <= 0) { 4528 drm_dbg_kms(&i915->drm, 4529 "Could not read test request from sink\n"); 4530 goto update_status; 4531 } 4532 4533 switch (request) { 4534 case DP_TEST_LINK_TRAINING: 4535 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n"); 4536 response = intel_dp_autotest_link_training(intel_dp); 4537 break; 4538 case DP_TEST_LINK_VIDEO_PATTERN: 4539 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n"); 4540 response = intel_dp_autotest_video_pattern(intel_dp); 4541 break; 4542 case DP_TEST_LINK_EDID_READ: 4543 drm_dbg_kms(&i915->drm, "EDID test requested\n"); 4544 response = intel_dp_autotest_edid(intel_dp); 4545 break; 4546 case DP_TEST_LINK_PHY_TEST_PATTERN: 4547 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); 4548 response = intel_dp_autotest_phy_pattern(intel_dp); 4549 break; 4550 default: 4551 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n", 4552 request); 4553 break; 4554 } 4555 4556 if (response & DP_TEST_ACK) 4557 intel_dp->compliance.test_type = request; 4558 4559 update_status: 4560 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); 4561 if (status <= 0) 4562 drm_dbg_kms(&i915->drm, 4563 "Could not write test response to sink\n"); 4564 } 4565 4566 static bool intel_dp_link_ok(struct intel_dp *intel_dp, 4567 u8 link_status[DP_LINK_STATUS_SIZE]) 4568 { 4569 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4570 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4571 bool uhbr = intel_dp->link_rate >= 1000000; 4572 bool ok; 4573 4574 if (uhbr) 4575 ok = drm_dp_128b132b_lane_channel_eq_done(link_status, 4576 intel_dp->lane_count); 4577 else 4578 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); 4579 4580 if (ok) 4581 return true; 4582 4583 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 4584 drm_dbg_kms(&i915->drm, 4585 "[ENCODER:%d:%s] %s link not ok, retraining\n", 4586 encoder->base.base.id, encoder->base.name, 4587 uhbr ? "128b/132b" : "8b/10b"); 4588 4589 return false; 4590 } 4591 4592 static void 4593 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack) 4594 { 4595 bool handled = false; 4596 4597 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled); 4598 4599 if (esi[1] & DP_CP_IRQ) { 4600 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 4601 ack[1] |= DP_CP_IRQ; 4602 } 4603 } 4604 4605 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp) 4606 { 4607 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4608 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4609 u8 link_status[DP_LINK_STATUS_SIZE] = {}; 4610 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2; 4611 4612 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status, 4613 esi_link_status_size) != esi_link_status_size) { 4614 drm_err(&i915->drm, 4615 "[ENCODER:%d:%s] Failed to read link status\n", 4616 encoder->base.base.id, encoder->base.name); 4617 return false; 4618 } 4619 4620 return intel_dp_link_ok(intel_dp, link_status); 4621 } 4622 4623 /** 4624 * intel_dp_check_mst_status - service any pending MST interrupts, check link status 4625 * @intel_dp: Intel DP struct 4626 * 4627 * Read any pending MST interrupts, call MST core to handle these and ack the 4628 * interrupts. Check if the main and AUX link state is ok. 4629 * 4630 * Returns: 4631 * - %true if pending interrupts were serviced (or no interrupts were 4632 * pending) w/o detecting an error condition. 4633 * - %false if an error condition - like AUX failure or a loss of link - is 4634 * detected, which needs servicing from the hotplug work. 4635 */ 4636 static bool 4637 intel_dp_check_mst_status(struct intel_dp *intel_dp) 4638 { 4639 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4640 bool link_ok = true; 4641 4642 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); 4643 4644 for (;;) { 4645 u8 esi[4] = {}; 4646 u8 ack[4] = {}; 4647 4648 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { 4649 drm_dbg_kms(&i915->drm, 4650 "failed to get ESI - device may have failed\n"); 4651 link_ok = false; 4652 4653 break; 4654 } 4655 4656 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi); 4657 4658 if (intel_dp->active_mst_links > 0 && link_ok && 4659 esi[3] & LINK_STATUS_CHANGED) { 4660 if (!intel_dp_mst_link_status(intel_dp)) 4661 link_ok = false; 4662 ack[3] |= LINK_STATUS_CHANGED; 4663 } 4664 4665 intel_dp_mst_hpd_irq(intel_dp, esi, ack); 4666 4667 if (!memchr_inv(ack, 0, sizeof(ack))) 4668 break; 4669 4670 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack)) 4671 drm_dbg_kms(&i915->drm, "Failed to ack ESI\n"); 4672 4673 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY)) 4674 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); 4675 } 4676 4677 return link_ok; 4678 } 4679 4680 static void 4681 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) 4682 { 4683 bool is_active; 4684 u8 buf = 0; 4685 4686 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux); 4687 if (intel_dp->frl.is_trained && !is_active) { 4688 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0) 4689 return; 4690 4691 buf &= ~DP_PCON_ENABLE_HDMI_LINK; 4692 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) 4693 return; 4694 4695 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); 4696 4697 intel_dp->frl.is_trained = false; 4698 4699 /* Restart FRL training or fall back to TMDS mode */ 4700 intel_dp_check_frl_training(intel_dp); 4701 } 4702 } 4703 4704 static bool 4705 intel_dp_needs_link_retrain(struct intel_dp *intel_dp) 4706 { 4707 u8 link_status[DP_LINK_STATUS_SIZE]; 4708 4709 if (!intel_dp->link_trained) 4710 return false; 4711 4712 /* 4713 * While PSR source HW is enabled, it will control main-link sending 4714 * frames, enabling and disabling it so trying to do a retrain will fail 4715 * as the link would or not be on or it could mix training patterns 4716 * and frame data at the same time causing retrain to fail. 4717 * Also when exiting PSR, HW will retrain the link anyways fixing 4718 * any link status error. 4719 */ 4720 if (intel_psr_enabled(intel_dp)) 4721 return false; 4722 4723 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 4724 link_status) < 0) 4725 return false; 4726 4727 /* 4728 * Validate the cached values of intel_dp->link_rate and 4729 * intel_dp->lane_count before attempting to retrain. 4730 * 4731 * FIXME would be nice to user the crtc state here, but since 4732 * we need to call this from the short HPD handler that seems 4733 * a bit hard. 4734 */ 4735 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, 4736 intel_dp->lane_count)) 4737 return false; 4738 4739 /* Retrain if link not ok */ 4740 return !intel_dp_link_ok(intel_dp, link_status); 4741 } 4742 4743 static bool intel_dp_has_connector(struct intel_dp *intel_dp, 4744 const struct drm_connector_state *conn_state) 4745 { 4746 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4747 struct intel_encoder *encoder; 4748 enum pipe pipe; 4749 4750 if (!conn_state->best_encoder) 4751 return false; 4752 4753 /* SST */ 4754 encoder = &dp_to_dig_port(intel_dp)->base; 4755 if (conn_state->best_encoder == &encoder->base) 4756 return true; 4757 4758 /* MST */ 4759 for_each_pipe(i915, pipe) { 4760 encoder = &intel_dp->mst_encoders[pipe]->base; 4761 if (conn_state->best_encoder == &encoder->base) 4762 return true; 4763 } 4764 4765 return false; 4766 } 4767 4768 int intel_dp_get_active_pipes(struct intel_dp *intel_dp, 4769 struct drm_modeset_acquire_ctx *ctx, 4770 u8 *pipe_mask) 4771 { 4772 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4773 struct drm_connector_list_iter conn_iter; 4774 struct intel_connector *connector; 4775 int ret = 0; 4776 4777 *pipe_mask = 0; 4778 4779 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 4780 for_each_intel_connector_iter(connector, &conn_iter) { 4781 struct drm_connector_state *conn_state = 4782 connector->base.state; 4783 struct intel_crtc_state *crtc_state; 4784 struct intel_crtc *crtc; 4785 4786 if (!intel_dp_has_connector(intel_dp, conn_state)) 4787 continue; 4788 4789 crtc = to_intel_crtc(conn_state->crtc); 4790 if (!crtc) 4791 continue; 4792 4793 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4794 if (ret) 4795 break; 4796 4797 crtc_state = to_intel_crtc_state(crtc->base.state); 4798 4799 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); 4800 4801 if (!crtc_state->hw.active) 4802 continue; 4803 4804 if (conn_state->commit && 4805 !try_wait_for_completion(&conn_state->commit->hw_done)) 4806 continue; 4807 4808 *pipe_mask |= BIT(crtc->pipe); 4809 } 4810 drm_connector_list_iter_end(&conn_iter); 4811 4812 return ret; 4813 } 4814 4815 static bool intel_dp_is_connected(struct intel_dp *intel_dp) 4816 { 4817 struct intel_connector *connector = intel_dp->attached_connector; 4818 4819 return connector->base.status == connector_status_connected || 4820 intel_dp->is_mst; 4821 } 4822 4823 int intel_dp_retrain_link(struct intel_encoder *encoder, 4824 struct drm_modeset_acquire_ctx *ctx) 4825 { 4826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4827 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4828 struct intel_crtc *crtc; 4829 u8 pipe_mask; 4830 int ret; 4831 4832 if (!intel_dp_is_connected(intel_dp)) 4833 return 0; 4834 4835 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4836 ctx); 4837 if (ret) 4838 return ret; 4839 4840 if (!intel_dp_needs_link_retrain(intel_dp)) 4841 return 0; 4842 4843 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); 4844 if (ret) 4845 return ret; 4846 4847 if (pipe_mask == 0) 4848 return 0; 4849 4850 if (!intel_dp_needs_link_retrain(intel_dp)) 4851 return 0; 4852 4853 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n", 4854 encoder->base.base.id, encoder->base.name); 4855 4856 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { 4857 const struct intel_crtc_state *crtc_state = 4858 to_intel_crtc_state(crtc->base.state); 4859 4860 /* Suppress underruns caused by re-training */ 4861 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 4862 if (crtc_state->has_pch_encoder) 4863 intel_set_pch_fifo_underrun_reporting(dev_priv, 4864 intel_crtc_pch_transcoder(crtc), false); 4865 } 4866 4867 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { 4868 const struct intel_crtc_state *crtc_state = 4869 to_intel_crtc_state(crtc->base.state); 4870 4871 /* retrain on the MST master transcoder */ 4872 if (DISPLAY_VER(dev_priv) >= 12 && 4873 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 4874 !intel_dp_mst_is_master_trans(crtc_state)) 4875 continue; 4876 4877 intel_dp_check_frl_training(intel_dp); 4878 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 4879 intel_dp_start_link_train(intel_dp, crtc_state); 4880 intel_dp_stop_link_train(intel_dp, crtc_state); 4881 break; 4882 } 4883 4884 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { 4885 const struct intel_crtc_state *crtc_state = 4886 to_intel_crtc_state(crtc->base.state); 4887 4888 /* Keep underrun reporting disabled until things are stable */ 4889 intel_crtc_wait_for_next_vblank(crtc); 4890 4891 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 4892 if (crtc_state->has_pch_encoder) 4893 intel_set_pch_fifo_underrun_reporting(dev_priv, 4894 intel_crtc_pch_transcoder(crtc), true); 4895 } 4896 4897 return 0; 4898 } 4899 4900 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, 4901 struct drm_modeset_acquire_ctx *ctx, 4902 u8 *pipe_mask) 4903 { 4904 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4905 struct drm_connector_list_iter conn_iter; 4906 struct intel_connector *connector; 4907 int ret = 0; 4908 4909 *pipe_mask = 0; 4910 4911 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 4912 for_each_intel_connector_iter(connector, &conn_iter) { 4913 struct drm_connector_state *conn_state = 4914 connector->base.state; 4915 struct intel_crtc_state *crtc_state; 4916 struct intel_crtc *crtc; 4917 4918 if (!intel_dp_has_connector(intel_dp, conn_state)) 4919 continue; 4920 4921 crtc = to_intel_crtc(conn_state->crtc); 4922 if (!crtc) 4923 continue; 4924 4925 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4926 if (ret) 4927 break; 4928 4929 crtc_state = to_intel_crtc_state(crtc->base.state); 4930 4931 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); 4932 4933 if (!crtc_state->hw.active) 4934 continue; 4935 4936 if (conn_state->commit && 4937 !try_wait_for_completion(&conn_state->commit->hw_done)) 4938 continue; 4939 4940 *pipe_mask |= BIT(crtc->pipe); 4941 } 4942 drm_connector_list_iter_end(&conn_iter); 4943 4944 return ret; 4945 } 4946 4947 static int intel_dp_do_phy_test(struct intel_encoder *encoder, 4948 struct drm_modeset_acquire_ctx *ctx) 4949 { 4950 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4951 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4952 struct intel_crtc *crtc; 4953 u8 pipe_mask; 4954 int ret; 4955 4956 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4957 ctx); 4958 if (ret) 4959 return ret; 4960 4961 ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask); 4962 if (ret) 4963 return ret; 4964 4965 if (pipe_mask == 0) 4966 return 0; 4967 4968 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n", 4969 encoder->base.base.id, encoder->base.name); 4970 4971 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { 4972 const struct intel_crtc_state *crtc_state = 4973 to_intel_crtc_state(crtc->base.state); 4974 4975 /* test on the MST master transcoder */ 4976 if (DISPLAY_VER(dev_priv) >= 12 && 4977 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 4978 !intel_dp_mst_is_master_trans(crtc_state)) 4979 continue; 4980 4981 intel_dp_process_phy_request(intel_dp, crtc_state); 4982 break; 4983 } 4984 4985 return 0; 4986 } 4987 4988 void intel_dp_phy_test(struct intel_encoder *encoder) 4989 { 4990 struct drm_modeset_acquire_ctx ctx; 4991 int ret; 4992 4993 drm_modeset_acquire_init(&ctx, 0); 4994 4995 for (;;) { 4996 ret = intel_dp_do_phy_test(encoder, &ctx); 4997 4998 if (ret == -EDEADLK) { 4999 drm_modeset_backoff(&ctx); 5000 continue; 5001 } 5002 5003 break; 5004 } 5005 5006 drm_modeset_drop_locks(&ctx); 5007 drm_modeset_acquire_fini(&ctx); 5008 drm_WARN(encoder->base.dev, ret, 5009 "Acquiring modeset locks failed with %i\n", ret); 5010 } 5011 5012 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp) 5013 { 5014 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5015 u8 val; 5016 5017 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5018 return; 5019 5020 if (drm_dp_dpcd_readb(&intel_dp->aux, 5021 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) 5022 return; 5023 5024 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); 5025 5026 if (val & DP_AUTOMATED_TEST_REQUEST) 5027 intel_dp_handle_test_request(intel_dp); 5028 5029 if (val & DP_CP_IRQ) 5030 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5031 5032 if (val & DP_SINK_SPECIFIC_IRQ) 5033 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n"); 5034 } 5035 5036 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp) 5037 { 5038 u8 val; 5039 5040 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5041 return; 5042 5043 if (drm_dp_dpcd_readb(&intel_dp->aux, 5044 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) 5045 return; 5046 5047 if (drm_dp_dpcd_writeb(&intel_dp->aux, 5048 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) 5049 return; 5050 5051 if (val & HDMI_LINK_STATUS_CHANGED) 5052 intel_dp_handle_hdmi_link_status_change(intel_dp); 5053 } 5054 5055 /* 5056 * According to DP spec 5057 * 5.1.2: 5058 * 1. Read DPCD 5059 * 2. Configure link according to Receiver Capabilities 5060 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 5061 * 4. Check link status on receipt of hot-plug interrupt 5062 * 5063 * intel_dp_short_pulse - handles short pulse interrupts 5064 * when full detection is not required. 5065 * Returns %true if short pulse is handled and full detection 5066 * is NOT required and %false otherwise. 5067 */ 5068 static bool 5069 intel_dp_short_pulse(struct intel_dp *intel_dp) 5070 { 5071 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 5072 u8 old_sink_count = intel_dp->sink_count; 5073 bool ret; 5074 5075 /* 5076 * Clearing compliance test variables to allow capturing 5077 * of values for next automated test request. 5078 */ 5079 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); 5080 5081 /* 5082 * Now read the DPCD to see if it's actually running 5083 * If the current value of sink count doesn't match with 5084 * the value that was stored earlier or dpcd read failed 5085 * we need to do full detection 5086 */ 5087 ret = intel_dp_get_dpcd(intel_dp); 5088 5089 if ((old_sink_count != intel_dp->sink_count) || !ret) { 5090 /* No need to proceed if we are going to do full detect */ 5091 return false; 5092 } 5093 5094 intel_dp_check_device_service_irq(intel_dp); 5095 intel_dp_check_link_service_irq(intel_dp); 5096 5097 /* Handle CEC interrupts, if any */ 5098 drm_dp_cec_irq(&intel_dp->aux); 5099 5100 /* defer to the hotplug work for link retraining if needed */ 5101 if (intel_dp_needs_link_retrain(intel_dp)) 5102 return false; 5103 5104 intel_psr_short_pulse(intel_dp); 5105 5106 switch (intel_dp->compliance.test_type) { 5107 case DP_TEST_LINK_TRAINING: 5108 drm_dbg_kms(&dev_priv->drm, 5109 "Link Training Compliance Test requested\n"); 5110 /* Send a Hotplug Uevent to userspace to start modeset */ 5111 drm_kms_helper_hotplug_event(&dev_priv->drm); 5112 break; 5113 case DP_TEST_LINK_PHY_TEST_PATTERN: 5114 drm_dbg_kms(&dev_priv->drm, 5115 "PHY test pattern Compliance Test requested\n"); 5116 /* 5117 * Schedule long hpd to do the test 5118 * 5119 * FIXME get rid of the ad-hoc phy test modeset code 5120 * and properly incorporate it into the normal modeset. 5121 */ 5122 return false; 5123 } 5124 5125 return true; 5126 } 5127 5128 /* XXX this is probably wrong for multiple downstream ports */ 5129 static enum drm_connector_status 5130 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 5131 { 5132 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5133 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5134 u8 *dpcd = intel_dp->dpcd; 5135 u8 type; 5136 5137 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp))) 5138 return connector_status_connected; 5139 5140 lspcon_resume(dig_port); 5141 5142 if (!intel_dp_get_dpcd(intel_dp)) 5143 return connector_status_disconnected; 5144 5145 /* if there's no downstream port, we're done */ 5146 if (!drm_dp_is_branch(dpcd)) 5147 return connector_status_connected; 5148 5149 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 5150 if (intel_dp_has_sink_count(intel_dp) && 5151 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 5152 return intel_dp->sink_count ? 5153 connector_status_connected : connector_status_disconnected; 5154 } 5155 5156 if (intel_dp_can_mst(intel_dp)) 5157 return connector_status_connected; 5158 5159 /* If no HPD, poke DDC gently */ 5160 if (drm_probe_ddc(&intel_dp->aux.ddc)) 5161 return connector_status_connected; 5162 5163 /* Well we tried, say unknown for unreliable port types */ 5164 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 5165 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 5166 if (type == DP_DS_PORT_TYPE_VGA || 5167 type == DP_DS_PORT_TYPE_NON_EDID) 5168 return connector_status_unknown; 5169 } else { 5170 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 5171 DP_DWN_STRM_PORT_TYPE_MASK; 5172 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 5173 type == DP_DWN_STRM_PORT_TYPE_OTHER) 5174 return connector_status_unknown; 5175 } 5176 5177 /* Anything else is out of spec, warn and ignore */ 5178 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n"); 5179 return connector_status_disconnected; 5180 } 5181 5182 static enum drm_connector_status 5183 edp_detect(struct intel_dp *intel_dp) 5184 { 5185 return connector_status_connected; 5186 } 5187 5188 /* 5189 * intel_digital_port_connected - is the specified port connected? 5190 * @encoder: intel_encoder 5191 * 5192 * In cases where there's a connector physically connected but it can't be used 5193 * by our hardware we also return false, since the rest of the driver should 5194 * pretty much treat the port as disconnected. This is relevant for type-C 5195 * (starting on ICL) where there's ownership involved. 5196 * 5197 * Return %true if port is connected, %false otherwise. 5198 */ 5199 bool intel_digital_port_connected(struct intel_encoder *encoder) 5200 { 5201 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5202 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5203 bool is_connected = false; 5204 intel_wakeref_t wakeref; 5205 5206 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) 5207 is_connected = dig_port->connected(encoder); 5208 5209 return is_connected; 5210 } 5211 5212 static const struct drm_edid * 5213 intel_dp_get_edid(struct intel_dp *intel_dp) 5214 { 5215 struct intel_connector *connector = intel_dp->attached_connector; 5216 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; 5217 5218 /* Use panel fixed edid if we have one */ 5219 if (fixed_edid) { 5220 /* invalid edid */ 5221 if (IS_ERR(fixed_edid)) 5222 return NULL; 5223 5224 return drm_edid_dup(fixed_edid); 5225 } 5226 5227 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc); 5228 } 5229 5230 static void 5231 intel_dp_update_dfp(struct intel_dp *intel_dp, 5232 const struct drm_edid *drm_edid) 5233 { 5234 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5235 struct intel_connector *connector = intel_dp->attached_connector; 5236 5237 intel_dp->dfp.max_bpc = 5238 drm_dp_downstream_max_bpc(intel_dp->dpcd, 5239 intel_dp->downstream_ports, drm_edid); 5240 5241 intel_dp->dfp.max_dotclock = 5242 drm_dp_downstream_max_dotclock(intel_dp->dpcd, 5243 intel_dp->downstream_ports); 5244 5245 intel_dp->dfp.min_tmds_clock = 5246 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, 5247 intel_dp->downstream_ports, 5248 drm_edid); 5249 intel_dp->dfp.max_tmds_clock = 5250 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, 5251 intel_dp->downstream_ports, 5252 drm_edid); 5253 5254 intel_dp->dfp.pcon_max_frl_bw = 5255 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, 5256 intel_dp->downstream_ports); 5257 5258 drm_dbg_kms(&i915->drm, 5259 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", 5260 connector->base.base.id, connector->base.name, 5261 intel_dp->dfp.max_bpc, 5262 intel_dp->dfp.max_dotclock, 5263 intel_dp->dfp.min_tmds_clock, 5264 intel_dp->dfp.max_tmds_clock, 5265 intel_dp->dfp.pcon_max_frl_bw); 5266 5267 intel_dp_get_pcon_dsc_cap(intel_dp); 5268 } 5269 5270 static bool 5271 intel_dp_can_ycbcr420(struct intel_dp *intel_dp) 5272 { 5273 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) && 5274 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough)) 5275 return true; 5276 5277 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) && 5278 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5279 return true; 5280 5281 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) && 5282 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5283 return true; 5284 5285 return false; 5286 } 5287 5288 static void 5289 intel_dp_update_420(struct intel_dp *intel_dp) 5290 { 5291 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5292 struct intel_connector *connector = intel_dp->attached_connector; 5293 5294 intel_dp->dfp.ycbcr420_passthrough = 5295 drm_dp_downstream_420_passthrough(intel_dp->dpcd, 5296 intel_dp->downstream_ports); 5297 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ 5298 intel_dp->dfp.ycbcr_444_to_420 = 5299 dp_to_dig_port(intel_dp)->lspcon.active || 5300 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, 5301 intel_dp->downstream_ports); 5302 intel_dp->dfp.rgb_to_ycbcr = 5303 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, 5304 intel_dp->downstream_ports, 5305 DP_DS_HDMI_BT709_RGB_YCBCR_CONV); 5306 5307 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp); 5308 5309 drm_dbg_kms(&i915->drm, 5310 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", 5311 connector->base.base.id, connector->base.name, 5312 str_yes_no(intel_dp->dfp.rgb_to_ycbcr), 5313 str_yes_no(connector->base.ycbcr_420_allowed), 5314 str_yes_no(intel_dp->dfp.ycbcr_444_to_420)); 5315 } 5316 5317 static void 5318 intel_dp_set_edid(struct intel_dp *intel_dp) 5319 { 5320 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5321 struct intel_connector *connector = intel_dp->attached_connector; 5322 const struct drm_edid *drm_edid; 5323 bool vrr_capable; 5324 5325 intel_dp_unset_edid(intel_dp); 5326 drm_edid = intel_dp_get_edid(intel_dp); 5327 connector->detect_edid = drm_edid; 5328 5329 /* Below we depend on display info having been updated */ 5330 drm_edid_connector_update(&connector->base, drm_edid); 5331 5332 vrr_capable = intel_vrr_is_capable(connector); 5333 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n", 5334 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable)); 5335 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable); 5336 5337 intel_dp_update_dfp(intel_dp, drm_edid); 5338 intel_dp_update_420(intel_dp); 5339 5340 drm_dp_cec_attach(&intel_dp->aux, 5341 connector->base.display_info.source_physical_address); 5342 } 5343 5344 static void 5345 intel_dp_unset_edid(struct intel_dp *intel_dp) 5346 { 5347 struct intel_connector *connector = intel_dp->attached_connector; 5348 5349 drm_dp_cec_unset_edid(&intel_dp->aux); 5350 drm_edid_free(connector->detect_edid); 5351 connector->detect_edid = NULL; 5352 5353 intel_dp->dfp.max_bpc = 0; 5354 intel_dp->dfp.max_dotclock = 0; 5355 intel_dp->dfp.min_tmds_clock = 0; 5356 intel_dp->dfp.max_tmds_clock = 0; 5357 5358 intel_dp->dfp.pcon_max_frl_bw = 0; 5359 5360 intel_dp->dfp.ycbcr_444_to_420 = false; 5361 connector->base.ycbcr_420_allowed = false; 5362 5363 drm_connector_set_vrr_capable_property(&connector->base, 5364 false); 5365 } 5366 5367 static void 5368 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) 5369 { 5370 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5371 5372 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ 5373 if (!HAS_DSC(i915)) 5374 return; 5375 5376 if (intel_dp_is_edp(intel_dp)) 5377 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], 5378 connector); 5379 else 5380 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], 5381 connector); 5382 } 5383 5384 static int 5385 intel_dp_detect(struct drm_connector *connector, 5386 struct drm_modeset_acquire_ctx *ctx, 5387 bool force) 5388 { 5389 struct drm_i915_private *dev_priv = to_i915(connector->dev); 5390 struct intel_connector *intel_connector = 5391 to_intel_connector(connector); 5392 struct intel_dp *intel_dp = intel_attached_dp(intel_connector); 5393 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5394 struct intel_encoder *encoder = &dig_port->base; 5395 enum drm_connector_status status; 5396 5397 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 5398 connector->base.id, connector->name); 5399 drm_WARN_ON(&dev_priv->drm, 5400 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 5401 5402 if (!intel_display_device_enabled(dev_priv)) 5403 return connector_status_disconnected; 5404 5405 /* Can't disconnect eDP */ 5406 if (intel_dp_is_edp(intel_dp)) 5407 status = edp_detect(intel_dp); 5408 else if (intel_digital_port_connected(encoder)) 5409 status = intel_dp_detect_dpcd(intel_dp); 5410 else 5411 status = connector_status_disconnected; 5412 5413 if (status == connector_status_disconnected) { 5414 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); 5415 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd)); 5416 5417 if (intel_dp->is_mst) { 5418 drm_dbg_kms(&dev_priv->drm, 5419 "MST device may have disappeared %d vs %d\n", 5420 intel_dp->is_mst, 5421 intel_dp->mst_mgr.mst_state); 5422 intel_dp->is_mst = false; 5423 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 5424 intel_dp->is_mst); 5425 } 5426 5427 goto out; 5428 } 5429 5430 intel_dp_detect_dsc_caps(intel_dp, intel_connector); 5431 5432 intel_dp_configure_mst(intel_dp); 5433 5434 /* 5435 * TODO: Reset link params when switching to MST mode, until MST 5436 * supports link training fallback params. 5437 */ 5438 if (intel_dp->reset_link_params || intel_dp->is_mst) { 5439 intel_dp_reset_max_link_params(intel_dp); 5440 intel_dp->reset_link_params = false; 5441 } 5442 5443 intel_dp_print_rates(intel_dp); 5444 5445 if (intel_dp->is_mst) { 5446 /* 5447 * If we are in MST mode then this connector 5448 * won't appear connected or have anything 5449 * with EDID on it 5450 */ 5451 status = connector_status_disconnected; 5452 goto out; 5453 } 5454 5455 /* 5456 * Some external monitors do not signal loss of link synchronization 5457 * with an IRQ_HPD, so force a link status check. 5458 */ 5459 if (!intel_dp_is_edp(intel_dp)) { 5460 int ret; 5461 5462 ret = intel_dp_retrain_link(encoder, ctx); 5463 if (ret) 5464 return ret; 5465 } 5466 5467 /* 5468 * Clearing NACK and defer counts to get their exact values 5469 * while reading EDID which are required by Compliance tests 5470 * 4.2.2.4 and 4.2.2.5 5471 */ 5472 intel_dp->aux.i2c_nack_count = 0; 5473 intel_dp->aux.i2c_defer_count = 0; 5474 5475 intel_dp_set_edid(intel_dp); 5476 if (intel_dp_is_edp(intel_dp) || 5477 to_intel_connector(connector)->detect_edid) 5478 status = connector_status_connected; 5479 5480 intel_dp_check_device_service_irq(intel_dp); 5481 5482 out: 5483 if (status != connector_status_connected && !intel_dp->is_mst) 5484 intel_dp_unset_edid(intel_dp); 5485 5486 if (!intel_dp_is_edp(intel_dp)) 5487 drm_dp_set_subconnector_property(connector, 5488 status, 5489 intel_dp->dpcd, 5490 intel_dp->downstream_ports); 5491 return status; 5492 } 5493 5494 static void 5495 intel_dp_force(struct drm_connector *connector) 5496 { 5497 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 5498 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5499 struct intel_encoder *intel_encoder = &dig_port->base; 5500 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 5501 5502 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 5503 connector->base.id, connector->name); 5504 intel_dp_unset_edid(intel_dp); 5505 5506 if (connector->status != connector_status_connected) 5507 return; 5508 5509 intel_dp_set_edid(intel_dp); 5510 } 5511 5512 static int intel_dp_get_modes(struct drm_connector *connector) 5513 { 5514 struct intel_connector *intel_connector = to_intel_connector(connector); 5515 int num_modes; 5516 5517 /* drm_edid_connector_update() done in ->detect() or ->force() */ 5518 num_modes = drm_edid_connector_add_modes(connector); 5519 5520 /* Also add fixed mode, which may or may not be present in EDID */ 5521 if (intel_dp_is_edp(intel_attached_dp(intel_connector))) 5522 num_modes += intel_panel_get_modes(intel_connector); 5523 5524 if (num_modes) 5525 return num_modes; 5526 5527 if (!intel_connector->detect_edid) { 5528 struct intel_dp *intel_dp = intel_attached_dp(intel_connector); 5529 struct drm_display_mode *mode; 5530 5531 mode = drm_dp_downstream_mode(connector->dev, 5532 intel_dp->dpcd, 5533 intel_dp->downstream_ports); 5534 if (mode) { 5535 drm_mode_probed_add(connector, mode); 5536 num_modes++; 5537 } 5538 } 5539 5540 return num_modes; 5541 } 5542 5543 static int 5544 intel_dp_connector_register(struct drm_connector *connector) 5545 { 5546 struct drm_i915_private *i915 = to_i915(connector->dev); 5547 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 5548 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5549 struct intel_lspcon *lspcon = &dig_port->lspcon; 5550 int ret; 5551 5552 ret = intel_connector_register(connector); 5553 if (ret) 5554 return ret; 5555 5556 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n", 5557 intel_dp->aux.name, connector->kdev->kobj.name); 5558 5559 intel_dp->aux.dev = connector->kdev; 5560 ret = drm_dp_aux_register(&intel_dp->aux); 5561 if (!ret) 5562 drm_dp_cec_register_connector(&intel_dp->aux, connector); 5563 5564 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata)) 5565 return ret; 5566 5567 /* 5568 * ToDo: Clean this up to handle lspcon init and resume more 5569 * efficiently and streamlined. 5570 */ 5571 if (lspcon_init(dig_port)) { 5572 lspcon_detect_hdr_capability(lspcon); 5573 if (lspcon->hdr_supported) 5574 drm_connector_attach_hdr_output_metadata_property(connector); 5575 } 5576 5577 return ret; 5578 } 5579 5580 static void 5581 intel_dp_connector_unregister(struct drm_connector *connector) 5582 { 5583 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 5584 5585 drm_dp_cec_unregister_connector(&intel_dp->aux); 5586 drm_dp_aux_unregister(&intel_dp->aux); 5587 intel_connector_unregister(connector); 5588 } 5589 5590 void intel_dp_encoder_flush_work(struct drm_encoder *encoder) 5591 { 5592 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 5593 struct intel_dp *intel_dp = &dig_port->dp; 5594 5595 intel_dp_mst_encoder_cleanup(dig_port); 5596 5597 intel_pps_vdd_off_sync(intel_dp); 5598 5599 /* 5600 * Ensure power off delay is respected on module remove, so that we can 5601 * reduce delays at driver probe. See pps_init_timestamps(). 5602 */ 5603 intel_pps_wait_power_cycle(intel_dp); 5604 5605 intel_dp_aux_fini(intel_dp); 5606 } 5607 5608 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) 5609 { 5610 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 5611 5612 intel_pps_vdd_off_sync(intel_dp); 5613 } 5614 5615 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder) 5616 { 5617 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 5618 5619 intel_pps_wait_power_cycle(intel_dp); 5620 } 5621 5622 static int intel_modeset_tile_group(struct intel_atomic_state *state, 5623 int tile_group_id) 5624 { 5625 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5626 struct drm_connector_list_iter conn_iter; 5627 struct drm_connector *connector; 5628 int ret = 0; 5629 5630 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 5631 drm_for_each_connector_iter(connector, &conn_iter) { 5632 struct drm_connector_state *conn_state; 5633 struct intel_crtc_state *crtc_state; 5634 struct intel_crtc *crtc; 5635 5636 if (!connector->has_tile || 5637 connector->tile_group->id != tile_group_id) 5638 continue; 5639 5640 conn_state = drm_atomic_get_connector_state(&state->base, 5641 connector); 5642 if (IS_ERR(conn_state)) { 5643 ret = PTR_ERR(conn_state); 5644 break; 5645 } 5646 5647 crtc = to_intel_crtc(conn_state->crtc); 5648 5649 if (!crtc) 5650 continue; 5651 5652 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 5653 crtc_state->uapi.mode_changed = true; 5654 5655 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 5656 if (ret) 5657 break; 5658 } 5659 drm_connector_list_iter_end(&conn_iter); 5660 5661 return ret; 5662 } 5663 5664 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) 5665 { 5666 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 5667 struct intel_crtc *crtc; 5668 5669 if (transcoders == 0) 5670 return 0; 5671 5672 for_each_intel_crtc(&dev_priv->drm, crtc) { 5673 struct intel_crtc_state *crtc_state; 5674 int ret; 5675 5676 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5677 if (IS_ERR(crtc_state)) 5678 return PTR_ERR(crtc_state); 5679 5680 if (!crtc_state->hw.enable) 5681 continue; 5682 5683 if (!(transcoders & BIT(crtc_state->cpu_transcoder))) 5684 continue; 5685 5686 crtc_state->uapi.mode_changed = true; 5687 5688 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 5689 if (ret) 5690 return ret; 5691 5692 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 5693 if (ret) 5694 return ret; 5695 5696 transcoders &= ~BIT(crtc_state->cpu_transcoder); 5697 } 5698 5699 drm_WARN_ON(&dev_priv->drm, transcoders != 0); 5700 5701 return 0; 5702 } 5703 5704 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, 5705 struct drm_connector *connector) 5706 { 5707 const struct drm_connector_state *old_conn_state = 5708 drm_atomic_get_old_connector_state(&state->base, connector); 5709 const struct intel_crtc_state *old_crtc_state; 5710 struct intel_crtc *crtc; 5711 u8 transcoders; 5712 5713 crtc = to_intel_crtc(old_conn_state->crtc); 5714 if (!crtc) 5715 return 0; 5716 5717 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 5718 5719 if (!old_crtc_state->hw.active) 5720 return 0; 5721 5722 transcoders = old_crtc_state->sync_mode_slaves_mask; 5723 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) 5724 transcoders |= BIT(old_crtc_state->master_transcoder); 5725 5726 return intel_modeset_affected_transcoders(state, 5727 transcoders); 5728 } 5729 5730 static int intel_dp_connector_atomic_check(struct drm_connector *conn, 5731 struct drm_atomic_state *_state) 5732 { 5733 struct drm_i915_private *dev_priv = to_i915(conn->dev); 5734 struct intel_atomic_state *state = to_intel_atomic_state(_state); 5735 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn); 5736 struct intel_connector *intel_conn = to_intel_connector(conn); 5737 struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder); 5738 int ret; 5739 5740 ret = intel_digital_connector_atomic_check(conn, &state->base); 5741 if (ret) 5742 return ret; 5743 5744 if (intel_dp_mst_source_support(intel_dp)) { 5745 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr); 5746 if (ret) 5747 return ret; 5748 } 5749 5750 /* 5751 * We don't enable port sync on BDW due to missing w/as and 5752 * due to not having adjusted the modeset sequence appropriately. 5753 */ 5754 if (DISPLAY_VER(dev_priv) < 9) 5755 return 0; 5756 5757 if (!intel_connector_needs_modeset(state, conn)) 5758 return 0; 5759 5760 if (conn->has_tile) { 5761 ret = intel_modeset_tile_group(state, conn->tile_group->id); 5762 if (ret) 5763 return ret; 5764 } 5765 5766 return intel_modeset_synced_crtcs(state, conn); 5767 } 5768 5769 static void intel_dp_oob_hotplug_event(struct drm_connector *connector, 5770 enum drm_connector_status hpd_state) 5771 { 5772 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 5773 struct drm_i915_private *i915 = to_i915(connector->dev); 5774 bool hpd_high = hpd_state == connector_status_connected; 5775 unsigned int hpd_pin = encoder->hpd_pin; 5776 bool need_work = false; 5777 5778 spin_lock_irq(&i915->irq_lock); 5779 if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) { 5780 i915->display.hotplug.event_bits |= BIT(hpd_pin); 5781 5782 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high); 5783 need_work = true; 5784 } 5785 spin_unlock_irq(&i915->irq_lock); 5786 5787 if (need_work) 5788 queue_delayed_work(i915->unordered_wq, &i915->display.hotplug.hotplug_work, 0); 5789 } 5790 5791 static const struct drm_connector_funcs intel_dp_connector_funcs = { 5792 .force = intel_dp_force, 5793 .fill_modes = drm_helper_probe_single_connector_modes, 5794 .atomic_get_property = intel_digital_connector_atomic_get_property, 5795 .atomic_set_property = intel_digital_connector_atomic_set_property, 5796 .late_register = intel_dp_connector_register, 5797 .early_unregister = intel_dp_connector_unregister, 5798 .destroy = intel_connector_destroy, 5799 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 5800 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 5801 .oob_hotplug_event = intel_dp_oob_hotplug_event, 5802 }; 5803 5804 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 5805 .detect_ctx = intel_dp_detect, 5806 .get_modes = intel_dp_get_modes, 5807 .mode_valid = intel_dp_mode_valid, 5808 .atomic_check = intel_dp_connector_atomic_check, 5809 }; 5810 5811 enum irqreturn 5812 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) 5813 { 5814 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 5815 struct intel_dp *intel_dp = &dig_port->dp; 5816 5817 if (dig_port->base.type == INTEL_OUTPUT_EDP && 5818 (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) { 5819 /* 5820 * vdd off can generate a long/short pulse on eDP which 5821 * would require vdd on to handle it, and thus we 5822 * would end up in an endless cycle of 5823 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." 5824 */ 5825 drm_dbg_kms(&i915->drm, 5826 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", 5827 long_hpd ? "long" : "short", 5828 dig_port->base.base.base.id, 5829 dig_port->base.base.name); 5830 return IRQ_HANDLED; 5831 } 5832 5833 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", 5834 dig_port->base.base.base.id, 5835 dig_port->base.base.name, 5836 long_hpd ? "long" : "short"); 5837 5838 if (long_hpd) { 5839 intel_dp->reset_link_params = true; 5840 return IRQ_NONE; 5841 } 5842 5843 if (intel_dp->is_mst) { 5844 if (!intel_dp_check_mst_status(intel_dp)) 5845 return IRQ_NONE; 5846 } else if (!intel_dp_short_pulse(intel_dp)) { 5847 return IRQ_NONE; 5848 } 5849 5850 return IRQ_HANDLED; 5851 } 5852 5853 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv, 5854 const struct intel_bios_encoder_data *devdata, 5855 enum port port) 5856 { 5857 /* 5858 * eDP not supported on g4x. so bail out early just 5859 * for a bit extra safety in case the VBT is bonkers. 5860 */ 5861 if (DISPLAY_VER(dev_priv) < 5) 5862 return false; 5863 5864 if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A) 5865 return true; 5866 5867 return devdata && intel_bios_encoder_supports_edp(devdata); 5868 } 5869 5870 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port) 5871 { 5872 const struct intel_bios_encoder_data *devdata = 5873 intel_bios_encoder_data_lookup(i915, port); 5874 5875 return _intel_dp_is_port_edp(i915, devdata, port); 5876 } 5877 5878 static bool 5879 has_gamut_metadata_dip(struct intel_encoder *encoder) 5880 { 5881 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 5882 enum port port = encoder->port; 5883 5884 if (intel_bios_encoder_is_lspcon(encoder->devdata)) 5885 return false; 5886 5887 if (DISPLAY_VER(i915) >= 11) 5888 return true; 5889 5890 if (port == PORT_A) 5891 return false; 5892 5893 if (IS_HASWELL(i915) || IS_BROADWELL(i915) || 5894 DISPLAY_VER(i915) >= 9) 5895 return true; 5896 5897 return false; 5898 } 5899 5900 static void 5901 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 5902 { 5903 struct drm_i915_private *dev_priv = to_i915(connector->dev); 5904 enum port port = dp_to_dig_port(intel_dp)->base.port; 5905 5906 if (!intel_dp_is_edp(intel_dp)) 5907 drm_connector_attach_dp_subconnector_property(connector); 5908 5909 if (!IS_G4X(dev_priv) && port != PORT_A) 5910 intel_attach_force_audio_property(connector); 5911 5912 intel_attach_broadcast_rgb_property(connector); 5913 if (HAS_GMCH(dev_priv)) 5914 drm_connector_attach_max_bpc_property(connector, 6, 10); 5915 else if (DISPLAY_VER(dev_priv) >= 5) 5916 drm_connector_attach_max_bpc_property(connector, 6, 12); 5917 5918 /* Register HDMI colorspace for case of lspcon */ 5919 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) { 5920 drm_connector_attach_content_type_property(connector); 5921 intel_attach_hdmi_colorspace_property(connector); 5922 } else { 5923 intel_attach_dp_colorspace_property(connector); 5924 } 5925 5926 if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) 5927 drm_connector_attach_hdr_output_metadata_property(connector); 5928 5929 if (HAS_VRR(dev_priv)) 5930 drm_connector_attach_vrr_capable_property(connector); 5931 } 5932 5933 static void 5934 intel_edp_add_properties(struct intel_dp *intel_dp) 5935 { 5936 struct intel_connector *connector = intel_dp->attached_connector; 5937 struct drm_i915_private *i915 = to_i915(connector->base.dev); 5938 const struct drm_display_mode *fixed_mode = 5939 intel_panel_preferred_fixed_mode(connector); 5940 5941 intel_attach_scaling_mode_property(&connector->base); 5942 5943 drm_connector_set_panel_orientation_with_quirk(&connector->base, 5944 i915->display.vbt.orientation, 5945 fixed_mode->hdisplay, 5946 fixed_mode->vdisplay); 5947 } 5948 5949 static void intel_edp_backlight_setup(struct intel_dp *intel_dp, 5950 struct intel_connector *connector) 5951 { 5952 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5953 enum pipe pipe = INVALID_PIPE; 5954 5955 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 5956 /* 5957 * Figure out the current pipe for the initial backlight setup. 5958 * If the current pipe isn't valid, try the PPS pipe, and if that 5959 * fails just assume pipe A. 5960 */ 5961 pipe = vlv_active_pipe(intel_dp); 5962 5963 if (pipe != PIPE_A && pipe != PIPE_B) 5964 pipe = intel_dp->pps.pps_pipe; 5965 5966 if (pipe != PIPE_A && pipe != PIPE_B) 5967 pipe = PIPE_A; 5968 } 5969 5970 intel_backlight_setup(connector, pipe); 5971 } 5972 5973 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 5974 struct intel_connector *intel_connector) 5975 { 5976 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 5977 struct drm_connector *connector = &intel_connector->base; 5978 struct drm_display_mode *fixed_mode; 5979 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 5980 bool has_dpcd; 5981 const struct drm_edid *drm_edid; 5982 5983 if (!intel_dp_is_edp(intel_dp)) 5984 return true; 5985 5986 /* 5987 * On IBX/CPT we may get here with LVDS already registered. Since the 5988 * driver uses the only internal power sequencer available for both 5989 * eDP and LVDS bail out early in this case to prevent interfering 5990 * with an already powered-on LVDS power sequencer. 5991 */ 5992 if (intel_get_lvds_encoder(dev_priv)) { 5993 drm_WARN_ON(&dev_priv->drm, 5994 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 5995 drm_info(&dev_priv->drm, 5996 "LVDS was detected, not registering eDP\n"); 5997 5998 return false; 5999 } 6000 6001 intel_bios_init_panel_early(dev_priv, &intel_connector->panel, 6002 encoder->devdata); 6003 6004 if (!intel_pps_init(intel_dp)) { 6005 drm_info(&dev_priv->drm, 6006 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n", 6007 encoder->base.base.id, encoder->base.name); 6008 /* 6009 * The BIOS may have still enabled VDD on the PPS even 6010 * though it's unusable. Make sure we turn it back off 6011 * and to release the power domain references/etc. 6012 */ 6013 goto out_vdd_off; 6014 } 6015 6016 /* 6017 * Enable HPD sense for live status check. 6018 * intel_hpd_irq_setup() will turn it off again 6019 * if it's no longer needed later. 6020 * 6021 * The DPCD probe below will make sure VDD is on. 6022 */ 6023 intel_hpd_enable_detection(encoder); 6024 6025 /* Cache DPCD and EDID for edp. */ 6026 has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector); 6027 6028 if (!has_dpcd) { 6029 /* if this fails, presume the device is a ghost */ 6030 drm_info(&dev_priv->drm, 6031 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n", 6032 encoder->base.base.id, encoder->base.name); 6033 goto out_vdd_off; 6034 } 6035 6036 /* 6037 * VBT and straps are liars. Also check HPD as that seems 6038 * to be the most reliable piece of information available. 6039 * 6040 * ... expect on devices that forgot to hook HPD up for eDP 6041 * (eg. Acer Chromebook C710), so we'll check it only if multiple 6042 * ports are attempting to use the same AUX CH, according to VBT. 6043 */ 6044 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) { 6045 /* 6046 * If this fails, presume the DPCD answer came 6047 * from some other port using the same AUX CH. 6048 * 6049 * FIXME maybe cleaner to check this before the 6050 * DPCD read? Would need sort out the VDD handling... 6051 */ 6052 if (!intel_digital_port_connected(encoder)) { 6053 drm_info(&dev_priv->drm, 6054 "[ENCODER:%d:%s] HPD is down, disabling eDP\n", 6055 encoder->base.base.id, encoder->base.name); 6056 goto out_vdd_off; 6057 } 6058 6059 /* 6060 * Unfortunately even the HPD based detection fails on 6061 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall 6062 * back to checking for a VGA branch device. Only do this 6063 * on known affected platforms to minimize false positives. 6064 */ 6065 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) && 6066 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) == 6067 DP_DWN_STRM_PORT_TYPE_ANALOG) { 6068 drm_info(&dev_priv->drm, 6069 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n", 6070 encoder->base.base.id, encoder->base.name); 6071 goto out_vdd_off; 6072 } 6073 } 6074 6075 mutex_lock(&dev_priv->drm.mode_config.mutex); 6076 drm_edid = drm_edid_read_ddc(connector, connector->ddc); 6077 if (!drm_edid) { 6078 /* Fallback to EDID from ACPI OpRegion, if any */ 6079 drm_edid = intel_opregion_get_edid(intel_connector); 6080 if (drm_edid) 6081 drm_dbg_kms(&dev_priv->drm, 6082 "[CONNECTOR:%d:%s] Using OpRegion EDID\n", 6083 connector->base.id, connector->name); 6084 } 6085 if (drm_edid) { 6086 if (drm_edid_connector_update(connector, drm_edid) || 6087 !drm_edid_connector_add_modes(connector)) { 6088 drm_edid_connector_update(connector, NULL); 6089 drm_edid_free(drm_edid); 6090 drm_edid = ERR_PTR(-EINVAL); 6091 } 6092 } else { 6093 drm_edid = ERR_PTR(-ENOENT); 6094 } 6095 6096 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, 6097 IS_ERR(drm_edid) ? NULL : drm_edid); 6098 6099 intel_panel_add_edid_fixed_modes(intel_connector, true); 6100 6101 /* MSO requires information from the EDID */ 6102 intel_edp_mso_init(intel_dp); 6103 6104 /* multiply the mode clock and horizontal timings for MSO */ 6105 list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head) 6106 intel_edp_mso_mode_fixup(intel_connector, fixed_mode); 6107 6108 /* fallback to VBT if available for eDP */ 6109 if (!intel_panel_preferred_fixed_mode(intel_connector)) 6110 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 6111 6112 mutex_unlock(&dev_priv->drm.mode_config.mutex); 6113 6114 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 6115 drm_info(&dev_priv->drm, 6116 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n", 6117 encoder->base.base.id, encoder->base.name); 6118 goto out_vdd_off; 6119 } 6120 6121 intel_panel_init(intel_connector, drm_edid); 6122 6123 intel_edp_backlight_setup(intel_dp, intel_connector); 6124 6125 intel_edp_add_properties(intel_dp); 6126 6127 intel_pps_init_late(intel_dp); 6128 6129 return true; 6130 6131 out_vdd_off: 6132 intel_pps_vdd_off_sync(intel_dp); 6133 6134 return false; 6135 } 6136 6137 static void intel_dp_modeset_retry_work_fn(struct work_struct *work) 6138 { 6139 struct intel_connector *intel_connector; 6140 struct drm_connector *connector; 6141 6142 intel_connector = container_of(work, typeof(*intel_connector), 6143 modeset_retry_work); 6144 connector = &intel_connector->base; 6145 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id, 6146 connector->name); 6147 6148 /* Grab the locks before changing connector property*/ 6149 mutex_lock(&connector->dev->mode_config.mutex); 6150 /* Set connector link status to BAD and send a Uevent to notify 6151 * userspace to do a modeset. 6152 */ 6153 drm_connector_set_link_status_property(connector, 6154 DRM_MODE_LINK_STATUS_BAD); 6155 mutex_unlock(&connector->dev->mode_config.mutex); 6156 /* Send Hotplug uevent so userspace can reprobe */ 6157 drm_kms_helper_connector_hotplug_event(connector); 6158 } 6159 6160 bool 6161 intel_dp_init_connector(struct intel_digital_port *dig_port, 6162 struct intel_connector *intel_connector) 6163 { 6164 struct drm_connector *connector = &intel_connector->base; 6165 struct intel_dp *intel_dp = &dig_port->dp; 6166 struct intel_encoder *intel_encoder = &dig_port->base; 6167 struct drm_device *dev = intel_encoder->base.dev; 6168 struct drm_i915_private *dev_priv = to_i915(dev); 6169 enum port port = intel_encoder->port; 6170 enum phy phy = intel_port_to_phy(dev_priv, port); 6171 int type; 6172 6173 /* Initialize the work for modeset in case of link train failure */ 6174 INIT_WORK(&intel_connector->modeset_retry_work, 6175 intel_dp_modeset_retry_work_fn); 6176 6177 if (drm_WARN(dev, dig_port->max_lanes < 1, 6178 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", 6179 dig_port->max_lanes, intel_encoder->base.base.id, 6180 intel_encoder->base.name)) 6181 return false; 6182 6183 intel_dp->reset_link_params = true; 6184 intel_dp->pps.pps_pipe = INVALID_PIPE; 6185 intel_dp->pps.active_pipe = INVALID_PIPE; 6186 6187 /* Preserve the current hw state. */ 6188 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); 6189 intel_dp->attached_connector = intel_connector; 6190 6191 if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) { 6192 /* 6193 * Currently we don't support eDP on TypeC ports, although in 6194 * theory it could work on TypeC legacy ports. 6195 */ 6196 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy)); 6197 type = DRM_MODE_CONNECTOR_eDP; 6198 intel_encoder->type = INTEL_OUTPUT_EDP; 6199 6200 /* eDP only on port B and/or C on vlv/chv */ 6201 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) || 6202 IS_CHERRYVIEW(dev_priv)) && 6203 port != PORT_B && port != PORT_C)) 6204 return false; 6205 } else { 6206 type = DRM_MODE_CONNECTOR_DisplayPort; 6207 } 6208 6209 intel_dp_set_default_sink_rates(intel_dp); 6210 intel_dp_set_default_max_sink_lane_count(intel_dp); 6211 6212 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6213 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp); 6214 6215 intel_dp_aux_init(intel_dp); 6216 intel_connector->dp.dsc_decompression_aux = &intel_dp->aux; 6217 6218 drm_dbg_kms(&dev_priv->drm, 6219 "Adding %s connector on [ENCODER:%d:%s]\n", 6220 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 6221 intel_encoder->base.base.id, intel_encoder->base.name); 6222 6223 drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs, 6224 type, &intel_dp->aux.ddc); 6225 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 6226 6227 if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12) 6228 connector->interlace_allowed = true; 6229 6230 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 6231 6232 intel_connector_attach_encoder(intel_connector, intel_encoder); 6233 6234 if (HAS_DDI(dev_priv)) 6235 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 6236 else 6237 intel_connector->get_hw_state = intel_connector_get_hw_state; 6238 6239 if (!intel_edp_init_connector(intel_dp, intel_connector)) { 6240 intel_dp_aux_fini(intel_dp); 6241 goto fail; 6242 } 6243 6244 intel_dp_set_source_rates(intel_dp); 6245 intel_dp_set_common_rates(intel_dp); 6246 intel_dp_reset_max_link_params(intel_dp); 6247 6248 /* init MST on ports that can support it */ 6249 intel_dp_mst_encoder_init(dig_port, 6250 intel_connector->base.base.id); 6251 6252 intel_dp_add_properties(intel_dp, connector); 6253 6254 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { 6255 int ret = intel_dp_hdcp_init(dig_port, intel_connector); 6256 if (ret) 6257 drm_dbg_kms(&dev_priv->drm, 6258 "HDCP init failed, skipping.\n"); 6259 } 6260 6261 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 6262 * 0xd. Failure to do so will result in spurious interrupts being 6263 * generated on the port when a cable is not attached. 6264 */ 6265 if (IS_G45(dev_priv)) { 6266 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 6267 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 6268 (temp & ~0xf) | 0xd); 6269 } 6270 6271 intel_dp->frl.is_trained = false; 6272 intel_dp->frl.trained_rate_gbps = 0; 6273 6274 intel_psr_init(intel_dp); 6275 6276 return true; 6277 6278 fail: 6279 intel_display_power_flush_work(dev_priv); 6280 drm_connector_cleanup(connector); 6281 6282 return false; 6283 } 6284 6285 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) 6286 { 6287 struct intel_encoder *encoder; 6288 6289 if (!HAS_DISPLAY(dev_priv)) 6290 return; 6291 6292 for_each_intel_encoder(&dev_priv->drm, encoder) { 6293 struct intel_dp *intel_dp; 6294 6295 if (encoder->type != INTEL_OUTPUT_DDI) 6296 continue; 6297 6298 intel_dp = enc_to_intel_dp(encoder); 6299 6300 if (!intel_dp_mst_source_support(intel_dp)) 6301 continue; 6302 6303 if (intel_dp->is_mst) 6304 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); 6305 } 6306 } 6307 6308 void intel_dp_mst_resume(struct drm_i915_private *dev_priv) 6309 { 6310 struct intel_encoder *encoder; 6311 6312 if (!HAS_DISPLAY(dev_priv)) 6313 return; 6314 6315 for_each_intel_encoder(&dev_priv->drm, encoder) { 6316 struct intel_dp *intel_dp; 6317 int ret; 6318 6319 if (encoder->type != INTEL_OUTPUT_DDI) 6320 continue; 6321 6322 intel_dp = enc_to_intel_dp(encoder); 6323 6324 if (!intel_dp_mst_source_support(intel_dp)) 6325 continue; 6326 6327 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, 6328 true); 6329 if (ret) { 6330 intel_dp->is_mst = false; 6331 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 6332 false); 6333 } 6334 } 6335 } 6336