1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2020 Google, Inc. 4 * 5 * Authors: 6 * Sean Paul <seanpaul@chromium.org> 7 */ 8 9 #include <drm/display/drm_dp_helper.h> 10 #include <drm/display/drm_dp_mst_helper.h> 11 #include <drm/display/drm_hdcp_helper.h> 12 #include <drm/drm_print.h> 13 14 #include "i915_reg.h" 15 #include "intel_ddi.h" 16 #include "intel_de.h" 17 #include "intel_display_types.h" 18 #include "intel_dp.h" 19 #include "intel_dp_hdcp.h" 20 #include "intel_hdcp.h" 21 #include "intel_hdcp_regs.h" 22 23 static u32 transcoder_to_stream_enc_status(enum transcoder cpu_transcoder) 24 { 25 switch (cpu_transcoder) { 26 case TRANSCODER_A: 27 return HDCP_STATUS_STREAM_A_ENC; 28 case TRANSCODER_B: 29 return HDCP_STATUS_STREAM_B_ENC; 30 case TRANSCODER_C: 31 return HDCP_STATUS_STREAM_C_ENC; 32 case TRANSCODER_D: 33 return HDCP_STATUS_STREAM_D_ENC; 34 default: 35 return 0; 36 } 37 } 38 39 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) 40 { 41 long ret; 42 43 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count)) 44 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, 45 msecs_to_jiffies(timeout)); 46 47 if (!ret) 48 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n"); 49 } 50 51 static 52 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 53 u8 *an) 54 { 55 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 56 u8 aksv[DRM_HDCP_KSV_LEN] = {}; 57 ssize_t dpcd_ret; 58 59 /* Output An first, that's easy */ 60 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN, 61 an, DRM_HDCP_AN_LEN); 62 if (dpcd_ret != DRM_HDCP_AN_LEN) { 63 drm_dbg_kms(&i915->drm, 64 "Failed to write An over DP/AUX (%zd)\n", 65 dpcd_ret); 66 return dpcd_ret >= 0 ? -EIO : dpcd_ret; 67 } 68 69 /* 70 * Since Aksv is Oh-So-Secret, we can't access it in software. So we 71 * send an empty buffer of the correct length through the DP helpers. On 72 * the other side, in the transfer hook, we'll generate a flag based on 73 * the destination address which will tickle the hardware to output the 74 * Aksv on our behalf after the header is sent. 75 */ 76 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV, 77 aksv, DRM_HDCP_KSV_LEN); 78 if (dpcd_ret != DRM_HDCP_KSV_LEN) { 79 drm_dbg_kms(&i915->drm, 80 "Failed to write Aksv over DP/AUX (%zd)\n", 81 dpcd_ret); 82 return dpcd_ret >= 0 ? -EIO : dpcd_ret; 83 } 84 return 0; 85 } 86 87 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port, 88 u8 *bksv) 89 { 90 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 91 ssize_t ret; 92 93 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, 94 DRM_HDCP_KSV_LEN); 95 if (ret != DRM_HDCP_KSV_LEN) { 96 drm_dbg_kms(&i915->drm, 97 "Read Bksv from DP/AUX failed (%zd)\n", ret); 98 return ret >= 0 ? -EIO : ret; 99 } 100 return 0; 101 } 102 103 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port, 104 u8 *bstatus) 105 { 106 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 107 ssize_t ret; 108 109 /* 110 * For some reason the HDMI and DP HDCP specs call this register 111 * definition by different names. In the HDMI spec, it's called BSTATUS, 112 * but in DP it's called BINFO. 113 */ 114 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO, 115 bstatus, DRM_HDCP_BSTATUS_LEN); 116 if (ret != DRM_HDCP_BSTATUS_LEN) { 117 drm_dbg_kms(&i915->drm, 118 "Read bstatus from DP/AUX failed (%zd)\n", ret); 119 return ret >= 0 ? -EIO : ret; 120 } 121 return 0; 122 } 123 124 static 125 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port, 126 u8 *bcaps) 127 { 128 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 129 ssize_t ret; 130 131 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS, 132 bcaps, 1); 133 if (ret != 1) { 134 drm_dbg_kms(&i915->drm, 135 "Read bcaps from DP/AUX failed (%zd)\n", ret); 136 return ret >= 0 ? -EIO : ret; 137 } 138 139 return 0; 140 } 141 142 static 143 int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port, 144 bool *repeater_present) 145 { 146 ssize_t ret; 147 u8 bcaps; 148 149 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); 150 if (ret) 151 return ret; 152 153 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; 154 return 0; 155 } 156 157 static 158 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 159 u8 *ri_prime) 160 { 161 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 162 ssize_t ret; 163 164 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, 165 ri_prime, DRM_HDCP_RI_LEN); 166 if (ret != DRM_HDCP_RI_LEN) { 167 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n", 168 ret); 169 return ret >= 0 ? -EIO : ret; 170 } 171 return 0; 172 } 173 174 static 175 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 176 bool *ksv_ready) 177 { 178 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 179 ssize_t ret; 180 u8 bstatus; 181 182 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 183 &bstatus, 1); 184 if (ret != 1) { 185 drm_dbg_kms(&i915->drm, 186 "Read bstatus from DP/AUX failed (%zd)\n", ret); 187 return ret >= 0 ? -EIO : ret; 188 } 189 *ksv_ready = bstatus & DP_BSTATUS_READY; 190 return 0; 191 } 192 193 static 194 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 195 int num_downstream, u8 *ksv_fifo) 196 { 197 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 198 ssize_t ret; 199 int i; 200 201 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ 202 for (i = 0; i < num_downstream; i += 3) { 203 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; 204 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 205 DP_AUX_HDCP_KSV_FIFO, 206 ksv_fifo + i * DRM_HDCP_KSV_LEN, 207 len); 208 if (ret != len) { 209 drm_dbg_kms(&i915->drm, 210 "Read ksv[%d] from DP/AUX failed (%zd)\n", 211 i, ret); 212 return ret >= 0 ? -EIO : ret; 213 } 214 } 215 return 0; 216 } 217 218 static 219 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 220 int i, u32 *part) 221 { 222 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 223 ssize_t ret; 224 225 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 226 return -EINVAL; 227 228 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 229 DP_AUX_HDCP_V_PRIME(i), part, 230 DRM_HDCP_V_PRIME_PART_LEN); 231 if (ret != DRM_HDCP_V_PRIME_PART_LEN) { 232 drm_dbg_kms(&i915->drm, 233 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); 234 return ret >= 0 ? -EIO : ret; 235 } 236 return 0; 237 } 238 239 static 240 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 241 enum transcoder cpu_transcoder, 242 bool enable) 243 { 244 /* Not used for single stream DisplayPort setups */ 245 return 0; 246 } 247 248 static 249 bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port, 250 struct intel_connector *connector) 251 { 252 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 253 ssize_t ret; 254 u8 bstatus; 255 256 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 257 &bstatus, 1); 258 if (ret != 1) { 259 drm_dbg_kms(&i915->drm, 260 "Read bstatus from DP/AUX failed (%zd)\n", ret); 261 return false; 262 } 263 264 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); 265 } 266 267 static 268 int intel_dp_hdcp_capable(struct intel_digital_port *dig_port, 269 bool *hdcp_capable) 270 { 271 ssize_t ret; 272 u8 bcaps; 273 274 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); 275 if (ret) 276 return ret; 277 278 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; 279 return 0; 280 } 281 282 struct hdcp2_dp_errata_stream_type { 283 u8 msg_id; 284 u8 stream_type; 285 } __packed; 286 287 struct hdcp2_dp_msg_data { 288 u8 msg_id; 289 u32 offset; 290 bool msg_detectable; 291 u32 timeout; 292 u32 timeout2; /* Added for non_paired situation */ 293 /* Timeout to read entire msg */ 294 u32 msg_read_timeout; 295 }; 296 297 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { 298 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0}, 299 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, 300 false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS}, 301 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, 302 false, 0, 0, 0 }, 303 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, 304 false, 0, 0, 0 }, 305 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, 306 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, 307 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS, HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS}, 308 { HDCP_2_2_AKE_SEND_PAIRING_INFO, 309 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, 310 HDCP_2_2_PAIRING_TIMEOUT_MS, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS }, 311 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 }, 312 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, 313 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 }, 314 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, 315 0, 0, 0 }, 316 { HDCP_2_2_REP_SEND_RECVID_LIST, 317 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, 318 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0, 0 }, 319 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, 320 0, 0, 0 }, 321 { HDCP_2_2_REP_STREAM_MANAGE, 322 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, 323 0, 0, 0}, 324 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, 325 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 }, 326 /* local define to shovel this through the write_2_2 interface */ 327 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 328 { HDCP_2_2_ERRATA_DP_STREAM_TYPE, 329 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, 330 0, 0 }, 331 }; 332 333 static struct drm_dp_aux * 334 intel_dp_hdcp_get_aux(struct intel_connector *connector) 335 { 336 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 337 338 if (intel_encoder_is_mst(connector->encoder)) 339 return &connector->port->aux; 340 else 341 return &dig_port->dp.aux; 342 } 343 344 static int 345 intel_dp_hdcp2_read_rx_status(struct intel_connector *connector, 346 u8 *rx_status) 347 { 348 struct drm_i915_private *i915 = to_i915(connector->base.dev); 349 struct drm_dp_aux *aux = intel_dp_hdcp_get_aux(connector); 350 ssize_t ret; 351 352 ret = drm_dp_dpcd_read(aux, 353 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, 354 HDCP_2_2_DP_RXSTATUS_LEN); 355 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { 356 drm_dbg_kms(&i915->drm, 357 "Read bstatus from DP/AUX failed (%zd)\n", ret); 358 return ret >= 0 ? -EIO : ret; 359 } 360 361 return 0; 362 } 363 364 static 365 int hdcp2_detect_msg_availability(struct intel_connector *connector, 366 u8 msg_id, bool *msg_ready) 367 { 368 u8 rx_status; 369 int ret; 370 371 *msg_ready = false; 372 ret = intel_dp_hdcp2_read_rx_status(connector, &rx_status); 373 if (ret < 0) 374 return ret; 375 376 switch (msg_id) { 377 case HDCP_2_2_AKE_SEND_HPRIME: 378 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) 379 *msg_ready = true; 380 break; 381 case HDCP_2_2_AKE_SEND_PAIRING_INFO: 382 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) 383 *msg_ready = true; 384 break; 385 case HDCP_2_2_REP_SEND_RECVID_LIST: 386 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 387 *msg_ready = true; 388 break; 389 default: 390 DRM_ERROR("Unidentified msg_id: %d\n", msg_id); 391 return -EINVAL; 392 } 393 394 return 0; 395 } 396 397 static ssize_t 398 intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector, 399 const struct hdcp2_dp_msg_data *hdcp2_msg_data) 400 { 401 struct drm_i915_private *i915 = to_i915(connector->base.dev); 402 struct intel_hdcp *hdcp = &connector->hdcp; 403 u8 msg_id = hdcp2_msg_data->msg_id; 404 int ret, timeout; 405 bool msg_ready = false; 406 407 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) 408 timeout = hdcp2_msg_data->timeout2; 409 else 410 timeout = hdcp2_msg_data->timeout; 411 412 /* 413 * There is no way to detect the CERT, LPRIME and STREAM_READY 414 * availability. So Wait for timeout and read the msg. 415 */ 416 if (!hdcp2_msg_data->msg_detectable) { 417 mdelay(timeout); 418 ret = 0; 419 } else { 420 /* 421 * As we want to check the msg availability at timeout, Ignoring 422 * the timeout at wait for CP_IRQ. 423 */ 424 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout); 425 ret = hdcp2_detect_msg_availability(connector, msg_id, 426 &msg_ready); 427 if (!msg_ready) 428 ret = -ETIMEDOUT; 429 } 430 431 if (ret) 432 drm_dbg_kms(&i915->drm, 433 "msg_id %d, ret %d, timeout(mSec): %d\n", 434 hdcp2_msg_data->msg_id, ret, timeout); 435 436 return ret; 437 } 438 439 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) 440 { 441 int i; 442 443 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++) 444 if (hdcp2_dp_msg_data[i].msg_id == msg_id) 445 return &hdcp2_dp_msg_data[i]; 446 447 return NULL; 448 } 449 450 static 451 int intel_dp_hdcp2_write_msg(struct intel_connector *connector, 452 void *buf, size_t size) 453 { 454 unsigned int offset; 455 u8 *byte = buf; 456 ssize_t ret, bytes_to_write, len; 457 const struct hdcp2_dp_msg_data *hdcp2_msg_data; 458 struct drm_dp_aux *aux; 459 460 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); 461 if (!hdcp2_msg_data) 462 return -EINVAL; 463 464 offset = hdcp2_msg_data->offset; 465 466 aux = intel_dp_hdcp_get_aux(connector); 467 468 /* No msg_id in DP HDCP2.2 msgs */ 469 bytes_to_write = size - 1; 470 byte++; 471 472 while (bytes_to_write) { 473 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? 474 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; 475 476 ret = drm_dp_dpcd_write(aux, 477 offset, (void *)byte, len); 478 if (ret < 0) 479 return ret; 480 481 bytes_to_write -= ret; 482 byte += ret; 483 offset += ret; 484 } 485 486 return size; 487 } 488 489 static 490 ssize_t get_receiver_id_list_rx_info(struct intel_connector *connector, 491 u32 *dev_cnt, u8 *byte) 492 { 493 struct drm_dp_aux *aux = intel_dp_hdcp_get_aux(connector); 494 ssize_t ret; 495 u8 *rx_info = byte; 496 497 ret = drm_dp_dpcd_read(aux, 498 DP_HDCP_2_2_REG_RXINFO_OFFSET, 499 (void *)rx_info, HDCP_2_2_RXINFO_LEN); 500 if (ret != HDCP_2_2_RXINFO_LEN) 501 return ret >= 0 ? -EIO : ret; 502 503 *dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 504 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 505 506 if (*dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) 507 *dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; 508 509 return ret; 510 } 511 512 static 513 int intel_dp_hdcp2_read_msg(struct intel_connector *connector, 514 u8 msg_id, void *buf, size_t size) 515 { 516 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 517 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 518 struct intel_hdcp *hdcp = &connector->hdcp; 519 struct drm_dp_aux *aux; 520 unsigned int offset; 521 u8 *byte = buf; 522 ssize_t ret, bytes_to_recv, len; 523 const struct hdcp2_dp_msg_data *hdcp2_msg_data; 524 ktime_t msg_end = ktime_set(0, 0); 525 bool msg_expired; 526 u32 dev_cnt; 527 528 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); 529 if (!hdcp2_msg_data) 530 return -EINVAL; 531 offset = hdcp2_msg_data->offset; 532 533 aux = intel_dp_hdcp_get_aux(connector); 534 535 ret = intel_dp_hdcp2_wait_for_msg(connector, hdcp2_msg_data); 536 if (ret < 0) 537 return ret; 538 539 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count); 540 541 /* DP adaptation msgs has no msg_id */ 542 byte++; 543 544 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { 545 ret = get_receiver_id_list_rx_info(connector, &dev_cnt, byte); 546 if (ret < 0) 547 return ret; 548 549 byte += ret; 550 size = sizeof(struct hdcp2_rep_send_receiverid_list) - 551 HDCP_2_2_RXINFO_LEN - HDCP_2_2_RECEIVER_IDS_MAX_LEN + 552 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); 553 offset += HDCP_2_2_RXINFO_LEN; 554 } 555 556 bytes_to_recv = size - 1; 557 558 while (bytes_to_recv) { 559 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? 560 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; 561 562 /* Entire msg read timeout since initiate of msg read */ 563 if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0) { 564 if (intel_encoder_is_mst(connector->encoder)) 565 msg_end = ktime_add_ms(ktime_get_raw(), 566 hdcp2_msg_data->msg_read_timeout * 567 connector->port->parent->num_ports); 568 else 569 msg_end = ktime_add_ms(ktime_get_raw(), 570 hdcp2_msg_data->msg_read_timeout); 571 } 572 573 ret = drm_dp_dpcd_read(aux, offset, 574 (void *)byte, len); 575 if (ret < 0) { 576 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n", 577 msg_id, ret); 578 return ret; 579 } 580 581 bytes_to_recv -= ret; 582 byte += ret; 583 offset += ret; 584 } 585 586 if (hdcp2_msg_data->msg_read_timeout > 0) { 587 msg_expired = ktime_after(ktime_get_raw(), msg_end); 588 if (msg_expired) { 589 drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n", 590 msg_id, hdcp2_msg_data->msg_read_timeout); 591 return -ETIMEDOUT; 592 } 593 } 594 595 byte = buf; 596 *byte = msg_id; 597 598 return size; 599 } 600 601 static 602 int intel_dp_hdcp2_config_stream_type(struct intel_connector *connector, 603 bool is_repeater, u8 content_type) 604 { 605 int ret; 606 struct hdcp2_dp_errata_stream_type stream_type_msg; 607 608 if (is_repeater) 609 return 0; 610 611 /* 612 * Errata for DP: As Stream type is used for encryption, Receiver 613 * should be communicated with stream type for the decryption of the 614 * content. 615 * Repeater will be communicated with stream type as a part of it's 616 * auth later in time. 617 */ 618 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; 619 stream_type_msg.stream_type = content_type; 620 621 ret = intel_dp_hdcp2_write_msg(connector, &stream_type_msg, 622 sizeof(stream_type_msg)); 623 624 return ret < 0 ? ret : 0; 625 626 } 627 628 static 629 int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port, 630 struct intel_connector *connector) 631 { 632 u8 rx_status; 633 int ret; 634 635 ret = intel_dp_hdcp2_read_rx_status(connector, 636 &rx_status); 637 if (ret) 638 return ret; 639 640 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) 641 ret = HDCP_REAUTH_REQUEST; 642 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) 643 ret = HDCP_LINK_INTEGRITY_FAILURE; 644 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 645 ret = HDCP_TOPOLOGY_CHANGE; 646 647 return ret; 648 } 649 650 static 651 int intel_dp_hdcp2_capable(struct intel_connector *connector, 652 bool *capable) 653 { 654 struct drm_dp_aux *aux; 655 u8 rx_caps[3]; 656 int ret; 657 658 aux = intel_dp_hdcp_get_aux(connector); 659 660 *capable = false; 661 ret = drm_dp_dpcd_read(aux, 662 DP_HDCP_2_2_REG_RX_CAPS_OFFSET, 663 rx_caps, HDCP_2_2_RXCAPS_LEN); 664 if (ret != HDCP_2_2_RXCAPS_LEN) 665 return ret >= 0 ? -EIO : ret; 666 667 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && 668 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) 669 *capable = true; 670 671 return 0; 672 } 673 674 static const struct intel_hdcp_shim intel_dp_hdcp_shim = { 675 .write_an_aksv = intel_dp_hdcp_write_an_aksv, 676 .read_bksv = intel_dp_hdcp_read_bksv, 677 .read_bstatus = intel_dp_hdcp_read_bstatus, 678 .repeater_present = intel_dp_hdcp_repeater_present, 679 .read_ri_prime = intel_dp_hdcp_read_ri_prime, 680 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 681 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 682 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 683 .toggle_signalling = intel_dp_hdcp_toggle_signalling, 684 .check_link = intel_dp_hdcp_check_link, 685 .hdcp_capable = intel_dp_hdcp_capable, 686 .write_2_2_msg = intel_dp_hdcp2_write_msg, 687 .read_2_2_msg = intel_dp_hdcp2_read_msg, 688 .config_stream_type = intel_dp_hdcp2_config_stream_type, 689 .check_2_2_link = intel_dp_hdcp2_check_link, 690 .hdcp_2_2_capable = intel_dp_hdcp2_capable, 691 .protocol = HDCP_PROTOCOL_DP, 692 }; 693 694 static int 695 intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector, 696 bool enable) 697 { 698 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 699 struct drm_i915_private *i915 = to_i915(connector->base.dev); 700 struct intel_hdcp *hdcp = &connector->hdcp; 701 int ret; 702 703 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 704 hdcp->stream_transcoder, enable, 705 TRANS_DDI_HDCP_SELECT); 706 if (ret) 707 drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n", 708 enable ? "Enable" : "Disable", ret); 709 return ret; 710 } 711 712 static int 713 intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector, 714 bool enable) 715 { 716 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 717 struct drm_i915_private *i915 = to_i915(connector->base.dev); 718 struct intel_hdcp *hdcp = &connector->hdcp; 719 enum port port = dig_port->base.port; 720 enum transcoder cpu_transcoder = hdcp->stream_transcoder; 721 u32 stream_enc_status; 722 int ret; 723 724 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); 725 if (ret) 726 return ret; 727 728 stream_enc_status = transcoder_to_stream_enc_status(cpu_transcoder); 729 if (!stream_enc_status) 730 return -EINVAL; 731 732 /* Wait for encryption confirmation */ 733 if (intel_de_wait_for_register(i915, 734 HDCP_STATUS(i915, cpu_transcoder, port), 735 stream_enc_status, 736 enable ? stream_enc_status : 0, 737 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 738 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", 739 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); 740 return -ETIMEDOUT; 741 } 742 743 return 0; 744 } 745 746 static int 747 intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector, 748 bool enable) 749 { 750 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 751 struct drm_i915_private *i915 = to_i915(connector->base.dev); 752 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 753 struct intel_hdcp *hdcp = &connector->hdcp; 754 enum transcoder cpu_transcoder = hdcp->stream_transcoder; 755 enum pipe pipe = (enum pipe)cpu_transcoder; 756 enum port port = dig_port->base.port; 757 int ret; 758 759 drm_WARN_ON(&i915->drm, enable && 760 !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port)) 761 & AUTH_STREAM_TYPE) != data->streams[0].stream_type); 762 763 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); 764 if (ret) 765 return ret; 766 767 /* Wait for encryption confirmation */ 768 if (intel_de_wait_for_register(i915, 769 HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe), 770 STREAM_ENCRYPTION_STATUS, 771 enable ? STREAM_ENCRYPTION_STATUS : 0, 772 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 773 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", 774 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); 775 return -ETIMEDOUT; 776 } 777 778 return 0; 779 } 780 781 static 782 int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port, 783 struct intel_connector *connector) 784 { 785 struct intel_hdcp *hdcp = &connector->hdcp; 786 int ret; 787 788 /* 789 * We do need to do the Link Check only for the connector involved with 790 * HDCP port authentication and encryption. 791 * We can re-use the hdcp->is_repeater flag to know that the connector 792 * involved with HDCP port authentication and encryption. 793 */ 794 if (hdcp->is_repeater) { 795 ret = intel_dp_hdcp2_check_link(dig_port, connector); 796 if (ret) 797 return ret; 798 } 799 800 return 0; 801 } 802 803 static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = { 804 .write_an_aksv = intel_dp_hdcp_write_an_aksv, 805 .read_bksv = intel_dp_hdcp_read_bksv, 806 .read_bstatus = intel_dp_hdcp_read_bstatus, 807 .repeater_present = intel_dp_hdcp_repeater_present, 808 .read_ri_prime = intel_dp_hdcp_read_ri_prime, 809 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 810 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 811 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 812 .toggle_signalling = intel_dp_hdcp_toggle_signalling, 813 .stream_encryption = intel_dp_mst_hdcp_stream_encryption, 814 .check_link = intel_dp_hdcp_check_link, 815 .hdcp_capable = intel_dp_hdcp_capable, 816 .write_2_2_msg = intel_dp_hdcp2_write_msg, 817 .read_2_2_msg = intel_dp_hdcp2_read_msg, 818 .config_stream_type = intel_dp_hdcp2_config_stream_type, 819 .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption, 820 .check_2_2_link = intel_dp_mst_hdcp2_check_link, 821 .hdcp_2_2_capable = intel_dp_hdcp2_capable, 822 .protocol = HDCP_PROTOCOL_DP, 823 }; 824 825 int intel_dp_hdcp_init(struct intel_digital_port *dig_port, 826 struct intel_connector *intel_connector) 827 { 828 struct drm_device *dev = intel_connector->base.dev; 829 struct drm_i915_private *dev_priv = to_i915(dev); 830 struct intel_encoder *intel_encoder = &dig_port->base; 831 enum port port = intel_encoder->port; 832 struct intel_dp *intel_dp = &dig_port->dp; 833 834 if (!is_hdcp_supported(dev_priv, port)) 835 return 0; 836 837 if (intel_connector->mst_port) 838 return intel_hdcp_init(intel_connector, dig_port, 839 &intel_dp_mst_hdcp_shim); 840 else if (!intel_dp_is_edp(intel_dp)) 841 return intel_hdcp_init(intel_connector, dig_port, 842 &intel_dp_hdcp_shim); 843 844 return 0; 845 } 846