1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/display/drm_hdcp_helper.h> 35 36 #include "i915_drv.h" 37 #include "i915_irq.h" 38 #include "i915_reg.h" 39 #include "intel_de.h" 40 #include "intel_display_types.h" 41 #include "intel_gmbus.h" 42 #include "intel_gmbus_regs.h" 43 44 struct intel_gmbus { 45 struct i2c_adapter adapter; 46 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 47 u32 force_bit; 48 u32 reg0; 49 i915_reg_t gpio_reg; 50 struct i2c_algo_bit_data bit_algo; 51 struct drm_i915_private *i915; 52 }; 53 54 enum gmbus_gpio { 55 GPIOA, 56 GPIOB, 57 GPIOC, 58 GPIOD, 59 GPIOE, 60 GPIOF, 61 GPIOG, 62 GPIOH, 63 __GPIOI_UNUSED, 64 GPIOJ, 65 GPIOK, 66 GPIOL, 67 GPIOM, 68 GPION, 69 GPIOO, 70 }; 71 72 struct gmbus_pin { 73 const char *name; 74 enum gmbus_gpio gpio; 75 }; 76 77 /* Map gmbus pin pairs to names and registers. */ 78 static const struct gmbus_pin gmbus_pins[] = { 79 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 80 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 81 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 82 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 83 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 84 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 85 }; 86 87 static const struct gmbus_pin gmbus_pins_bdw[] = { 88 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 89 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 90 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 91 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 92 }; 93 94 static const struct gmbus_pin gmbus_pins_skl[] = { 95 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 96 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 97 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 98 }; 99 100 static const struct gmbus_pin gmbus_pins_bxt[] = { 101 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 102 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 103 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 104 }; 105 106 static const struct gmbus_pin gmbus_pins_cnp[] = { 107 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 108 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 109 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 110 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 111 }; 112 113 static const struct gmbus_pin gmbus_pins_icp[] = { 114 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 115 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 116 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 117 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 118 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 119 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 120 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 121 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 122 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 123 }; 124 125 static const struct gmbus_pin gmbus_pins_dg1[] = { 126 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 127 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 128 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 129 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 130 }; 131 132 static const struct gmbus_pin gmbus_pins_dg2[] = { 133 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 134 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 135 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 136 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 137 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 138 }; 139 140 static const struct gmbus_pin gmbus_pins_mtp[] = { 141 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 142 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 143 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 144 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 145 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, 146 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 147 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 148 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 149 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 150 }; 151 152 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, 153 unsigned int pin) 154 { 155 const struct gmbus_pin *pins; 156 size_t size; 157 158 if (INTEL_PCH_TYPE(i915) >= PCH_LNL) { 159 pins = gmbus_pins_mtp; 160 size = ARRAY_SIZE(gmbus_pins_mtp); 161 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) { 162 pins = gmbus_pins_dg2; 163 size = ARRAY_SIZE(gmbus_pins_dg2); 164 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { 165 pins = gmbus_pins_dg1; 166 size = ARRAY_SIZE(gmbus_pins_dg1); 167 } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) { 168 pins = gmbus_pins_mtp; 169 size = ARRAY_SIZE(gmbus_pins_mtp); 170 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { 171 pins = gmbus_pins_icp; 172 size = ARRAY_SIZE(gmbus_pins_icp); 173 } else if (HAS_PCH_CNP(i915)) { 174 pins = gmbus_pins_cnp; 175 size = ARRAY_SIZE(gmbus_pins_cnp); 176 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 177 pins = gmbus_pins_bxt; 178 size = ARRAY_SIZE(gmbus_pins_bxt); 179 } else if (DISPLAY_VER(i915) == 9) { 180 pins = gmbus_pins_skl; 181 size = ARRAY_SIZE(gmbus_pins_skl); 182 } else if (IS_BROADWELL(i915)) { 183 pins = gmbus_pins_bdw; 184 size = ARRAY_SIZE(gmbus_pins_bdw); 185 } else { 186 pins = gmbus_pins; 187 size = ARRAY_SIZE(gmbus_pins); 188 } 189 190 if (pin >= size || !pins[pin].name) 191 return NULL; 192 193 return &pins[pin]; 194 } 195 196 bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin) 197 { 198 return get_gmbus_pin(i915, pin); 199 } 200 201 /* Intel GPIO access functions */ 202 203 #define I2C_RISEFALL_TIME 10 204 205 static inline struct intel_gmbus * 206 to_intel_gmbus(struct i2c_adapter *i2c) 207 { 208 return container_of(i2c, struct intel_gmbus, adapter); 209 } 210 211 void 212 intel_gmbus_reset(struct drm_i915_private *i915) 213 { 214 intel_de_write(i915, GMBUS0(i915), 0); 215 intel_de_write(i915, GMBUS4(i915), 0); 216 } 217 218 static void pnv_gmbus_clock_gating(struct drm_i915_private *i915, 219 bool enable) 220 { 221 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 222 intel_de_rmw(i915, DSPCLK_GATE_D(i915), PNV_GMBUSUNIT_CLOCK_GATE_DISABLE, 223 !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 224 } 225 226 static void pch_gmbus_clock_gating(struct drm_i915_private *i915, 227 bool enable) 228 { 229 intel_de_rmw(i915, SOUTH_DSPCLK_GATE_D, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 230 !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 231 } 232 233 static void bxt_gmbus_clock_gating(struct drm_i915_private *i915, 234 bool enable) 235 { 236 intel_de_rmw(i915, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS, 237 !enable ? BXT_GMBUS_GATING_DIS : 0); 238 } 239 240 static u32 get_reserved(struct intel_gmbus *bus) 241 { 242 struct drm_i915_private *i915 = bus->i915; 243 u32 reserved = 0; 244 245 /* On most chips, these bits must be preserved in software. */ 246 if (!IS_I830(i915) && !IS_I845G(i915)) 247 reserved = intel_de_read_notrace(i915, bus->gpio_reg) & 248 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); 249 250 return reserved; 251 } 252 253 static int get_clock(void *data) 254 { 255 struct intel_gmbus *bus = data; 256 struct drm_i915_private *i915 = bus->i915; 257 u32 reserved = get_reserved(bus); 258 259 intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 260 intel_de_write_notrace(i915, bus->gpio_reg, reserved); 261 262 return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 263 } 264 265 static int get_data(void *data) 266 { 267 struct intel_gmbus *bus = data; 268 struct drm_i915_private *i915 = bus->i915; 269 u32 reserved = get_reserved(bus); 270 271 intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 272 intel_de_write_notrace(i915, bus->gpio_reg, reserved); 273 274 return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 275 } 276 277 static void set_clock(void *data, int state_high) 278 { 279 struct intel_gmbus *bus = data; 280 struct drm_i915_private *i915 = bus->i915; 281 u32 reserved = get_reserved(bus); 282 u32 clock_bits; 283 284 if (state_high) 285 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 286 else 287 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 288 GPIO_CLOCK_VAL_MASK; 289 290 intel_de_write_notrace(i915, bus->gpio_reg, reserved | clock_bits); 291 intel_de_posting_read(i915, bus->gpio_reg); 292 } 293 294 static void set_data(void *data, int state_high) 295 { 296 struct intel_gmbus *bus = data; 297 struct drm_i915_private *i915 = bus->i915; 298 u32 reserved = get_reserved(bus); 299 u32 data_bits; 300 301 if (state_high) 302 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 303 else 304 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 305 GPIO_DATA_VAL_MASK; 306 307 intel_de_write_notrace(i915, bus->gpio_reg, reserved | data_bits); 308 intel_de_posting_read(i915, bus->gpio_reg); 309 } 310 311 static int 312 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 313 { 314 struct intel_gmbus *bus = to_intel_gmbus(adapter); 315 struct drm_i915_private *i915 = bus->i915; 316 317 intel_gmbus_reset(i915); 318 319 if (IS_PINEVIEW(i915)) 320 pnv_gmbus_clock_gating(i915, false); 321 322 set_data(bus, 1); 323 set_clock(bus, 1); 324 udelay(I2C_RISEFALL_TIME); 325 return 0; 326 } 327 328 static void 329 intel_gpio_post_xfer(struct i2c_adapter *adapter) 330 { 331 struct intel_gmbus *bus = to_intel_gmbus(adapter); 332 struct drm_i915_private *i915 = bus->i915; 333 334 set_data(bus, 1); 335 set_clock(bus, 1); 336 337 if (IS_PINEVIEW(i915)) 338 pnv_gmbus_clock_gating(i915, true); 339 } 340 341 static void 342 intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 343 { 344 struct i2c_algo_bit_data *algo; 345 346 algo = &bus->bit_algo; 347 348 bus->gpio_reg = gpio_reg; 349 bus->adapter.algo_data = algo; 350 algo->setsda = set_data; 351 algo->setscl = set_clock; 352 algo->getsda = get_data; 353 algo->getscl = get_clock; 354 algo->pre_xfer = intel_gpio_pre_xfer; 355 algo->post_xfer = intel_gpio_post_xfer; 356 algo->udelay = I2C_RISEFALL_TIME; 357 algo->timeout = usecs_to_jiffies(2200); 358 algo->data = bus; 359 } 360 361 static bool has_gmbus_irq(struct drm_i915_private *i915) 362 { 363 /* 364 * encoder->shutdown() may want to use GMBUS 365 * after irqs have already been disabled. 366 */ 367 return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915); 368 } 369 370 static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en) 371 { 372 DEFINE_WAIT(wait); 373 u32 gmbus2; 374 int ret; 375 376 /* Important: The hw handles only the first bit, so set only one! Since 377 * we also need to check for NAKs besides the hw ready/idle signal, we 378 * need to wake up periodically and check that ourselves. 379 */ 380 if (!has_gmbus_irq(i915)) 381 irq_en = 0; 382 383 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 384 intel_de_write_fw(i915, GMBUS4(i915), irq_en); 385 386 status |= GMBUS_SATOER; 387 ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 388 2); 389 if (ret) 390 ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 391 50); 392 393 intel_de_write_fw(i915, GMBUS4(i915), 0); 394 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 395 396 if (gmbus2 & GMBUS_SATOER) 397 return -ENXIO; 398 399 return ret; 400 } 401 402 static int 403 gmbus_wait_idle(struct drm_i915_private *i915) 404 { 405 DEFINE_WAIT(wait); 406 u32 irq_enable; 407 int ret; 408 409 /* Important: The hw handles only the first bit, so set only one! */ 410 irq_enable = 0; 411 if (has_gmbus_irq(i915)) 412 irq_enable = GMBUS_IDLE_EN; 413 414 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 415 intel_de_write_fw(i915, GMBUS4(i915), irq_enable); 416 417 ret = intel_de_wait_for_register_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10); 418 419 intel_de_write_fw(i915, GMBUS4(i915), 0); 420 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 421 422 return ret; 423 } 424 425 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915) 426 { 427 return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 428 GMBUS_BYTE_COUNT_MAX; 429 } 430 431 static int 432 gmbus_xfer_read_chunk(struct drm_i915_private *i915, 433 unsigned short addr, u8 *buf, unsigned int len, 434 u32 gmbus0_reg, u32 gmbus1_index) 435 { 436 unsigned int size = len; 437 bool burst_read = len > gmbus_max_xfer_size(i915); 438 bool extra_byte_added = false; 439 440 if (burst_read) { 441 /* 442 * As per HW Spec, for 512Bytes need to read extra Byte and 443 * Ignore the extra byte read. 444 */ 445 if (len == 512) { 446 extra_byte_added = true; 447 len++; 448 } 449 size = len % 256 + 256; 450 intel_de_write_fw(i915, GMBUS0(i915), 451 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 452 } 453 454 intel_de_write_fw(i915, GMBUS1(i915), 455 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 456 while (len) { 457 int ret; 458 u32 val, loop = 0; 459 460 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 461 if (ret) 462 return ret; 463 464 val = intel_de_read_fw(i915, GMBUS3(i915)); 465 do { 466 if (extra_byte_added && len == 1) 467 break; 468 469 *buf++ = val & 0xff; 470 val >>= 8; 471 } while (--len && ++loop < 4); 472 473 if (burst_read && len == size - 4) 474 /* Reset the override bit */ 475 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg); 476 } 477 478 return 0; 479 } 480 481 /* 482 * HW spec says that 512Bytes in Burst read need special treatment. 483 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 484 * an I2C slave, which supports such a lengthy burst read too for experiments. 485 * 486 * So until things get clarified on HW support, to avoid the burst read length 487 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 488 */ 489 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 490 491 static int 492 gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg, 493 u32 gmbus0_reg, u32 gmbus1_index) 494 { 495 u8 *buf = msg->buf; 496 unsigned int rx_size = msg->len; 497 unsigned int len; 498 int ret; 499 500 do { 501 if (HAS_GMBUS_BURST_READ(i915)) 502 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 503 else 504 len = min(rx_size, gmbus_max_xfer_size(i915)); 505 506 ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len, 507 gmbus0_reg, gmbus1_index); 508 if (ret) 509 return ret; 510 511 rx_size -= len; 512 buf += len; 513 } while (rx_size != 0); 514 515 return 0; 516 } 517 518 static int 519 gmbus_xfer_write_chunk(struct drm_i915_private *i915, 520 unsigned short addr, u8 *buf, unsigned int len, 521 u32 gmbus1_index) 522 { 523 unsigned int chunk_size = len; 524 u32 val, loop; 525 526 val = loop = 0; 527 while (len && loop < 4) { 528 val |= *buf++ << (8 * loop++); 529 len -= 1; 530 } 531 532 intel_de_write_fw(i915, GMBUS3(i915), val); 533 intel_de_write_fw(i915, GMBUS1(i915), 534 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 535 while (len) { 536 int ret; 537 538 val = loop = 0; 539 do { 540 val |= *buf++ << (8 * loop); 541 } while (--len && ++loop < 4); 542 543 intel_de_write_fw(i915, GMBUS3(i915), val); 544 545 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 546 if (ret) 547 return ret; 548 } 549 550 return 0; 551 } 552 553 static int 554 gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg, 555 u32 gmbus1_index) 556 { 557 u8 *buf = msg->buf; 558 unsigned int tx_size = msg->len; 559 unsigned int len; 560 int ret; 561 562 do { 563 len = min(tx_size, gmbus_max_xfer_size(i915)); 564 565 ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len, 566 gmbus1_index); 567 if (ret) 568 return ret; 569 570 buf += len; 571 tx_size -= len; 572 } while (tx_size != 0); 573 574 return 0; 575 } 576 577 /* 578 * The gmbus controller can combine a 1 or 2 byte write with another read/write 579 * that immediately follows it by using an "INDEX" cycle. 580 */ 581 static bool 582 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 583 { 584 return (i + 1 < num && 585 msgs[i].addr == msgs[i + 1].addr && 586 !(msgs[i].flags & I2C_M_RD) && 587 (msgs[i].len == 1 || msgs[i].len == 2) && 588 msgs[i + 1].len > 0); 589 } 590 591 static int 592 gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs, 593 u32 gmbus0_reg) 594 { 595 u32 gmbus1_index = 0; 596 u32 gmbus5 = 0; 597 int ret; 598 599 if (msgs[0].len == 2) 600 gmbus5 = GMBUS_2BYTE_INDEX_EN | 601 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 602 if (msgs[0].len == 1) 603 gmbus1_index = GMBUS_CYCLE_INDEX | 604 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 605 606 /* GMBUS5 holds 16-bit index */ 607 if (gmbus5) 608 intel_de_write_fw(i915, GMBUS5(i915), gmbus5); 609 610 if (msgs[1].flags & I2C_M_RD) 611 ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg, 612 gmbus1_index); 613 else 614 ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index); 615 616 /* Clear GMBUS5 after each index transfer */ 617 if (gmbus5) 618 intel_de_write_fw(i915, GMBUS5(i915), 0); 619 620 return ret; 621 } 622 623 static int 624 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 625 u32 gmbus0_source) 626 { 627 struct intel_gmbus *bus = to_intel_gmbus(adapter); 628 struct drm_i915_private *i915 = bus->i915; 629 int i = 0, inc, try = 0; 630 int ret = 0; 631 632 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 633 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 634 bxt_gmbus_clock_gating(i915, false); 635 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 636 pch_gmbus_clock_gating(i915, false); 637 638 retry: 639 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0); 640 641 for (; i < num; i += inc) { 642 inc = 1; 643 if (gmbus_is_index_xfer(msgs, i, num)) { 644 ret = gmbus_index_xfer(i915, &msgs[i], 645 gmbus0_source | bus->reg0); 646 inc = 2; /* an index transmission is two msgs */ 647 } else if (msgs[i].flags & I2C_M_RD) { 648 ret = gmbus_xfer_read(i915, &msgs[i], 649 gmbus0_source | bus->reg0, 0); 650 } else { 651 ret = gmbus_xfer_write(i915, &msgs[i], 0); 652 } 653 654 if (!ret) 655 ret = gmbus_wait(i915, 656 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 657 if (ret == -ETIMEDOUT) 658 goto timeout; 659 else if (ret) 660 goto clear_err; 661 } 662 663 /* Generate a STOP condition on the bus. Note that gmbus can't generata 664 * a STOP on the very first cycle. To simplify the code we 665 * unconditionally generate the STOP condition with an additional gmbus 666 * cycle. */ 667 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 668 669 /* Mark the GMBUS interface as disabled after waiting for idle. 670 * We will re-enable it at the start of the next xfer, 671 * till then let it sleep. 672 */ 673 if (gmbus_wait_idle(i915)) { 674 drm_dbg_kms(&i915->drm, 675 "GMBUS [%s] timed out waiting for idle\n", 676 adapter->name); 677 ret = -ETIMEDOUT; 678 } 679 intel_de_write_fw(i915, GMBUS0(i915), 0); 680 ret = ret ?: i; 681 goto out; 682 683 clear_err: 684 /* 685 * Wait for bus to IDLE before clearing NAK. 686 * If we clear the NAK while bus is still active, then it will stay 687 * active and the next transaction may fail. 688 * 689 * If no ACK is received during the address phase of a transaction, the 690 * adapter must report -ENXIO. It is not clear what to return if no ACK 691 * is received at other times. But we have to be careful to not return 692 * spurious -ENXIO because that will prevent i2c and drm edid functions 693 * from retrying. So return -ENXIO only when gmbus properly quiescents - 694 * timing out seems to happen when there _is_ a ddc chip present, but 695 * it's slow responding and only answers on the 2nd retry. 696 */ 697 ret = -ENXIO; 698 if (gmbus_wait_idle(i915)) { 699 drm_dbg_kms(&i915->drm, 700 "GMBUS [%s] timed out after NAK\n", 701 adapter->name); 702 ret = -ETIMEDOUT; 703 } 704 705 /* Toggle the Software Clear Interrupt bit. This has the effect 706 * of resetting the GMBUS controller and so clearing the 707 * BUS_ERROR raised by the slave's NAK. 708 */ 709 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT); 710 intel_de_write_fw(i915, GMBUS1(i915), 0); 711 intel_de_write_fw(i915, GMBUS0(i915), 0); 712 713 drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 714 adapter->name, msgs[i].addr, 715 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 716 717 /* 718 * Passive adapters sometimes NAK the first probe. Retry the first 719 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 720 * has retries internally. See also the retry loop in 721 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 722 */ 723 if (ret == -ENXIO && i == 0 && try++ == 0) { 724 drm_dbg_kms(&i915->drm, 725 "GMBUS [%s] NAK on first message, retry\n", 726 adapter->name); 727 goto retry; 728 } 729 730 goto out; 731 732 timeout: 733 drm_dbg_kms(&i915->drm, 734 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 735 bus->adapter.name, bus->reg0 & 0xff); 736 intel_de_write_fw(i915, GMBUS0(i915), 0); 737 738 /* 739 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 740 * instead. Use EAGAIN to have i2c core retry. 741 */ 742 ret = -EAGAIN; 743 744 out: 745 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 746 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 747 bxt_gmbus_clock_gating(i915, true); 748 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 749 pch_gmbus_clock_gating(i915, true); 750 751 return ret; 752 } 753 754 static int 755 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 756 { 757 struct intel_gmbus *bus = to_intel_gmbus(adapter); 758 struct drm_i915_private *i915 = bus->i915; 759 intel_wakeref_t wakeref; 760 int ret; 761 762 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 763 764 if (bus->force_bit) { 765 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 766 if (ret < 0) 767 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 768 } else { 769 ret = do_gmbus_xfer(adapter, msgs, num, 0); 770 if (ret == -EAGAIN) 771 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 772 } 773 774 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 775 776 return ret; 777 } 778 779 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 780 { 781 struct intel_gmbus *bus = to_intel_gmbus(adapter); 782 struct drm_i915_private *i915 = bus->i915; 783 u8 cmd = DRM_HDCP_DDC_AKSV; 784 u8 buf[DRM_HDCP_KSV_LEN] = {}; 785 struct i2c_msg msgs[] = { 786 { 787 .addr = DRM_HDCP_DDC_ADDR, 788 .flags = 0, 789 .len = sizeof(cmd), 790 .buf = &cmd, 791 }, 792 { 793 .addr = DRM_HDCP_DDC_ADDR, 794 .flags = 0, 795 .len = sizeof(buf), 796 .buf = buf, 797 } 798 }; 799 intel_wakeref_t wakeref; 800 int ret; 801 802 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 803 mutex_lock(&i915->display.gmbus.mutex); 804 805 /* 806 * In order to output Aksv to the receiver, use an indexed write to 807 * pass the i2c command, and tell GMBUS to use the HW-provided value 808 * instead of sourcing GMBUS3 for the data. 809 */ 810 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 811 812 mutex_unlock(&i915->display.gmbus.mutex); 813 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 814 815 return ret; 816 } 817 818 static u32 gmbus_func(struct i2c_adapter *adapter) 819 { 820 return i2c_bit_algo.functionality(adapter) & 821 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 822 /* I2C_FUNC_10BIT_ADDR | */ 823 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 824 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 825 } 826 827 static const struct i2c_algorithm gmbus_algorithm = { 828 .master_xfer = gmbus_xfer, 829 .functionality = gmbus_func 830 }; 831 832 static void gmbus_lock_bus(struct i2c_adapter *adapter, 833 unsigned int flags) 834 { 835 struct intel_gmbus *bus = to_intel_gmbus(adapter); 836 struct drm_i915_private *i915 = bus->i915; 837 838 mutex_lock(&i915->display.gmbus.mutex); 839 } 840 841 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 842 unsigned int flags) 843 { 844 struct intel_gmbus *bus = to_intel_gmbus(adapter); 845 struct drm_i915_private *i915 = bus->i915; 846 847 return mutex_trylock(&i915->display.gmbus.mutex); 848 } 849 850 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 851 unsigned int flags) 852 { 853 struct intel_gmbus *bus = to_intel_gmbus(adapter); 854 struct drm_i915_private *i915 = bus->i915; 855 856 mutex_unlock(&i915->display.gmbus.mutex); 857 } 858 859 static const struct i2c_lock_operations gmbus_lock_ops = { 860 .lock_bus = gmbus_lock_bus, 861 .trylock_bus = gmbus_trylock_bus, 862 .unlock_bus = gmbus_unlock_bus, 863 }; 864 865 /** 866 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 867 * @i915: i915 device private 868 */ 869 int intel_gmbus_setup(struct drm_i915_private *i915) 870 { 871 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 872 unsigned int pin; 873 int ret; 874 875 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 876 i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE; 877 else if (!HAS_GMCH(i915)) 878 /* 879 * Broxton uses the same PCH offsets for South Display Engine, 880 * even though it doesn't have a PCH. 881 */ 882 i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE; 883 884 mutex_init(&i915->display.gmbus.mutex); 885 init_waitqueue_head(&i915->display.gmbus.wait_queue); 886 887 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 888 const struct gmbus_pin *gmbus_pin; 889 struct intel_gmbus *bus; 890 891 gmbus_pin = get_gmbus_pin(i915, pin); 892 if (!gmbus_pin) 893 continue; 894 895 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 896 if (!bus) { 897 ret = -ENOMEM; 898 goto err; 899 } 900 901 bus->adapter.owner = THIS_MODULE; 902 snprintf(bus->adapter.name, 903 sizeof(bus->adapter.name), 904 "i915 gmbus %s", gmbus_pin->name); 905 906 bus->adapter.dev.parent = &pdev->dev; 907 bus->i915 = i915; 908 909 bus->adapter.algo = &gmbus_algorithm; 910 bus->adapter.lock_ops = &gmbus_lock_ops; 911 912 /* 913 * We wish to retry with bit banging 914 * after a timed out GMBUS attempt. 915 */ 916 bus->adapter.retries = 1; 917 918 /* By default use a conservative clock rate */ 919 bus->reg0 = pin | GMBUS_RATE_100KHZ; 920 921 /* gmbus seems to be broken on i830 */ 922 if (IS_I830(i915)) 923 bus->force_bit = 1; 924 925 intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio)); 926 927 ret = i2c_add_adapter(&bus->adapter); 928 if (ret) { 929 kfree(bus); 930 goto err; 931 } 932 933 i915->display.gmbus.bus[pin] = bus; 934 } 935 936 intel_gmbus_reset(i915); 937 938 return 0; 939 940 err: 941 intel_gmbus_teardown(i915); 942 943 return ret; 944 } 945 946 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915, 947 unsigned int pin) 948 { 949 if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) || 950 !i915->display.gmbus.bus[pin])) 951 return NULL; 952 953 return &i915->display.gmbus.bus[pin]->adapter; 954 } 955 956 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 957 { 958 struct intel_gmbus *bus = to_intel_gmbus(adapter); 959 struct drm_i915_private *i915 = bus->i915; 960 961 mutex_lock(&i915->display.gmbus.mutex); 962 963 bus->force_bit += force_bit ? 1 : -1; 964 drm_dbg_kms(&i915->drm, 965 "%sabling bit-banging on %s. force bit now %d\n", 966 force_bit ? "en" : "dis", adapter->name, 967 bus->force_bit); 968 969 mutex_unlock(&i915->display.gmbus.mutex); 970 } 971 972 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 973 { 974 struct intel_gmbus *bus = to_intel_gmbus(adapter); 975 976 return bus->force_bit; 977 } 978 979 void intel_gmbus_teardown(struct drm_i915_private *i915) 980 { 981 unsigned int pin; 982 983 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 984 struct intel_gmbus *bus; 985 986 bus = i915->display.gmbus.bus[pin]; 987 if (!bus) 988 continue; 989 990 i2c_del_adapter(&bus->adapter); 991 992 kfree(bus); 993 i915->display.gmbus.bus[pin] = NULL; 994 } 995 } 996 997 void intel_gmbus_irq_handler(struct drm_i915_private *i915) 998 { 999 wake_up_all(&i915->display.gmbus.wait_queue); 1000 } 1001