1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/display/drm_hdcp_helper.h> 35 36 #include "i915_drv.h" 37 #include "i915_irq.h" 38 #include "i915_reg.h" 39 #include "intel_de.h" 40 #include "intel_display_types.h" 41 #include "intel_gmbus.h" 42 #include "intel_gmbus_regs.h" 43 44 struct intel_gmbus { 45 struct i2c_adapter adapter; 46 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 47 u32 force_bit; 48 u32 reg0; 49 i915_reg_t gpio_reg; 50 struct i2c_algo_bit_data bit_algo; 51 struct drm_i915_private *i915; 52 }; 53 54 enum gmbus_gpio { 55 GPIOA, 56 GPIOB, 57 GPIOC, 58 GPIOD, 59 GPIOE, 60 GPIOF, 61 GPIOG, 62 GPIOH, 63 __GPIOI_UNUSED, 64 GPIOJ, 65 GPIOK, 66 GPIOL, 67 GPIOM, 68 GPION, 69 GPIOO, 70 }; 71 72 struct gmbus_pin { 73 const char *name; 74 enum gmbus_gpio gpio; 75 }; 76 77 /* Map gmbus pin pairs to names and registers. */ 78 static const struct gmbus_pin gmbus_pins[] = { 79 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 80 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 81 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 82 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 83 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 84 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 85 }; 86 87 static const struct gmbus_pin gmbus_pins_bdw[] = { 88 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 89 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 90 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 91 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 92 }; 93 94 static const struct gmbus_pin gmbus_pins_skl[] = { 95 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 96 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 97 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 98 }; 99 100 static const struct gmbus_pin gmbus_pins_bxt[] = { 101 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 102 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 103 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 104 }; 105 106 static const struct gmbus_pin gmbus_pins_cnp[] = { 107 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 108 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 109 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 110 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 111 }; 112 113 static const struct gmbus_pin gmbus_pins_icp[] = { 114 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 115 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 116 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 117 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 118 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 119 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 120 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 121 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 122 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 123 }; 124 125 static const struct gmbus_pin gmbus_pins_dg1[] = { 126 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 127 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 128 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 129 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 130 }; 131 132 static const struct gmbus_pin gmbus_pins_dg2[] = { 133 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 134 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 135 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 136 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 137 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 138 }; 139 140 static const struct gmbus_pin gmbus_pins_mtp[] = { 141 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 142 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 143 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 144 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 145 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, 146 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 147 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 148 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 149 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 150 }; 151 152 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, 153 unsigned int pin) 154 { 155 const struct gmbus_pin *pins; 156 size_t size; 157 158 if (INTEL_PCH_TYPE(i915) >= PCH_DG2) { 159 pins = gmbus_pins_dg2; 160 size = ARRAY_SIZE(gmbus_pins_dg2); 161 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { 162 pins = gmbus_pins_dg1; 163 size = ARRAY_SIZE(gmbus_pins_dg1); 164 } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) { 165 pins = gmbus_pins_mtp; 166 size = ARRAY_SIZE(gmbus_pins_mtp); 167 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { 168 pins = gmbus_pins_icp; 169 size = ARRAY_SIZE(gmbus_pins_icp); 170 } else if (HAS_PCH_CNP(i915)) { 171 pins = gmbus_pins_cnp; 172 size = ARRAY_SIZE(gmbus_pins_cnp); 173 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 174 pins = gmbus_pins_bxt; 175 size = ARRAY_SIZE(gmbus_pins_bxt); 176 } else if (DISPLAY_VER(i915) == 9) { 177 pins = gmbus_pins_skl; 178 size = ARRAY_SIZE(gmbus_pins_skl); 179 } else if (IS_BROADWELL(i915)) { 180 pins = gmbus_pins_bdw; 181 size = ARRAY_SIZE(gmbus_pins_bdw); 182 } else { 183 pins = gmbus_pins; 184 size = ARRAY_SIZE(gmbus_pins); 185 } 186 187 if (pin >= size || !pins[pin].name) 188 return NULL; 189 190 return &pins[pin]; 191 } 192 193 bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin) 194 { 195 return get_gmbus_pin(i915, pin); 196 } 197 198 /* Intel GPIO access functions */ 199 200 #define I2C_RISEFALL_TIME 10 201 202 static inline struct intel_gmbus * 203 to_intel_gmbus(struct i2c_adapter *i2c) 204 { 205 return container_of(i2c, struct intel_gmbus, adapter); 206 } 207 208 void 209 intel_gmbus_reset(struct drm_i915_private *i915) 210 { 211 intel_de_write(i915, GMBUS0(i915), 0); 212 intel_de_write(i915, GMBUS4(i915), 0); 213 } 214 215 static void pnv_gmbus_clock_gating(struct drm_i915_private *i915, 216 bool enable) 217 { 218 u32 val; 219 220 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 221 val = intel_de_read(i915, DSPCLK_GATE_D(i915)); 222 if (!enable) 223 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 224 else 225 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 226 intel_de_write(i915, DSPCLK_GATE_D(i915), val); 227 } 228 229 static void pch_gmbus_clock_gating(struct drm_i915_private *i915, 230 bool enable) 231 { 232 u32 val; 233 234 val = intel_de_read(i915, SOUTH_DSPCLK_GATE_D); 235 if (!enable) 236 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 237 else 238 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 239 intel_de_write(i915, SOUTH_DSPCLK_GATE_D, val); 240 } 241 242 static void bxt_gmbus_clock_gating(struct drm_i915_private *i915, 243 bool enable) 244 { 245 u32 val; 246 247 val = intel_de_read(i915, GEN9_CLKGATE_DIS_4); 248 if (!enable) 249 val |= BXT_GMBUS_GATING_DIS; 250 else 251 val &= ~BXT_GMBUS_GATING_DIS; 252 intel_de_write(i915, GEN9_CLKGATE_DIS_4, val); 253 } 254 255 static u32 get_reserved(struct intel_gmbus *bus) 256 { 257 struct drm_i915_private *i915 = bus->i915; 258 u32 reserved = 0; 259 260 /* On most chips, these bits must be preserved in software. */ 261 if (!IS_I830(i915) && !IS_I845G(i915)) 262 reserved = intel_de_read_notrace(i915, bus->gpio_reg) & 263 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); 264 265 return reserved; 266 } 267 268 static int get_clock(void *data) 269 { 270 struct intel_gmbus *bus = data; 271 struct drm_i915_private *i915 = bus->i915; 272 u32 reserved = get_reserved(bus); 273 274 intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 275 intel_de_write_notrace(i915, bus->gpio_reg, reserved); 276 277 return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 278 } 279 280 static int get_data(void *data) 281 { 282 struct intel_gmbus *bus = data; 283 struct drm_i915_private *i915 = bus->i915; 284 u32 reserved = get_reserved(bus); 285 286 intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 287 intel_de_write_notrace(i915, bus->gpio_reg, reserved); 288 289 return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 290 } 291 292 static void set_clock(void *data, int state_high) 293 { 294 struct intel_gmbus *bus = data; 295 struct drm_i915_private *i915 = bus->i915; 296 u32 reserved = get_reserved(bus); 297 u32 clock_bits; 298 299 if (state_high) 300 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 301 else 302 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 303 GPIO_CLOCK_VAL_MASK; 304 305 intel_de_write_notrace(i915, bus->gpio_reg, reserved | clock_bits); 306 intel_de_posting_read(i915, bus->gpio_reg); 307 } 308 309 static void set_data(void *data, int state_high) 310 { 311 struct intel_gmbus *bus = data; 312 struct drm_i915_private *i915 = bus->i915; 313 u32 reserved = get_reserved(bus); 314 u32 data_bits; 315 316 if (state_high) 317 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 318 else 319 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 320 GPIO_DATA_VAL_MASK; 321 322 intel_de_write_notrace(i915, bus->gpio_reg, reserved | data_bits); 323 intel_de_posting_read(i915, bus->gpio_reg); 324 } 325 326 static int 327 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 328 { 329 struct intel_gmbus *bus = to_intel_gmbus(adapter); 330 struct drm_i915_private *i915 = bus->i915; 331 332 intel_gmbus_reset(i915); 333 334 if (IS_PINEVIEW(i915)) 335 pnv_gmbus_clock_gating(i915, false); 336 337 set_data(bus, 1); 338 set_clock(bus, 1); 339 udelay(I2C_RISEFALL_TIME); 340 return 0; 341 } 342 343 static void 344 intel_gpio_post_xfer(struct i2c_adapter *adapter) 345 { 346 struct intel_gmbus *bus = to_intel_gmbus(adapter); 347 struct drm_i915_private *i915 = bus->i915; 348 349 set_data(bus, 1); 350 set_clock(bus, 1); 351 352 if (IS_PINEVIEW(i915)) 353 pnv_gmbus_clock_gating(i915, true); 354 } 355 356 static void 357 intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 358 { 359 struct i2c_algo_bit_data *algo; 360 361 algo = &bus->bit_algo; 362 363 bus->gpio_reg = gpio_reg; 364 bus->adapter.algo_data = algo; 365 algo->setsda = set_data; 366 algo->setscl = set_clock; 367 algo->getsda = get_data; 368 algo->getscl = get_clock; 369 algo->pre_xfer = intel_gpio_pre_xfer; 370 algo->post_xfer = intel_gpio_post_xfer; 371 algo->udelay = I2C_RISEFALL_TIME; 372 algo->timeout = usecs_to_jiffies(2200); 373 algo->data = bus; 374 } 375 376 static bool has_gmbus_irq(struct drm_i915_private *i915) 377 { 378 /* 379 * encoder->shutdown() may want to use GMBUS 380 * after irqs have already been disabled. 381 */ 382 return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915); 383 } 384 385 static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en) 386 { 387 DEFINE_WAIT(wait); 388 u32 gmbus2; 389 int ret; 390 391 /* Important: The hw handles only the first bit, so set only one! Since 392 * we also need to check for NAKs besides the hw ready/idle signal, we 393 * need to wake up periodically and check that ourselves. 394 */ 395 if (!has_gmbus_irq(i915)) 396 irq_en = 0; 397 398 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 399 intel_de_write_fw(i915, GMBUS4(i915), irq_en); 400 401 status |= GMBUS_SATOER; 402 ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 403 2); 404 if (ret) 405 ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status, 406 50); 407 408 intel_de_write_fw(i915, GMBUS4(i915), 0); 409 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 410 411 if (gmbus2 & GMBUS_SATOER) 412 return -ENXIO; 413 414 return ret; 415 } 416 417 static int 418 gmbus_wait_idle(struct drm_i915_private *i915) 419 { 420 DEFINE_WAIT(wait); 421 u32 irq_enable; 422 int ret; 423 424 /* Important: The hw handles only the first bit, so set only one! */ 425 irq_enable = 0; 426 if (has_gmbus_irq(i915)) 427 irq_enable = GMBUS_IDLE_EN; 428 429 add_wait_queue(&i915->display.gmbus.wait_queue, &wait); 430 intel_de_write_fw(i915, GMBUS4(i915), irq_enable); 431 432 ret = intel_de_wait_for_register_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10); 433 434 intel_de_write_fw(i915, GMBUS4(i915), 0); 435 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait); 436 437 return ret; 438 } 439 440 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915) 441 { 442 return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 443 GMBUS_BYTE_COUNT_MAX; 444 } 445 446 static int 447 gmbus_xfer_read_chunk(struct drm_i915_private *i915, 448 unsigned short addr, u8 *buf, unsigned int len, 449 u32 gmbus0_reg, u32 gmbus1_index) 450 { 451 unsigned int size = len; 452 bool burst_read = len > gmbus_max_xfer_size(i915); 453 bool extra_byte_added = false; 454 455 if (burst_read) { 456 /* 457 * As per HW Spec, for 512Bytes need to read extra Byte and 458 * Ignore the extra byte read. 459 */ 460 if (len == 512) { 461 extra_byte_added = true; 462 len++; 463 } 464 size = len % 256 + 256; 465 intel_de_write_fw(i915, GMBUS0(i915), 466 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 467 } 468 469 intel_de_write_fw(i915, GMBUS1(i915), 470 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 471 while (len) { 472 int ret; 473 u32 val, loop = 0; 474 475 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 476 if (ret) 477 return ret; 478 479 val = intel_de_read_fw(i915, GMBUS3(i915)); 480 do { 481 if (extra_byte_added && len == 1) 482 break; 483 484 *buf++ = val & 0xff; 485 val >>= 8; 486 } while (--len && ++loop < 4); 487 488 if (burst_read && len == size - 4) 489 /* Reset the override bit */ 490 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg); 491 } 492 493 return 0; 494 } 495 496 /* 497 * HW spec says that 512Bytes in Burst read need special treatment. 498 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 499 * an I2C slave, which supports such a lengthy burst read too for experiments. 500 * 501 * So until things get clarified on HW support, to avoid the burst read length 502 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 503 */ 504 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 505 506 static int 507 gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg, 508 u32 gmbus0_reg, u32 gmbus1_index) 509 { 510 u8 *buf = msg->buf; 511 unsigned int rx_size = msg->len; 512 unsigned int len; 513 int ret; 514 515 do { 516 if (HAS_GMBUS_BURST_READ(i915)) 517 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 518 else 519 len = min(rx_size, gmbus_max_xfer_size(i915)); 520 521 ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len, 522 gmbus0_reg, gmbus1_index); 523 if (ret) 524 return ret; 525 526 rx_size -= len; 527 buf += len; 528 } while (rx_size != 0); 529 530 return 0; 531 } 532 533 static int 534 gmbus_xfer_write_chunk(struct drm_i915_private *i915, 535 unsigned short addr, u8 *buf, unsigned int len, 536 u32 gmbus1_index) 537 { 538 unsigned int chunk_size = len; 539 u32 val, loop; 540 541 val = loop = 0; 542 while (len && loop < 4) { 543 val |= *buf++ << (8 * loop++); 544 len -= 1; 545 } 546 547 intel_de_write_fw(i915, GMBUS3(i915), val); 548 intel_de_write_fw(i915, GMBUS1(i915), 549 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 550 while (len) { 551 int ret; 552 553 val = loop = 0; 554 do { 555 val |= *buf++ << (8 * loop); 556 } while (--len && ++loop < 4); 557 558 intel_de_write_fw(i915, GMBUS3(i915), val); 559 560 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 561 if (ret) 562 return ret; 563 } 564 565 return 0; 566 } 567 568 static int 569 gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg, 570 u32 gmbus1_index) 571 { 572 u8 *buf = msg->buf; 573 unsigned int tx_size = msg->len; 574 unsigned int len; 575 int ret; 576 577 do { 578 len = min(tx_size, gmbus_max_xfer_size(i915)); 579 580 ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len, 581 gmbus1_index); 582 if (ret) 583 return ret; 584 585 buf += len; 586 tx_size -= len; 587 } while (tx_size != 0); 588 589 return 0; 590 } 591 592 /* 593 * The gmbus controller can combine a 1 or 2 byte write with another read/write 594 * that immediately follows it by using an "INDEX" cycle. 595 */ 596 static bool 597 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 598 { 599 return (i + 1 < num && 600 msgs[i].addr == msgs[i + 1].addr && 601 !(msgs[i].flags & I2C_M_RD) && 602 (msgs[i].len == 1 || msgs[i].len == 2) && 603 msgs[i + 1].len > 0); 604 } 605 606 static int 607 gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs, 608 u32 gmbus0_reg) 609 { 610 u32 gmbus1_index = 0; 611 u32 gmbus5 = 0; 612 int ret; 613 614 if (msgs[0].len == 2) 615 gmbus5 = GMBUS_2BYTE_INDEX_EN | 616 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 617 if (msgs[0].len == 1) 618 gmbus1_index = GMBUS_CYCLE_INDEX | 619 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 620 621 /* GMBUS5 holds 16-bit index */ 622 if (gmbus5) 623 intel_de_write_fw(i915, GMBUS5(i915), gmbus5); 624 625 if (msgs[1].flags & I2C_M_RD) 626 ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg, 627 gmbus1_index); 628 else 629 ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index); 630 631 /* Clear GMBUS5 after each index transfer */ 632 if (gmbus5) 633 intel_de_write_fw(i915, GMBUS5(i915), 0); 634 635 return ret; 636 } 637 638 static int 639 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 640 u32 gmbus0_source) 641 { 642 struct intel_gmbus *bus = to_intel_gmbus(adapter); 643 struct drm_i915_private *i915 = bus->i915; 644 int i = 0, inc, try = 0; 645 int ret = 0; 646 647 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 648 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 649 bxt_gmbus_clock_gating(i915, false); 650 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 651 pch_gmbus_clock_gating(i915, false); 652 653 retry: 654 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0); 655 656 for (; i < num; i += inc) { 657 inc = 1; 658 if (gmbus_is_index_xfer(msgs, i, num)) { 659 ret = gmbus_index_xfer(i915, &msgs[i], 660 gmbus0_source | bus->reg0); 661 inc = 2; /* an index transmission is two msgs */ 662 } else if (msgs[i].flags & I2C_M_RD) { 663 ret = gmbus_xfer_read(i915, &msgs[i], 664 gmbus0_source | bus->reg0, 0); 665 } else { 666 ret = gmbus_xfer_write(i915, &msgs[i], 0); 667 } 668 669 if (!ret) 670 ret = gmbus_wait(i915, 671 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 672 if (ret == -ETIMEDOUT) 673 goto timeout; 674 else if (ret) 675 goto clear_err; 676 } 677 678 /* Generate a STOP condition on the bus. Note that gmbus can't generata 679 * a STOP on the very first cycle. To simplify the code we 680 * unconditionally generate the STOP condition with an additional gmbus 681 * cycle. */ 682 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 683 684 /* Mark the GMBUS interface as disabled after waiting for idle. 685 * We will re-enable it at the start of the next xfer, 686 * till then let it sleep. 687 */ 688 if (gmbus_wait_idle(i915)) { 689 drm_dbg_kms(&i915->drm, 690 "GMBUS [%s] timed out waiting for idle\n", 691 adapter->name); 692 ret = -ETIMEDOUT; 693 } 694 intel_de_write_fw(i915, GMBUS0(i915), 0); 695 ret = ret ?: i; 696 goto out; 697 698 clear_err: 699 /* 700 * Wait for bus to IDLE before clearing NAK. 701 * If we clear the NAK while bus is still active, then it will stay 702 * active and the next transaction may fail. 703 * 704 * If no ACK is received during the address phase of a transaction, the 705 * adapter must report -ENXIO. It is not clear what to return if no ACK 706 * is received at other times. But we have to be careful to not return 707 * spurious -ENXIO because that will prevent i2c and drm edid functions 708 * from retrying. So return -ENXIO only when gmbus properly quiescents - 709 * timing out seems to happen when there _is_ a ddc chip present, but 710 * it's slow responding and only answers on the 2nd retry. 711 */ 712 ret = -ENXIO; 713 if (gmbus_wait_idle(i915)) { 714 drm_dbg_kms(&i915->drm, 715 "GMBUS [%s] timed out after NAK\n", 716 adapter->name); 717 ret = -ETIMEDOUT; 718 } 719 720 /* Toggle the Software Clear Interrupt bit. This has the effect 721 * of resetting the GMBUS controller and so clearing the 722 * BUS_ERROR raised by the slave's NAK. 723 */ 724 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT); 725 intel_de_write_fw(i915, GMBUS1(i915), 0); 726 intel_de_write_fw(i915, GMBUS0(i915), 0); 727 728 drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 729 adapter->name, msgs[i].addr, 730 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 731 732 /* 733 * Passive adapters sometimes NAK the first probe. Retry the first 734 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 735 * has retries internally. See also the retry loop in 736 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 737 */ 738 if (ret == -ENXIO && i == 0 && try++ == 0) { 739 drm_dbg_kms(&i915->drm, 740 "GMBUS [%s] NAK on first message, retry\n", 741 adapter->name); 742 goto retry; 743 } 744 745 goto out; 746 747 timeout: 748 drm_dbg_kms(&i915->drm, 749 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 750 bus->adapter.name, bus->reg0 & 0xff); 751 intel_de_write_fw(i915, GMBUS0(i915), 0); 752 753 /* 754 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 755 * instead. Use EAGAIN to have i2c core retry. 756 */ 757 ret = -EAGAIN; 758 759 out: 760 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 761 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 762 bxt_gmbus_clock_gating(i915, true); 763 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 764 pch_gmbus_clock_gating(i915, true); 765 766 return ret; 767 } 768 769 static int 770 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 771 { 772 struct intel_gmbus *bus = to_intel_gmbus(adapter); 773 struct drm_i915_private *i915 = bus->i915; 774 intel_wakeref_t wakeref; 775 int ret; 776 777 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 778 779 if (bus->force_bit) { 780 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 781 if (ret < 0) 782 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 783 } else { 784 ret = do_gmbus_xfer(adapter, msgs, num, 0); 785 if (ret == -EAGAIN) 786 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 787 } 788 789 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 790 791 return ret; 792 } 793 794 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 795 { 796 struct intel_gmbus *bus = to_intel_gmbus(adapter); 797 struct drm_i915_private *i915 = bus->i915; 798 u8 cmd = DRM_HDCP_DDC_AKSV; 799 u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 800 struct i2c_msg msgs[] = { 801 { 802 .addr = DRM_HDCP_DDC_ADDR, 803 .flags = 0, 804 .len = sizeof(cmd), 805 .buf = &cmd, 806 }, 807 { 808 .addr = DRM_HDCP_DDC_ADDR, 809 .flags = 0, 810 .len = sizeof(buf), 811 .buf = buf, 812 } 813 }; 814 intel_wakeref_t wakeref; 815 int ret; 816 817 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 818 mutex_lock(&i915->display.gmbus.mutex); 819 820 /* 821 * In order to output Aksv to the receiver, use an indexed write to 822 * pass the i2c command, and tell GMBUS to use the HW-provided value 823 * instead of sourcing GMBUS3 for the data. 824 */ 825 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 826 827 mutex_unlock(&i915->display.gmbus.mutex); 828 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 829 830 return ret; 831 } 832 833 static u32 gmbus_func(struct i2c_adapter *adapter) 834 { 835 return i2c_bit_algo.functionality(adapter) & 836 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 837 /* I2C_FUNC_10BIT_ADDR | */ 838 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 839 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 840 } 841 842 static const struct i2c_algorithm gmbus_algorithm = { 843 .master_xfer = gmbus_xfer, 844 .functionality = gmbus_func 845 }; 846 847 static void gmbus_lock_bus(struct i2c_adapter *adapter, 848 unsigned int flags) 849 { 850 struct intel_gmbus *bus = to_intel_gmbus(adapter); 851 struct drm_i915_private *i915 = bus->i915; 852 853 mutex_lock(&i915->display.gmbus.mutex); 854 } 855 856 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 857 unsigned int flags) 858 { 859 struct intel_gmbus *bus = to_intel_gmbus(adapter); 860 struct drm_i915_private *i915 = bus->i915; 861 862 return mutex_trylock(&i915->display.gmbus.mutex); 863 } 864 865 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 866 unsigned int flags) 867 { 868 struct intel_gmbus *bus = to_intel_gmbus(adapter); 869 struct drm_i915_private *i915 = bus->i915; 870 871 mutex_unlock(&i915->display.gmbus.mutex); 872 } 873 874 static const struct i2c_lock_operations gmbus_lock_ops = { 875 .lock_bus = gmbus_lock_bus, 876 .trylock_bus = gmbus_trylock_bus, 877 .unlock_bus = gmbus_unlock_bus, 878 }; 879 880 /** 881 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 882 * @i915: i915 device private 883 */ 884 int intel_gmbus_setup(struct drm_i915_private *i915) 885 { 886 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 887 unsigned int pin; 888 int ret; 889 890 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 891 i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE; 892 else if (!HAS_GMCH(i915)) 893 /* 894 * Broxton uses the same PCH offsets for South Display Engine, 895 * even though it doesn't have a PCH. 896 */ 897 i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE; 898 899 mutex_init(&i915->display.gmbus.mutex); 900 init_waitqueue_head(&i915->display.gmbus.wait_queue); 901 902 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 903 const struct gmbus_pin *gmbus_pin; 904 struct intel_gmbus *bus; 905 906 gmbus_pin = get_gmbus_pin(i915, pin); 907 if (!gmbus_pin) 908 continue; 909 910 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 911 if (!bus) { 912 ret = -ENOMEM; 913 goto err; 914 } 915 916 bus->adapter.owner = THIS_MODULE; 917 bus->adapter.class = I2C_CLASS_DDC; 918 snprintf(bus->adapter.name, 919 sizeof(bus->adapter.name), 920 "i915 gmbus %s", gmbus_pin->name); 921 922 bus->adapter.dev.parent = &pdev->dev; 923 bus->i915 = i915; 924 925 bus->adapter.algo = &gmbus_algorithm; 926 bus->adapter.lock_ops = &gmbus_lock_ops; 927 928 /* 929 * We wish to retry with bit banging 930 * after a timed out GMBUS attempt. 931 */ 932 bus->adapter.retries = 1; 933 934 /* By default use a conservative clock rate */ 935 bus->reg0 = pin | GMBUS_RATE_100KHZ; 936 937 /* gmbus seems to be broken on i830 */ 938 if (IS_I830(i915)) 939 bus->force_bit = 1; 940 941 intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio)); 942 943 ret = i2c_add_adapter(&bus->adapter); 944 if (ret) { 945 kfree(bus); 946 goto err; 947 } 948 949 i915->display.gmbus.bus[pin] = bus; 950 } 951 952 intel_gmbus_reset(i915); 953 954 return 0; 955 956 err: 957 intel_gmbus_teardown(i915); 958 959 return ret; 960 } 961 962 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915, 963 unsigned int pin) 964 { 965 if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) || 966 !i915->display.gmbus.bus[pin])) 967 return NULL; 968 969 return &i915->display.gmbus.bus[pin]->adapter; 970 } 971 972 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 973 { 974 struct intel_gmbus *bus = to_intel_gmbus(adapter); 975 struct drm_i915_private *i915 = bus->i915; 976 977 mutex_lock(&i915->display.gmbus.mutex); 978 979 bus->force_bit += force_bit ? 1 : -1; 980 drm_dbg_kms(&i915->drm, 981 "%sabling bit-banging on %s. force bit now %d\n", 982 force_bit ? "en" : "dis", adapter->name, 983 bus->force_bit); 984 985 mutex_unlock(&i915->display.gmbus.mutex); 986 } 987 988 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 989 { 990 struct intel_gmbus *bus = to_intel_gmbus(adapter); 991 992 return bus->force_bit; 993 } 994 995 void intel_gmbus_teardown(struct drm_i915_private *i915) 996 { 997 unsigned int pin; 998 999 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) { 1000 struct intel_gmbus *bus; 1001 1002 bus = i915->display.gmbus.bus[pin]; 1003 if (!bus) 1004 continue; 1005 1006 i2c_del_adapter(&bus->adapter); 1007 1008 kfree(bus); 1009 i915->display.gmbus.bus[pin] = NULL; 1010 } 1011 } 1012