1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 #include <drm/i915_drm.h> 31 32 #include "gem/i915_gem_pm.h" 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "intel_display_types.h" 37 #include "intel_frontbuffer.h" 38 #include "intel_overlay.h" 39 40 /* Limits for overlay size. According to intel doc, the real limits are: 41 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 42 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 43 * the mininum of both. */ 44 #define IMAGE_MAX_WIDTH 2048 45 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 46 /* on 830 and 845 these large limits result in the card hanging */ 47 #define IMAGE_MAX_WIDTH_LEGACY 1024 48 #define IMAGE_MAX_HEIGHT_LEGACY 1088 49 50 /* overlay register definitions */ 51 /* OCMD register */ 52 #define OCMD_TILED_SURFACE (0x1<<19) 53 #define OCMD_MIRROR_MASK (0x3<<17) 54 #define OCMD_MIRROR_MODE (0x3<<17) 55 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 56 #define OCMD_MIRROR_VERTICAL (0x2<<17) 57 #define OCMD_MIRROR_BOTH (0x3<<17) 58 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 59 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 60 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 61 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 62 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 63 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 64 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 65 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 66 #define OCMD_YUV_422_PACKED (0x8<<10) 67 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 68 #define OCMD_YUV_420_PLANAR (0xc<<10) 69 #define OCMD_YUV_422_PLANAR (0xd<<10) 70 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 71 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 72 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 73 #define OCMD_BUF_TYPE_MASK (0x1<<5) 74 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 75 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 76 #define OCMD_TEST_MODE (0x1<<4) 77 #define OCMD_BUFFER_SELECT (0x3<<2) 78 #define OCMD_BUFFER0 (0x0<<2) 79 #define OCMD_BUFFER1 (0x1<<2) 80 #define OCMD_FIELD_SELECT (0x1<<2) 81 #define OCMD_FIELD0 (0x0<<1) 82 #define OCMD_FIELD1 (0x1<<1) 83 #define OCMD_ENABLE (0x1<<0) 84 85 /* OCONFIG register */ 86 #define OCONF_PIPE_MASK (0x1<<18) 87 #define OCONF_PIPE_A (0x0<<18) 88 #define OCONF_PIPE_B (0x1<<18) 89 #define OCONF_GAMMA2_ENABLE (0x1<<16) 90 #define OCONF_CSC_MODE_BT601 (0x0<<5) 91 #define OCONF_CSC_MODE_BT709 (0x1<<5) 92 #define OCONF_CSC_BYPASS (0x1<<4) 93 #define OCONF_CC_OUT_8BIT (0x1<<3) 94 #define OCONF_TEST_MODE (0x1<<2) 95 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 96 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 97 98 /* DCLRKM (dst-key) register */ 99 #define DST_KEY_ENABLE (0x1<<31) 100 #define CLK_RGB24_MASK 0x0 101 #define CLK_RGB16_MASK 0x070307 102 #define CLK_RGB15_MASK 0x070707 103 #define CLK_RGB8I_MASK 0xffffff 104 105 #define RGB16_TO_COLORKEY(c) \ 106 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) 107 #define RGB15_TO_COLORKEY(c) \ 108 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) 109 110 /* overlay flip addr flag */ 111 #define OFC_UPDATE 0x1 112 113 /* polyphase filter coefficients */ 114 #define N_HORIZ_Y_TAPS 5 115 #define N_VERT_Y_TAPS 3 116 #define N_HORIZ_UV_TAPS 3 117 #define N_VERT_UV_TAPS 3 118 #define N_PHASES 17 119 #define MAX_TAPS 5 120 121 /* memory bufferd overlay registers */ 122 struct overlay_registers { 123 u32 OBUF_0Y; 124 u32 OBUF_1Y; 125 u32 OBUF_0U; 126 u32 OBUF_0V; 127 u32 OBUF_1U; 128 u32 OBUF_1V; 129 u32 OSTRIDE; 130 u32 YRGB_VPH; 131 u32 UV_VPH; 132 u32 HORZ_PH; 133 u32 INIT_PHS; 134 u32 DWINPOS; 135 u32 DWINSZ; 136 u32 SWIDTH; 137 u32 SWIDTHSW; 138 u32 SHEIGHT; 139 u32 YRGBSCALE; 140 u32 UVSCALE; 141 u32 OCLRC0; 142 u32 OCLRC1; 143 u32 DCLRKV; 144 u32 DCLRKM; 145 u32 SCLRKVH; 146 u32 SCLRKVL; 147 u32 SCLRKEN; 148 u32 OCONFIG; 149 u32 OCMD; 150 u32 RESERVED1; /* 0x6C */ 151 u32 OSTART_0Y; 152 u32 OSTART_1Y; 153 u32 OSTART_0U; 154 u32 OSTART_0V; 155 u32 OSTART_1U; 156 u32 OSTART_1V; 157 u32 OTILEOFF_0Y; 158 u32 OTILEOFF_1Y; 159 u32 OTILEOFF_0U; 160 u32 OTILEOFF_0V; 161 u32 OTILEOFF_1U; 162 u32 OTILEOFF_1V; 163 u32 FASTHSCALE; /* 0xA0 */ 164 u32 UVSCALEV; /* 0xA4 */ 165 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 166 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 167 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 168 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 169 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 170 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 171 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 172 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 173 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 174 }; 175 176 struct intel_overlay { 177 struct drm_i915_private *i915; 178 struct intel_context *context; 179 struct intel_crtc *crtc; 180 struct i915_vma *vma; 181 struct i915_vma *old_vma; 182 bool active; 183 bool pfit_active; 184 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 185 u32 color_key:24; 186 u32 color_key_enabled:1; 187 u32 brightness, contrast, saturation; 188 u32 old_xscale, old_yscale; 189 /* register access */ 190 struct drm_i915_gem_object *reg_bo; 191 struct overlay_registers __iomem *regs; 192 u32 flip_addr; 193 /* flip handling */ 194 struct i915_active last_flip; 195 void (*flip_complete)(struct intel_overlay *ovl); 196 }; 197 198 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 199 bool enable) 200 { 201 struct pci_dev *pdev = dev_priv->drm.pdev; 202 u8 val; 203 204 /* WA_OVERLAY_CLKGATE:alm */ 205 if (enable) 206 I915_WRITE(DSPCLK_GATE_D, 0); 207 else 208 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 209 210 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 211 pci_bus_read_config_byte(pdev->bus, 212 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 213 if (enable) 214 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 215 else 216 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 217 pci_bus_write_config_byte(pdev->bus, 218 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 219 } 220 221 static struct i915_request * 222 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 223 { 224 struct i915_request *rq; 225 int err; 226 227 overlay->flip_complete = fn; 228 229 rq = i915_request_create(overlay->context); 230 if (IS_ERR(rq)) 231 return rq; 232 233 err = i915_active_ref(&overlay->last_flip, rq->timeline, rq); 234 if (err) { 235 i915_request_add(rq); 236 return ERR_PTR(err); 237 } 238 239 return rq; 240 } 241 242 /* overlay needs to be disable in OCMD reg */ 243 static int intel_overlay_on(struct intel_overlay *overlay) 244 { 245 struct drm_i915_private *dev_priv = overlay->i915; 246 struct i915_request *rq; 247 u32 *cs; 248 249 WARN_ON(overlay->active); 250 251 rq = alloc_request(overlay, NULL); 252 if (IS_ERR(rq)) 253 return PTR_ERR(rq); 254 255 cs = intel_ring_begin(rq, 4); 256 if (IS_ERR(cs)) { 257 i915_request_add(rq); 258 return PTR_ERR(cs); 259 } 260 261 overlay->active = true; 262 263 if (IS_I830(dev_priv)) 264 i830_overlay_clock_gating(dev_priv, false); 265 266 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 267 *cs++ = overlay->flip_addr | OFC_UPDATE; 268 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 269 *cs++ = MI_NOOP; 270 intel_ring_advance(rq, cs); 271 272 i915_request_add(rq); 273 274 return i915_active_wait(&overlay->last_flip); 275 } 276 277 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 278 struct i915_vma *vma) 279 { 280 enum pipe pipe = overlay->crtc->pipe; 281 282 WARN_ON(overlay->old_vma); 283 284 intel_frontbuffer_track(overlay->vma ? overlay->vma->obj->frontbuffer : NULL, 285 vma ? vma->obj->frontbuffer : NULL, 286 INTEL_FRONTBUFFER_OVERLAY(pipe)); 287 288 intel_frontbuffer_flip_prepare(overlay->i915, 289 INTEL_FRONTBUFFER_OVERLAY(pipe)); 290 291 overlay->old_vma = overlay->vma; 292 if (vma) 293 overlay->vma = i915_vma_get(vma); 294 else 295 overlay->vma = NULL; 296 } 297 298 /* overlay needs to be enabled in OCMD reg */ 299 static int intel_overlay_continue(struct intel_overlay *overlay, 300 struct i915_vma *vma, 301 bool load_polyphase_filter) 302 { 303 struct drm_i915_private *dev_priv = overlay->i915; 304 struct i915_request *rq; 305 u32 flip_addr = overlay->flip_addr; 306 u32 tmp, *cs; 307 308 WARN_ON(!overlay->active); 309 310 if (load_polyphase_filter) 311 flip_addr |= OFC_UPDATE; 312 313 /* check for underruns */ 314 tmp = I915_READ(DOVSTA); 315 if (tmp & (1 << 17)) 316 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); 317 318 rq = alloc_request(overlay, NULL); 319 if (IS_ERR(rq)) 320 return PTR_ERR(rq); 321 322 cs = intel_ring_begin(rq, 2); 323 if (IS_ERR(cs)) { 324 i915_request_add(rq); 325 return PTR_ERR(cs); 326 } 327 328 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 329 *cs++ = flip_addr; 330 intel_ring_advance(rq, cs); 331 332 intel_overlay_flip_prepare(overlay, vma); 333 i915_request_add(rq); 334 335 return 0; 336 } 337 338 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 339 { 340 struct i915_vma *vma; 341 342 vma = fetch_and_zero(&overlay->old_vma); 343 if (WARN_ON(!vma)) 344 return; 345 346 intel_frontbuffer_flip_complete(overlay->i915, 347 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 348 349 i915_gem_object_unpin_from_display_plane(vma); 350 i915_vma_put(vma); 351 } 352 353 static void 354 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 355 { 356 intel_overlay_release_old_vma(overlay); 357 } 358 359 static void intel_overlay_off_tail(struct intel_overlay *overlay) 360 { 361 struct drm_i915_private *dev_priv = overlay->i915; 362 363 intel_overlay_release_old_vma(overlay); 364 365 overlay->crtc->overlay = NULL; 366 overlay->crtc = NULL; 367 overlay->active = false; 368 369 if (IS_I830(dev_priv)) 370 i830_overlay_clock_gating(dev_priv, true); 371 } 372 373 static void 374 intel_overlay_last_flip_retire(struct i915_active *active) 375 { 376 struct intel_overlay *overlay = 377 container_of(active, typeof(*overlay), last_flip); 378 379 if (overlay->flip_complete) 380 overlay->flip_complete(overlay); 381 } 382 383 /* overlay needs to be disabled in OCMD reg */ 384 static int intel_overlay_off(struct intel_overlay *overlay) 385 { 386 struct i915_request *rq; 387 u32 *cs, flip_addr = overlay->flip_addr; 388 389 WARN_ON(!overlay->active); 390 391 /* According to intel docs the overlay hw may hang (when switching 392 * off) without loading the filter coeffs. It is however unclear whether 393 * this applies to the disabling of the overlay or to the switching off 394 * of the hw. Do it in both cases */ 395 flip_addr |= OFC_UPDATE; 396 397 rq = alloc_request(overlay, intel_overlay_off_tail); 398 if (IS_ERR(rq)) 399 return PTR_ERR(rq); 400 401 cs = intel_ring_begin(rq, 6); 402 if (IS_ERR(cs)) { 403 i915_request_add(rq); 404 return PTR_ERR(cs); 405 } 406 407 /* wait for overlay to go idle */ 408 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 409 *cs++ = flip_addr; 410 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 411 412 /* turn overlay off */ 413 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 414 *cs++ = flip_addr; 415 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 416 417 intel_ring_advance(rq, cs); 418 419 intel_overlay_flip_prepare(overlay, NULL); 420 i915_request_add(rq); 421 422 return i915_active_wait(&overlay->last_flip); 423 } 424 425 /* recover from an interruption due to a signal 426 * We have to be careful not to repeat work forever an make forward progess. */ 427 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 428 { 429 return i915_active_wait(&overlay->last_flip); 430 } 431 432 /* Wait for pending overlay flip and release old frame. 433 * Needs to be called before the overlay register are changed 434 * via intel_overlay_(un)map_regs 435 */ 436 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 437 { 438 struct drm_i915_private *dev_priv = overlay->i915; 439 struct i915_request *rq; 440 u32 *cs; 441 442 lockdep_assert_held(&dev_priv->drm.struct_mutex); 443 444 /* 445 * Only wait if there is actually an old frame to release to 446 * guarantee forward progress. 447 */ 448 if (!overlay->old_vma) 449 return 0; 450 451 if (!(I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 452 intel_overlay_release_old_vid_tail(overlay); 453 return 0; 454 } 455 456 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 457 if (IS_ERR(rq)) 458 return PTR_ERR(rq); 459 460 cs = intel_ring_begin(rq, 2); 461 if (IS_ERR(cs)) { 462 i915_request_add(rq); 463 return PTR_ERR(cs); 464 } 465 466 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 467 *cs++ = MI_NOOP; 468 intel_ring_advance(rq, cs); 469 470 i915_request_add(rq); 471 472 return i915_active_wait(&overlay->last_flip); 473 } 474 475 void intel_overlay_reset(struct drm_i915_private *dev_priv) 476 { 477 struct intel_overlay *overlay = dev_priv->overlay; 478 479 if (!overlay) 480 return; 481 482 overlay->old_xscale = 0; 483 overlay->old_yscale = 0; 484 overlay->crtc = NULL; 485 overlay->active = false; 486 } 487 488 static int packed_depth_bytes(u32 format) 489 { 490 switch (format & I915_OVERLAY_DEPTH_MASK) { 491 case I915_OVERLAY_YUV422: 492 return 4; 493 case I915_OVERLAY_YUV411: 494 /* return 6; not implemented */ 495 default: 496 return -EINVAL; 497 } 498 } 499 500 static int packed_width_bytes(u32 format, short width) 501 { 502 switch (format & I915_OVERLAY_DEPTH_MASK) { 503 case I915_OVERLAY_YUV422: 504 return width << 1; 505 default: 506 return -EINVAL; 507 } 508 } 509 510 static int uv_hsubsampling(u32 format) 511 { 512 switch (format & I915_OVERLAY_DEPTH_MASK) { 513 case I915_OVERLAY_YUV422: 514 case I915_OVERLAY_YUV420: 515 return 2; 516 case I915_OVERLAY_YUV411: 517 case I915_OVERLAY_YUV410: 518 return 4; 519 default: 520 return -EINVAL; 521 } 522 } 523 524 static int uv_vsubsampling(u32 format) 525 { 526 switch (format & I915_OVERLAY_DEPTH_MASK) { 527 case I915_OVERLAY_YUV420: 528 case I915_OVERLAY_YUV410: 529 return 2; 530 case I915_OVERLAY_YUV422: 531 case I915_OVERLAY_YUV411: 532 return 1; 533 default: 534 return -EINVAL; 535 } 536 } 537 538 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 539 { 540 u32 sw; 541 542 if (IS_GEN(dev_priv, 2)) 543 sw = ALIGN((offset & 31) + width, 32); 544 else 545 sw = ALIGN((offset & 63) + width, 64); 546 547 if (sw == 0) 548 return 0; 549 550 return (sw - 32) >> 3; 551 } 552 553 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 554 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 555 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 556 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 557 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 558 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 559 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 560 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 561 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 562 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 563 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 564 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 565 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 566 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 567 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 568 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 569 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 570 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 571 }; 572 573 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 574 [ 0] = { 0x3000, 0x1800, 0x1800, }, 575 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 576 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 577 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 578 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 579 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 580 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 581 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 582 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 583 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 584 [10] = { 0xb100, 0x1eb8, 0x3620, }, 585 [11] = { 0xb100, 0x1f18, 0x34a0, }, 586 [12] = { 0xb100, 0x1f68, 0x3360, }, 587 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 588 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 589 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 590 [16] = { 0x3000, 0x0800, 0x3000, }, 591 }; 592 593 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 594 { 595 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 596 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 597 sizeof(uv_static_hcoeffs)); 598 } 599 600 static bool update_scaling_factors(struct intel_overlay *overlay, 601 struct overlay_registers __iomem *regs, 602 struct drm_intel_overlay_put_image *params) 603 { 604 /* fixed point with a 12 bit shift */ 605 u32 xscale, yscale, xscale_UV, yscale_UV; 606 #define FP_SHIFT 12 607 #define FRACT_MASK 0xfff 608 bool scale_changed = false; 609 int uv_hscale = uv_hsubsampling(params->flags); 610 int uv_vscale = uv_vsubsampling(params->flags); 611 612 if (params->dst_width > 1) 613 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 614 params->dst_width; 615 else 616 xscale = 1 << FP_SHIFT; 617 618 if (params->dst_height > 1) 619 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 620 params->dst_height; 621 else 622 yscale = 1 << FP_SHIFT; 623 624 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 625 xscale_UV = xscale/uv_hscale; 626 yscale_UV = yscale/uv_vscale; 627 /* make the Y scale to UV scale ratio an exact multiply */ 628 xscale = xscale_UV * uv_hscale; 629 yscale = yscale_UV * uv_vscale; 630 /*} else { 631 xscale_UV = 0; 632 yscale_UV = 0; 633 }*/ 634 635 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 636 scale_changed = true; 637 overlay->old_xscale = xscale; 638 overlay->old_yscale = yscale; 639 640 iowrite32(((yscale & FRACT_MASK) << 20) | 641 ((xscale >> FP_SHIFT) << 16) | 642 ((xscale & FRACT_MASK) << 3), 643 ®s->YRGBSCALE); 644 645 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 646 ((xscale_UV >> FP_SHIFT) << 16) | 647 ((xscale_UV & FRACT_MASK) << 3), 648 ®s->UVSCALE); 649 650 iowrite32((((yscale >> FP_SHIFT) << 16) | 651 ((yscale_UV >> FP_SHIFT) << 0)), 652 ®s->UVSCALEV); 653 654 if (scale_changed) 655 update_polyphase_filter(regs); 656 657 return scale_changed; 658 } 659 660 static void update_colorkey(struct intel_overlay *overlay, 661 struct overlay_registers __iomem *regs) 662 { 663 const struct intel_plane_state *state = 664 to_intel_plane_state(overlay->crtc->base.primary->state); 665 u32 key = overlay->color_key; 666 u32 format = 0; 667 u32 flags = 0; 668 669 if (overlay->color_key_enabled) 670 flags |= DST_KEY_ENABLE; 671 672 if (state->base.visible) 673 format = state->base.fb->format->format; 674 675 switch (format) { 676 case DRM_FORMAT_C8: 677 key = 0; 678 flags |= CLK_RGB8I_MASK; 679 break; 680 case DRM_FORMAT_XRGB1555: 681 key = RGB15_TO_COLORKEY(key); 682 flags |= CLK_RGB15_MASK; 683 break; 684 case DRM_FORMAT_RGB565: 685 key = RGB16_TO_COLORKEY(key); 686 flags |= CLK_RGB16_MASK; 687 break; 688 default: 689 flags |= CLK_RGB24_MASK; 690 break; 691 } 692 693 iowrite32(key, ®s->DCLRKV); 694 iowrite32(flags, ®s->DCLRKM); 695 } 696 697 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 698 { 699 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 700 701 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 702 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 703 case I915_OVERLAY_YUV422: 704 cmd |= OCMD_YUV_422_PLANAR; 705 break; 706 case I915_OVERLAY_YUV420: 707 cmd |= OCMD_YUV_420_PLANAR; 708 break; 709 case I915_OVERLAY_YUV411: 710 case I915_OVERLAY_YUV410: 711 cmd |= OCMD_YUV_410_PLANAR; 712 break; 713 } 714 } else { /* YUV packed */ 715 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 716 case I915_OVERLAY_YUV422: 717 cmd |= OCMD_YUV_422_PACKED; 718 break; 719 case I915_OVERLAY_YUV411: 720 cmd |= OCMD_YUV_411_PACKED; 721 break; 722 } 723 724 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 725 case I915_OVERLAY_NO_SWAP: 726 break; 727 case I915_OVERLAY_UV_SWAP: 728 cmd |= OCMD_UV_SWAP; 729 break; 730 case I915_OVERLAY_Y_SWAP: 731 cmd |= OCMD_Y_SWAP; 732 break; 733 case I915_OVERLAY_Y_AND_UV_SWAP: 734 cmd |= OCMD_Y_AND_UV_SWAP; 735 break; 736 } 737 } 738 739 return cmd; 740 } 741 742 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 743 struct drm_i915_gem_object *new_bo, 744 struct drm_intel_overlay_put_image *params) 745 { 746 struct overlay_registers __iomem *regs = overlay->regs; 747 struct drm_i915_private *dev_priv = overlay->i915; 748 u32 swidth, swidthsw, sheight, ostride; 749 enum pipe pipe = overlay->crtc->pipe; 750 bool scale_changed = false; 751 struct i915_vma *vma; 752 int ret, tmp_width; 753 754 lockdep_assert_held(&dev_priv->drm.struct_mutex); 755 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 756 757 ret = intel_overlay_release_old_vid(overlay); 758 if (ret != 0) 759 return ret; 760 761 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 762 763 i915_gem_object_lock(new_bo); 764 vma = i915_gem_object_pin_to_display_plane(new_bo, 765 0, NULL, PIN_MAPPABLE); 766 i915_gem_object_unlock(new_bo); 767 if (IS_ERR(vma)) { 768 ret = PTR_ERR(vma); 769 goto out_pin_section; 770 } 771 intel_frontbuffer_flush(new_bo->frontbuffer, ORIGIN_DIRTYFB); 772 773 if (!overlay->active) { 774 u32 oconfig; 775 776 oconfig = OCONF_CC_OUT_8BIT; 777 if (IS_GEN(dev_priv, 4)) 778 oconfig |= OCONF_CSC_MODE_BT709; 779 oconfig |= pipe == 0 ? 780 OCONF_PIPE_A : OCONF_PIPE_B; 781 iowrite32(oconfig, ®s->OCONFIG); 782 783 ret = intel_overlay_on(overlay); 784 if (ret != 0) 785 goto out_unpin; 786 } 787 788 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 789 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 790 791 if (params->flags & I915_OVERLAY_YUV_PACKED) 792 tmp_width = packed_width_bytes(params->flags, 793 params->src_width); 794 else 795 tmp_width = params->src_width; 796 797 swidth = params->src_width; 798 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 799 sheight = params->src_height; 800 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 801 ostride = params->stride_Y; 802 803 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 804 int uv_hscale = uv_hsubsampling(params->flags); 805 int uv_vscale = uv_vsubsampling(params->flags); 806 u32 tmp_U, tmp_V; 807 808 swidth |= (params->src_width / uv_hscale) << 16; 809 sheight |= (params->src_height / uv_vscale) << 16; 810 811 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 812 params->src_width / uv_hscale); 813 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 814 params->src_width / uv_hscale); 815 swidthsw |= max(tmp_U, tmp_V) << 16; 816 817 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 818 ®s->OBUF_0U); 819 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 820 ®s->OBUF_0V); 821 822 ostride |= params->stride_UV << 16; 823 } 824 825 iowrite32(swidth, ®s->SWIDTH); 826 iowrite32(swidthsw, ®s->SWIDTHSW); 827 iowrite32(sheight, ®s->SHEIGHT); 828 iowrite32(ostride, ®s->OSTRIDE); 829 830 scale_changed = update_scaling_factors(overlay, regs, params); 831 832 update_colorkey(overlay, regs); 833 834 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 835 836 ret = intel_overlay_continue(overlay, vma, scale_changed); 837 if (ret) 838 goto out_unpin; 839 840 return 0; 841 842 out_unpin: 843 i915_gem_object_unpin_from_display_plane(vma); 844 out_pin_section: 845 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 846 847 return ret; 848 } 849 850 int intel_overlay_switch_off(struct intel_overlay *overlay) 851 { 852 struct drm_i915_private *dev_priv = overlay->i915; 853 int ret; 854 855 lockdep_assert_held(&dev_priv->drm.struct_mutex); 856 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 857 858 ret = intel_overlay_recover_from_interrupt(overlay); 859 if (ret != 0) 860 return ret; 861 862 if (!overlay->active) 863 return 0; 864 865 ret = intel_overlay_release_old_vid(overlay); 866 if (ret != 0) 867 return ret; 868 869 iowrite32(0, &overlay->regs->OCMD); 870 871 return intel_overlay_off(overlay); 872 } 873 874 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 875 struct intel_crtc *crtc) 876 { 877 if (!crtc->active) 878 return -EINVAL; 879 880 /* can't use the overlay with double wide pipe */ 881 if (crtc->config->double_wide) 882 return -EINVAL; 883 884 return 0; 885 } 886 887 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 888 { 889 struct drm_i915_private *dev_priv = overlay->i915; 890 u32 pfit_control = I915_READ(PFIT_CONTROL); 891 u32 ratio; 892 893 /* XXX: This is not the same logic as in the xorg driver, but more in 894 * line with the intel documentation for the i965 895 */ 896 if (INTEL_GEN(dev_priv) >= 4) { 897 /* on i965 use the PGM reg to read out the autoscaler values */ 898 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 899 } else { 900 if (pfit_control & VERT_AUTO_SCALE) 901 ratio = I915_READ(PFIT_AUTO_RATIOS); 902 else 903 ratio = I915_READ(PFIT_PGM_RATIOS); 904 ratio >>= PFIT_VERT_SCALE_SHIFT; 905 } 906 907 overlay->pfit_vscale_ratio = ratio; 908 } 909 910 static int check_overlay_dst(struct intel_overlay *overlay, 911 struct drm_intel_overlay_put_image *rec) 912 { 913 const struct intel_crtc_state *pipe_config = 914 overlay->crtc->config; 915 916 if (rec->dst_x < pipe_config->pipe_src_w && 917 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 918 rec->dst_y < pipe_config->pipe_src_h && 919 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 920 return 0; 921 else 922 return -EINVAL; 923 } 924 925 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 926 { 927 u32 tmp; 928 929 /* downscaling limit is 8.0 */ 930 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 931 if (tmp > 7) 932 return -EINVAL; 933 934 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 935 if (tmp > 7) 936 return -EINVAL; 937 938 return 0; 939 } 940 941 static int check_overlay_src(struct drm_i915_private *dev_priv, 942 struct drm_intel_overlay_put_image *rec, 943 struct drm_i915_gem_object *new_bo) 944 { 945 int uv_hscale = uv_hsubsampling(rec->flags); 946 int uv_vscale = uv_vsubsampling(rec->flags); 947 u32 stride_mask; 948 int depth; 949 u32 tmp; 950 951 /* check src dimensions */ 952 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 953 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 954 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 955 return -EINVAL; 956 } else { 957 if (rec->src_height > IMAGE_MAX_HEIGHT || 958 rec->src_width > IMAGE_MAX_WIDTH) 959 return -EINVAL; 960 } 961 962 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 963 if (rec->src_height < N_VERT_Y_TAPS*4 || 964 rec->src_width < N_HORIZ_Y_TAPS*4) 965 return -EINVAL; 966 967 /* check alignment constraints */ 968 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 969 case I915_OVERLAY_RGB: 970 /* not implemented */ 971 return -EINVAL; 972 973 case I915_OVERLAY_YUV_PACKED: 974 if (uv_vscale != 1) 975 return -EINVAL; 976 977 depth = packed_depth_bytes(rec->flags); 978 if (depth < 0) 979 return depth; 980 981 /* ignore UV planes */ 982 rec->stride_UV = 0; 983 rec->offset_U = 0; 984 rec->offset_V = 0; 985 /* check pixel alignment */ 986 if (rec->offset_Y % depth) 987 return -EINVAL; 988 break; 989 990 case I915_OVERLAY_YUV_PLANAR: 991 if (uv_vscale < 0 || uv_hscale < 0) 992 return -EINVAL; 993 /* no offset restrictions for planar formats */ 994 break; 995 996 default: 997 return -EINVAL; 998 } 999 1000 if (rec->src_width % uv_hscale) 1001 return -EINVAL; 1002 1003 /* stride checking */ 1004 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1005 stride_mask = 255; 1006 else 1007 stride_mask = 63; 1008 1009 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1010 return -EINVAL; 1011 if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) 1012 return -EINVAL; 1013 1014 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1015 4096 : 8192; 1016 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1017 return -EINVAL; 1018 1019 /* check buffer dimensions */ 1020 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1021 case I915_OVERLAY_RGB: 1022 case I915_OVERLAY_YUV_PACKED: 1023 /* always 4 Y values per depth pixels */ 1024 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1025 return -EINVAL; 1026 1027 tmp = rec->stride_Y*rec->src_height; 1028 if (rec->offset_Y + tmp > new_bo->base.size) 1029 return -EINVAL; 1030 break; 1031 1032 case I915_OVERLAY_YUV_PLANAR: 1033 if (rec->src_width > rec->stride_Y) 1034 return -EINVAL; 1035 if (rec->src_width/uv_hscale > rec->stride_UV) 1036 return -EINVAL; 1037 1038 tmp = rec->stride_Y * rec->src_height; 1039 if (rec->offset_Y + tmp > new_bo->base.size) 1040 return -EINVAL; 1041 1042 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1043 if (rec->offset_U + tmp > new_bo->base.size || 1044 rec->offset_V + tmp > new_bo->base.size) 1045 return -EINVAL; 1046 break; 1047 } 1048 1049 return 0; 1050 } 1051 1052 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1053 struct drm_file *file_priv) 1054 { 1055 struct drm_intel_overlay_put_image *params = data; 1056 struct drm_i915_private *dev_priv = to_i915(dev); 1057 struct intel_overlay *overlay; 1058 struct drm_crtc *drmmode_crtc; 1059 struct intel_crtc *crtc; 1060 struct drm_i915_gem_object *new_bo; 1061 int ret; 1062 1063 overlay = dev_priv->overlay; 1064 if (!overlay) { 1065 DRM_DEBUG("userspace bug: no overlay\n"); 1066 return -ENODEV; 1067 } 1068 1069 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1070 drm_modeset_lock_all(dev); 1071 mutex_lock(&dev->struct_mutex); 1072 1073 ret = intel_overlay_switch_off(overlay); 1074 1075 mutex_unlock(&dev->struct_mutex); 1076 drm_modeset_unlock_all(dev); 1077 1078 return ret; 1079 } 1080 1081 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1082 if (!drmmode_crtc) 1083 return -ENOENT; 1084 crtc = to_intel_crtc(drmmode_crtc); 1085 1086 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1087 if (!new_bo) 1088 return -ENOENT; 1089 1090 drm_modeset_lock_all(dev); 1091 mutex_lock(&dev->struct_mutex); 1092 1093 if (i915_gem_object_is_tiled(new_bo)) { 1094 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); 1095 ret = -EINVAL; 1096 goto out_unlock; 1097 } 1098 1099 ret = intel_overlay_recover_from_interrupt(overlay); 1100 if (ret != 0) 1101 goto out_unlock; 1102 1103 if (overlay->crtc != crtc) { 1104 ret = intel_overlay_switch_off(overlay); 1105 if (ret != 0) 1106 goto out_unlock; 1107 1108 ret = check_overlay_possible_on_crtc(overlay, crtc); 1109 if (ret != 0) 1110 goto out_unlock; 1111 1112 overlay->crtc = crtc; 1113 crtc->overlay = overlay; 1114 1115 /* line too wide, i.e. one-line-mode */ 1116 if (crtc->config->pipe_src_w > 1024 && 1117 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1118 overlay->pfit_active = true; 1119 update_pfit_vscale_ratio(overlay); 1120 } else 1121 overlay->pfit_active = false; 1122 } 1123 1124 ret = check_overlay_dst(overlay, params); 1125 if (ret != 0) 1126 goto out_unlock; 1127 1128 if (overlay->pfit_active) { 1129 params->dst_y = (((u32)params->dst_y << 12) / 1130 overlay->pfit_vscale_ratio); 1131 /* shifting right rounds downwards, so add 1 */ 1132 params->dst_height = (((u32)params->dst_height << 12) / 1133 overlay->pfit_vscale_ratio) + 1; 1134 } 1135 1136 if (params->src_scan_height > params->src_height || 1137 params->src_scan_width > params->src_width) { 1138 ret = -EINVAL; 1139 goto out_unlock; 1140 } 1141 1142 ret = check_overlay_src(dev_priv, params, new_bo); 1143 if (ret != 0) 1144 goto out_unlock; 1145 1146 /* Check scaling after src size to prevent a divide-by-zero. */ 1147 ret = check_overlay_scaling(params); 1148 if (ret != 0) 1149 goto out_unlock; 1150 1151 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1152 if (ret != 0) 1153 goto out_unlock; 1154 1155 mutex_unlock(&dev->struct_mutex); 1156 drm_modeset_unlock_all(dev); 1157 i915_gem_object_put(new_bo); 1158 1159 return 0; 1160 1161 out_unlock: 1162 mutex_unlock(&dev->struct_mutex); 1163 drm_modeset_unlock_all(dev); 1164 i915_gem_object_put(new_bo); 1165 1166 return ret; 1167 } 1168 1169 static void update_reg_attrs(struct intel_overlay *overlay, 1170 struct overlay_registers __iomem *regs) 1171 { 1172 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1173 ®s->OCLRC0); 1174 iowrite32(overlay->saturation, ®s->OCLRC1); 1175 } 1176 1177 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1178 { 1179 int i; 1180 1181 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1182 return false; 1183 1184 for (i = 0; i < 3; i++) { 1185 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1186 return false; 1187 } 1188 1189 return true; 1190 } 1191 1192 static bool check_gamma5_errata(u32 gamma5) 1193 { 1194 int i; 1195 1196 for (i = 0; i < 3; i++) { 1197 if (((gamma5 >> i*8) & 0xff) == 0x80) 1198 return false; 1199 } 1200 1201 return true; 1202 } 1203 1204 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1205 { 1206 if (!check_gamma_bounds(0, attrs->gamma0) || 1207 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1208 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1209 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1210 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1211 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1212 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1213 return -EINVAL; 1214 1215 if (!check_gamma5_errata(attrs->gamma5)) 1216 return -EINVAL; 1217 1218 return 0; 1219 } 1220 1221 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1222 struct drm_file *file_priv) 1223 { 1224 struct drm_intel_overlay_attrs *attrs = data; 1225 struct drm_i915_private *dev_priv = to_i915(dev); 1226 struct intel_overlay *overlay; 1227 int ret; 1228 1229 overlay = dev_priv->overlay; 1230 if (!overlay) { 1231 DRM_DEBUG("userspace bug: no overlay\n"); 1232 return -ENODEV; 1233 } 1234 1235 drm_modeset_lock_all(dev); 1236 mutex_lock(&dev->struct_mutex); 1237 1238 ret = -EINVAL; 1239 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1240 attrs->color_key = overlay->color_key; 1241 attrs->brightness = overlay->brightness; 1242 attrs->contrast = overlay->contrast; 1243 attrs->saturation = overlay->saturation; 1244 1245 if (!IS_GEN(dev_priv, 2)) { 1246 attrs->gamma0 = I915_READ(OGAMC0); 1247 attrs->gamma1 = I915_READ(OGAMC1); 1248 attrs->gamma2 = I915_READ(OGAMC2); 1249 attrs->gamma3 = I915_READ(OGAMC3); 1250 attrs->gamma4 = I915_READ(OGAMC4); 1251 attrs->gamma5 = I915_READ(OGAMC5); 1252 } 1253 } else { 1254 if (attrs->brightness < -128 || attrs->brightness > 127) 1255 goto out_unlock; 1256 if (attrs->contrast > 255) 1257 goto out_unlock; 1258 if (attrs->saturation > 1023) 1259 goto out_unlock; 1260 1261 overlay->color_key = attrs->color_key; 1262 overlay->brightness = attrs->brightness; 1263 overlay->contrast = attrs->contrast; 1264 overlay->saturation = attrs->saturation; 1265 1266 update_reg_attrs(overlay, overlay->regs); 1267 1268 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1269 if (IS_GEN(dev_priv, 2)) 1270 goto out_unlock; 1271 1272 if (overlay->active) { 1273 ret = -EBUSY; 1274 goto out_unlock; 1275 } 1276 1277 ret = check_gamma(attrs); 1278 if (ret) 1279 goto out_unlock; 1280 1281 I915_WRITE(OGAMC0, attrs->gamma0); 1282 I915_WRITE(OGAMC1, attrs->gamma1); 1283 I915_WRITE(OGAMC2, attrs->gamma2); 1284 I915_WRITE(OGAMC3, attrs->gamma3); 1285 I915_WRITE(OGAMC4, attrs->gamma4); 1286 I915_WRITE(OGAMC5, attrs->gamma5); 1287 } 1288 } 1289 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1290 1291 ret = 0; 1292 out_unlock: 1293 mutex_unlock(&dev->struct_mutex); 1294 drm_modeset_unlock_all(dev); 1295 1296 return ret; 1297 } 1298 1299 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1300 { 1301 struct drm_i915_private *i915 = overlay->i915; 1302 struct drm_i915_gem_object *obj; 1303 struct i915_vma *vma; 1304 int err; 1305 1306 mutex_lock(&i915->drm.struct_mutex); 1307 1308 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1309 if (obj == NULL) 1310 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1311 if (IS_ERR(obj)) { 1312 err = PTR_ERR(obj); 1313 goto err_unlock; 1314 } 1315 1316 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1317 if (IS_ERR(vma)) { 1318 err = PTR_ERR(vma); 1319 goto err_put_bo; 1320 } 1321 1322 if (use_phys) 1323 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1324 else 1325 overlay->flip_addr = i915_ggtt_offset(vma); 1326 overlay->regs = i915_vma_pin_iomap(vma); 1327 i915_vma_unpin(vma); 1328 1329 if (IS_ERR(overlay->regs)) { 1330 err = PTR_ERR(overlay->regs); 1331 goto err_put_bo; 1332 } 1333 1334 overlay->reg_bo = obj; 1335 mutex_unlock(&i915->drm.struct_mutex); 1336 return 0; 1337 1338 err_put_bo: 1339 i915_gem_object_put(obj); 1340 err_unlock: 1341 mutex_unlock(&i915->drm.struct_mutex); 1342 return err; 1343 } 1344 1345 void intel_overlay_setup(struct drm_i915_private *dev_priv) 1346 { 1347 struct intel_overlay *overlay; 1348 int ret; 1349 1350 if (!HAS_OVERLAY(dev_priv)) 1351 return; 1352 1353 if (!HAS_ENGINE(dev_priv, RCS0)) 1354 return; 1355 1356 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1357 if (!overlay) 1358 return; 1359 1360 overlay->i915 = dev_priv; 1361 overlay->context = dev_priv->engine[RCS0]->kernel_context; 1362 GEM_BUG_ON(!overlay->context); 1363 1364 overlay->color_key = 0x0101fe; 1365 overlay->color_key_enabled = true; 1366 overlay->brightness = -19; 1367 overlay->contrast = 75; 1368 overlay->saturation = 146; 1369 1370 i915_active_init(dev_priv, 1371 &overlay->last_flip, 1372 NULL, intel_overlay_last_flip_retire); 1373 1374 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1375 if (ret) 1376 goto out_free; 1377 1378 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1379 update_polyphase_filter(overlay->regs); 1380 update_reg_attrs(overlay, overlay->regs); 1381 1382 dev_priv->overlay = overlay; 1383 DRM_INFO("Initialized overlay support.\n"); 1384 return; 1385 1386 out_free: 1387 kfree(overlay); 1388 } 1389 1390 void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1391 { 1392 struct intel_overlay *overlay; 1393 1394 overlay = fetch_and_zero(&dev_priv->overlay); 1395 if (!overlay) 1396 return; 1397 1398 /* 1399 * The bo's should be free'd by the generic code already. 1400 * Furthermore modesetting teardown happens beforehand so the 1401 * hardware should be off already. 1402 */ 1403 WARN_ON(overlay->active); 1404 1405 i915_gem_object_put(overlay->reg_bo); 1406 i915_active_fini(&overlay->last_flip); 1407 1408 kfree(overlay); 1409 } 1410 1411 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1412 1413 struct intel_overlay_error_state { 1414 struct overlay_registers regs; 1415 unsigned long base; 1416 u32 dovsta; 1417 u32 isr; 1418 }; 1419 1420 struct intel_overlay_error_state * 1421 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1422 { 1423 struct intel_overlay *overlay = dev_priv->overlay; 1424 struct intel_overlay_error_state *error; 1425 1426 if (!overlay || !overlay->active) 1427 return NULL; 1428 1429 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1430 if (error == NULL) 1431 return NULL; 1432 1433 error->dovsta = I915_READ(DOVSTA); 1434 error->isr = I915_READ(GEN2_ISR); 1435 error->base = overlay->flip_addr; 1436 1437 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1438 1439 return error; 1440 } 1441 1442 void 1443 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1444 struct intel_overlay_error_state *error) 1445 { 1446 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1447 error->dovsta, error->isr); 1448 i915_error_printf(m, " Register file at 0x%08lx:\n", 1449 error->base); 1450 1451 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1452 P(OBUF_0Y); 1453 P(OBUF_1Y); 1454 P(OBUF_0U); 1455 P(OBUF_0V); 1456 P(OBUF_1U); 1457 P(OBUF_1V); 1458 P(OSTRIDE); 1459 P(YRGB_VPH); 1460 P(UV_VPH); 1461 P(HORZ_PH); 1462 P(INIT_PHS); 1463 P(DWINPOS); 1464 P(DWINSZ); 1465 P(SWIDTH); 1466 P(SWIDTHSW); 1467 P(SHEIGHT); 1468 P(YRGBSCALE); 1469 P(UVSCALE); 1470 P(OCLRC0); 1471 P(OCLRC1); 1472 P(DCLRKV); 1473 P(DCLRKM); 1474 P(SCLRKVH); 1475 P(SCLRKVL); 1476 P(SCLRKEN); 1477 P(OCONFIG); 1478 P(OCMD); 1479 P(OSTART_0Y); 1480 P(OSTART_1Y); 1481 P(OSTART_0U); 1482 P(OSTART_0V); 1483 P(OSTART_1U); 1484 P(OSTART_1V); 1485 P(OTILEOFF_0Y); 1486 P(OTILEOFF_1Y); 1487 P(OTILEOFF_0U); 1488 P(OTILEOFF_0V); 1489 P(OTILEOFF_1U); 1490 P(OTILEOFF_1V); 1491 P(FASTHSCALE); 1492 P(UVSCALEV); 1493 #undef P 1494 } 1495 1496 #endif 1497