1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_damage_helper.h> 26 27 #include "display/intel_dp.h" 28 29 #include "i915_drv.h" 30 #include "intel_atomic.h" 31 #include "intel_crtc.h" 32 #include "intel_de.h" 33 #include "intel_display_types.h" 34 #include "intel_dp_aux.h" 35 #include "intel_hdmi.h" 36 #include "intel_psr.h" 37 #include "intel_snps_phy.h" 38 #include "skl_universal_plane.h" 39 40 /** 41 * DOC: Panel Self Refresh (PSR/SRD) 42 * 43 * Since Haswell Display controller supports Panel Self-Refresh on display 44 * panels witch have a remote frame buffer (RFB) implemented according to PSR 45 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 46 * when system is idle but display is on as it eliminates display refresh 47 * request to DDR memory completely as long as the frame buffer for that 48 * display is unchanged. 49 * 50 * Panel Self Refresh must be supported by both Hardware (source) and 51 * Panel (sink). 52 * 53 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 54 * to power down the link and memory controller. For DSI panels the same idea 55 * is called "manual mode". 56 * 57 * The implementation uses the hardware-based PSR support which automatically 58 * enters/exits self-refresh mode. The hardware takes care of sending the 59 * required DP aux message and could even retrain the link (that part isn't 60 * enabled yet though). The hardware also keeps track of any frontbuffer 61 * changes to know when to exit self-refresh mode again. Unfortunately that 62 * part doesn't work too well, hence why the i915 PSR support uses the 63 * software frontbuffer tracking to make sure it doesn't miss a screen 64 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 65 * get called by the frontbuffer tracking code. Note that because of locking 66 * issues the self-refresh re-enable code is done from a work queue, which 67 * must be correctly synchronized/cancelled when shutting down the pipe." 68 * 69 * DC3CO (DC3 clock off) 70 * 71 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 72 * clock off automatically during PSR2 idle state. 73 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 74 * entry/exit allows the HW to enter a low-power state even when page flipping 75 * periodically (for instance a 30fps video playback scenario). 76 * 77 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 78 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 79 * frames, if no other flip occurs and the function above is executed, DC3CO is 80 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 81 * of another flip. 82 * Front buffer modifications do not trigger DC3CO activation on purpose as it 83 * would bring a lot of complexity and most of the moderns systems will only 84 * use page flips. 85 */ 86 87 static bool psr_global_enabled(struct intel_dp *intel_dp) 88 { 89 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 90 91 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 92 case I915_PSR_DEBUG_DEFAULT: 93 return i915->params.enable_psr; 94 case I915_PSR_DEBUG_DISABLE: 95 return false; 96 default: 97 return true; 98 } 99 } 100 101 static bool psr2_global_enabled(struct intel_dp *intel_dp) 102 { 103 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 104 case I915_PSR_DEBUG_DISABLE: 105 case I915_PSR_DEBUG_FORCE_PSR1: 106 return false; 107 default: 108 return true; 109 } 110 } 111 112 static void psr_irq_control(struct intel_dp *intel_dp) 113 { 114 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 115 enum transcoder trans_shift; 116 i915_reg_t imr_reg; 117 u32 mask, val; 118 119 /* 120 * gen12+ has registers relative to transcoder and one per transcoder 121 * using the same bit definition: handle it as TRANSCODER_EDP to force 122 * 0 shift in bit definition 123 */ 124 if (DISPLAY_VER(dev_priv) >= 12) { 125 trans_shift = 0; 126 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 127 } else { 128 trans_shift = intel_dp->psr.transcoder; 129 imr_reg = EDP_PSR_IMR; 130 } 131 132 mask = EDP_PSR_ERROR(trans_shift); 133 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 134 mask |= EDP_PSR_POST_EXIT(trans_shift) | 135 EDP_PSR_PRE_ENTRY(trans_shift); 136 137 /* Warning: it is masking/setting reserved bits too */ 138 val = intel_de_read(dev_priv, imr_reg); 139 val &= ~EDP_PSR_TRANS_MASK(trans_shift); 140 val |= ~mask; 141 intel_de_write(dev_priv, imr_reg, val); 142 } 143 144 static void psr_event_print(struct drm_i915_private *i915, 145 u32 val, bool psr2_enabled) 146 { 147 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 148 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 149 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 150 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 151 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 152 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 153 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 154 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 155 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 156 if (val & PSR_EVENT_GRAPHICS_RESET) 157 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 158 if (val & PSR_EVENT_PCH_INTERRUPT) 159 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 160 if (val & PSR_EVENT_MEMORY_UP) 161 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 162 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 163 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 164 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 165 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 166 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 167 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 168 if (val & PSR_EVENT_REGISTER_UPDATE) 169 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 170 if (val & PSR_EVENT_HDCP_ENABLE) 171 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 172 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 173 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 174 if (val & PSR_EVENT_VBI_ENABLE) 175 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 176 if (val & PSR_EVENT_LPSP_MODE_EXIT) 177 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 178 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 179 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 180 } 181 182 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 183 { 184 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 185 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 186 ktime_t time_ns = ktime_get(); 187 enum transcoder trans_shift; 188 i915_reg_t imr_reg; 189 190 if (DISPLAY_VER(dev_priv) >= 12) { 191 trans_shift = 0; 192 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); 193 } else { 194 trans_shift = intel_dp->psr.transcoder; 195 imr_reg = EDP_PSR_IMR; 196 } 197 198 if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { 199 intel_dp->psr.last_entry_attempt = time_ns; 200 drm_dbg_kms(&dev_priv->drm, 201 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 202 transcoder_name(cpu_transcoder)); 203 } 204 205 if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { 206 intel_dp->psr.last_exit = time_ns; 207 drm_dbg_kms(&dev_priv->drm, 208 "[transcoder %s] PSR exit completed\n", 209 transcoder_name(cpu_transcoder)); 210 211 if (DISPLAY_VER(dev_priv) >= 9) { 212 u32 val = intel_de_read(dev_priv, 213 PSR_EVENT(cpu_transcoder)); 214 bool psr2_enabled = intel_dp->psr.psr2_enabled; 215 216 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 217 val); 218 psr_event_print(dev_priv, val, psr2_enabled); 219 } 220 } 221 222 if (psr_iir & EDP_PSR_ERROR(trans_shift)) { 223 u32 val; 224 225 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 226 transcoder_name(cpu_transcoder)); 227 228 intel_dp->psr.irq_aux_error = true; 229 230 /* 231 * If this interruption is not masked it will keep 232 * interrupting so fast that it prevents the scheduled 233 * work to run. 234 * Also after a PSR error, we don't want to arm PSR 235 * again so we don't care about unmask the interruption 236 * or unset irq_aux_error. 237 */ 238 val = intel_de_read(dev_priv, imr_reg); 239 val |= EDP_PSR_ERROR(trans_shift); 240 intel_de_write(dev_priv, imr_reg, val); 241 242 schedule_work(&intel_dp->psr.work); 243 } 244 } 245 246 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 247 { 248 u8 alpm_caps = 0; 249 250 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 251 &alpm_caps) != 1) 252 return false; 253 return alpm_caps & DP_ALPM_CAP; 254 } 255 256 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 257 { 258 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 259 u8 val = 8; /* assume the worst if we can't read the value */ 260 261 if (drm_dp_dpcd_readb(&intel_dp->aux, 262 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 263 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 264 else 265 drm_dbg_kms(&i915->drm, 266 "Unable to get sink synchronization latency, assuming 8 frames\n"); 267 return val; 268 } 269 270 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 271 { 272 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 273 ssize_t r; 274 u16 w; 275 u8 y; 276 277 /* If sink don't have specific granularity requirements set legacy ones */ 278 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 279 /* As PSR2 HW sends full lines, we do not care about x granularity */ 280 w = 4; 281 y = 4; 282 goto exit; 283 } 284 285 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); 286 if (r != 2) 287 drm_dbg_kms(&i915->drm, 288 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 289 /* 290 * Spec says that if the value read is 0 the default granularity should 291 * be used instead. 292 */ 293 if (r != 2 || w == 0) 294 w = 4; 295 296 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 297 if (r != 1) { 298 drm_dbg_kms(&i915->drm, 299 "Unable to read DP_PSR2_SU_Y_GRANULARITY\n"); 300 y = 4; 301 } 302 if (y == 0) 303 y = 1; 304 305 exit: 306 intel_dp->psr.su_w_granularity = w; 307 intel_dp->psr.su_y_granularity = y; 308 } 309 310 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 311 { 312 struct drm_i915_private *dev_priv = 313 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 314 315 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 316 sizeof(intel_dp->psr_dpcd)); 317 318 if (!intel_dp->psr_dpcd[0]) 319 return; 320 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 321 intel_dp->psr_dpcd[0]); 322 323 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 324 drm_dbg_kms(&dev_priv->drm, 325 "PSR support not currently available for this panel\n"); 326 return; 327 } 328 329 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 330 drm_dbg_kms(&dev_priv->drm, 331 "Panel lacks power state control, PSR cannot be enabled\n"); 332 return; 333 } 334 335 intel_dp->psr.sink_support = true; 336 intel_dp->psr.sink_sync_latency = 337 intel_dp_get_sink_sync_latency(intel_dp); 338 339 if (DISPLAY_VER(dev_priv) >= 9 && 340 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 341 bool y_req = intel_dp->psr_dpcd[1] & 342 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 343 bool alpm = intel_dp_get_alpm_status(intel_dp); 344 345 /* 346 * All panels that supports PSR version 03h (PSR2 + 347 * Y-coordinate) can handle Y-coordinates in VSC but we are 348 * only sure that it is going to be used when required by the 349 * panel. This way panel is capable to do selective update 350 * without a aux frame sync. 351 * 352 * To support PSR version 02h and PSR version 03h without 353 * Y-coordinate requirement panels we would need to enable 354 * GTC first. 355 */ 356 intel_dp->psr.sink_psr2_support = y_req && alpm; 357 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 358 intel_dp->psr.sink_psr2_support ? "" : "not "); 359 360 if (intel_dp->psr.sink_psr2_support) { 361 intel_dp->psr.colorimetry_support = 362 intel_dp_get_colorimetry_status(intel_dp); 363 intel_dp_get_su_granularity(intel_dp); 364 } 365 } 366 } 367 368 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 369 { 370 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 371 u8 dpcd_val = DP_PSR_ENABLE; 372 373 /* Enable ALPM at sink for psr2 */ 374 if (intel_dp->psr.psr2_enabled) { 375 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 376 DP_ALPM_ENABLE | 377 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 378 379 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 380 } else { 381 if (intel_dp->psr.link_standby) 382 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 383 384 if (DISPLAY_VER(dev_priv) >= 8) 385 dpcd_val |= DP_PSR_CRC_VERIFICATION; 386 } 387 388 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 389 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 390 391 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 392 393 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 394 } 395 396 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 397 { 398 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 399 u32 val = 0; 400 401 if (DISPLAY_VER(dev_priv) >= 11) 402 val |= EDP_PSR_TP4_TIME_0US; 403 404 if (dev_priv->params.psr_safest_params) { 405 val |= EDP_PSR_TP1_TIME_2500us; 406 val |= EDP_PSR_TP2_TP3_TIME_2500us; 407 goto check_tp3_sel; 408 } 409 410 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) 411 val |= EDP_PSR_TP1_TIME_0us; 412 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) 413 val |= EDP_PSR_TP1_TIME_100us; 414 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) 415 val |= EDP_PSR_TP1_TIME_500us; 416 else 417 val |= EDP_PSR_TP1_TIME_2500us; 418 419 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) 420 val |= EDP_PSR_TP2_TP3_TIME_0us; 421 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) 422 val |= EDP_PSR_TP2_TP3_TIME_100us; 423 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) 424 val |= EDP_PSR_TP2_TP3_TIME_500us; 425 else 426 val |= EDP_PSR_TP2_TP3_TIME_2500us; 427 428 check_tp3_sel: 429 if (intel_dp_source_supports_tps3(dev_priv) && 430 drm_dp_tps3_supported(intel_dp->dpcd)) 431 val |= EDP_PSR_TP1_TP3_SEL; 432 else 433 val |= EDP_PSR_TP1_TP2_SEL; 434 435 return val; 436 } 437 438 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 439 { 440 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 441 int idle_frames; 442 443 /* Let's use 6 as the minimum to cover all known cases including the 444 * off-by-one issue that HW has in some cases. 445 */ 446 idle_frames = max(6, dev_priv->vbt.psr.idle_frames); 447 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 448 449 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 450 idle_frames = 0xf; 451 452 return idle_frames; 453 } 454 455 static void hsw_activate_psr1(struct intel_dp *intel_dp) 456 { 457 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 458 u32 max_sleep_time = 0x1f; 459 u32 val = EDP_PSR_ENABLE; 460 461 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 462 463 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 464 if (IS_HASWELL(dev_priv)) 465 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 466 467 if (intel_dp->psr.link_standby) 468 val |= EDP_PSR_LINK_STANDBY; 469 470 val |= intel_psr1_get_tp_time(intel_dp); 471 472 if (DISPLAY_VER(dev_priv) >= 8) 473 val |= EDP_PSR_CRC_ENABLE; 474 475 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) & 476 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 477 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val); 478 } 479 480 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 481 { 482 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 483 u32 val = 0; 484 485 if (dev_priv->params.psr_safest_params) 486 return EDP_PSR2_TP2_TIME_2500us; 487 488 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 489 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 490 val |= EDP_PSR2_TP2_TIME_50us; 491 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 492 val |= EDP_PSR2_TP2_TIME_100us; 493 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 494 val |= EDP_PSR2_TP2_TIME_500us; 495 else 496 val |= EDP_PSR2_TP2_TIME_2500us; 497 498 return val; 499 } 500 501 static void hsw_activate_psr2(struct intel_dp *intel_dp) 502 { 503 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 504 u32 val = EDP_PSR2_ENABLE; 505 506 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 507 508 if (!IS_ALDERLAKE_P(dev_priv)) 509 val |= EDP_SU_TRACK_ENABLE; 510 511 if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) 512 val |= EDP_Y_COORDINATE_ENABLE; 513 514 val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); 515 val |= intel_psr2_get_tp_time(intel_dp); 516 517 /* Wa_22012278275:adl-p */ 518 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) { 519 static const u8 map[] = { 520 2, /* 5 lines */ 521 1, /* 6 lines */ 522 0, /* 7 lines */ 523 3, /* 8 lines */ 524 6, /* 9 lines */ 525 5, /* 10 lines */ 526 4, /* 11 lines */ 527 7, /* 12 lines */ 528 }; 529 /* 530 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 531 * comments bellow for more information 532 */ 533 u32 tmp, lines = 7; 534 535 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 536 537 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 538 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT; 539 val |= tmp; 540 541 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 542 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT; 543 val |= tmp; 544 } else if (DISPLAY_VER(dev_priv) >= 12) { 545 /* 546 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default 547 * values from BSpec. In order to setting an optimal power 548 * consumption, lower than 4k resoluition mode needs to decrese 549 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution 550 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. 551 */ 552 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 553 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); 554 val |= TGL_EDP_PSR2_FAST_WAKE(7); 555 } else if (DISPLAY_VER(dev_priv) >= 9) { 556 val |= EDP_PSR2_IO_BUFFER_WAKE(7); 557 val |= EDP_PSR2_FAST_WAKE(7); 558 } 559 560 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 561 val |= EDP_PSR2_SU_SDP_SCANLINE; 562 563 if (intel_dp->psr.psr2_sel_fetch_enabled) { 564 u32 tmp; 565 566 /* Wa_1408330847 */ 567 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 568 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 569 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 570 DIS_RAM_BYPASS_PSR2_MAN_TRACK); 571 572 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 573 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 574 } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { 575 intel_de_write(dev_priv, 576 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0); 577 } 578 579 /* 580 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 581 * recommending keep this bit unset while PSR2 is enabled. 582 */ 583 intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0); 584 585 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 586 } 587 588 static bool 589 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 590 { 591 if (IS_ALDERLAKE_P(dev_priv)) 592 return trans == TRANSCODER_A || trans == TRANSCODER_B; 593 else if (DISPLAY_VER(dev_priv) >= 12) 594 return trans == TRANSCODER_A; 595 else 596 return trans == TRANSCODER_EDP; 597 } 598 599 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 600 { 601 if (!cstate || !cstate->hw.active) 602 return 0; 603 604 return DIV_ROUND_UP(1000 * 1000, 605 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 606 } 607 608 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 609 u32 idle_frames) 610 { 611 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 612 u32 val; 613 614 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 615 val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder)); 616 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 617 val |= idle_frames; 618 intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 619 } 620 621 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 622 { 623 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 624 625 psr2_program_idle_frames(intel_dp, 0); 626 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 627 } 628 629 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 630 { 631 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 632 633 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 634 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 635 } 636 637 static void tgl_dc3co_disable_work(struct work_struct *work) 638 { 639 struct intel_dp *intel_dp = 640 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 641 642 mutex_lock(&intel_dp->psr.lock); 643 /* If delayed work is pending, it is not idle */ 644 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 645 goto unlock; 646 647 tgl_psr2_disable_dc3co(intel_dp); 648 unlock: 649 mutex_unlock(&intel_dp->psr.lock); 650 } 651 652 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 653 { 654 if (!intel_dp->psr.dc3co_exitline) 655 return; 656 657 cancel_delayed_work(&intel_dp->psr.dc3co_work); 658 /* Before PSR2 exit disallow dc3co*/ 659 tgl_psr2_disable_dc3co(intel_dp); 660 } 661 662 static bool 663 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 664 struct intel_crtc_state *crtc_state) 665 { 666 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 667 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 668 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 669 enum port port = dig_port->base.port; 670 671 if (IS_ALDERLAKE_P(dev_priv)) 672 return pipe <= PIPE_B && port <= PORT_B; 673 else 674 return pipe == PIPE_A && port == PORT_A; 675 } 676 677 static void 678 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 679 struct intel_crtc_state *crtc_state) 680 { 681 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 682 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 683 u32 exit_scanlines; 684 685 /* 686 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 687 * disable DC3CO until the changed dc3co activating/deactivating sequence 688 * is applied. B.Specs:49196 689 */ 690 return; 691 692 /* 693 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 694 * TODO: when the issue is addressed, this restriction should be removed. 695 */ 696 if (crtc_state->enable_psr2_sel_fetch) 697 return; 698 699 if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO)) 700 return; 701 702 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 703 return; 704 705 /* Wa_16011303918:adl-p */ 706 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 707 return; 708 709 /* 710 * DC3CO Exit time 200us B.Spec 49196 711 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 712 */ 713 exit_scanlines = 714 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 715 716 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 717 return; 718 719 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 720 } 721 722 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 723 struct intel_crtc_state *crtc_state) 724 { 725 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 726 727 if (!dev_priv->params.enable_psr2_sel_fetch && 728 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 729 drm_dbg_kms(&dev_priv->drm, 730 "PSR2 sel fetch not enabled, disabled by parameter\n"); 731 return false; 732 } 733 734 if (crtc_state->uapi.async_flip) { 735 drm_dbg_kms(&dev_priv->drm, 736 "PSR2 sel fetch not enabled, async flip enabled\n"); 737 return false; 738 } 739 740 /* Wa_14010254185 Wa_14010103792 */ 741 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 742 drm_dbg_kms(&dev_priv->drm, 743 "PSR2 sel fetch not enabled, missing the implementation of WAs\n"); 744 return false; 745 } 746 747 return crtc_state->enable_psr2_sel_fetch = true; 748 } 749 750 static bool psr2_granularity_check(struct intel_dp *intel_dp, 751 struct intel_crtc_state *crtc_state) 752 { 753 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 754 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 755 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 756 u16 y_granularity = 0; 757 758 /* PSR2 HW only send full lines so we only need to validate the width */ 759 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) 760 return false; 761 762 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) 763 return false; 764 765 /* HW tracking is only aligned to 4 lines */ 766 if (!crtc_state->enable_psr2_sel_fetch) 767 return intel_dp->psr.su_y_granularity == 4; 768 769 /* 770 * adl_p has 1 line granularity. For other platforms with SW tracking we 771 * can adjust the y coordinates to match sink requirement if multiple of 772 * 4. 773 */ 774 if (IS_ALDERLAKE_P(dev_priv)) 775 y_granularity = intel_dp->psr.su_y_granularity; 776 else if (intel_dp->psr.su_y_granularity <= 2) 777 y_granularity = 4; 778 else if ((intel_dp->psr.su_y_granularity % 4) == 0) 779 y_granularity = intel_dp->psr.su_y_granularity; 780 781 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 782 return false; 783 784 crtc_state->su_y_granularity = y_granularity; 785 return true; 786 } 787 788 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp, 789 struct intel_crtc_state *crtc_state) 790 { 791 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 792 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 793 u32 hblank_total, hblank_ns, req_ns; 794 795 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 796 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 797 798 /* From spec: (72 / number of lanes) * 1000 / symbol clock frequency MHz */ 799 req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000); 800 801 if ((hblank_ns - req_ns) > 100) 802 return true; 803 804 if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 805 return false; 806 807 crtc_state->req_psr2_sdp_prior_scanline = true; 808 return true; 809 } 810 811 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 812 struct intel_crtc_state *crtc_state) 813 { 814 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 815 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 816 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 817 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 818 819 if (!intel_dp->psr.sink_psr2_support) 820 return false; 821 822 /* JSL and EHL only supports eDP 1.3 */ 823 if (IS_JSL_EHL(dev_priv)) { 824 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); 825 return false; 826 } 827 828 /* Wa_16011181250 */ 829 if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) || 830 IS_DG2(dev_priv)) { 831 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); 832 return false; 833 } 834 835 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 836 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); 837 return false; 838 } 839 840 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 841 drm_dbg_kms(&dev_priv->drm, 842 "PSR2 not supported in transcoder %s\n", 843 transcoder_name(crtc_state->cpu_transcoder)); 844 return false; 845 } 846 847 if (!psr2_global_enabled(intel_dp)) { 848 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); 849 return false; 850 } 851 852 /* 853 * DSC and PSR2 cannot be enabled simultaneously. If a requested 854 * resolution requires DSC to be enabled, priority is given to DSC 855 * over PSR2. 856 */ 857 if (crtc_state->dsc.compression_enable) { 858 drm_dbg_kms(&dev_priv->drm, 859 "PSR2 cannot be enabled since DSC is enabled\n"); 860 return false; 861 } 862 863 if (crtc_state->crc_enabled) { 864 drm_dbg_kms(&dev_priv->drm, 865 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 866 return false; 867 } 868 869 if (DISPLAY_VER(dev_priv) >= 12) { 870 psr_max_h = 5120; 871 psr_max_v = 3200; 872 max_bpp = 30; 873 } else if (DISPLAY_VER(dev_priv) >= 10) { 874 psr_max_h = 4096; 875 psr_max_v = 2304; 876 max_bpp = 24; 877 } else if (DISPLAY_VER(dev_priv) == 9) { 878 psr_max_h = 3640; 879 psr_max_v = 2304; 880 max_bpp = 24; 881 } 882 883 if (crtc_state->pipe_bpp > max_bpp) { 884 drm_dbg_kms(&dev_priv->drm, 885 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 886 crtc_state->pipe_bpp, max_bpp); 887 return false; 888 } 889 890 /* Wa_16011303918:adl-p */ 891 if (crtc_state->vrr.enable && 892 IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 893 drm_dbg_kms(&dev_priv->drm, 894 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 895 return false; 896 } 897 898 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { 899 drm_dbg_kms(&dev_priv->drm, 900 "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n"); 901 return false; 902 } 903 904 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 905 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 906 !HAS_PSR_HW_TRACKING(dev_priv)) { 907 drm_dbg_kms(&dev_priv->drm, 908 "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); 909 return false; 910 } 911 } 912 913 /* Wa_2209313811 */ 914 if (!crtc_state->enable_psr2_sel_fetch && 915 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) { 916 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n"); 917 goto unsupported; 918 } 919 920 if (!psr2_granularity_check(intel_dp, crtc_state)) { 921 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); 922 goto unsupported; 923 } 924 925 if (!crtc_state->enable_psr2_sel_fetch && 926 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 927 drm_dbg_kms(&dev_priv->drm, 928 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 929 crtc_hdisplay, crtc_vdisplay, 930 psr_max_h, psr_max_v); 931 goto unsupported; 932 } 933 934 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 935 return true; 936 937 unsupported: 938 crtc_state->enable_psr2_sel_fetch = false; 939 return false; 940 } 941 942 void intel_psr_compute_config(struct intel_dp *intel_dp, 943 struct intel_crtc_state *crtc_state, 944 struct drm_connector_state *conn_state) 945 { 946 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 947 const struct drm_display_mode *adjusted_mode = 948 &crtc_state->hw.adjusted_mode; 949 int psr_setup_time; 950 951 /* 952 * Current PSR panels dont work reliably with VRR enabled 953 * So if VRR is enabled, do not enable PSR. 954 */ 955 if (crtc_state->vrr.enable) 956 return; 957 958 if (!CAN_PSR(intel_dp)) 959 return; 960 961 if (!psr_global_enabled(intel_dp)) { 962 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 963 return; 964 } 965 966 if (intel_dp->psr.sink_not_reliable) { 967 drm_dbg_kms(&dev_priv->drm, 968 "PSR sink implementation is not reliable\n"); 969 return; 970 } 971 972 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 973 drm_dbg_kms(&dev_priv->drm, 974 "PSR condition failed: Interlaced mode enabled\n"); 975 return; 976 } 977 978 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 979 if (psr_setup_time < 0) { 980 drm_dbg_kms(&dev_priv->drm, 981 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 982 intel_dp->psr_dpcd[1]); 983 return; 984 } 985 986 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 987 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 988 drm_dbg_kms(&dev_priv->drm, 989 "PSR condition failed: PSR setup time (%d us) too long\n", 990 psr_setup_time); 991 return; 992 } 993 994 crtc_state->has_psr = true; 995 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 996 997 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 998 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 999 &crtc_state->psr_vsc); 1000 } 1001 1002 void intel_psr_get_config(struct intel_encoder *encoder, 1003 struct intel_crtc_state *pipe_config) 1004 { 1005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1006 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1007 struct intel_dp *intel_dp; 1008 u32 val; 1009 1010 if (!dig_port) 1011 return; 1012 1013 intel_dp = &dig_port->dp; 1014 if (!CAN_PSR(intel_dp)) 1015 return; 1016 1017 mutex_lock(&intel_dp->psr.lock); 1018 if (!intel_dp->psr.enabled) 1019 goto unlock; 1020 1021 /* 1022 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1023 * enabled/disabled because of frontbuffer tracking and others. 1024 */ 1025 pipe_config->has_psr = true; 1026 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; 1027 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1028 1029 if (!intel_dp->psr.psr2_enabled) 1030 goto unlock; 1031 1032 if (HAS_PSR2_SEL_FETCH(dev_priv)) { 1033 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder)); 1034 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1035 pipe_config->enable_psr2_sel_fetch = true; 1036 } 1037 1038 if (DISPLAY_VER(dev_priv) >= 12) { 1039 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder)); 1040 val &= EXITLINE_MASK; 1041 pipe_config->dc3co_exitline = val; 1042 } 1043 unlock: 1044 mutex_unlock(&intel_dp->psr.lock); 1045 } 1046 1047 static void intel_psr_activate(struct intel_dp *intel_dp) 1048 { 1049 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1050 enum transcoder transcoder = intel_dp->psr.transcoder; 1051 1052 if (transcoder_has_psr2(dev_priv, transcoder)) 1053 drm_WARN_ON(&dev_priv->drm, 1054 intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE); 1055 1056 drm_WARN_ON(&dev_priv->drm, 1057 intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE); 1058 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); 1059 lockdep_assert_held(&intel_dp->psr.lock); 1060 1061 /* psr1 and psr2 are mutually exclusive.*/ 1062 if (intel_dp->psr.psr2_enabled) 1063 hsw_activate_psr2(intel_dp); 1064 else 1065 hsw_activate_psr1(intel_dp); 1066 1067 intel_dp->psr.active = true; 1068 } 1069 1070 static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp) 1071 { 1072 switch (intel_dp->psr.pipe) { 1073 case PIPE_A: 1074 return LATENCY_REPORTING_REMOVED_PIPE_A; 1075 case PIPE_B: 1076 return LATENCY_REPORTING_REMOVED_PIPE_B; 1077 case PIPE_C: 1078 return LATENCY_REPORTING_REMOVED_PIPE_C; 1079 default: 1080 MISSING_CASE(intel_dp->psr.pipe); 1081 return 0; 1082 } 1083 } 1084 1085 static void intel_psr_enable_source(struct intel_dp *intel_dp, 1086 const struct intel_crtc_state *crtc_state) 1087 { 1088 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1089 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1090 u32 mask; 1091 1092 /* 1093 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 1094 * mask LPSP to avoid dependency on other drivers that might block 1095 * runtime_pm besides preventing other hw tracking issues now we 1096 * can rely on frontbuffer tracking. 1097 */ 1098 mask = EDP_PSR_DEBUG_MASK_MEMUP | 1099 EDP_PSR_DEBUG_MASK_HPD | 1100 EDP_PSR_DEBUG_MASK_LPSP | 1101 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 1102 1103 if (DISPLAY_VER(dev_priv) < 11) 1104 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 1105 1106 intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder), 1107 mask); 1108 1109 psr_irq_control(intel_dp); 1110 1111 if (intel_dp->psr.dc3co_exitline) { 1112 u32 val; 1113 1114 /* 1115 * TODO: if future platforms supports DC3CO in more than one 1116 * transcoder, EXITLINE will need to be unset when disabling PSR 1117 */ 1118 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 1119 val &= ~EXITLINE_MASK; 1120 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT; 1121 val |= EXITLINE_ENABLE; 1122 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 1123 } 1124 1125 if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) 1126 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 1127 intel_dp->psr.psr2_sel_fetch_enabled ? 1128 IGNORE_PSR2_HW_TRACKING : 0); 1129 1130 if (intel_dp->psr.psr2_enabled) { 1131 if (DISPLAY_VER(dev_priv) == 9) 1132 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1133 PSR2_VSC_ENABLE_PROG_HEADER | 1134 PSR2_ADD_VERTICAL_LINE_COUNT); 1135 1136 /* 1137 * Wa_16014451276:adlp 1138 * All supported adlp panels have 1-based X granularity, this may 1139 * cause issues if non-supported panels are used. 1140 */ 1141 if (IS_ALDERLAKE_P(dev_priv)) 1142 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, 1143 ADLP_1_BASED_X_GRANULARITY); 1144 1145 /* Wa_16011168373:adl-p */ 1146 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1147 intel_de_rmw(dev_priv, 1148 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1149 TRANS_SET_CONTEXT_LATENCY_MASK, 1150 TRANS_SET_CONTEXT_LATENCY_VALUE(1)); 1151 1152 /* Wa_16012604467:adlp */ 1153 if (IS_ALDERLAKE_P(dev_priv)) 1154 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0, 1155 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 1156 1157 /* Wa_16013835468:tgl[b0+], dg1 */ 1158 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) || 1159 IS_DG1(dev_priv)) { 1160 u16 vtotal, vblank; 1161 1162 vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal - 1163 crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1164 vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end - 1165 crtc_state->uapi.adjusted_mode.crtc_vblank_start; 1166 if (vblank > vtotal) 1167 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, 1168 wa_16013835468_bit_get(intel_dp)); 1169 } 1170 } 1171 } 1172 1173 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 1174 { 1175 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1176 u32 val; 1177 1178 /* 1179 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 1180 * will still keep the error set even after the reset done in the 1181 * irq_preinstall and irq_uninstall hooks. 1182 * And enabling in this situation cause the screen to freeze in the 1183 * first time that PSR HW tries to activate so lets keep PSR disabled 1184 * to avoid any rendering problems. 1185 */ 1186 if (DISPLAY_VER(dev_priv) >= 12) { 1187 val = intel_de_read(dev_priv, 1188 TRANS_PSR_IIR(intel_dp->psr.transcoder)); 1189 val &= EDP_PSR_ERROR(0); 1190 } else { 1191 val = intel_de_read(dev_priv, EDP_PSR_IIR); 1192 val &= EDP_PSR_ERROR(intel_dp->psr.transcoder); 1193 } 1194 if (val) { 1195 intel_dp->psr.sink_not_reliable = true; 1196 drm_dbg_kms(&dev_priv->drm, 1197 "PSR interruption error set, not enabling PSR\n"); 1198 return false; 1199 } 1200 1201 return true; 1202 } 1203 1204 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 1205 const struct intel_crtc_state *crtc_state) 1206 { 1207 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1208 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1209 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 1210 struct intel_encoder *encoder = &dig_port->base; 1211 u32 val; 1212 1213 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); 1214 1215 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; 1216 intel_dp->psr.busy_frontbuffer_bits = 0; 1217 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1218 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 1219 /* DC5/DC6 requires at least 6 idle frames */ 1220 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 1221 intel_dp->psr.dc3co_exit_delay = val; 1222 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 1223 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 1224 intel_dp->psr.req_psr2_sdp_prior_scanline = 1225 crtc_state->req_psr2_sdp_prior_scanline; 1226 1227 if (!psr_interrupt_error_check(intel_dp)) 1228 return; 1229 1230 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 1231 intel_dp->psr.psr2_enabled ? "2" : "1"); 1232 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); 1233 intel_snps_phy_update_psr_power_state(dev_priv, phy, true); 1234 intel_psr_enable_sink(intel_dp); 1235 intel_psr_enable_source(intel_dp, crtc_state); 1236 intel_dp->psr.enabled = true; 1237 intel_dp->psr.paused = false; 1238 1239 intel_psr_activate(intel_dp); 1240 } 1241 1242 static void intel_psr_exit(struct intel_dp *intel_dp) 1243 { 1244 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1245 u32 val; 1246 1247 if (!intel_dp->psr.active) { 1248 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) { 1249 val = intel_de_read(dev_priv, 1250 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1251 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 1252 } 1253 1254 val = intel_de_read(dev_priv, 1255 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1256 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 1257 1258 return; 1259 } 1260 1261 if (intel_dp->psr.psr2_enabled) { 1262 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 1263 val = intel_de_read(dev_priv, 1264 EDP_PSR2_CTL(intel_dp->psr.transcoder)); 1265 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 1266 val &= ~EDP_PSR2_ENABLE; 1267 intel_de_write(dev_priv, 1268 EDP_PSR2_CTL(intel_dp->psr.transcoder), val); 1269 } else { 1270 val = intel_de_read(dev_priv, 1271 EDP_PSR_CTL(intel_dp->psr.transcoder)); 1272 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 1273 val &= ~EDP_PSR_ENABLE; 1274 intel_de_write(dev_priv, 1275 EDP_PSR_CTL(intel_dp->psr.transcoder), val); 1276 } 1277 intel_dp->psr.active = false; 1278 } 1279 1280 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 1281 { 1282 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1283 i915_reg_t psr_status; 1284 u32 psr_status_mask; 1285 1286 if (intel_dp->psr.psr2_enabled) { 1287 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1288 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1289 } else { 1290 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1291 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1292 } 1293 1294 /* Wait till PSR is idle */ 1295 if (intel_de_wait_for_clear(dev_priv, psr_status, 1296 psr_status_mask, 2000)) 1297 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1298 } 1299 1300 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 1301 { 1302 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1303 enum phy phy = intel_port_to_phy(dev_priv, 1304 dp_to_dig_port(intel_dp)->base.port); 1305 1306 lockdep_assert_held(&intel_dp->psr.lock); 1307 1308 if (!intel_dp->psr.enabled) 1309 return; 1310 1311 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 1312 intel_dp->psr.psr2_enabled ? "2" : "1"); 1313 1314 intel_psr_exit(intel_dp); 1315 intel_psr_wait_exit_locked(intel_dp); 1316 1317 /* Wa_1408330847 */ 1318 if (intel_dp->psr.psr2_sel_fetch_enabled && 1319 IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1320 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, 1321 DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); 1322 1323 if (intel_dp->psr.psr2_enabled) { 1324 /* Wa_16011168373:adl-p */ 1325 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) 1326 intel_de_rmw(dev_priv, 1327 TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder), 1328 TRANS_SET_CONTEXT_LATENCY_MASK, 0); 1329 1330 /* Wa_16012604467:adlp */ 1331 if (IS_ALDERLAKE_P(dev_priv)) 1332 intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 1333 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 1334 1335 /* Wa_16013835468:tgl[b0+], dg1 */ 1336 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) || 1337 IS_DG1(dev_priv)) 1338 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 1339 wa_16013835468_bit_get(intel_dp), 0); 1340 } 1341 1342 intel_snps_phy_update_psr_power_state(dev_priv, phy, false); 1343 1344 /* Disable PSR on Sink */ 1345 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1346 1347 if (intel_dp->psr.psr2_enabled) 1348 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1349 1350 intel_dp->psr.enabled = false; 1351 } 1352 1353 /** 1354 * intel_psr_disable - Disable PSR 1355 * @intel_dp: Intel DP 1356 * @old_crtc_state: old CRTC state 1357 * 1358 * This function needs to be called before disabling pipe. 1359 */ 1360 void intel_psr_disable(struct intel_dp *intel_dp, 1361 const struct intel_crtc_state *old_crtc_state) 1362 { 1363 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1364 1365 if (!old_crtc_state->has_psr) 1366 return; 1367 1368 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) 1369 return; 1370 1371 mutex_lock(&intel_dp->psr.lock); 1372 1373 intel_psr_disable_locked(intel_dp); 1374 1375 mutex_unlock(&intel_dp->psr.lock); 1376 cancel_work_sync(&intel_dp->psr.work); 1377 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 1378 } 1379 1380 /** 1381 * intel_psr_pause - Pause PSR 1382 * @intel_dp: Intel DP 1383 * 1384 * This function need to be called after enabling psr. 1385 */ 1386 void intel_psr_pause(struct intel_dp *intel_dp) 1387 { 1388 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1389 struct intel_psr *psr = &intel_dp->psr; 1390 1391 if (!CAN_PSR(intel_dp)) 1392 return; 1393 1394 mutex_lock(&psr->lock); 1395 1396 if (!psr->enabled) { 1397 mutex_unlock(&psr->lock); 1398 return; 1399 } 1400 1401 /* If we ever hit this, we will need to add refcount to pause/resume */ 1402 drm_WARN_ON(&dev_priv->drm, psr->paused); 1403 1404 intel_psr_exit(intel_dp); 1405 intel_psr_wait_exit_locked(intel_dp); 1406 psr->paused = true; 1407 1408 mutex_unlock(&psr->lock); 1409 1410 cancel_work_sync(&psr->work); 1411 cancel_delayed_work_sync(&psr->dc3co_work); 1412 } 1413 1414 /** 1415 * intel_psr_resume - Resume PSR 1416 * @intel_dp: Intel DP 1417 * 1418 * This function need to be called after pausing psr. 1419 */ 1420 void intel_psr_resume(struct intel_dp *intel_dp) 1421 { 1422 struct intel_psr *psr = &intel_dp->psr; 1423 1424 if (!CAN_PSR(intel_dp)) 1425 return; 1426 1427 mutex_lock(&psr->lock); 1428 1429 if (!psr->paused) 1430 goto unlock; 1431 1432 psr->paused = false; 1433 intel_psr_activate(intel_dp); 1434 1435 unlock: 1436 mutex_unlock(&psr->lock); 1437 } 1438 1439 static inline u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv) 1440 { 1441 return IS_ALDERLAKE_P(dev_priv) ? 1442 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 1443 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 1444 } 1445 1446 static inline u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv) 1447 { 1448 return IS_ALDERLAKE_P(dev_priv) ? 1449 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 1450 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 1451 } 1452 1453 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) 1454 { 1455 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1456 1457 if (intel_dp->psr.psr2_sel_fetch_enabled) 1458 intel_de_rmw(dev_priv, 1459 PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0, 1460 man_trk_ctl_single_full_frame_bit_get(dev_priv)); 1461 1462 /* 1463 * Display WA #0884: skl+ 1464 * This documented WA for bxt can be safely applied 1465 * broadly so we can force HW tracking to exit PSR 1466 * instead of disabling and re-enabling. 1467 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1468 * but it makes more sense write to the current active 1469 * pipe. 1470 * 1471 * This workaround do not exist for platforms with display 10 or newer 1472 * but testing proved that it works for up display 13, for newer 1473 * than that testing will be needed. 1474 */ 1475 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); 1476 } 1477 1478 void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane, 1479 const struct intel_crtc_state *crtc_state) 1480 { 1481 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1482 enum pipe pipe = plane->pipe; 1483 1484 if (!crtc_state->enable_psr2_sel_fetch) 1485 return; 1486 1487 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); 1488 } 1489 1490 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 1491 const struct intel_crtc_state *crtc_state, 1492 const struct intel_plane_state *plane_state, 1493 int color_plane) 1494 { 1495 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1496 enum pipe pipe = plane->pipe; 1497 const struct drm_rect *clip; 1498 u32 val; 1499 int x, y; 1500 1501 if (!crtc_state->enable_psr2_sel_fetch) 1502 return; 1503 1504 if (plane->id == PLANE_CURSOR) { 1505 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1506 plane_state->ctl); 1507 return; 1508 } 1509 1510 clip = &plane_state->psr2_sel_fetch_area; 1511 1512 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; 1513 val |= plane_state->uapi.dst.x1; 1514 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); 1515 1516 x = plane_state->view.color_plane[color_plane].x; 1517 1518 /* 1519 * From Bspec: UV surface Start Y Position = half of Y plane Y 1520 * start position. 1521 */ 1522 if (!color_plane) 1523 y = plane_state->view.color_plane[color_plane].y + clip->y1; 1524 else 1525 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2; 1526 1527 val = y << 16 | x; 1528 1529 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), 1530 val); 1531 1532 /* Sizes are 0 based */ 1533 val = (drm_rect_height(clip) - 1) << 16; 1534 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1535 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); 1536 1537 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 1538 PLANE_SEL_FETCH_CTL_ENABLE); 1539 } 1540 1541 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) 1542 { 1543 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1544 1545 if (!crtc_state->enable_psr2_sel_fetch) 1546 return; 1547 1548 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), 1549 crtc_state->psr2_man_track_ctl); 1550 } 1551 1552 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 1553 struct drm_rect *clip, bool full_update) 1554 { 1555 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1556 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1557 u32 val = 0; 1558 1559 if (!IS_ALDERLAKE_P(dev_priv)) 1560 val = PSR2_MAN_TRK_CTL_ENABLE; 1561 1562 /* SF partial frame enable has to be set even on full update */ 1563 val |= man_trk_ctl_partial_frame_bit_get(dev_priv); 1564 1565 if (full_update) { 1566 /* 1567 * Not applying Wa_14014971508:adlp as we do not support the 1568 * feature that requires this workaround. 1569 */ 1570 val |= man_trk_ctl_single_full_frame_bit_get(dev_priv); 1571 goto exit; 1572 } 1573 1574 if (clip->y1 == -1) 1575 goto exit; 1576 1577 if (IS_ALDERLAKE_P(dev_priv)) { 1578 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1); 1579 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1); 1580 } else { 1581 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); 1582 1583 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); 1584 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); 1585 } 1586 exit: 1587 crtc_state->psr2_man_track_ctl = val; 1588 } 1589 1590 static void clip_area_update(struct drm_rect *overlap_damage_area, 1591 struct drm_rect *damage_area) 1592 { 1593 if (overlap_damage_area->y1 == -1) { 1594 overlap_damage_area->y1 = damage_area->y1; 1595 overlap_damage_area->y2 = damage_area->y2; 1596 return; 1597 } 1598 1599 if (damage_area->y1 < overlap_damage_area->y1) 1600 overlap_damage_area->y1 = damage_area->y1; 1601 1602 if (damage_area->y2 > overlap_damage_area->y2) 1603 overlap_damage_area->y2 = damage_area->y2; 1604 } 1605 1606 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state, 1607 struct drm_rect *pipe_clip) 1608 { 1609 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1610 const u16 y_alignment = crtc_state->su_y_granularity; 1611 1612 pipe_clip->y1 -= pipe_clip->y1 % y_alignment; 1613 if (pipe_clip->y2 % y_alignment) 1614 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; 1615 1616 if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable) 1617 drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n"); 1618 } 1619 1620 /* 1621 * TODO: Not clear how to handle planes with negative position, 1622 * also planes are not updated if they have a negative X 1623 * position so for now doing a full update in this cases 1624 * 1625 * Plane scaling and rotation is not supported by selective fetch and both 1626 * properties can change without a modeset, so need to be check at every 1627 * atomic commmit. 1628 */ 1629 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 1630 { 1631 if (plane_state->uapi.dst.y1 < 0 || 1632 plane_state->uapi.dst.x1 < 0 || 1633 plane_state->scaler_id >= 0 || 1634 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) 1635 return false; 1636 1637 return true; 1638 } 1639 1640 /* 1641 * Check for pipe properties that is not supported by selective fetch. 1642 * 1643 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 1644 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 1645 * enabled and going to the full update path. 1646 */ 1647 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 1648 { 1649 if (crtc_state->scaler_state.scaler_id >= 0) 1650 return false; 1651 1652 return true; 1653 } 1654 1655 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 1656 struct intel_crtc *crtc) 1657 { 1658 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1659 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; 1660 struct intel_plane_state *new_plane_state, *old_plane_state; 1661 struct intel_plane *plane; 1662 bool full_update = false; 1663 int i, ret; 1664 1665 if (!crtc_state->enable_psr2_sel_fetch) 1666 return 0; 1667 1668 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 1669 full_update = true; 1670 goto skip_sel_fetch_set_loop; 1671 } 1672 1673 /* 1674 * Calculate minimal selective fetch area of each plane and calculate 1675 * the pipe damaged area. 1676 * In the next loop the plane selective fetch area will actually be set 1677 * using whole pipe damaged area. 1678 */ 1679 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1680 new_plane_state, i) { 1681 struct drm_rect src, damaged_area = { .y1 = -1 }; 1682 struct drm_atomic_helper_damage_iter iter; 1683 struct drm_rect clip; 1684 1685 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 1686 continue; 1687 1688 if (!new_plane_state->uapi.visible && 1689 !old_plane_state->uapi.visible) 1690 continue; 1691 1692 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1693 full_update = true; 1694 break; 1695 } 1696 1697 /* 1698 * If visibility or plane moved, mark the whole plane area as 1699 * damaged as it needs to be complete redraw in the new and old 1700 * position. 1701 */ 1702 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 1703 !drm_rect_equals(&new_plane_state->uapi.dst, 1704 &old_plane_state->uapi.dst)) { 1705 if (old_plane_state->uapi.visible) { 1706 damaged_area.y1 = old_plane_state->uapi.dst.y1; 1707 damaged_area.y2 = old_plane_state->uapi.dst.y2; 1708 clip_area_update(&pipe_clip, &damaged_area); 1709 } 1710 1711 if (new_plane_state->uapi.visible) { 1712 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1713 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1714 clip_area_update(&pipe_clip, &damaged_area); 1715 } 1716 continue; 1717 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 1718 /* If alpha changed mark the whole plane area as damaged */ 1719 damaged_area.y1 = new_plane_state->uapi.dst.y1; 1720 damaged_area.y2 = new_plane_state->uapi.dst.y2; 1721 clip_area_update(&pipe_clip, &damaged_area); 1722 continue; 1723 } 1724 1725 drm_rect_fp_to_int(&src, &new_plane_state->uapi.src); 1726 1727 drm_atomic_helper_damage_iter_init(&iter, 1728 &old_plane_state->uapi, 1729 &new_plane_state->uapi); 1730 drm_atomic_for_each_plane_damage(&iter, &clip) { 1731 if (drm_rect_intersect(&clip, &src)) 1732 clip_area_update(&damaged_area, &clip); 1733 } 1734 1735 if (damaged_area.y1 == -1) 1736 continue; 1737 1738 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 1739 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 1740 clip_area_update(&pipe_clip, &damaged_area); 1741 } 1742 1743 if (full_update) 1744 goto skip_sel_fetch_set_loop; 1745 1746 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 1747 if (ret) 1748 return ret; 1749 1750 intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip); 1751 1752 /* 1753 * Now that we have the pipe damaged area check if it intersect with 1754 * every plane, if it does set the plane selective fetch area. 1755 */ 1756 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 1757 new_plane_state, i) { 1758 struct drm_rect *sel_fetch_area, inter; 1759 struct intel_plane *linked = new_plane_state->planar_linked_plane; 1760 1761 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 1762 !new_plane_state->uapi.visible) 1763 continue; 1764 1765 inter = pipe_clip; 1766 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 1767 continue; 1768 1769 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 1770 full_update = true; 1771 break; 1772 } 1773 1774 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 1775 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 1776 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 1777 crtc_state->update_planes |= BIT(plane->id); 1778 1779 /* 1780 * Sel_fetch_area is calculated for UV plane. Use 1781 * same area for Y plane as well. 1782 */ 1783 if (linked) { 1784 struct intel_plane_state *linked_new_plane_state; 1785 struct drm_rect *linked_sel_fetch_area; 1786 1787 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 1788 if (IS_ERR(linked_new_plane_state)) 1789 return PTR_ERR(linked_new_plane_state); 1790 1791 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 1792 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 1793 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 1794 crtc_state->update_planes |= BIT(linked->id); 1795 } 1796 } 1797 1798 skip_sel_fetch_set_loop: 1799 psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); 1800 return 0; 1801 } 1802 1803 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 1804 struct intel_crtc *crtc) 1805 { 1806 struct drm_i915_private *i915 = to_i915(state->base.dev); 1807 const struct intel_crtc_state *crtc_state = 1808 intel_atomic_get_new_crtc_state(state, crtc); 1809 struct intel_encoder *encoder; 1810 1811 if (!HAS_PSR(i915)) 1812 return; 1813 1814 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1815 crtc_state->uapi.encoder_mask) { 1816 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1817 struct intel_psr *psr = &intel_dp->psr; 1818 bool needs_to_disable = false; 1819 1820 mutex_lock(&psr->lock); 1821 1822 /* 1823 * Reasons to disable: 1824 * - PSR disabled in new state 1825 * - All planes will go inactive 1826 * - Changing between PSR versions 1827 */ 1828 needs_to_disable |= intel_crtc_needs_modeset(crtc_state); 1829 needs_to_disable |= !crtc_state->has_psr; 1830 needs_to_disable |= !crtc_state->active_planes; 1831 needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled; 1832 1833 if (psr->enabled && needs_to_disable) 1834 intel_psr_disable_locked(intel_dp); 1835 1836 mutex_unlock(&psr->lock); 1837 } 1838 } 1839 1840 static void _intel_psr_post_plane_update(const struct intel_atomic_state *state, 1841 const struct intel_crtc_state *crtc_state) 1842 { 1843 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1844 struct intel_encoder *encoder; 1845 1846 if (!crtc_state->has_psr) 1847 return; 1848 1849 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 1850 crtc_state->uapi.encoder_mask) { 1851 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1852 struct intel_psr *psr = &intel_dp->psr; 1853 1854 mutex_lock(&psr->lock); 1855 1856 if (psr->sink_not_reliable) 1857 goto exit; 1858 1859 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); 1860 1861 /* Only enable if there is active planes */ 1862 if (!psr->enabled && crtc_state->active_planes) 1863 intel_psr_enable_locked(intel_dp, crtc_state); 1864 1865 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1866 if (crtc_state->crc_enabled && psr->enabled) 1867 psr_force_hw_tracking_exit(intel_dp); 1868 1869 exit: 1870 mutex_unlock(&psr->lock); 1871 } 1872 } 1873 1874 void intel_psr_post_plane_update(const struct intel_atomic_state *state) 1875 { 1876 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1877 struct intel_crtc_state *crtc_state; 1878 struct intel_crtc *crtc; 1879 int i; 1880 1881 if (!HAS_PSR(dev_priv)) 1882 return; 1883 1884 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) 1885 _intel_psr_post_plane_update(state, crtc_state); 1886 } 1887 1888 static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 1889 { 1890 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1891 1892 /* 1893 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 1894 * As all higher states has bit 4 of PSR2 state set we can just wait for 1895 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 1896 */ 1897 return intel_de_wait_for_clear(dev_priv, 1898 EDP_PSR2_STATUS(intel_dp->psr.transcoder), 1899 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50); 1900 } 1901 1902 static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp) 1903 { 1904 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1905 1906 /* 1907 * From bspec: Panel Self Refresh (BDW+) 1908 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 1909 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 1910 * defensive enough to cover everything. 1911 */ 1912 return intel_de_wait_for_clear(dev_priv, 1913 EDP_PSR_STATUS(intel_dp->psr.transcoder), 1914 EDP_PSR_STATUS_STATE_MASK, 50); 1915 } 1916 1917 /** 1918 * intel_psr_wait_for_idle - wait for PSR be ready for a pipe update 1919 * @new_crtc_state: new CRTC state 1920 * 1921 * This function is expected to be called from pipe_update_start() where it is 1922 * not expected to race with PSR enable or disable. 1923 */ 1924 void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state) 1925 { 1926 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); 1927 struct intel_encoder *encoder; 1928 1929 if (!new_crtc_state->has_psr) 1930 return; 1931 1932 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, 1933 new_crtc_state->uapi.encoder_mask) { 1934 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1935 int ret; 1936 1937 mutex_lock(&intel_dp->psr.lock); 1938 1939 if (!intel_dp->psr.enabled) { 1940 mutex_unlock(&intel_dp->psr.lock); 1941 continue; 1942 } 1943 1944 if (intel_dp->psr.psr2_enabled) 1945 ret = _psr2_ready_for_pipe_update_locked(intel_dp); 1946 else 1947 ret = _psr1_ready_for_pipe_update_locked(intel_dp); 1948 1949 if (ret) 1950 drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n"); 1951 1952 mutex_unlock(&intel_dp->psr.lock); 1953 } 1954 } 1955 1956 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 1957 { 1958 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1959 i915_reg_t reg; 1960 u32 mask; 1961 int err; 1962 1963 if (!intel_dp->psr.enabled) 1964 return false; 1965 1966 if (intel_dp->psr.psr2_enabled) { 1967 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder); 1968 mask = EDP_PSR2_STATUS_STATE_MASK; 1969 } else { 1970 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder); 1971 mask = EDP_PSR_STATUS_STATE_MASK; 1972 } 1973 1974 mutex_unlock(&intel_dp->psr.lock); 1975 1976 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 1977 if (err) 1978 drm_err(&dev_priv->drm, 1979 "Timed out waiting for PSR Idle for re-enable\n"); 1980 1981 /* After the unlocked wait, verify that PSR is still wanted! */ 1982 mutex_lock(&intel_dp->psr.lock); 1983 return err == 0 && intel_dp->psr.enabled; 1984 } 1985 1986 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 1987 { 1988 struct drm_connector_list_iter conn_iter; 1989 struct drm_device *dev = &dev_priv->drm; 1990 struct drm_modeset_acquire_ctx ctx; 1991 struct drm_atomic_state *state; 1992 struct drm_connector *conn; 1993 int err = 0; 1994 1995 state = drm_atomic_state_alloc(dev); 1996 if (!state) 1997 return -ENOMEM; 1998 1999 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 2000 state->acquire_ctx = &ctx; 2001 2002 retry: 2003 2004 drm_connector_list_iter_begin(dev, &conn_iter); 2005 drm_for_each_connector_iter(conn, &conn_iter) { 2006 struct drm_connector_state *conn_state; 2007 struct drm_crtc_state *crtc_state; 2008 2009 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 2010 continue; 2011 2012 conn_state = drm_atomic_get_connector_state(state, conn); 2013 if (IS_ERR(conn_state)) { 2014 err = PTR_ERR(conn_state); 2015 break; 2016 } 2017 2018 if (!conn_state->crtc) 2019 continue; 2020 2021 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 2022 if (IS_ERR(crtc_state)) { 2023 err = PTR_ERR(crtc_state); 2024 break; 2025 } 2026 2027 /* Mark mode as changed to trigger a pipe->update() */ 2028 crtc_state->mode_changed = true; 2029 } 2030 drm_connector_list_iter_end(&conn_iter); 2031 2032 if (err == 0) 2033 err = drm_atomic_commit(state); 2034 2035 if (err == -EDEADLK) { 2036 drm_atomic_state_clear(state); 2037 err = drm_modeset_backoff(&ctx); 2038 if (!err) 2039 goto retry; 2040 } 2041 2042 drm_modeset_drop_locks(&ctx); 2043 drm_modeset_acquire_fini(&ctx); 2044 drm_atomic_state_put(state); 2045 2046 return err; 2047 } 2048 2049 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 2050 { 2051 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2052 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 2053 u32 old_mode; 2054 int ret; 2055 2056 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 2057 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 2058 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 2059 return -EINVAL; 2060 } 2061 2062 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 2063 if (ret) 2064 return ret; 2065 2066 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 2067 intel_dp->psr.debug = val; 2068 2069 /* 2070 * Do it right away if it's already enabled, otherwise it will be done 2071 * when enabling the source. 2072 */ 2073 if (intel_dp->psr.enabled) 2074 psr_irq_control(intel_dp); 2075 2076 mutex_unlock(&intel_dp->psr.lock); 2077 2078 if (old_mode != mode) 2079 ret = intel_psr_fastset_force(dev_priv); 2080 2081 return ret; 2082 } 2083 2084 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 2085 { 2086 struct intel_psr *psr = &intel_dp->psr; 2087 2088 intel_psr_disable_locked(intel_dp); 2089 psr->sink_not_reliable = true; 2090 /* let's make sure that sink is awaken */ 2091 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 2092 } 2093 2094 static void intel_psr_work(struct work_struct *work) 2095 { 2096 struct intel_dp *intel_dp = 2097 container_of(work, typeof(*intel_dp), psr.work); 2098 2099 mutex_lock(&intel_dp->psr.lock); 2100 2101 if (!intel_dp->psr.enabled) 2102 goto unlock; 2103 2104 if (READ_ONCE(intel_dp->psr.irq_aux_error)) 2105 intel_psr_handle_irq(intel_dp); 2106 2107 /* 2108 * We have to make sure PSR is ready for re-enable 2109 * otherwise it keeps disabled until next full enable/disable cycle. 2110 * PSR might take some time to get fully disabled 2111 * and be ready for re-enable. 2112 */ 2113 if (!__psr_wait_for_idle_locked(intel_dp)) 2114 goto unlock; 2115 2116 /* 2117 * The delayed work can race with an invalidate hence we need to 2118 * recheck. Since psr_flush first clears this and then reschedules we 2119 * won't ever miss a flush when bailing out here. 2120 */ 2121 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 2122 goto unlock; 2123 2124 intel_psr_activate(intel_dp); 2125 unlock: 2126 mutex_unlock(&intel_dp->psr.lock); 2127 } 2128 2129 /** 2130 * intel_psr_invalidate - Invalidade PSR 2131 * @dev_priv: i915 device 2132 * @frontbuffer_bits: frontbuffer plane tracking bits 2133 * @origin: which operation caused the invalidate 2134 * 2135 * Since the hardware frontbuffer tracking has gaps we need to integrate 2136 * with the software frontbuffer tracking. This function gets called every 2137 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 2138 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 2139 * 2140 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 2141 */ 2142 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 2143 unsigned frontbuffer_bits, enum fb_op_origin origin) 2144 { 2145 struct intel_encoder *encoder; 2146 2147 if (origin == ORIGIN_FLIP) 2148 return; 2149 2150 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2151 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2152 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2153 2154 mutex_lock(&intel_dp->psr.lock); 2155 if (!intel_dp->psr.enabled) { 2156 mutex_unlock(&intel_dp->psr.lock); 2157 continue; 2158 } 2159 2160 pipe_frontbuffer_bits &= 2161 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2162 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 2163 2164 if (pipe_frontbuffer_bits) 2165 intel_psr_exit(intel_dp); 2166 2167 mutex_unlock(&intel_dp->psr.lock); 2168 } 2169 } 2170 /* 2171 * When we will be completely rely on PSR2 S/W tracking in future, 2172 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 2173 * event also therefore tgl_dc3co_flush_locked() require to be changed 2174 * accordingly in future. 2175 */ 2176 static void 2177 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 2178 enum fb_op_origin origin) 2179 { 2180 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || 2181 !intel_dp->psr.active) 2182 return; 2183 2184 /* 2185 * At every frontbuffer flush flip event modified delay of delayed work, 2186 * when delayed work schedules that means display has been idle. 2187 */ 2188 if (!(frontbuffer_bits & 2189 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 2190 return; 2191 2192 tgl_psr2_enable_dc3co(intel_dp); 2193 mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work, 2194 intel_dp->psr.dc3co_exit_delay); 2195 } 2196 2197 /** 2198 * intel_psr_flush - Flush PSR 2199 * @dev_priv: i915 device 2200 * @frontbuffer_bits: frontbuffer plane tracking bits 2201 * @origin: which operation caused the flush 2202 * 2203 * Since the hardware frontbuffer tracking has gaps we need to integrate 2204 * with the software frontbuffer tracking. This function gets called every 2205 * time frontbuffer rendering has completed and flushed out to memory. PSR 2206 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 2207 * 2208 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 2209 */ 2210 void intel_psr_flush(struct drm_i915_private *dev_priv, 2211 unsigned frontbuffer_bits, enum fb_op_origin origin) 2212 { 2213 struct intel_encoder *encoder; 2214 2215 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2216 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 2217 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2218 2219 mutex_lock(&intel_dp->psr.lock); 2220 if (!intel_dp->psr.enabled) { 2221 mutex_unlock(&intel_dp->psr.lock); 2222 continue; 2223 } 2224 2225 pipe_frontbuffer_bits &= 2226 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 2227 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 2228 2229 /* 2230 * If the PSR is paused by an explicit intel_psr_paused() call, 2231 * we have to ensure that the PSR is not activated until 2232 * intel_psr_resume() is called. 2233 */ 2234 if (intel_dp->psr.paused) { 2235 mutex_unlock(&intel_dp->psr.lock); 2236 continue; 2237 } 2238 2239 if (origin == ORIGIN_FLIP || 2240 (origin == ORIGIN_CURSOR_UPDATE && 2241 !intel_dp->psr.psr2_sel_fetch_enabled)) { 2242 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 2243 mutex_unlock(&intel_dp->psr.lock); 2244 continue; 2245 } 2246 2247 /* By definition flush = invalidate + flush */ 2248 if (pipe_frontbuffer_bits) 2249 psr_force_hw_tracking_exit(intel_dp); 2250 2251 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 2252 schedule_work(&intel_dp->psr.work); 2253 mutex_unlock(&intel_dp->psr.lock); 2254 } 2255 } 2256 2257 /** 2258 * intel_psr_init - Init basic PSR work and mutex. 2259 * @intel_dp: Intel DP 2260 * 2261 * This function is called after the initializing connector. 2262 * (the initializing of connector treats the handling of connector capabilities) 2263 * And it initializes basic PSR stuff for each DP Encoder. 2264 */ 2265 void intel_psr_init(struct intel_dp *intel_dp) 2266 { 2267 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2268 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2269 2270 if (!HAS_PSR(dev_priv)) 2271 return; 2272 2273 /* 2274 * HSW spec explicitly says PSR is tied to port A. 2275 * BDW+ platforms have a instance of PSR registers per transcoder but 2276 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 2277 * than eDP one. 2278 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 2279 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 2280 * But GEN12 supports a instance of PSR registers per transcoder. 2281 */ 2282 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { 2283 drm_dbg_kms(&dev_priv->drm, 2284 "PSR condition failed: Port not supported\n"); 2285 return; 2286 } 2287 2288 intel_dp->psr.source_support = true; 2289 2290 if (dev_priv->params.enable_psr == -1) 2291 if (!dev_priv->vbt.psr.enable) 2292 dev_priv->params.enable_psr = 0; 2293 2294 /* Set link_standby x link_off defaults */ 2295 if (DISPLAY_VER(dev_priv) < 12) 2296 /* For new platforms up to TGL let's respect VBT back again */ 2297 intel_dp->psr.link_standby = dev_priv->vbt.psr.full_link; 2298 2299 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 2300 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 2301 mutex_init(&intel_dp->psr.lock); 2302 } 2303 2304 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 2305 u8 *status, u8 *error_status) 2306 { 2307 struct drm_dp_aux *aux = &intel_dp->aux; 2308 int ret; 2309 2310 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 2311 if (ret != 1) 2312 return ret; 2313 2314 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 2315 if (ret != 1) 2316 return ret; 2317 2318 *status = *status & DP_PSR_SINK_STATE_MASK; 2319 2320 return 0; 2321 } 2322 2323 static void psr_alpm_check(struct intel_dp *intel_dp) 2324 { 2325 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2326 struct drm_dp_aux *aux = &intel_dp->aux; 2327 struct intel_psr *psr = &intel_dp->psr; 2328 u8 val; 2329 int r; 2330 2331 if (!psr->psr2_enabled) 2332 return; 2333 2334 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 2335 if (r != 1) { 2336 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 2337 return; 2338 } 2339 2340 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 2341 intel_psr_disable_locked(intel_dp); 2342 psr->sink_not_reliable = true; 2343 drm_dbg_kms(&dev_priv->drm, 2344 "ALPM lock timeout error, disabling PSR\n"); 2345 2346 /* Clearing error */ 2347 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 2348 } 2349 } 2350 2351 static void psr_capability_changed_check(struct intel_dp *intel_dp) 2352 { 2353 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2354 struct intel_psr *psr = &intel_dp->psr; 2355 u8 val; 2356 int r; 2357 2358 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 2359 if (r != 1) { 2360 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 2361 return; 2362 } 2363 2364 if (val & DP_PSR_CAPS_CHANGE) { 2365 intel_psr_disable_locked(intel_dp); 2366 psr->sink_not_reliable = true; 2367 drm_dbg_kms(&dev_priv->drm, 2368 "Sink PSR capability changed, disabling PSR\n"); 2369 2370 /* Clearing it */ 2371 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 2372 } 2373 } 2374 2375 void intel_psr_short_pulse(struct intel_dp *intel_dp) 2376 { 2377 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2378 struct intel_psr *psr = &intel_dp->psr; 2379 u8 status, error_status; 2380 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 2381 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 2382 DP_PSR_LINK_CRC_ERROR; 2383 2384 if (!CAN_PSR(intel_dp)) 2385 return; 2386 2387 mutex_lock(&psr->lock); 2388 2389 if (!psr->enabled) 2390 goto exit; 2391 2392 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 2393 drm_err(&dev_priv->drm, 2394 "Error reading PSR status or error status\n"); 2395 goto exit; 2396 } 2397 2398 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 2399 intel_psr_disable_locked(intel_dp); 2400 psr->sink_not_reliable = true; 2401 } 2402 2403 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 2404 drm_dbg_kms(&dev_priv->drm, 2405 "PSR sink internal error, disabling PSR\n"); 2406 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 2407 drm_dbg_kms(&dev_priv->drm, 2408 "PSR RFB storage error, disabling PSR\n"); 2409 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 2410 drm_dbg_kms(&dev_priv->drm, 2411 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 2412 if (error_status & DP_PSR_LINK_CRC_ERROR) 2413 drm_dbg_kms(&dev_priv->drm, 2414 "PSR Link CRC error, disabling PSR\n"); 2415 2416 if (error_status & ~errors) 2417 drm_err(&dev_priv->drm, 2418 "PSR_ERROR_STATUS unhandled errors %x\n", 2419 error_status & ~errors); 2420 /* clear status register */ 2421 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 2422 2423 psr_alpm_check(intel_dp); 2424 psr_capability_changed_check(intel_dp); 2425 2426 exit: 2427 mutex_unlock(&psr->lock); 2428 } 2429 2430 bool intel_psr_enabled(struct intel_dp *intel_dp) 2431 { 2432 bool ret; 2433 2434 if (!CAN_PSR(intel_dp)) 2435 return false; 2436 2437 mutex_lock(&intel_dp->psr.lock); 2438 ret = intel_dp->psr.enabled; 2439 mutex_unlock(&intel_dp->psr.lock); 2440 2441 return ret; 2442 } 2443