1 /* 2 * Copyright © 2006-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28 /* 29 * This information is private to VBT parsing in intel_bios.c. 30 * 31 * Please do NOT include anywhere else. 32 */ 33 #ifndef _INTEL_BIOS_PRIVATE 34 #error "intel_vbt_defs.h is private to intel_bios.c" 35 #endif 36 37 #ifndef _INTEL_VBT_DEFS_H_ 38 #define _INTEL_VBT_DEFS_H_ 39 40 #include "intel_bios.h" 41 42 /** 43 * struct vbt_header - VBT Header structure 44 * @signature: VBT signature, always starts with "$VBT" 45 * @version: Version of this structure 46 * @header_size: Size of this structure 47 * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks) 48 * @vbt_checksum: Checksum 49 * @reserved0: Reserved 50 * @bdb_offset: Offset of &struct bdb_header from beginning of VBT 51 * @aim_offset: Offsets of add-in data blocks from beginning of VBT 52 */ 53 struct vbt_header { 54 u8 signature[20]; 55 u16 version; 56 u16 header_size; 57 u16 vbt_size; 58 u8 vbt_checksum; 59 u8 reserved0; 60 u32 bdb_offset; 61 u32 aim_offset[4]; 62 } __packed; 63 64 /** 65 * struct bdb_header - BDB Header structure 66 * @signature: BDB signature "BIOS_DATA_BLOCK" 67 * @version: Version of the data block definitions 68 * @header_size: Size of this structure 69 * @bdb_size: Size of BDB (BDB Header and data blocks) 70 */ 71 struct bdb_header { 72 u8 signature[16]; 73 u16 version; 74 u16 header_size; 75 u16 bdb_size; 76 } __packed; 77 78 /* 79 * There are several types of BIOS data blocks (BDBs), each block has 80 * an ID and size in the first 3 bytes (ID in first, size in next 2). 81 * Known types are listed below. 82 */ 83 enum bdb_block_id { 84 BDB_GENERAL_FEATURES = 1, 85 BDB_GENERAL_DEFINITIONS = 2, 86 BDB_OLD_TOGGLE_LIST = 3, 87 BDB_MODE_SUPPORT_LIST = 4, 88 BDB_GENERIC_MODE_TABLE = 5, 89 BDB_EXT_MMIO_REGS = 6, 90 BDB_SWF_IO = 7, 91 BDB_SWF_MMIO = 8, 92 BDB_PSR = 9, 93 BDB_MODE_REMOVAL_TABLE = 10, 94 BDB_CHILD_DEVICE_TABLE = 11, 95 BDB_DRIVER_FEATURES = 12, 96 BDB_DRIVER_PERSISTENCE = 13, 97 BDB_EXT_TABLE_PTRS = 14, 98 BDB_DOT_CLOCK_OVERRIDE = 15, 99 BDB_DISPLAY_SELECT = 16, 100 BDB_DRIVER_ROTATION = 18, 101 BDB_DISPLAY_REMOVE = 19, 102 BDB_OEM_CUSTOM = 20, 103 BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */ 104 BDB_SDVO_LVDS_OPTIONS = 22, 105 BDB_SDVO_PANEL_DTDS = 23, 106 BDB_SDVO_LVDS_PNP_IDS = 24, 107 BDB_SDVO_LVDS_POWER_SEQ = 25, 108 BDB_TV_OPTIONS = 26, 109 BDB_EDP = 27, 110 BDB_LVDS_OPTIONS = 40, 111 BDB_LVDS_LFP_DATA_PTRS = 41, 112 BDB_LVDS_LFP_DATA = 42, 113 BDB_LVDS_BACKLIGHT = 43, 114 BDB_LFP_POWER = 44, 115 BDB_MIPI_CONFIG = 52, 116 BDB_MIPI_SEQUENCE = 53, 117 BDB_COMPRESSION_PARAMETERS = 56, 118 BDB_GENERIC_DTD = 58, 119 BDB_SKIP = 254, /* VBIOS private block, ignore */ 120 }; 121 122 /* 123 * Block 1 - General Bit Definitions 124 */ 125 126 struct bdb_general_features { 127 /* bits 1 */ 128 u8 panel_fitting:2; 129 u8 flexaim:1; 130 u8 msg_enable:1; 131 u8 clear_screen:3; 132 u8 color_flip:1; 133 134 /* bits 2 */ 135 u8 download_ext_vbt:1; 136 u8 enable_ssc:1; 137 u8 ssc_freq:1; 138 u8 enable_lfp_on_override:1; 139 u8 disable_ssc_ddt:1; 140 u8 underscan_vga_timings:1; 141 u8 display_clock_mode:1; 142 u8 vbios_hotplug_support:1; 143 144 /* bits 3 */ 145 u8 disable_smooth_vision:1; 146 u8 single_dvi:1; 147 u8 rotate_180:1; /* 181 */ 148 u8 fdi_rx_polarity_inverted:1; 149 u8 vbios_extended_mode:1; /* 160 */ 150 u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */ 151 u8 panel_best_fit_timing:1; /* 160 */ 152 u8 ignore_strap_state:1; /* 160 */ 153 154 /* bits 4 */ 155 u8 legacy_monitor_detect; 156 157 /* bits 5 */ 158 u8 int_crt_support:1; 159 u8 int_tv_support:1; 160 u8 int_efp_support:1; 161 u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */ 162 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 163 u8 dp_ssc_dongle_supported:1; 164 u8 rsvd11:2; /* finish byte */ 165 166 /* bits 6 */ 167 u8 tc_hpd_retry_timeout:7; /* 242 */ 168 u8 rsvd12:1; 169 170 /* bits 7 */ 171 u8 afc_startup_config:2;/* 249 */ 172 u8 rsvd13:6; 173 } __packed; 174 175 /* 176 * Block 2 - General Bytes Definition 177 */ 178 179 /* pre-915 */ 180 #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 181 #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 182 #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 183 #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 184 185 /* Pre 915 */ 186 #define DEVICE_TYPE_NONE 0x00 187 #define DEVICE_TYPE_CRT 0x01 188 #define DEVICE_TYPE_TV 0x09 189 #define DEVICE_TYPE_EFP 0x12 190 #define DEVICE_TYPE_LFP 0x22 191 /* On 915+ */ 192 #define DEVICE_TYPE_CRT_DPMS 0x6001 193 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 194 #define DEVICE_TYPE_TV_COMPOSITE 0x0209 195 #define DEVICE_TYPE_TV_MACROVISION 0x0289 196 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 197 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 198 #define DEVICE_TYPE_TV_SCART 0x0209 199 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 200 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 201 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 202 #define DEVICE_TYPE_EFP_DVI_I 0x6053 203 #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 204 #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 205 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 206 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 207 #define DEVICE_TYPE_LFP_PANELLINK 0x5012 208 #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 209 #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 210 #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 211 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 212 213 /* Add the device class for LFP, TV, HDMI */ 214 #define DEVICE_TYPE_INT_LFP 0x1022 215 #define DEVICE_TYPE_INT_TV 0x1009 216 #define DEVICE_TYPE_HDMI 0x60D2 217 #define DEVICE_TYPE_DP 0x68C6 218 #define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 219 #define DEVICE_TYPE_eDP 0x78C6 220 221 #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) 222 #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) 223 #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) 224 #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) 225 #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) 226 #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) 227 #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) 228 #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) 229 #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) 230 #define DEVICE_TYPE_LVDS_SIGNALING (1 << 5) 231 #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) 232 #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) 233 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) 234 #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) 235 #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) 236 237 #define DEVICE_CFG_NONE 0x00 238 #define DEVICE_CFG_12BIT_DVOB 0x01 239 #define DEVICE_CFG_12BIT_DVOC 0x02 240 #define DEVICE_CFG_24BIT_DVOBC 0x09 241 #define DEVICE_CFG_24BIT_DVOCB 0x0a 242 #define DEVICE_CFG_DUAL_DVOB 0x11 243 #define DEVICE_CFG_DUAL_DVOC 0x12 244 #define DEVICE_CFG_DUAL_DVOBC 0x13 245 #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 246 #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 247 248 #define DEVICE_WIRE_NONE 0x00 249 #define DEVICE_WIRE_DVOB 0x01 250 #define DEVICE_WIRE_DVOC 0x02 251 #define DEVICE_WIRE_DVOBC 0x03 252 #define DEVICE_WIRE_DVOBB 0x05 253 #define DEVICE_WIRE_DVOCC 0x06 254 #define DEVICE_WIRE_DVOB_MASTER 0x0d 255 #define DEVICE_WIRE_DVOC_MASTER 0x0e 256 257 /* dvo_port pre BDB 155 */ 258 #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 259 #define DEVICE_PORT_DVOB 0x01 260 #define DEVICE_PORT_DVOC 0x02 261 262 /* dvo_port BDB 155+ */ 263 #define DVO_PORT_HDMIA 0 264 #define DVO_PORT_HDMIB 1 265 #define DVO_PORT_HDMIC 2 266 #define DVO_PORT_HDMID 3 267 #define DVO_PORT_LVDS 4 268 #define DVO_PORT_TV 5 269 #define DVO_PORT_CRT 6 270 #define DVO_PORT_DPB 7 271 #define DVO_PORT_DPC 8 272 #define DVO_PORT_DPD 9 273 #define DVO_PORT_DPA 10 274 #define DVO_PORT_DPE 11 /* 193 */ 275 #define DVO_PORT_HDMIE 12 /* 193 */ 276 #define DVO_PORT_DPF 13 /* N/A */ 277 #define DVO_PORT_HDMIF 14 /* N/A */ 278 #define DVO_PORT_DPG 15 /* 217 */ 279 #define DVO_PORT_HDMIG 16 /* 217 */ 280 #define DVO_PORT_DPH 17 /* 217 */ 281 #define DVO_PORT_HDMIH 18 /* 217 */ 282 #define DVO_PORT_DPI 19 /* 217 */ 283 #define DVO_PORT_HDMII 20 /* 217 */ 284 #define DVO_PORT_MIPIA 21 /* 171 */ 285 #define DVO_PORT_MIPIB 22 /* 171 */ 286 #define DVO_PORT_MIPIC 23 /* 171 */ 287 #define DVO_PORT_MIPID 24 /* 171 */ 288 289 #define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204 */ 290 #define HDMI_MAX_DATA_RATE_297 1 /* 204 */ 291 #define HDMI_MAX_DATA_RATE_165 2 /* 204 */ 292 293 #define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33 294 295 /* DDC Bus DDI Type 155+ */ 296 enum vbt_gmbus_ddi { 297 DDC_BUS_DDI_B = 0x1, 298 DDC_BUS_DDI_C, 299 DDC_BUS_DDI_D, 300 DDC_BUS_DDI_F, 301 ICL_DDC_BUS_DDI_A = 0x1, 302 ICL_DDC_BUS_DDI_B, 303 TGL_DDC_BUS_DDI_C, 304 RKL_DDC_BUS_DDI_D = 0x3, 305 RKL_DDC_BUS_DDI_E, 306 ICL_DDC_BUS_PORT_1 = 0x4, 307 ICL_DDC_BUS_PORT_2, 308 ICL_DDC_BUS_PORT_3, 309 ICL_DDC_BUS_PORT_4, 310 TGL_DDC_BUS_PORT_5, 311 TGL_DDC_BUS_PORT_6, 312 ADLS_DDC_BUS_PORT_TC1 = 0x2, 313 ADLS_DDC_BUS_PORT_TC2, 314 ADLS_DDC_BUS_PORT_TC3, 315 ADLS_DDC_BUS_PORT_TC4, 316 ADLP_DDC_BUS_PORT_TC1 = 0x3, 317 ADLP_DDC_BUS_PORT_TC2, 318 ADLP_DDC_BUS_PORT_TC3, 319 ADLP_DDC_BUS_PORT_TC4 320 321 }; 322 323 #define DP_AUX_A 0x40 324 #define DP_AUX_B 0x10 325 #define DP_AUX_C 0x20 326 #define DP_AUX_D 0x30 327 #define DP_AUX_E 0x50 328 #define DP_AUX_F 0x60 329 #define DP_AUX_G 0x70 330 #define DP_AUX_H 0x80 331 #define DP_AUX_I 0x90 332 333 /* DP max link rate 216+ */ 334 #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR3 0 335 #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR2 1 336 #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR 2 337 #define BDB_216_VBT_DP_MAX_LINK_RATE_LBR 3 338 339 /* DP max link rate 230+ */ 340 #define BDB_230_VBT_DP_MAX_LINK_RATE_DEF 0 341 #define BDB_230_VBT_DP_MAX_LINK_RATE_LBR 1 342 #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR 2 343 #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR2 3 344 #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR3 4 345 #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10 5 346 #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5 6 347 #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20 7 348 349 /* 350 * The child device config, aka the display device data structure, provides a 351 * description of a port and its configuration on the platform. 352 * 353 * The child device config size has been increased, and fields have been added 354 * and their meaning has changed over time. Care must be taken when accessing 355 * basically any of the fields to ensure the correct interpretation for the BDB 356 * version in question. 357 * 358 * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve 359 * space for the full structure below, and initialize the tail not actually 360 * present in VBT to zeros. Accessing those fields is fine, as long as the 361 * default zero is taken into account, again according to the BDB version. 362 * 363 * BDB versions 155 and below are considered legacy, and version 155 seems to be 364 * a baseline for some of the VBT documentation. When adding new fields, please 365 * include the BDB version when the field was added, if it's above that. 366 */ 367 struct child_device_config { 368 u16 handle; 369 u16 device_type; /* See DEVICE_TYPE_* above */ 370 371 union { 372 u8 device_id[10]; /* ascii string */ 373 struct { 374 u8 i2c_speed; 375 u8 dp_onboard_redriver; /* 158 */ 376 u8 dp_ondock_redriver; /* 158 */ 377 u8 hdmi_level_shifter_value:5; /* 169 */ 378 u8 hdmi_max_data_rate:3; /* 204 */ 379 u16 dtd_buf_ptr; /* 161 */ 380 u8 edidless_efp:1; /* 161 */ 381 u8 compression_enable:1; /* 198 */ 382 u8 compression_method_cps:1; /* 198 */ 383 u8 ganged_edp:1; /* 202 */ 384 u8 reserved0:4; 385 u8 compression_structure_index:4; /* 198 */ 386 u8 reserved1:4; 387 u8 slave_port; /* 202 */ 388 u8 reserved2; 389 } __packed; 390 } __packed; 391 392 u16 addin_offset; 393 u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */ 394 u8 i2c_pin; 395 u8 slave_addr; 396 u8 ddc_pin; 397 u16 edid_ptr; 398 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 399 400 union { 401 struct { 402 u8 dvo2_port; 403 u8 i2c2_pin; 404 u8 slave2_addr; 405 u8 ddc2_pin; 406 } __packed; 407 struct { 408 u8 efp_routed:1; /* 158 */ 409 u8 lane_reversal:1; /* 184 */ 410 u8 lspcon:1; /* 192 */ 411 u8 iboost:1; /* 196 */ 412 u8 hpd_invert:1; /* 196 */ 413 u8 use_vbt_vswing:1; /* 218 */ 414 u8 flag_reserved:2; 415 u8 hdmi_support:1; /* 158 */ 416 u8 dp_support:1; /* 158 */ 417 u8 tmds_support:1; /* 158 */ 418 u8 support_reserved:5; 419 u8 aux_channel; 420 u8 dongle_detect; 421 } __packed; 422 } __packed; 423 424 u8 pipe_cap:2; 425 u8 sdvo_stall:1; /* 158 */ 426 u8 hpd_status:2; 427 u8 integrated_encoder:1; 428 u8 capabilities_reserved:2; 429 u8 dvo_wiring; /* See DEVICE_WIRE_* above */ 430 431 union { 432 u8 dvo2_wiring; 433 u8 mipi_bridge_type; /* 171 */ 434 } __packed; 435 436 u16 extended_type; 437 u8 dvo_function; 438 u8 dp_usb_type_c:1; /* 195 */ 439 u8 tbt:1; /* 209 */ 440 u8 flags2_reserved:2; /* 195 */ 441 u8 dp_port_trace_length:4; /* 209 */ 442 u8 dp_gpio_index; /* 195 */ 443 u16 dp_gpio_pin_num; /* 195 */ 444 u8 dp_iboost_level:4; /* 196 */ 445 u8 hdmi_iboost_level:4; /* 196 */ 446 u8 dp_max_link_rate:3; /* 216/230 GLK+ */ 447 u8 dp_max_link_rate_reserved:5; /* 216/230 */ 448 } __packed; 449 450 struct bdb_general_definitions { 451 /* DDC GPIO */ 452 u8 crt_ddc_gmbus_pin; 453 454 /* DPMS bits */ 455 u8 dpms_acpi:1; 456 u8 skip_boot_crt_detect:1; 457 u8 dpms_aim:1; 458 u8 rsvd1:5; /* finish byte */ 459 460 /* boot device bits */ 461 u8 boot_display[2]; 462 u8 child_dev_size; 463 464 /* 465 * Device info: 466 * If TV is present, it'll be at devices[0]. 467 * LVDS will be next, either devices[0] or [1], if present. 468 * On some platforms the number of device is 6. But could be as few as 469 * 4 if both TV and LVDS are missing. 470 * And the device num is related with the size of general definition 471 * block. It is obtained by using the following formula: 472 * number = (block_size - sizeof(bdb_general_definitions))/ 473 * defs->child_dev_size; 474 */ 475 u8 devices[]; 476 } __packed; 477 478 /* 479 * Block 9 - SRD Feature Block 480 */ 481 482 struct psr_table { 483 /* Feature bits */ 484 u8 full_link:1; 485 u8 require_aux_to_wakeup:1; 486 u8 feature_bits_rsvd:6; 487 488 /* Wait times */ 489 u8 idle_frames:4; 490 u8 lines_to_wait:3; 491 u8 wait_times_rsvd:1; 492 493 /* TP wake up time in multiple of 100 */ 494 u16 tp1_wakeup_time; 495 u16 tp2_tp3_wakeup_time; 496 } __packed; 497 498 struct bdb_psr { 499 struct psr_table psr_table[16]; 500 501 /* PSR2 TP2/TP3 wakeup time for 16 panels */ 502 u32 psr2_tp2_tp3_wakeup_time; 503 } __packed; 504 505 /* 506 * Block 12 - Driver Features Data Block 507 */ 508 509 #define BDB_DRIVER_FEATURE_NO_LVDS 0 510 #define BDB_DRIVER_FEATURE_INT_LVDS 1 511 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 512 #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3 513 514 struct bdb_driver_features { 515 u8 boot_dev_algorithm:1; 516 u8 block_display_switch:1; 517 u8 allow_display_switch:1; 518 u8 hotplug_dvo:1; 519 u8 dual_view_zoom:1; 520 u8 int15h_hook:1; 521 u8 sprite_in_clone:1; 522 u8 primary_lfp_id:1; 523 524 u16 boot_mode_x; 525 u16 boot_mode_y; 526 u8 boot_mode_bpp; 527 u8 boot_mode_refresh; 528 529 u16 enable_lfp_primary:1; 530 u16 selective_mode_pruning:1; 531 u16 dual_frequency:1; 532 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 533 u16 nt_clone_support:1; 534 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 535 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 536 u16 cui_aspect_scaling:1; 537 u16 preserve_aspect_ratio:1; 538 u16 sdvo_device_power_down:1; 539 u16 crt_hotplug:1; 540 u16 lvds_config:2; 541 u16 tv_hotplug:1; 542 u16 hdmi_config:2; 543 544 u8 static_display:1; 545 u8 reserved2:7; 546 u16 legacy_crt_max_x; 547 u16 legacy_crt_max_y; 548 u8 legacy_crt_max_refresh; 549 550 u8 hdmi_termination; 551 u8 custom_vbt_version; 552 /* Driver features data block */ 553 u16 rmpm_enabled:1; 554 u16 s2ddt_enabled:1; 555 u16 dpst_enabled:1; 556 u16 bltclt_enabled:1; 557 u16 adb_enabled:1; 558 u16 drrs_enabled:1; 559 u16 grs_enabled:1; 560 u16 gpmt_enabled:1; 561 u16 tbt_enabled:1; 562 u16 psr_enabled:1; 563 u16 ips_enabled:1; 564 u16 reserved3:4; 565 u16 pc_feature_valid:1; 566 } __packed; 567 568 /* 569 * Block 22 - SDVO LVDS General Options 570 */ 571 572 struct bdb_sdvo_lvds_options { 573 u8 panel_backlight; 574 u8 h40_set_panel_type; 575 u8 panel_type; 576 u8 ssc_clk_freq; 577 u16 als_low_trip; 578 u16 als_high_trip; 579 u8 sclalarcoeff_tab_row_num; 580 u8 sclalarcoeff_tab_row_size; 581 u8 coefficient[8]; 582 u8 panel_misc_bits_1; 583 u8 panel_misc_bits_2; 584 u8 panel_misc_bits_3; 585 u8 panel_misc_bits_4; 586 } __packed; 587 588 /* 589 * Block 23 - SDVO LVDS Panel DTDs 590 */ 591 592 struct lvds_dvo_timing { 593 u16 clock; /**< In 10khz */ 594 u8 hactive_lo; 595 u8 hblank_lo; 596 u8 hblank_hi:4; 597 u8 hactive_hi:4; 598 u8 vactive_lo; 599 u8 vblank_lo; 600 u8 vblank_hi:4; 601 u8 vactive_hi:4; 602 u8 hsync_off_lo; 603 u8 hsync_pulse_width_lo; 604 u8 vsync_pulse_width_lo:4; 605 u8 vsync_off_lo:4; 606 u8 vsync_pulse_width_hi:2; 607 u8 vsync_off_hi:2; 608 u8 hsync_pulse_width_hi:2; 609 u8 hsync_off_hi:2; 610 u8 himage_lo; 611 u8 vimage_lo; 612 u8 vimage_hi:4; 613 u8 himage_hi:4; 614 u8 h_border; 615 u8 v_border; 616 u8 rsvd1:3; 617 u8 digital:2; 618 u8 vsync_positive:1; 619 u8 hsync_positive:1; 620 u8 non_interlaced:1; 621 } __packed; 622 623 struct bdb_sdvo_panel_dtds { 624 struct lvds_dvo_timing dtds[4]; 625 } __packed; 626 627 /* 628 * Block 27 - eDP VBT Block 629 */ 630 631 #define EDP_18BPP 0 632 #define EDP_24BPP 1 633 #define EDP_30BPP 2 634 #define EDP_RATE_1_62 0 635 #define EDP_RATE_2_7 1 636 #define EDP_LANE_1 0 637 #define EDP_LANE_2 1 638 #define EDP_LANE_4 3 639 #define EDP_PREEMPHASIS_NONE 0 640 #define EDP_PREEMPHASIS_3_5dB 1 641 #define EDP_PREEMPHASIS_6dB 2 642 #define EDP_PREEMPHASIS_9_5dB 3 643 #define EDP_VSWING_0_4V 0 644 #define EDP_VSWING_0_6V 1 645 #define EDP_VSWING_0_8V 2 646 #define EDP_VSWING_1_2V 3 647 648 649 struct edp_fast_link_params { 650 u8 rate:4; 651 u8 lanes:4; 652 u8 preemphasis:4; 653 u8 vswing:4; 654 } __packed; 655 656 struct edp_pwm_delays { 657 u16 pwm_on_to_backlight_enable; 658 u16 backlight_disable_to_pwm_off; 659 } __packed; 660 661 struct edp_full_link_params { 662 u8 preemphasis:4; 663 u8 vswing:4; 664 } __packed; 665 666 struct bdb_edp { 667 struct edp_power_seq power_seqs[16]; 668 u32 color_depth; 669 struct edp_fast_link_params fast_link_params[16]; 670 u32 sdrrs_msa_timing_delay; 671 672 /* ith bit indicates enabled/disabled for (i+1)th panel */ 673 u16 edp_s3d_feature; /* 162 */ 674 u16 edp_t3_optimization; /* 165 */ 675 u64 edp_vswing_preemph; /* 173 */ 676 u16 fast_link_training; /* 182 */ 677 u16 dpcd_600h_write_required; /* 185 */ 678 struct edp_pwm_delays pwm_delays[16]; /* 186 */ 679 u16 full_link_params_provided; /* 199 */ 680 struct edp_full_link_params full_link_params[16]; /* 199 */ 681 } __packed; 682 683 /* 684 * Block 40 - LFP Data Block 685 */ 686 687 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ 688 #define MODE_MASK 0x3 689 690 struct bdb_lvds_options { 691 u8 panel_type; 692 u8 panel_type2; /* 212 */ 693 /* LVDS capabilities, stored in a dword */ 694 u8 pfit_mode:2; 695 u8 pfit_text_mode_enhanced:1; 696 u8 pfit_gfx_mode_enhanced:1; 697 u8 pfit_ratio_auto:1; 698 u8 pixel_dither:1; 699 u8 lvds_edid:1; 700 u8 rsvd2:1; 701 u8 rsvd4; 702 /* LVDS Panel channel bits stored here */ 703 u32 lvds_panel_channel_bits; 704 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ 705 u16 ssc_bits; 706 u16 ssc_freq; 707 u16 ssc_ddt; 708 /* Panel color depth defined here */ 709 u16 panel_color_depth; 710 /* LVDS panel type bits stored here */ 711 u32 dps_panel_type_bits; 712 /* LVDS backlight control type bits stored here */ 713 u32 blt_control_type_bits; 714 715 u16 lcdvcc_s0_enable; /* 200 */ 716 u32 rotation; /* 228 */ 717 } __packed; 718 719 /* 720 * Block 41 - LFP Data Table Pointers 721 */ 722 723 /* LFP pointer table contains entries to the struct below */ 724 struct lvds_lfp_data_ptr { 725 u16 fp_timing_offset; /* offsets are from start of bdb */ 726 u8 fp_table_size; 727 u16 dvo_timing_offset; 728 u8 dvo_table_size; 729 u16 panel_pnp_id_offset; 730 u8 pnp_table_size; 731 } __packed; 732 733 struct bdb_lvds_lfp_data_ptrs { 734 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ 735 struct lvds_lfp_data_ptr ptr[16]; 736 } __packed; 737 738 /* 739 * Block 42 - LFP Data Tables 740 */ 741 742 /* LFP data has 3 blocks per entry */ 743 struct lvds_fp_timing { 744 u16 x_res; 745 u16 y_res; 746 u32 lvds_reg; 747 u32 lvds_reg_val; 748 u32 pp_on_reg; 749 u32 pp_on_reg_val; 750 u32 pp_off_reg; 751 u32 pp_off_reg_val; 752 u32 pp_cycle_reg; 753 u32 pp_cycle_reg_val; 754 u32 pfit_reg; 755 u32 pfit_reg_val; 756 u16 terminator; 757 } __packed; 758 759 struct lvds_pnp_id { 760 u16 mfg_name; 761 u16 product_code; 762 u32 serial; 763 u8 mfg_week; 764 u8 mfg_year; 765 } __packed; 766 767 struct lvds_lfp_data_entry { 768 struct lvds_fp_timing fp_timing; 769 struct lvds_dvo_timing dvo_timing; 770 struct lvds_pnp_id pnp_id; 771 } __packed; 772 773 struct bdb_lvds_lfp_data { 774 struct lvds_lfp_data_entry data[16]; 775 } __packed; 776 777 /* 778 * Block 43 - LFP Backlight Control Data Block 779 */ 780 781 #define BDB_BACKLIGHT_TYPE_NONE 0 782 #define BDB_BACKLIGHT_TYPE_PWM 2 783 784 struct lfp_backlight_data_entry { 785 u8 type:2; 786 u8 active_low_pwm:1; 787 u8 obsolete1:5; 788 u16 pwm_freq_hz; 789 u8 min_brightness; /* Obsolete from 234+ */ 790 u8 obsolete2; 791 u8 obsolete3; 792 } __packed; 793 794 struct lfp_backlight_control_method { 795 u8 type:4; 796 u8 controller:4; 797 } __packed; 798 799 struct lfp_brightness_level { 800 u16 level; 801 u16 reserved; 802 } __packed; 803 804 #define EXP_BDB_LFP_BL_DATA_SIZE_REV_191 \ 805 offsetof(struct bdb_lfp_backlight_data, brightness_level) 806 #define EXP_BDB_LFP_BL_DATA_SIZE_REV_234 \ 807 offsetof(struct bdb_lfp_backlight_data, brightness_precision_bits) 808 809 struct bdb_lfp_backlight_data { 810 u8 entry_size; 811 struct lfp_backlight_data_entry data[16]; 812 u8 level[16]; /* Obsolete from 234+ */ 813 struct lfp_backlight_control_method backlight_control[16]; 814 struct lfp_brightness_level brightness_level[16]; /* 234+ */ 815 struct lfp_brightness_level brightness_min_level[16]; /* 234+ */ 816 u8 brightness_precision_bits[16]; /* 236+ */ 817 } __packed; 818 819 /* 820 * Block 44 - LFP Power Conservation Features Block 821 */ 822 823 struct als_data_entry { 824 u16 backlight_adjust; 825 u16 lux; 826 } __packed; 827 828 struct agressiveness_profile_entry { 829 u8 dpst_agressiveness : 4; 830 u8 lace_agressiveness : 4; 831 } __packed; 832 833 struct bdb_lfp_power { 834 u8 lfp_feature_bits; 835 struct als_data_entry als[5]; 836 u8 lace_aggressiveness_profile; 837 u16 dpst; 838 u16 psr; 839 u16 drrs; 840 u16 lace_support; 841 u16 adt; 842 u16 dmrrs; 843 u16 adb; 844 u16 lace_enabled_status; 845 struct agressiveness_profile_entry aggressivenes[16]; 846 u16 hobl; /* 232+ */ 847 u16 vrr_feature_enabled; /* 233+ */ 848 } __packed; 849 850 /* 851 * Block 52 - MIPI Configuration Block 852 */ 853 854 #define MAX_MIPI_CONFIGURATIONS 6 855 856 struct bdb_mipi_config { 857 struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; 858 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; 859 } __packed; 860 861 /* 862 * Block 53 - MIPI Sequence Block 863 */ 864 865 struct bdb_mipi_sequence { 866 u8 version; 867 u8 data[]; /* up to 6 variable length blocks */ 868 } __packed; 869 870 /* 871 * Block 56 - Compression Parameters 872 */ 873 874 #define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0 875 #define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1 876 #define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2 877 #define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3 878 879 #define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */ 880 #define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2) 881 882 struct dsc_compression_parameters_entry { 883 u8 version_major:4; 884 u8 version_minor:4; 885 886 u8 rc_buffer_block_size:2; 887 u8 reserved1:6; 888 889 /* 890 * Buffer size in bytes: 891 * 892 * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes 893 */ 894 u8 rc_buffer_size; 895 u32 slices_per_line; 896 897 u8 line_buffer_depth:4; 898 u8 reserved2:4; 899 900 /* Flag Bits 1 */ 901 u8 block_prediction_enable:1; 902 u8 reserved3:7; 903 904 u8 max_bpp; /* mapping */ 905 906 /* Color depth capabilities */ 907 u8 reserved4:1; 908 u8 support_8bpc:1; 909 u8 support_10bpc:1; 910 u8 support_12bpc:1; 911 u8 reserved5:4; 912 913 u16 slice_height; 914 } __packed; 915 916 struct bdb_compression_parameters { 917 u16 entry_size; 918 struct dsc_compression_parameters_entry data[16]; 919 } __packed; 920 921 /* 922 * Block 58 - Generic DTD Block 923 */ 924 925 struct generic_dtd_entry { 926 u32 pixel_clock; 927 u16 hactive; 928 u16 hblank; 929 u16 hfront_porch; 930 u16 hsync; 931 u16 vactive; 932 u16 vblank; 933 u16 vfront_porch; 934 u16 vsync; 935 u16 width_mm; 936 u16 height_mm; 937 938 /* Flags */ 939 u8 rsvd_flags:6; 940 u8 vsync_positive_polarity:1; 941 u8 hsync_positive_polarity:1; 942 943 u8 rsvd[3]; 944 } __packed; 945 946 struct bdb_generic_dtd { 947 u16 gdtd_size; 948 struct generic_dtd_entry dtd[]; /* up to 24 DTD's */ 949 } __packed; 950 951 #endif /* _INTEL_VBT_DEFS_H_ */ 952