1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 * 5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com> 6 * Manasi Navare <manasi.d.navare@intel.com> 7 */ 8 #include <linux/limits.h> 9 10 #include <drm/display/drm_dsc_helper.h> 11 12 #include "i915_drv.h" 13 #include "i915_reg.h" 14 #include "intel_crtc.h" 15 #include "intel_de.h" 16 #include "intel_display_types.h" 17 #include "intel_dsi.h" 18 #include "intel_qp_tables.h" 19 #include "intel_vdsc.h" 20 #include "intel_vdsc_regs.h" 21 22 enum ROW_INDEX_BPP { 23 ROW_INDEX_6BPP = 0, 24 ROW_INDEX_8BPP, 25 ROW_INDEX_10BPP, 26 ROW_INDEX_12BPP, 27 ROW_INDEX_15BPP, 28 MAX_ROW_INDEX 29 }; 30 31 enum COLUMN_INDEX_BPC { 32 COLUMN_INDEX_8BPC = 0, 33 COLUMN_INDEX_10BPC, 34 COLUMN_INDEX_12BPC, 35 COLUMN_INDEX_14BPC, 36 COLUMN_INDEX_16BPC, 37 MAX_COLUMN_INDEX 38 }; 39 40 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ 41 static const u16 rc_buf_thresh[] = { 42 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, 43 7744, 7872, 8000, 8064 44 }; 45 46 struct rc_parameters { 47 u16 initial_xmit_delay; 48 u8 first_line_bpg_offset; 49 u16 initial_offset; 50 u8 flatness_min_qp; 51 u8 flatness_max_qp; 52 u8 rc_quant_incr_limit0; 53 u8 rc_quant_incr_limit1; 54 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; 55 }; 56 57 /* 58 * Selected Rate Control Related Parameter Recommended Values 59 * from DSC_v1.11 spec & C Model release: DSC_model_20161212 60 */ 61 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = { 62 { 63 /* 6BPP/8BPC */ 64 { 768, 15, 6144, 3, 13, 11, 11, { 65 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 }, 66 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 }, 67 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 }, 68 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 } 69 } 70 }, 71 /* 6BPP/10BPC */ 72 { 768, 15, 6144, 7, 17, 15, 15, { 73 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 }, 74 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 }, 75 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 }, 76 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 }, 77 { 17, 18, -12 } 78 } 79 }, 80 /* 6BPP/12BPC */ 81 { 768, 15, 6144, 11, 21, 19, 19, { 82 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 }, 83 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 }, 84 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 }, 85 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 }, 86 { 21, 22, -12 } 87 } 88 }, 89 /* 6BPP/14BPC */ 90 { 768, 15, 6144, 15, 25, 23, 27, { 91 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 }, 92 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 }, 93 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 }, 94 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 }, 95 { 25, 26, -12 } 96 } 97 }, 98 /* 6BPP/16BPC */ 99 { 768, 15, 6144, 19, 29, 27, 27, { 100 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 }, 101 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 }, 102 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 }, 103 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 }, 104 { 29, 30, -12 } 105 } 106 }, 107 }, 108 { 109 /* 8BPP/8BPC */ 110 { 512, 12, 6144, 3, 12, 11, 11, { 111 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 112 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 113 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 }, 114 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 115 } 116 }, 117 /* 8BPP/10BPC */ 118 { 512, 12, 6144, 7, 16, 15, 15, { 119 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 }, 120 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 121 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 122 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 123 } 124 }, 125 /* 8BPP/12BPC */ 126 { 512, 12, 6144, 11, 20, 19, 19, { 127 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 }, 128 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 129 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 130 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 131 { 21, 23, -12 } 132 } 133 }, 134 /* 8BPP/14BPC */ 135 { 512, 12, 6144, 15, 24, 23, 23, { 136 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 }, 137 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 138 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 }, 139 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 }, 140 { 24, 25, -12 } 141 } 142 }, 143 /* 8BPP/16BPC */ 144 { 512, 12, 6144, 19, 28, 27, 27, { 145 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 }, 146 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 147 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 }, 148 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 }, 149 { 28, 29, -12 } 150 } 151 }, 152 }, 153 { 154 /* 10BPP/8BPC */ 155 { 410, 15, 5632, 3, 12, 11, 11, { 156 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 }, 157 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 158 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 }, 159 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 } 160 } 161 }, 162 /* 10BPP/10BPC */ 163 { 410, 15, 5632, 7, 16, 15, 15, { 164 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 }, 165 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 166 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 }, 167 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 } 168 } 169 }, 170 /* 10BPP/12BPC */ 171 { 410, 15, 5632, 11, 20, 19, 19, { 172 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 }, 173 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 174 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 }, 175 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 }, 176 { 19, 20, -12 } 177 } 178 }, 179 /* 10BPP/14BPC */ 180 { 410, 15, 5632, 15, 24, 23, 23, { 181 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 }, 182 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 183 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 }, 184 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 }, 185 { 23, 24, -12 } 186 } 187 }, 188 /* 10BPP/16BPC */ 189 { 410, 15, 5632, 19, 28, 27, 27, { 190 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 }, 191 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 192 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 }, 193 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 }, 194 { 27, 28, -12 } 195 } 196 }, 197 }, 198 { 199 /* 12BPP/8BPC */ 200 { 341, 15, 2048, 3, 12, 11, 11, { 201 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 }, 202 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 }, 203 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, 204 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 } 205 } 206 }, 207 /* 12BPP/10BPC */ 208 { 341, 15, 2048, 7, 16, 15, 15, { 209 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 }, 210 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 }, 211 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 }, 212 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 } 213 } 214 }, 215 /* 12BPP/12BPC */ 216 { 341, 15, 2048, 11, 20, 19, 19, { 217 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 }, 218 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 }, 219 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 }, 220 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 }, 221 { 21, 23, -12 } 222 } 223 }, 224 /* 12BPP/14BPC */ 225 { 341, 15, 2048, 15, 24, 23, 23, { 226 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 }, 227 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 }, 228 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 }, 229 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 }, 230 { 22, 23, -12 } 231 } 232 }, 233 /* 12BPP/16BPC */ 234 { 341, 15, 2048, 19, 28, 27, 27, { 235 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 }, 236 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 }, 237 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 }, 238 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 }, 239 { 26, 27, -12 } 240 } 241 }, 242 }, 243 { 244 /* 15BPP/8BPC */ 245 { 273, 15, 2048, 3, 12, 11, 11, { 246 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 }, 247 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 }, 248 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 }, 249 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 } 250 } 251 }, 252 /* 15BPP/10BPC */ 253 { 273, 15, 2048, 7, 16, 15, 15, { 254 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 }, 255 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 }, 256 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 }, 257 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 } 258 } 259 }, 260 /* 15BPP/12BPC */ 261 { 273, 15, 2048, 11, 20, 19, 19, { 262 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 }, 263 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 }, 264 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 }, 265 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 }, 266 { 16, 17, -12 } 267 } 268 }, 269 /* 15BPP/14BPC */ 270 { 273, 15, 2048, 15, 24, 23, 23, { 271 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 }, 272 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 }, 273 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 }, 274 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 }, 275 { 20, 21, -12 } 276 } 277 }, 278 /* 15BPP/16BPC */ 279 { 273, 15, 2048, 19, 28, 27, 27, { 280 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 }, 281 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 }, 282 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 }, 283 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 }, 284 { 24, 25, -12 } 285 } 286 } 287 } 288 289 }; 290 291 static int get_row_index_for_rc_params(u16 compressed_bpp) 292 { 293 switch (compressed_bpp) { 294 case 6: 295 return ROW_INDEX_6BPP; 296 case 8: 297 return ROW_INDEX_8BPP; 298 case 10: 299 return ROW_INDEX_10BPP; 300 case 12: 301 return ROW_INDEX_12BPP; 302 case 15: 303 return ROW_INDEX_15BPP; 304 default: 305 return -EINVAL; 306 } 307 } 308 309 static int get_column_index_for_rc_params(u8 bits_per_component) 310 { 311 switch (bits_per_component) { 312 case 8: 313 return COLUMN_INDEX_8BPC; 314 case 10: 315 return COLUMN_INDEX_10BPC; 316 case 12: 317 return COLUMN_INDEX_12BPC; 318 case 14: 319 return COLUMN_INDEX_14BPC; 320 case 16: 321 return COLUMN_INDEX_16BPC; 322 default: 323 return -EINVAL; 324 } 325 } 326 327 static const struct rc_parameters *get_rc_params(u16 compressed_bpp, 328 u8 bits_per_component) 329 { 330 int row_index, column_index; 331 332 row_index = get_row_index_for_rc_params(compressed_bpp); 333 if (row_index < 0) 334 return NULL; 335 336 column_index = get_column_index_for_rc_params(bits_per_component); 337 if (column_index < 0) 338 return NULL; 339 340 return &rc_parameters[row_index][column_index]; 341 } 342 343 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) 344 { 345 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 346 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 347 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 348 349 if (!HAS_DSC(i915)) 350 return false; 351 352 if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A) 353 return false; 354 355 return true; 356 } 357 358 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 359 { 360 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 361 362 if (DISPLAY_VER(i915) >= 12) 363 return true; 364 365 if (cpu_transcoder == TRANSCODER_EDP || 366 cpu_transcoder == TRANSCODER_DSI_0 || 367 cpu_transcoder == TRANSCODER_DSI_1) 368 return false; 369 370 /* There's no pipe A DSC engine on ICL */ 371 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); 372 373 return true; 374 } 375 376 static void 377 calculate_rc_params(struct rc_parameters *rc, 378 struct drm_dsc_config *vdsc_cfg) 379 { 380 int bpc = vdsc_cfg->bits_per_component; 381 int bpp = vdsc_cfg->bits_per_pixel >> 4; 382 static const s8 ofs_und6[] = { 383 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 384 }; 385 static const s8 ofs_und8[] = { 386 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 387 }; 388 static const s8 ofs_und12[] = { 389 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 390 }; 391 static const s8 ofs_und15[] = { 392 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 393 }; 394 int qp_bpc_modifier = (bpc - 8) * 2; 395 u32 res, buf_i, bpp_i; 396 397 if (vdsc_cfg->slice_height >= 8) 398 rc->first_line_bpg_offset = 399 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100); 400 else 401 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); 402 403 /* Our hw supports only 444 modes as of today */ 404 if (bpp >= 12) 405 rc->initial_offset = 2048; 406 else if (bpp >= 10) 407 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); 408 else if (bpp >= 8) 409 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); 410 else 411 rc->initial_offset = 6144; 412 413 /* initial_xmit_delay = rc_model_size/2/compression_bpp */ 414 rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); 415 416 rc->flatness_min_qp = 3 + qp_bpc_modifier; 417 rc->flatness_max_qp = 12 + qp_bpc_modifier; 418 419 rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; 420 rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; 421 422 bpp_i = (2 * (bpp - 6)); 423 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { 424 /* Read range_minqp and range_max_qp from qp tables */ 425 rc->rc_range_params[buf_i].range_min_qp = 426 intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420); 427 rc->rc_range_params[buf_i].range_max_qp = 428 intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420); 429 430 /* Calculate range_bgp_offset */ 431 if (bpp <= 6) { 432 rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i]; 433 } else if (bpp <= 8) { 434 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2); 435 rc->rc_range_params[buf_i].range_bpg_offset = 436 ofs_und6[buf_i] + res; 437 } else if (bpp <= 12) { 438 rc->rc_range_params[buf_i].range_bpg_offset = 439 ofs_und8[buf_i]; 440 } else if (bpp <= 15) { 441 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3); 442 rc->rc_range_params[buf_i].range_bpg_offset = 443 ofs_und12[buf_i] + res; 444 } else { 445 rc->rc_range_params[buf_i].range_bpg_offset = 446 ofs_und15[buf_i]; 447 } 448 } 449 } 450 451 static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config, 452 struct drm_dsc_config *vdsc_cfg) 453 { 454 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB || 455 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { 456 if (vdsc_cfg->slice_height > 4095) 457 return -EINVAL; 458 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000) 459 return -EINVAL; 460 } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 461 if (vdsc_cfg->slice_width % 2) 462 return -EINVAL; 463 if (vdsc_cfg->slice_height % 2) 464 return -EINVAL; 465 if (vdsc_cfg->slice_height > 4094) 466 return -EINVAL; 467 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000) 468 return -EINVAL; 469 } 470 471 return 0; 472 } 473 474 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) 475 { 476 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 477 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 478 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; 479 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; 480 const struct rc_parameters *rc_params; 481 struct rc_parameters *rc = NULL; 482 int err; 483 u8 i = 0; 484 485 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; 486 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, 487 pipe_config->dsc.slice_count); 488 489 err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg); 490 491 if (err) { 492 drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n"); 493 return err; 494 } 495 496 /* 497 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0 498 * else 1 499 */ 500 vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 && 501 pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444; 502 503 if (DISPLAY_VER(dev_priv) >= 14 && 504 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 505 vdsc_cfg->native_420 = true; 506 /* We do not support YcBCr422 as of now */ 507 vdsc_cfg->native_422 = false; 508 vdsc_cfg->simple_422 = false; 509 /* Gen 11 does not support VBR */ 510 vdsc_cfg->vbr_enable = false; 511 512 /* Gen 11 only supports integral values of bpp */ 513 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; 514 515 /* 516 * According to DSC 1.2 specs in Section 4.1 if native_420 is set: 517 * -We need to double the current bpp. 518 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice 519 * height < 8. 520 * -second_line_offset_adj is 512 as shown by emperical values to yeild best chroma 521 * preservation in second line. 522 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded 523 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11 524 * fractional bits. 525 */ 526 if (vdsc_cfg->native_420) { 527 vdsc_cfg->bits_per_pixel <<= 1; 528 529 if (vdsc_cfg->slice_height >= 8) 530 vdsc_cfg->second_line_bpg_offset = 12; 531 else 532 vdsc_cfg->second_line_bpg_offset = 533 2 * (vdsc_cfg->slice_height - 1); 534 535 vdsc_cfg->second_line_offset_adj = 512; 536 vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11, 537 vdsc_cfg->slice_height - 1); 538 } 539 540 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; 541 542 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 543 /* 544 * six 0s are appended to the lsb of each threshold value 545 * internally in h/w. 546 * Only 8 bits are allowed for programming RcBufThreshold 547 */ 548 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; 549 } 550 551 /* 552 * For 6bpp, RC Buffer threshold 12 and 13 need a different value 553 * as per C Model 554 */ 555 if (compressed_bpp == 6) { 556 vdsc_cfg->rc_buf_thresh[12] = 0x7C; 557 vdsc_cfg->rc_buf_thresh[13] = 0x7D; 558 } 559 560 /* 561 * From XE_LPD onwards we supports compression bpps in steps of 1 562 * upto uncompressed bpp-1, hence add calculations for all the rc 563 * parameters 564 */ 565 if (DISPLAY_VER(dev_priv) >= 13) { 566 rc = kmalloc(sizeof(*rc), GFP_KERNEL); 567 if (!rc) 568 return -ENOMEM; 569 570 calculate_rc_params(rc, vdsc_cfg); 571 rc_params = rc; 572 } else { 573 rc_params = get_rc_params(compressed_bpp, 574 vdsc_cfg->bits_per_component); 575 if (!rc_params) 576 return -EINVAL; 577 } 578 579 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; 580 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; 581 vdsc_cfg->initial_offset = rc_params->initial_offset; 582 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; 583 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; 584 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; 585 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; 586 587 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 588 vdsc_cfg->rc_range_params[i].range_min_qp = 589 rc_params->rc_range_params[i].range_min_qp; 590 vdsc_cfg->rc_range_params[i].range_max_qp = 591 rc_params->rc_range_params[i].range_max_qp; 592 /* 593 * Range BPG Offset uses 2's complement and is only a 6 bits. So 594 * mask it to get only 6 bits. 595 */ 596 vdsc_cfg->rc_range_params[i].range_bpg_offset = 597 rc_params->rc_range_params[i].range_bpg_offset & 598 DSC_RANGE_BPG_OFFSET_MASK; 599 } 600 601 /* 602 * BitsPerComponent value determines mux_word_size: 603 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to 604 * 48 bits otherwise 64 605 */ 606 if (vdsc_cfg->bits_per_component <= 10) 607 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 608 else 609 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 610 611 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ 612 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / 613 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); 614 615 kfree(rc); 616 617 return 0; 618 } 619 620 enum intel_display_power_domain 621 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 622 { 623 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 624 enum pipe pipe = crtc->pipe; 625 626 /* 627 * VDSC/joining uses a separate power well, PW2, and requires 628 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: 629 * 630 * - ICL eDP/DSI transcoder 631 * - Display version 12 (except RKL) pipe A 632 * 633 * For any other pipe, VDSC/joining uses the power well associated with 634 * the pipe in use. Hence another reference on the pipe power domain 635 * will suffice. (Except no VDSC/joining on ICL pipe A.) 636 */ 637 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) 638 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 639 else if (is_pipe_dsc(crtc, cpu_transcoder)) 640 return POWER_DOMAIN_PIPE(pipe); 641 else 642 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 643 } 644 645 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) 646 { 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 648 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 649 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 650 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 651 enum pipe pipe = crtc->pipe; 652 u32 pps_val = 0; 653 u32 rc_buf_thresh_dword[4]; 654 u32 rc_range_params_dword[8]; 655 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; 656 int i = 0; 657 658 if (crtc_state->bigjoiner_pipes) 659 num_vdsc_instances *= 2; 660 661 /* Populate PICTURE_PARAMETER_SET_0 registers */ 662 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << 663 DSC_VER_MIN_SHIFT | 664 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | 665 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; 666 if (vdsc_cfg->dsc_version_minor == 2) { 667 pps_val |= DSC_ALT_ICH_SEL; 668 if (vdsc_cfg->native_420) 669 pps_val |= DSC_NATIVE_420_ENABLE; 670 if (vdsc_cfg->native_422) 671 pps_val |= DSC_NATIVE_422_ENABLE; 672 } 673 if (vdsc_cfg->block_pred_enable) 674 pps_val |= DSC_BLOCK_PREDICTION; 675 if (vdsc_cfg->convert_rgb) 676 pps_val |= DSC_COLOR_SPACE_CONVERSION; 677 if (vdsc_cfg->simple_422) 678 pps_val |= DSC_422_ENABLE; 679 if (vdsc_cfg->vbr_enable) 680 pps_val |= DSC_VBR_ENABLE; 681 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); 682 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 683 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0, 684 pps_val); 685 /* 686 * If 2 VDSC instances are needed, configure PPS for second 687 * VDSC 688 */ 689 if (crtc_state->dsc.dsc_split) 690 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, 691 pps_val); 692 } else { 693 intel_de_write(dev_priv, 694 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), 695 pps_val); 696 if (crtc_state->dsc.dsc_split) 697 intel_de_write(dev_priv, 698 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), 699 pps_val); 700 } 701 702 /* Populate PICTURE_PARAMETER_SET_1 registers */ 703 pps_val = 0; 704 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); 705 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); 706 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 707 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1, 708 pps_val); 709 /* 710 * If 2 VDSC instances are needed, configure PPS for second 711 * VDSC 712 */ 713 if (crtc_state->dsc.dsc_split) 714 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, 715 pps_val); 716 } else { 717 intel_de_write(dev_priv, 718 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), 719 pps_val); 720 if (crtc_state->dsc.dsc_split) 721 intel_de_write(dev_priv, 722 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), 723 pps_val); 724 } 725 726 /* Populate PICTURE_PARAMETER_SET_2 registers */ 727 pps_val = 0; 728 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | 729 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 730 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); 731 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 732 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2, 733 pps_val); 734 /* 735 * If 2 VDSC instances are needed, configure PPS for second 736 * VDSC 737 */ 738 if (crtc_state->dsc.dsc_split) 739 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, 740 pps_val); 741 } else { 742 intel_de_write(dev_priv, 743 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), 744 pps_val); 745 if (crtc_state->dsc.dsc_split) 746 intel_de_write(dev_priv, 747 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), 748 pps_val); 749 } 750 751 /* Populate PICTURE_PARAMETER_SET_3 registers */ 752 pps_val = 0; 753 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | 754 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); 755 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); 756 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 757 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3, 758 pps_val); 759 /* 760 * If 2 VDSC instances are needed, configure PPS for second 761 * VDSC 762 */ 763 if (crtc_state->dsc.dsc_split) 764 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3, 765 pps_val); 766 } else { 767 intel_de_write(dev_priv, 768 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), 769 pps_val); 770 if (crtc_state->dsc.dsc_split) 771 intel_de_write(dev_priv, 772 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), 773 pps_val); 774 } 775 776 /* Populate PICTURE_PARAMETER_SET_4 registers */ 777 pps_val = 0; 778 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | 779 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); 780 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); 781 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 782 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4, 783 pps_val); 784 /* 785 * If 2 VDSC instances are needed, configure PPS for second 786 * VDSC 787 */ 788 if (crtc_state->dsc.dsc_split) 789 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4, 790 pps_val); 791 } else { 792 intel_de_write(dev_priv, 793 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), 794 pps_val); 795 if (crtc_state->dsc.dsc_split) 796 intel_de_write(dev_priv, 797 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), 798 pps_val); 799 } 800 801 /* Populate PICTURE_PARAMETER_SET_5 registers */ 802 pps_val = 0; 803 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | 804 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); 805 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); 806 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 807 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5, 808 pps_val); 809 /* 810 * If 2 VDSC instances are needed, configure PPS for second 811 * VDSC 812 */ 813 if (crtc_state->dsc.dsc_split) 814 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5, 815 pps_val); 816 } else { 817 intel_de_write(dev_priv, 818 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), 819 pps_val); 820 if (crtc_state->dsc.dsc_split) 821 intel_de_write(dev_priv, 822 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), 823 pps_val); 824 } 825 826 /* Populate PICTURE_PARAMETER_SET_6 registers */ 827 pps_val = 0; 828 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | 829 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | 830 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | 831 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); 832 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); 833 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 834 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6, 835 pps_val); 836 /* 837 * If 2 VDSC instances are needed, configure PPS for second 838 * VDSC 839 */ 840 if (crtc_state->dsc.dsc_split) 841 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6, 842 pps_val); 843 } else { 844 intel_de_write(dev_priv, 845 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), 846 pps_val); 847 if (crtc_state->dsc.dsc_split) 848 intel_de_write(dev_priv, 849 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), 850 pps_val); 851 } 852 853 /* Populate PICTURE_PARAMETER_SET_7 registers */ 854 pps_val = 0; 855 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | 856 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); 857 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); 858 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 859 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7, 860 pps_val); 861 /* 862 * If 2 VDSC instances are needed, configure PPS for second 863 * VDSC 864 */ 865 if (crtc_state->dsc.dsc_split) 866 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7, 867 pps_val); 868 } else { 869 intel_de_write(dev_priv, 870 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), 871 pps_val); 872 if (crtc_state->dsc.dsc_split) 873 intel_de_write(dev_priv, 874 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), 875 pps_val); 876 } 877 878 /* Populate PICTURE_PARAMETER_SET_8 registers */ 879 pps_val = 0; 880 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | 881 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); 882 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); 883 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 884 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8, 885 pps_val); 886 /* 887 * If 2 VDSC instances are needed, configure PPS for second 888 * VDSC 889 */ 890 if (crtc_state->dsc.dsc_split) 891 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8, 892 pps_val); 893 } else { 894 intel_de_write(dev_priv, 895 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), 896 pps_val); 897 if (crtc_state->dsc.dsc_split) 898 intel_de_write(dev_priv, 899 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), 900 pps_val); 901 } 902 903 /* Populate PICTURE_PARAMETER_SET_9 registers */ 904 pps_val = 0; 905 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | 906 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); 907 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); 908 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 909 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9, 910 pps_val); 911 /* 912 * If 2 VDSC instances are needed, configure PPS for second 913 * VDSC 914 */ 915 if (crtc_state->dsc.dsc_split) 916 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9, 917 pps_val); 918 } else { 919 intel_de_write(dev_priv, 920 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), 921 pps_val); 922 if (crtc_state->dsc.dsc_split) 923 intel_de_write(dev_priv, 924 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), 925 pps_val); 926 } 927 928 /* Populate PICTURE_PARAMETER_SET_10 registers */ 929 pps_val = 0; 930 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | 931 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | 932 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | 933 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); 934 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); 935 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 936 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10, 937 pps_val); 938 /* 939 * If 2 VDSC instances are needed, configure PPS for second 940 * VDSC 941 */ 942 if (crtc_state->dsc.dsc_split) 943 intel_de_write(dev_priv, 944 DSCC_PICTURE_PARAMETER_SET_10, pps_val); 945 } else { 946 intel_de_write(dev_priv, 947 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), 948 pps_val); 949 if (crtc_state->dsc.dsc_split) 950 intel_de_write(dev_priv, 951 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), 952 pps_val); 953 } 954 955 /* Populate Picture parameter set 16 */ 956 pps_val = 0; 957 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | 958 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / 959 vdsc_cfg->slice_width) | 960 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / 961 vdsc_cfg->slice_height); 962 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); 963 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 964 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16, 965 pps_val); 966 /* 967 * If 2 VDSC instances are needed, configure PPS for second 968 * VDSC 969 */ 970 if (crtc_state->dsc.dsc_split) 971 intel_de_write(dev_priv, 972 DSCC_PICTURE_PARAMETER_SET_16, pps_val); 973 } else { 974 intel_de_write(dev_priv, 975 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), 976 pps_val); 977 if (crtc_state->dsc.dsc_split) 978 intel_de_write(dev_priv, 979 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), 980 pps_val); 981 } 982 983 if (DISPLAY_VER(dev_priv) >= 14) { 984 /* Populate PICTURE_PARAMETER_SET_17 registers */ 985 pps_val = 0; 986 pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); 987 drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); 988 intel_de_write(dev_priv, 989 MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe), 990 pps_val); 991 if (crtc_state->dsc.dsc_split) 992 intel_de_write(dev_priv, 993 MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe), 994 pps_val); 995 996 /* Populate PICTURE_PARAMETER_SET_18 registers */ 997 pps_val = 0; 998 pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | 999 DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); 1000 drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); 1001 intel_de_write(dev_priv, 1002 MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe), 1003 pps_val); 1004 if (crtc_state->dsc.dsc_split) 1005 intel_de_write(dev_priv, 1006 MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe), 1007 pps_val); 1008 } 1009 1010 /* Populate the RC_BUF_THRESH registers */ 1011 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); 1012 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { 1013 rc_buf_thresh_dword[i / 4] |= 1014 (u32)(vdsc_cfg->rc_buf_thresh[i] << 1015 BITS_PER_BYTE * (i % 4)); 1016 drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i, 1017 rc_buf_thresh_dword[i / 4]); 1018 } 1019 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 1020 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, 1021 rc_buf_thresh_dword[0]); 1022 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, 1023 rc_buf_thresh_dword[1]); 1024 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1, 1025 rc_buf_thresh_dword[2]); 1026 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, 1027 rc_buf_thresh_dword[3]); 1028 if (crtc_state->dsc.dsc_split) { 1029 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, 1030 rc_buf_thresh_dword[0]); 1031 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, 1032 rc_buf_thresh_dword[1]); 1033 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1, 1034 rc_buf_thresh_dword[2]); 1035 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW, 1036 rc_buf_thresh_dword[3]); 1037 } 1038 } else { 1039 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe), 1040 rc_buf_thresh_dword[0]); 1041 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), 1042 rc_buf_thresh_dword[1]); 1043 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe), 1044 rc_buf_thresh_dword[2]); 1045 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), 1046 rc_buf_thresh_dword[3]); 1047 if (crtc_state->dsc.dsc_split) { 1048 intel_de_write(dev_priv, 1049 ICL_DSC1_RC_BUF_THRESH_0(pipe), 1050 rc_buf_thresh_dword[0]); 1051 intel_de_write(dev_priv, 1052 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), 1053 rc_buf_thresh_dword[1]); 1054 intel_de_write(dev_priv, 1055 ICL_DSC1_RC_BUF_THRESH_1(pipe), 1056 rc_buf_thresh_dword[2]); 1057 intel_de_write(dev_priv, 1058 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), 1059 rc_buf_thresh_dword[3]); 1060 } 1061 } 1062 1063 /* Populate the RC_RANGE_PARAMETERS registers */ 1064 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); 1065 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 1066 rc_range_params_dword[i / 2] |= 1067 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << 1068 RC_BPG_OFFSET_SHIFT) | 1069 (vdsc_cfg->rc_range_params[i].range_max_qp << 1070 RC_MAX_QP_SHIFT) | 1071 (vdsc_cfg->rc_range_params[i].range_min_qp << 1072 RC_MIN_QP_SHIFT)) << 16 * (i % 2)); 1073 drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i, 1074 rc_range_params_dword[i / 2]); 1075 } 1076 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 1077 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, 1078 rc_range_params_dword[0]); 1079 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW, 1080 rc_range_params_dword[1]); 1081 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1, 1082 rc_range_params_dword[2]); 1083 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW, 1084 rc_range_params_dword[3]); 1085 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2, 1086 rc_range_params_dword[4]); 1087 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW, 1088 rc_range_params_dword[5]); 1089 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3, 1090 rc_range_params_dword[6]); 1091 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW, 1092 rc_range_params_dword[7]); 1093 if (crtc_state->dsc.dsc_split) { 1094 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0, 1095 rc_range_params_dword[0]); 1096 intel_de_write(dev_priv, 1097 DSCC_RC_RANGE_PARAMETERS_0_UDW, 1098 rc_range_params_dword[1]); 1099 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1, 1100 rc_range_params_dword[2]); 1101 intel_de_write(dev_priv, 1102 DSCC_RC_RANGE_PARAMETERS_1_UDW, 1103 rc_range_params_dword[3]); 1104 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2, 1105 rc_range_params_dword[4]); 1106 intel_de_write(dev_priv, 1107 DSCC_RC_RANGE_PARAMETERS_2_UDW, 1108 rc_range_params_dword[5]); 1109 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3, 1110 rc_range_params_dword[6]); 1111 intel_de_write(dev_priv, 1112 DSCC_RC_RANGE_PARAMETERS_3_UDW, 1113 rc_range_params_dword[7]); 1114 } 1115 } else { 1116 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), 1117 rc_range_params_dword[0]); 1118 intel_de_write(dev_priv, 1119 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), 1120 rc_range_params_dword[1]); 1121 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), 1122 rc_range_params_dword[2]); 1123 intel_de_write(dev_priv, 1124 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), 1125 rc_range_params_dword[3]); 1126 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), 1127 rc_range_params_dword[4]); 1128 intel_de_write(dev_priv, 1129 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), 1130 rc_range_params_dword[5]); 1131 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), 1132 rc_range_params_dword[6]); 1133 intel_de_write(dev_priv, 1134 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), 1135 rc_range_params_dword[7]); 1136 if (crtc_state->dsc.dsc_split) { 1137 intel_de_write(dev_priv, 1138 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), 1139 rc_range_params_dword[0]); 1140 intel_de_write(dev_priv, 1141 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), 1142 rc_range_params_dword[1]); 1143 intel_de_write(dev_priv, 1144 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), 1145 rc_range_params_dword[2]); 1146 intel_de_write(dev_priv, 1147 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), 1148 rc_range_params_dword[3]); 1149 intel_de_write(dev_priv, 1150 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), 1151 rc_range_params_dword[4]); 1152 intel_de_write(dev_priv, 1153 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), 1154 rc_range_params_dword[5]); 1155 intel_de_write(dev_priv, 1156 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), 1157 rc_range_params_dword[6]); 1158 intel_de_write(dev_priv, 1159 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), 1160 rc_range_params_dword[7]); 1161 } 1162 } 1163 } 1164 1165 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, 1166 const struct intel_crtc_state *crtc_state) 1167 { 1168 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1169 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1170 struct mipi_dsi_device *dsi; 1171 struct drm_dsc_picture_parameter_set pps; 1172 enum port port; 1173 1174 if (!crtc_state->dsc.compression_enable) 1175 return; 1176 1177 drm_dsc_pps_payload_pack(&pps, vdsc_cfg); 1178 1179 for_each_dsi_port(port, intel_dsi->ports) { 1180 dsi = intel_dsi->dsi_hosts[port]->device; 1181 1182 mipi_dsi_picture_parameter_set(dsi, &pps); 1183 mipi_dsi_compression_mode(dsi, true); 1184 } 1185 } 1186 1187 void intel_dsc_dp_pps_write(struct intel_encoder *encoder, 1188 const struct intel_crtc_state *crtc_state) 1189 { 1190 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1191 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1192 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; 1193 1194 if (!crtc_state->dsc.compression_enable) 1195 return; 1196 1197 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ 1198 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header); 1199 1200 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ 1201 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); 1202 1203 dig_port->write_infoframe(encoder, crtc_state, 1204 DP_SDP_PPS, &dp_dsc_pps_sdp, 1205 sizeof(dp_dsc_pps_sdp)); 1206 } 1207 1208 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 1209 { 1210 return is_pipe_dsc(crtc, cpu_transcoder) ? 1211 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; 1212 } 1213 1214 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 1215 { 1216 return is_pipe_dsc(crtc, cpu_transcoder) ? 1217 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; 1218 } 1219 1220 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) 1221 { 1222 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1223 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1224 u32 dss_ctl1_val = 0; 1225 1226 if (crtc_state->bigjoiner_pipes && !crtc_state->dsc.compression_enable) { 1227 if (intel_crtc_is_bigjoiner_slave(crtc_state)) 1228 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE; 1229 else 1230 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER; 1231 1232 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); 1233 } 1234 } 1235 1236 void intel_dsc_enable(const struct intel_crtc_state *crtc_state) 1237 { 1238 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1239 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1240 u32 dss_ctl1_val = 0; 1241 u32 dss_ctl2_val = 0; 1242 1243 if (!crtc_state->dsc.compression_enable) 1244 return; 1245 1246 intel_dsc_pps_configure(crtc_state); 1247 1248 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; 1249 if (crtc_state->dsc.dsc_split) { 1250 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; 1251 dss_ctl1_val |= JOINER_ENABLE; 1252 } 1253 if (crtc_state->bigjoiner_pipes) { 1254 dss_ctl1_val |= BIG_JOINER_ENABLE; 1255 if (!intel_crtc_is_bigjoiner_slave(crtc_state)) 1256 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE; 1257 } 1258 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); 1259 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); 1260 } 1261 1262 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) 1263 { 1264 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1265 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1266 1267 /* Disable only if either of them is enabled */ 1268 if (old_crtc_state->dsc.compression_enable || 1269 old_crtc_state->bigjoiner_pipes) { 1270 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); 1271 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); 1272 } 1273 } 1274 1275 void intel_dsc_get_config(struct intel_crtc_state *crtc_state) 1276 { 1277 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1278 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1279 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1280 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1281 enum pipe pipe = crtc->pipe; 1282 enum intel_display_power_domain power_domain; 1283 intel_wakeref_t wakeref; 1284 u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0; 1285 1286 if (!intel_dsc_source_support(crtc_state)) 1287 return; 1288 1289 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder); 1290 1291 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1292 if (!wakeref) 1293 return; 1294 1295 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); 1296 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); 1297 1298 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; 1299 if (!crtc_state->dsc.compression_enable) 1300 goto out; 1301 1302 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && 1303 (dss_ctl1 & JOINER_ENABLE); 1304 1305 /* FIXME: add more state readout as needed */ 1306 1307 /* PPS0 & PPS1 */ 1308 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 1309 pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); 1310 } else { 1311 pps0 = intel_de_read(dev_priv, 1312 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)); 1313 pps1 = intel_de_read(dev_priv, 1314 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); 1315 } 1316 1317 vdsc_cfg->bits_per_pixel = pps1; 1318 1319 if (pps0 & DSC_NATIVE_420_ENABLE) 1320 vdsc_cfg->bits_per_pixel >>= 1; 1321 1322 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; 1323 out: 1324 intel_display_power_put(dev_priv, power_domain, wakeref); 1325 } 1326