1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <linux/gpio/consumer.h> 27 #include <linux/slab.h> 28 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_crtc.h> 31 #include <drm/drm_edid.h> 32 #include <drm/drm_mipi_dsi.h> 33 34 #include "i915_drv.h" 35 #include "intel_atomic.h" 36 #include "intel_connector.h" 37 #include "intel_display_types.h" 38 #include "intel_dsi.h" 39 #include "intel_fifo_underrun.h" 40 #include "intel_panel.h" 41 #include "intel_sideband.h" 42 43 /* return pixels in terms of txbyteclkhs */ 44 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 45 u16 burst_mode_ratio) 46 { 47 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 48 8 * 100), lane_count); 49 } 50 51 /* return pixels equvalent to txbyteclkhs */ 52 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 53 u16 burst_mode_ratio) 54 { 55 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 56 (bpp * burst_mode_ratio)); 57 } 58 59 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 60 { 61 /* It just so happens the VBT matches register contents. */ 62 switch (fmt) { 63 case VID_MODE_FORMAT_RGB888: 64 return MIPI_DSI_FMT_RGB888; 65 case VID_MODE_FORMAT_RGB666: 66 return MIPI_DSI_FMT_RGB666; 67 case VID_MODE_FORMAT_RGB666_PACKED: 68 return MIPI_DSI_FMT_RGB666_PACKED; 69 case VID_MODE_FORMAT_RGB565: 70 return MIPI_DSI_FMT_RGB565; 71 default: 72 MISSING_CASE(fmt); 73 return MIPI_DSI_FMT_RGB666; 74 } 75 } 76 77 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 78 { 79 struct drm_encoder *encoder = &intel_dsi->base.base; 80 struct drm_device *dev = encoder->dev; 81 struct drm_i915_private *dev_priv = to_i915(dev); 82 u32 mask; 83 84 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 85 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 86 87 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), 88 mask, 100)) 89 DRM_ERROR("DPI FIFOs are not empty\n"); 90 } 91 92 static void write_data(struct drm_i915_private *dev_priv, 93 i915_reg_t reg, 94 const u8 *data, u32 len) 95 { 96 u32 i, j; 97 98 for (i = 0; i < len; i += 4) { 99 u32 val = 0; 100 101 for (j = 0; j < min_t(u32, len - i, 4); j++) 102 val |= *data++ << 8 * j; 103 104 I915_WRITE(reg, val); 105 } 106 } 107 108 static void read_data(struct drm_i915_private *dev_priv, 109 i915_reg_t reg, 110 u8 *data, u32 len) 111 { 112 u32 i, j; 113 114 for (i = 0; i < len; i += 4) { 115 u32 val = I915_READ(reg); 116 117 for (j = 0; j < min_t(u32, len - i, 4); j++) 118 *data++ = val >> 8 * j; 119 } 120 } 121 122 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 123 const struct mipi_dsi_msg *msg) 124 { 125 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 126 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; 127 struct drm_i915_private *dev_priv = to_i915(dev); 128 enum port port = intel_dsi_host->port; 129 struct mipi_dsi_packet packet; 130 ssize_t ret; 131 const u8 *header, *data; 132 i915_reg_t data_reg, ctrl_reg; 133 u32 data_mask, ctrl_mask; 134 135 ret = mipi_dsi_create_packet(&packet, msg); 136 if (ret < 0) 137 return ret; 138 139 header = packet.header; 140 data = packet.payload; 141 142 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 143 data_reg = MIPI_LP_GEN_DATA(port); 144 data_mask = LP_DATA_FIFO_FULL; 145 ctrl_reg = MIPI_LP_GEN_CTRL(port); 146 ctrl_mask = LP_CTRL_FIFO_FULL; 147 } else { 148 data_reg = MIPI_HS_GEN_DATA(port); 149 data_mask = HS_DATA_FIFO_FULL; 150 ctrl_reg = MIPI_HS_GEN_CTRL(port); 151 ctrl_mask = HS_CTRL_FIFO_FULL; 152 } 153 154 /* note: this is never true for reads */ 155 if (packet.payload_length) { 156 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 157 data_mask, 50)) 158 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); 159 160 write_data(dev_priv, data_reg, packet.payload, 161 packet.payload_length); 162 } 163 164 if (msg->rx_len) { 165 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); 166 } 167 168 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 169 ctrl_mask, 50)) { 170 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); 171 } 172 173 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); 174 175 /* ->rx_len is set only for reads */ 176 if (msg->rx_len) { 177 data_mask = GEN_READ_DATA_AVAIL; 178 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), 179 data_mask, 50)) 180 DRM_ERROR("Timeout waiting for read data.\n"); 181 182 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); 183 } 184 185 /* XXX: fix for reads and writes */ 186 return 4 + packet.payload_length; 187 } 188 189 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 190 struct mipi_dsi_device *dsi) 191 { 192 return 0; 193 } 194 195 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 196 struct mipi_dsi_device *dsi) 197 { 198 return 0; 199 } 200 201 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 202 .attach = intel_dsi_host_attach, 203 .detach = intel_dsi_host_detach, 204 .transfer = intel_dsi_host_transfer, 205 }; 206 207 /* 208 * send a video mode command 209 * 210 * XXX: commands with data in MIPI_DPI_DATA? 211 */ 212 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 213 enum port port) 214 { 215 struct drm_encoder *encoder = &intel_dsi->base.base; 216 struct drm_device *dev = encoder->dev; 217 struct drm_i915_private *dev_priv = to_i915(dev); 218 u32 mask; 219 220 /* XXX: pipe, hs */ 221 if (hs) 222 cmd &= ~DPI_LP_MODE; 223 else 224 cmd |= DPI_LP_MODE; 225 226 /* clear bit */ 227 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 228 229 /* XXX: old code skips write if control unchanged */ 230 if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) 231 DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd); 232 233 I915_WRITE(MIPI_DPI_CONTROL(port), cmd); 234 235 mask = SPL_PKT_SENT_INTERRUPT; 236 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) 237 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); 238 239 return 0; 240 } 241 242 static void band_gap_reset(struct drm_i915_private *dev_priv) 243 { 244 vlv_flisdsi_get(dev_priv); 245 246 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 247 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 248 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 249 udelay(150); 250 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 251 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 252 253 vlv_flisdsi_put(dev_priv); 254 } 255 256 static int intel_dsi_compute_config(struct intel_encoder *encoder, 257 struct intel_crtc_state *pipe_config, 258 struct drm_connector_state *conn_state) 259 { 260 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 261 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 262 base); 263 struct intel_connector *intel_connector = intel_dsi->attached_connector; 264 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 265 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 266 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 267 int ret; 268 269 DRM_DEBUG_KMS("\n"); 270 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 271 272 if (fixed_mode) { 273 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 274 275 if (HAS_GMCH(dev_priv)) 276 intel_gmch_panel_fitting(crtc, pipe_config, 277 conn_state->scaling_mode); 278 else 279 intel_pch_panel_fitting(crtc, pipe_config, 280 conn_state->scaling_mode); 281 } 282 283 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 284 return -EINVAL; 285 286 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 287 adjusted_mode->flags = 0; 288 289 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 290 pipe_config->pipe_bpp = 24; 291 else 292 pipe_config->pipe_bpp = 18; 293 294 if (IS_GEN9_LP(dev_priv)) { 295 /* Enable Frame time stamp based scanline reporting */ 296 adjusted_mode->private_flags |= 297 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 298 299 /* Dual link goes to DSI transcoder A. */ 300 if (intel_dsi->ports == BIT(PORT_C)) 301 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 302 else 303 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 304 305 ret = bxt_dsi_pll_compute(encoder, pipe_config); 306 if (ret) 307 return -EINVAL; 308 } else { 309 ret = vlv_dsi_pll_compute(encoder, pipe_config); 310 if (ret) 311 return -EINVAL; 312 } 313 314 pipe_config->clock_set = true; 315 316 return 0; 317 } 318 319 static bool glk_dsi_enable_io(struct intel_encoder *encoder) 320 { 321 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 322 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 323 enum port port; 324 u32 tmp; 325 bool cold_boot = false; 326 327 /* Set the MIPI mode 328 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 329 * Power ON MIPI IO first and then write into IO reset and LP wake bits 330 */ 331 for_each_dsi_port(port, intel_dsi->ports) { 332 tmp = I915_READ(MIPI_CTRL(port)); 333 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); 334 } 335 336 /* Put the IO into reset */ 337 tmp = I915_READ(MIPI_CTRL(PORT_A)); 338 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 339 I915_WRITE(MIPI_CTRL(PORT_A), tmp); 340 341 /* Program LP Wake */ 342 for_each_dsi_port(port, intel_dsi->ports) { 343 tmp = I915_READ(MIPI_CTRL(port)); 344 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) 345 tmp &= ~GLK_LP_WAKE; 346 else 347 tmp |= GLK_LP_WAKE; 348 I915_WRITE(MIPI_CTRL(port), tmp); 349 } 350 351 /* Wait for Pwr ACK */ 352 for_each_dsi_port(port, intel_dsi->ports) { 353 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 354 GLK_MIPIIO_PORT_POWERED, 20)) 355 DRM_ERROR("MIPIO port is powergated\n"); 356 } 357 358 /* Check for cold boot scenario */ 359 for_each_dsi_port(port, intel_dsi->ports) { 360 cold_boot |= 361 !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY); 362 } 363 364 return cold_boot; 365 } 366 367 static void glk_dsi_device_ready(struct intel_encoder *encoder) 368 { 369 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 370 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 371 enum port port; 372 u32 val; 373 374 /* Wait for MIPI PHY status bit to set */ 375 for_each_dsi_port(port, intel_dsi->ports) { 376 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 377 GLK_PHY_STATUS_PORT_READY, 20)) 378 DRM_ERROR("PHY is not ON\n"); 379 } 380 381 /* Get IO out of reset */ 382 val = I915_READ(MIPI_CTRL(PORT_A)); 383 I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED); 384 385 /* Get IO out of Low power state*/ 386 for_each_dsi_port(port, intel_dsi->ports) { 387 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { 388 val = I915_READ(MIPI_DEVICE_READY(port)); 389 val &= ~ULPS_STATE_MASK; 390 val |= DEVICE_READY; 391 I915_WRITE(MIPI_DEVICE_READY(port), val); 392 usleep_range(10, 15); 393 } else { 394 /* Enter ULPS */ 395 val = I915_READ(MIPI_DEVICE_READY(port)); 396 val &= ~ULPS_STATE_MASK; 397 val |= (ULPS_STATE_ENTER | DEVICE_READY); 398 I915_WRITE(MIPI_DEVICE_READY(port), val); 399 400 /* Wait for ULPS active */ 401 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 402 GLK_ULPS_NOT_ACTIVE, 20)) 403 DRM_ERROR("ULPS not active\n"); 404 405 /* Exit ULPS */ 406 val = I915_READ(MIPI_DEVICE_READY(port)); 407 val &= ~ULPS_STATE_MASK; 408 val |= (ULPS_STATE_EXIT | DEVICE_READY); 409 I915_WRITE(MIPI_DEVICE_READY(port), val); 410 411 /* Enter Normal Mode */ 412 val = I915_READ(MIPI_DEVICE_READY(port)); 413 val &= ~ULPS_STATE_MASK; 414 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 415 I915_WRITE(MIPI_DEVICE_READY(port), val); 416 417 val = I915_READ(MIPI_CTRL(port)); 418 val &= ~GLK_LP_WAKE; 419 I915_WRITE(MIPI_CTRL(port), val); 420 } 421 } 422 423 /* Wait for Stop state */ 424 for_each_dsi_port(port, intel_dsi->ports) { 425 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 426 GLK_DATA_LANE_STOP_STATE, 20)) 427 DRM_ERROR("Date lane not in STOP state\n"); 428 } 429 430 /* Wait for AFE LATCH */ 431 for_each_dsi_port(port, intel_dsi->ports) { 432 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), 433 AFE_LATCHOUT, 20)) 434 DRM_ERROR("D-PHY not entering LP-11 state\n"); 435 } 436 } 437 438 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 439 { 440 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 441 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 442 enum port port; 443 u32 val; 444 445 DRM_DEBUG_KMS("\n"); 446 447 /* Enable MIPI PHY transparent latch */ 448 for_each_dsi_port(port, intel_dsi->ports) { 449 val = I915_READ(BXT_MIPI_PORT_CTRL(port)); 450 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); 451 usleep_range(2000, 2500); 452 } 453 454 /* Clear ULPS and set device ready */ 455 for_each_dsi_port(port, intel_dsi->ports) { 456 val = I915_READ(MIPI_DEVICE_READY(port)); 457 val &= ~ULPS_STATE_MASK; 458 I915_WRITE(MIPI_DEVICE_READY(port), val); 459 usleep_range(2000, 2500); 460 val |= DEVICE_READY; 461 I915_WRITE(MIPI_DEVICE_READY(port), val); 462 } 463 } 464 465 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 466 { 467 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 468 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 469 enum port port; 470 u32 val; 471 472 DRM_DEBUG_KMS("\n"); 473 474 vlv_flisdsi_get(dev_priv); 475 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 476 * needed everytime after power gate */ 477 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 478 vlv_flisdsi_put(dev_priv); 479 480 /* bandgap reset is needed after everytime we do power gate */ 481 band_gap_reset(dev_priv); 482 483 for_each_dsi_port(port, intel_dsi->ports) { 484 485 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); 486 usleep_range(2500, 3000); 487 488 /* Enable MIPI PHY transparent latch 489 * Common bit for both MIPI Port A & MIPI Port C 490 * No similar bit in MIPI Port C reg 491 */ 492 val = I915_READ(MIPI_PORT_CTRL(PORT_A)); 493 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); 494 usleep_range(1000, 1500); 495 496 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); 497 usleep_range(2500, 3000); 498 499 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); 500 usleep_range(2500, 3000); 501 } 502 } 503 504 static void intel_dsi_device_ready(struct intel_encoder *encoder) 505 { 506 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 507 508 if (IS_GEMINILAKE(dev_priv)) 509 glk_dsi_device_ready(encoder); 510 else if (IS_GEN9_LP(dev_priv)) 511 bxt_dsi_device_ready(encoder); 512 else 513 vlv_dsi_device_ready(encoder); 514 } 515 516 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 517 { 518 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 519 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 520 enum port port; 521 u32 val; 522 523 /* Enter ULPS */ 524 for_each_dsi_port(port, intel_dsi->ports) { 525 val = I915_READ(MIPI_DEVICE_READY(port)); 526 val &= ~ULPS_STATE_MASK; 527 val |= (ULPS_STATE_ENTER | DEVICE_READY); 528 I915_WRITE(MIPI_DEVICE_READY(port), val); 529 } 530 531 /* Wait for MIPI PHY status bit to unset */ 532 for_each_dsi_port(port, intel_dsi->ports) { 533 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 534 GLK_PHY_STATUS_PORT_READY, 20)) 535 DRM_ERROR("PHY is not turning OFF\n"); 536 } 537 538 /* Wait for Pwr ACK bit to unset */ 539 for_each_dsi_port(port, intel_dsi->ports) { 540 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 541 GLK_MIPIIO_PORT_POWERED, 20)) 542 DRM_ERROR("MIPI IO Port is not powergated\n"); 543 } 544 } 545 546 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 547 { 548 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 549 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 550 enum port port; 551 u32 tmp; 552 553 /* Put the IO into reset */ 554 tmp = I915_READ(MIPI_CTRL(PORT_A)); 555 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 556 I915_WRITE(MIPI_CTRL(PORT_A), tmp); 557 558 /* Wait for MIPI PHY status bit to unset */ 559 for_each_dsi_port(port, intel_dsi->ports) { 560 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 561 GLK_PHY_STATUS_PORT_READY, 20)) 562 DRM_ERROR("PHY is not turning OFF\n"); 563 } 564 565 /* Clear MIPI mode */ 566 for_each_dsi_port(port, intel_dsi->ports) { 567 tmp = I915_READ(MIPI_CTRL(port)); 568 tmp &= ~GLK_MIPIIO_ENABLE; 569 I915_WRITE(MIPI_CTRL(port), tmp); 570 } 571 } 572 573 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 574 { 575 glk_dsi_enter_low_power_mode(encoder); 576 glk_dsi_disable_mipi_io(encoder); 577 } 578 579 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 580 { 581 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 582 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 583 enum port port; 584 585 DRM_DEBUG_KMS("\n"); 586 for_each_dsi_port(port, intel_dsi->ports) { 587 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 588 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 589 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); 590 u32 val; 591 592 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 593 ULPS_STATE_ENTER); 594 usleep_range(2000, 2500); 595 596 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 597 ULPS_STATE_EXIT); 598 usleep_range(2000, 2500); 599 600 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | 601 ULPS_STATE_ENTER); 602 usleep_range(2000, 2500); 603 604 /* 605 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 606 * Port A only. MIPI Port C has no similar bit for checking. 607 */ 608 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && 609 intel_de_wait_for_clear(dev_priv, port_ctrl, 610 AFE_LATCHOUT, 30)) 611 DRM_ERROR("DSI LP not going Low\n"); 612 613 /* Disable MIPI PHY transparent latch */ 614 val = I915_READ(port_ctrl); 615 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); 616 usleep_range(1000, 1500); 617 618 I915_WRITE(MIPI_DEVICE_READY(port), 0x00); 619 usleep_range(2000, 2500); 620 } 621 } 622 623 static void intel_dsi_port_enable(struct intel_encoder *encoder, 624 const struct intel_crtc_state *crtc_state) 625 { 626 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 627 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 628 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 629 enum port port; 630 631 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 632 u32 temp; 633 if (IS_GEN9_LP(dev_priv)) { 634 for_each_dsi_port(port, intel_dsi->ports) { 635 temp = I915_READ(MIPI_CTRL(port)); 636 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | 637 intel_dsi->pixel_overlap << 638 BXT_PIXEL_OVERLAP_CNT_SHIFT; 639 I915_WRITE(MIPI_CTRL(port), temp); 640 } 641 } else { 642 temp = I915_READ(VLV_CHICKEN_3); 643 temp &= ~PIXEL_OVERLAP_CNT_MASK | 644 intel_dsi->pixel_overlap << 645 PIXEL_OVERLAP_CNT_SHIFT; 646 I915_WRITE(VLV_CHICKEN_3, temp); 647 } 648 } 649 650 for_each_dsi_port(port, intel_dsi->ports) { 651 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 652 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 653 u32 temp; 654 655 temp = I915_READ(port_ctrl); 656 657 temp &= ~LANE_CONFIGURATION_MASK; 658 temp &= ~DUAL_LINK_MODE_MASK; 659 660 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 661 temp |= (intel_dsi->dual_link - 1) 662 << DUAL_LINK_MODE_SHIFT; 663 if (IS_BROXTON(dev_priv)) 664 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 665 else 666 temp |= crtc->pipe ? 667 LANE_CONFIGURATION_DUAL_LINK_B : 668 LANE_CONFIGURATION_DUAL_LINK_A; 669 } 670 671 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) 672 temp |= DITHERING_ENABLE; 673 674 /* assert ip_tg_enable signal */ 675 I915_WRITE(port_ctrl, temp | DPI_ENABLE); 676 POSTING_READ(port_ctrl); 677 } 678 } 679 680 static void intel_dsi_port_disable(struct intel_encoder *encoder) 681 { 682 struct drm_device *dev = encoder->base.dev; 683 struct drm_i915_private *dev_priv = to_i915(dev); 684 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 685 enum port port; 686 687 for_each_dsi_port(port, intel_dsi->ports) { 688 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 689 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 690 u32 temp; 691 692 /* de-assert ip_tg_enable signal */ 693 temp = I915_READ(port_ctrl); 694 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); 695 POSTING_READ(port_ctrl); 696 } 697 } 698 699 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 700 const struct intel_crtc_state *pipe_config); 701 static void intel_dsi_unprepare(struct intel_encoder *encoder); 702 703 /* 704 * Panel enable/disable sequences from the VBT spec. 705 * 706 * Note the spec has AssertReset / DeassertReset swapped from their 707 * usual naming. We use the normal names to avoid confusion (so below 708 * they are swapped compared to the spec). 709 * 710 * Steps starting with MIPI refer to VBT sequences, note that for v2 711 * VBTs several steps which have a VBT in v2 are expected to be handled 712 * directly by the driver, by directly driving gpios for example. 713 * 714 * v2 video mode seq v3 video mode seq command mode seq 715 * - power on - MIPIPanelPowerOn - power on 716 * - wait t1+t2 - wait t1+t2 717 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 718 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 719 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 720 * - MIPITearOn 721 * - MIPIDisplayOn 722 * - turn on DPI - turn on DPI - set pipe to dsr mode 723 * - MIPIDisplayOn - MIPIDisplayOn 724 * - wait t5 - wait t5 725 * - backlight on - MIPIBacklightOn - backlight on 726 * ... ... ... issue mem cmds ... 727 * - backlight off - MIPIBacklightOff - backlight off 728 * - wait t6 - wait t6 729 * - MIPIDisplayOff 730 * - turn off DPI - turn off DPI - disable pipe dsr mode 731 * - MIPITearOff 732 * - MIPIDisplayOff - MIPIDisplayOff 733 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 734 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 735 * - wait t3 - wait t3 736 * - power off - MIPIPanelPowerOff - power off 737 * - wait t4 - wait t4 738 */ 739 740 /* 741 * DSI port enable has to be done before pipe and plane enable, so we do it in 742 * the pre_enable hook instead of the enable hook. 743 */ 744 static void intel_dsi_pre_enable(struct intel_encoder *encoder, 745 const struct intel_crtc_state *pipe_config, 746 const struct drm_connector_state *conn_state) 747 { 748 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 749 struct drm_crtc *crtc = pipe_config->base.crtc; 750 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 752 int pipe = intel_crtc->pipe; 753 enum port port; 754 u32 val; 755 bool glk_cold_boot = false; 756 757 DRM_DEBUG_KMS("\n"); 758 759 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 760 761 /* 762 * The BIOS may leave the PLL in a wonky state where it doesn't 763 * lock. It needs to be fully powered down to fix it. 764 */ 765 if (IS_GEN9_LP(dev_priv)) { 766 bxt_dsi_pll_disable(encoder); 767 bxt_dsi_pll_enable(encoder, pipe_config); 768 } else { 769 vlv_dsi_pll_disable(encoder); 770 vlv_dsi_pll_enable(encoder, pipe_config); 771 } 772 773 if (IS_BROXTON(dev_priv)) { 774 /* Add MIPI IO reset programming for modeset */ 775 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 776 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 777 val | MIPIO_RST_CTRL); 778 779 /* Power up DSI regulator */ 780 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 781 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0); 782 } 783 784 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 785 u32 val; 786 787 /* Disable DPOunit clock gating, can stall pipe */ 788 val = I915_READ(DSPCLK_GATE_D); 789 val |= DPOUNIT_CLOCK_GATE_DISABLE; 790 I915_WRITE(DSPCLK_GATE_D, val); 791 } 792 793 if (!IS_GEMINILAKE(dev_priv)) 794 intel_dsi_prepare(encoder, pipe_config); 795 796 /* Power on, try both CRC pmic gpio and VBT */ 797 if (intel_dsi->gpio_panel) 798 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 799 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 800 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 801 802 /* Deassert reset */ 803 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 804 805 if (IS_GEMINILAKE(dev_priv)) { 806 glk_cold_boot = glk_dsi_enable_io(encoder); 807 808 /* Prepare port in cold boot(s3/s4) scenario */ 809 if (glk_cold_boot) 810 intel_dsi_prepare(encoder, pipe_config); 811 } 812 813 /* Put device in ready state (LP-11) */ 814 intel_dsi_device_ready(encoder); 815 816 /* Prepare port in normal boot scenario */ 817 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) 818 intel_dsi_prepare(encoder, pipe_config); 819 820 /* Send initialization commands in LP mode */ 821 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 822 823 /* Enable port in pre-enable phase itself because as per hw team 824 * recommendation, port should be enabled befor plane & pipe */ 825 if (is_cmd_mode(intel_dsi)) { 826 for_each_dsi_port(port, intel_dsi->ports) 827 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 828 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 829 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 830 } else { 831 msleep(20); /* XXX */ 832 for_each_dsi_port(port, intel_dsi->ports) 833 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 834 intel_dsi_msleep(intel_dsi, 100); 835 836 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 837 838 intel_dsi_port_enable(encoder, pipe_config); 839 } 840 841 intel_panel_enable_backlight(pipe_config, conn_state); 842 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 843 } 844 845 /* 846 * DSI port disable has to be done after pipe and plane disable, so we do it in 847 * the post_disable hook. 848 */ 849 static void intel_dsi_disable(struct intel_encoder *encoder, 850 const struct intel_crtc_state *old_crtc_state, 851 const struct drm_connector_state *old_conn_state) 852 { 853 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 854 enum port port; 855 856 DRM_DEBUG_KMS("\n"); 857 858 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 859 intel_panel_disable_backlight(old_conn_state); 860 861 /* 862 * According to the spec we should send SHUTDOWN before 863 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 864 * has shown that the v3 sequence works for v2 VBTs too 865 */ 866 if (is_vid_mode(intel_dsi)) { 867 /* Send Shutdown command to the panel in LP mode */ 868 for_each_dsi_port(port, intel_dsi->ports) 869 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 870 msleep(10); 871 } 872 } 873 874 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 875 { 876 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 877 878 if (IS_GEMINILAKE(dev_priv)) 879 glk_dsi_clear_device_ready(encoder); 880 else 881 vlv_dsi_clear_device_ready(encoder); 882 } 883 884 static void intel_dsi_post_disable(struct intel_encoder *encoder, 885 const struct intel_crtc_state *pipe_config, 886 const struct drm_connector_state *conn_state) 887 { 888 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 889 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 890 enum port port; 891 u32 val; 892 893 DRM_DEBUG_KMS("\n"); 894 895 if (is_vid_mode(intel_dsi)) { 896 for_each_dsi_port(port, intel_dsi->ports) 897 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 898 899 intel_dsi_port_disable(encoder); 900 usleep_range(2000, 5000); 901 } 902 903 intel_dsi_unprepare(encoder); 904 905 /* 906 * if disable packets are sent before sending shutdown packet then in 907 * some next enable sequence send turn on packet error is observed 908 */ 909 if (is_cmd_mode(intel_dsi)) 910 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 911 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 912 913 /* Transition to LP-00 */ 914 intel_dsi_clear_device_ready(encoder); 915 916 if (IS_BROXTON(dev_priv)) { 917 /* Power down DSI regulator to save power */ 918 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 919 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT); 920 921 /* Add MIPI IO reset programming for modeset */ 922 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 923 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 924 val & ~MIPIO_RST_CTRL); 925 } 926 927 if (IS_GEN9_LP(dev_priv)) { 928 bxt_dsi_pll_disable(encoder); 929 } else { 930 u32 val; 931 932 vlv_dsi_pll_disable(encoder); 933 934 val = I915_READ(DSPCLK_GATE_D); 935 val &= ~DPOUNIT_CLOCK_GATE_DISABLE; 936 I915_WRITE(DSPCLK_GATE_D, val); 937 } 938 939 /* Assert reset */ 940 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 941 942 /* Power off, try both CRC pmic gpio and VBT */ 943 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); 944 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 945 if (intel_dsi->gpio_panel) 946 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 947 948 /* 949 * FIXME As we do with eDP, just make a note of the time here 950 * and perform the wait before the next panel power on. 951 */ 952 intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); 953 } 954 955 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 956 enum pipe *pipe) 957 { 958 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 959 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 960 intel_wakeref_t wakeref; 961 enum port port; 962 bool active = false; 963 964 DRM_DEBUG_KMS("\n"); 965 966 wakeref = intel_display_power_get_if_enabled(dev_priv, 967 encoder->power_domain); 968 if (!wakeref) 969 return false; 970 971 /* 972 * On Broxton the PLL needs to be enabled with a valid divider 973 * configuration, otherwise accessing DSI registers will hang the 974 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 975 */ 976 if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) 977 goto out_put_power; 978 979 /* XXX: this only works for one DSI output */ 980 for_each_dsi_port(port, intel_dsi->ports) { 981 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? 982 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 983 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; 984 985 /* 986 * Due to some hardware limitations on VLV/CHV, the DPI enable 987 * bit in port C control register does not get set. As a 988 * workaround, check pipe B conf instead. 989 */ 990 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 991 port == PORT_C) 992 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 993 994 /* Try command mode if video mode not enabled */ 995 if (!enabled) { 996 u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); 997 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 998 } 999 1000 if (!enabled) 1001 continue; 1002 1003 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) 1004 continue; 1005 1006 if (IS_GEN9_LP(dev_priv)) { 1007 u32 tmp = I915_READ(MIPI_CTRL(port)); 1008 tmp &= BXT_PIPE_SELECT_MASK; 1009 tmp >>= BXT_PIPE_SELECT_SHIFT; 1010 1011 if (WARN_ON(tmp > PIPE_C)) 1012 continue; 1013 1014 *pipe = tmp; 1015 } else { 1016 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 1017 } 1018 1019 active = true; 1020 break; 1021 } 1022 1023 out_put_power: 1024 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1025 1026 return active; 1027 } 1028 1029 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1030 struct intel_crtc_state *pipe_config) 1031 { 1032 struct drm_device *dev = encoder->base.dev; 1033 struct drm_i915_private *dev_priv = to_i915(dev); 1034 struct drm_display_mode *adjusted_mode = 1035 &pipe_config->base.adjusted_mode; 1036 struct drm_display_mode *adjusted_mode_sw; 1037 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 1038 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1039 unsigned int lane_count = intel_dsi->lane_count; 1040 unsigned int bpp, fmt; 1041 enum port port; 1042 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1043 u16 hfp_sw, hsync_sw, hbp_sw; 1044 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1045 crtc_hblank_start_sw, crtc_hblank_end_sw; 1046 1047 /* FIXME: hw readout should not depend on SW state */ 1048 adjusted_mode_sw = &crtc->config->base.adjusted_mode; 1049 1050 /* 1051 * Atleast one port is active as encoder->get_config called only if 1052 * encoder->get_hw_state() returns true. 1053 */ 1054 for_each_dsi_port(port, intel_dsi->ports) { 1055 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1056 break; 1057 } 1058 1059 fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; 1060 bpp = mipi_dsi_pixel_format_to_bpp( 1061 pixel_format_from_register_bits(fmt)); 1062 1063 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1064 1065 /* Enable Frame time stamo based scanline reporting */ 1066 adjusted_mode->private_flags |= 1067 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 1068 1069 /* In terms of pixels */ 1070 adjusted_mode->crtc_hdisplay = 1071 I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); 1072 adjusted_mode->crtc_vdisplay = 1073 I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); 1074 adjusted_mode->crtc_vtotal = 1075 I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); 1076 1077 hactive = adjusted_mode->crtc_hdisplay; 1078 hfp = I915_READ(MIPI_HFP_COUNT(port)); 1079 1080 /* 1081 * Meaningful for video mode non-burst sync pulse mode only, 1082 * can be zero for non-burst sync events and burst modes 1083 */ 1084 hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); 1085 hbp = I915_READ(MIPI_HBP_COUNT(port)); 1086 1087 /* harizontal values are in terms of high speed byte clock */ 1088 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1089 intel_dsi->burst_mode_ratio); 1090 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1091 intel_dsi->burst_mode_ratio); 1092 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1093 intel_dsi->burst_mode_ratio); 1094 1095 if (intel_dsi->dual_link) { 1096 hfp *= 2; 1097 hsync *= 2; 1098 hbp *= 2; 1099 } 1100 1101 /* vertical values are in terms of lines */ 1102 vfp = I915_READ(MIPI_VFP_COUNT(port)); 1103 vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); 1104 vbp = I915_READ(MIPI_VBP_COUNT(port)); 1105 1106 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1107 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1108 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1109 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1110 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1111 1112 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1113 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1114 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1115 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1116 1117 /* 1118 * In BXT DSI there is no regs programmed with few horizontal timings 1119 * in Pixels but txbyteclkhs.. So retrieval process adds some 1120 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1121 * Actually here for the given adjusted_mode, we are calculating the 1122 * value programmed to the port and then back to the horizontal timing 1123 * param in pixels. This is the expected value, including roundup errors 1124 * And if that is same as retrieved value from port, then 1125 * (HW state) adjusted_mode's horizontal timings are corrected to 1126 * match with SW state to nullify the errors. 1127 */ 1128 /* Calculating the value programmed to the Port register */ 1129 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1130 adjusted_mode_sw->crtc_hdisplay; 1131 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1132 adjusted_mode_sw->crtc_hsync_start; 1133 hbp_sw = adjusted_mode_sw->crtc_htotal - 1134 adjusted_mode_sw->crtc_hsync_end; 1135 1136 if (intel_dsi->dual_link) { 1137 hfp_sw /= 2; 1138 hsync_sw /= 2; 1139 hbp_sw /= 2; 1140 } 1141 1142 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1143 intel_dsi->burst_mode_ratio); 1144 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1145 intel_dsi->burst_mode_ratio); 1146 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1147 intel_dsi->burst_mode_ratio); 1148 1149 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1150 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1151 intel_dsi->burst_mode_ratio); 1152 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1153 intel_dsi->burst_mode_ratio); 1154 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1155 intel_dsi->burst_mode_ratio); 1156 1157 if (intel_dsi->dual_link) { 1158 hfp_sw *= 2; 1159 hsync_sw *= 2; 1160 hbp_sw *= 2; 1161 } 1162 1163 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1164 hsync_sw + hbp_sw; 1165 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1166 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1167 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1168 crtc_hblank_end_sw = crtc_htotal_sw; 1169 1170 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1171 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1172 1173 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1174 adjusted_mode->crtc_hsync_start = 1175 adjusted_mode_sw->crtc_hsync_start; 1176 1177 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1178 adjusted_mode->crtc_hsync_end = 1179 adjusted_mode_sw->crtc_hsync_end; 1180 1181 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1182 adjusted_mode->crtc_hblank_start = 1183 adjusted_mode_sw->crtc_hblank_start; 1184 1185 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1186 adjusted_mode->crtc_hblank_end = 1187 adjusted_mode_sw->crtc_hblank_end; 1188 } 1189 1190 static void intel_dsi_get_config(struct intel_encoder *encoder, 1191 struct intel_crtc_state *pipe_config) 1192 { 1193 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1194 u32 pclk; 1195 DRM_DEBUG_KMS("\n"); 1196 1197 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1198 1199 if (IS_GEN9_LP(dev_priv)) { 1200 bxt_dsi_get_pipe_config(encoder, pipe_config); 1201 pclk = bxt_dsi_get_pclk(encoder, pipe_config); 1202 } else { 1203 pclk = vlv_dsi_get_pclk(encoder, pipe_config); 1204 } 1205 1206 if (pclk) { 1207 pipe_config->base.adjusted_mode.crtc_clock = pclk; 1208 pipe_config->port_clock = pclk; 1209 } 1210 } 1211 1212 /* return txclkesc cycles in terms of divider and duration in us */ 1213 static u16 txclkesc(u32 divider, unsigned int us) 1214 { 1215 switch (divider) { 1216 case ESCAPE_CLOCK_DIVIDER_1: 1217 default: 1218 return 20 * us; 1219 case ESCAPE_CLOCK_DIVIDER_2: 1220 return 10 * us; 1221 case ESCAPE_CLOCK_DIVIDER_4: 1222 return 5 * us; 1223 } 1224 } 1225 1226 static void set_dsi_timings(struct drm_encoder *encoder, 1227 const struct drm_display_mode *adjusted_mode) 1228 { 1229 struct drm_device *dev = encoder->dev; 1230 struct drm_i915_private *dev_priv = to_i915(dev); 1231 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1232 enum port port; 1233 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1234 unsigned int lane_count = intel_dsi->lane_count; 1235 1236 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1237 1238 hactive = adjusted_mode->crtc_hdisplay; 1239 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1240 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1241 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1242 1243 if (intel_dsi->dual_link) { 1244 hactive /= 2; 1245 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1246 hactive += intel_dsi->pixel_overlap; 1247 hfp /= 2; 1248 hsync /= 2; 1249 hbp /= 2; 1250 } 1251 1252 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1253 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1254 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1255 1256 /* horizontal values are in terms of high speed byte clock */ 1257 hactive = txbyteclkhs(hactive, bpp, lane_count, 1258 intel_dsi->burst_mode_ratio); 1259 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1260 hsync = txbyteclkhs(hsync, bpp, lane_count, 1261 intel_dsi->burst_mode_ratio); 1262 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1263 1264 for_each_dsi_port(port, intel_dsi->ports) { 1265 if (IS_GEN9_LP(dev_priv)) { 1266 /* 1267 * Program hdisplay and vdisplay on MIPI transcoder. 1268 * This is different from calculated hactive and 1269 * vactive, as they are calculated per channel basis, 1270 * whereas these values should be based on resolution. 1271 */ 1272 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), 1273 adjusted_mode->crtc_hdisplay); 1274 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), 1275 adjusted_mode->crtc_vdisplay); 1276 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), 1277 adjusted_mode->crtc_vtotal); 1278 } 1279 1280 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); 1281 I915_WRITE(MIPI_HFP_COUNT(port), hfp); 1282 1283 /* meaningful for video mode non-burst sync pulse mode only, 1284 * can be zero for non-burst sync events and burst modes */ 1285 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); 1286 I915_WRITE(MIPI_HBP_COUNT(port), hbp); 1287 1288 /* vertical values are in terms of lines */ 1289 I915_WRITE(MIPI_VFP_COUNT(port), vfp); 1290 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); 1291 I915_WRITE(MIPI_VBP_COUNT(port), vbp); 1292 } 1293 } 1294 1295 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1296 { 1297 switch (fmt) { 1298 case MIPI_DSI_FMT_RGB888: 1299 return VID_MODE_FORMAT_RGB888; 1300 case MIPI_DSI_FMT_RGB666: 1301 return VID_MODE_FORMAT_RGB666; 1302 case MIPI_DSI_FMT_RGB666_PACKED: 1303 return VID_MODE_FORMAT_RGB666_PACKED; 1304 case MIPI_DSI_FMT_RGB565: 1305 return VID_MODE_FORMAT_RGB565; 1306 default: 1307 MISSING_CASE(fmt); 1308 return VID_MODE_FORMAT_RGB666; 1309 } 1310 } 1311 1312 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 1313 const struct intel_crtc_state *pipe_config) 1314 { 1315 struct drm_encoder *encoder = &intel_encoder->base; 1316 struct drm_device *dev = encoder->dev; 1317 struct drm_i915_private *dev_priv = to_i915(dev); 1318 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 1319 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1320 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1321 enum port port; 1322 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1323 u32 val, tmp; 1324 u16 mode_hdisplay; 1325 1326 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); 1327 1328 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1329 1330 if (intel_dsi->dual_link) { 1331 mode_hdisplay /= 2; 1332 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1333 mode_hdisplay += intel_dsi->pixel_overlap; 1334 } 1335 1336 for_each_dsi_port(port, intel_dsi->ports) { 1337 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1338 /* 1339 * escape clock divider, 20MHz, shared for A and C. 1340 * device ready must be off when doing this! txclkesc? 1341 */ 1342 tmp = I915_READ(MIPI_CTRL(PORT_A)); 1343 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1344 I915_WRITE(MIPI_CTRL(PORT_A), tmp | 1345 ESCAPE_CLOCK_DIVIDER_1); 1346 1347 /* read request priority is per pipe */ 1348 tmp = I915_READ(MIPI_CTRL(port)); 1349 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1350 I915_WRITE(MIPI_CTRL(port), tmp | 1351 READ_REQUEST_PRIORITY_HIGH); 1352 } else if (IS_GEN9_LP(dev_priv)) { 1353 enum pipe pipe = intel_crtc->pipe; 1354 1355 tmp = I915_READ(MIPI_CTRL(port)); 1356 tmp &= ~BXT_PIPE_SELECT_MASK; 1357 1358 tmp |= BXT_PIPE_SELECT(pipe); 1359 I915_WRITE(MIPI_CTRL(port), tmp); 1360 } 1361 1362 /* XXX: why here, why like this? handling in irq handler?! */ 1363 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); 1364 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); 1365 1366 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); 1367 1368 I915_WRITE(MIPI_DPI_RESOLUTION(port), 1369 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | 1370 mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1371 } 1372 1373 set_dsi_timings(encoder, adjusted_mode); 1374 1375 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1376 if (is_cmd_mode(intel_dsi)) { 1377 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1378 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1379 } else { 1380 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1381 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1382 } 1383 1384 tmp = 0; 1385 if (intel_dsi->eotp_pkt == 0) 1386 tmp |= EOT_DISABLE; 1387 if (intel_dsi->clock_stop) 1388 tmp |= CLOCKSTOP; 1389 1390 if (IS_GEN9_LP(dev_priv)) { 1391 tmp |= BXT_DPHY_DEFEATURE_EN; 1392 if (!is_cmd_mode(intel_dsi)) 1393 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1394 } 1395 1396 for_each_dsi_port(port, intel_dsi->ports) { 1397 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); 1398 1399 /* timeouts for recovery. one frame IIUC. if counter expires, 1400 * EOT and stop state. */ 1401 1402 /* 1403 * In burst mode, value greater than one DPI line Time in byte 1404 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1405 * said value is recommended. 1406 * 1407 * In non-burst mode, Value greater than one DPI frame time in 1408 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1409 * said value is recommended. 1410 * 1411 * In DBI only mode, value greater than one DBI frame time in 1412 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1413 * said value is recommended. 1414 */ 1415 1416 if (is_vid_mode(intel_dsi) && 1417 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 1418 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), 1419 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, 1420 intel_dsi->lane_count, 1421 intel_dsi->burst_mode_ratio) + 1); 1422 } else { 1423 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), 1424 txbyteclkhs(adjusted_mode->crtc_vtotal * 1425 adjusted_mode->crtc_htotal, 1426 bpp, intel_dsi->lane_count, 1427 intel_dsi->burst_mode_ratio) + 1); 1428 } 1429 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); 1430 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), 1431 intel_dsi->turn_arnd_val); 1432 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), 1433 intel_dsi->rst_timer_val); 1434 1435 /* dphy stuff */ 1436 1437 /* in terms of low power clock */ 1438 I915_WRITE(MIPI_INIT_COUNT(port), 1439 txclkesc(intel_dsi->escape_clk_div, 100)); 1440 1441 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { 1442 /* 1443 * BXT spec says write MIPI_INIT_COUNT for 1444 * both the ports, even if only one is 1445 * getting used. So write the other port 1446 * if not in dual link mode. 1447 */ 1448 I915_WRITE(MIPI_INIT_COUNT(port == 1449 PORT_A ? PORT_C : PORT_A), 1450 intel_dsi->init_count); 1451 } 1452 1453 /* recovery disables */ 1454 I915_WRITE(MIPI_EOT_DISABLE(port), tmp); 1455 1456 /* in terms of low power clock */ 1457 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); 1458 1459 /* in terms of txbyteclkhs. actual high to low switch + 1460 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1461 * 1462 * XXX: write MIPI_STOP_STATE_STALL? 1463 */ 1464 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), 1465 intel_dsi->hs_to_lp_count); 1466 1467 /* XXX: low power clock equivalence in terms of byte clock. 1468 * the number of byte clocks occupied in one low power clock. 1469 * based on txbyteclkhs and txclkesc. 1470 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1471 * ) / 105.??? 1472 */ 1473 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); 1474 1475 if (IS_GEMINILAKE(dev_priv)) { 1476 I915_WRITE(MIPI_TLPX_TIME_COUNT(port), 1477 intel_dsi->lp_byte_clk); 1478 /* Shadow of DPHY reg */ 1479 I915_WRITE(MIPI_CLK_LANE_TIMING(port), 1480 intel_dsi->dphy_reg); 1481 } 1482 1483 /* the bw essential for transmitting 16 long packets containing 1484 * 252 bytes meant for dcs write memory command is programmed in 1485 * this register in terms of byte clocks. based on dsi transfer 1486 * rate and the number of lanes configured the time taken to 1487 * transmit 16 long packets in a dsi stream varies. */ 1488 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); 1489 1490 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), 1491 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | 1492 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1493 1494 if (is_vid_mode(intel_dsi)) 1495 /* Some panels might have resolution which is not a 1496 * multiple of 64 like 1366 x 768. Enable RANDOM 1497 * resolution support for such panels by default */ 1498 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), 1499 intel_dsi->video_frmt_cfg_bits | 1500 intel_dsi->video_mode_format | 1501 IP_TG_CONFIG | 1502 RANDOM_DPI_DISPLAY_RESOLUTION); 1503 } 1504 } 1505 1506 static void intel_dsi_unprepare(struct intel_encoder *encoder) 1507 { 1508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1509 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 1510 enum port port; 1511 u32 val; 1512 1513 if (IS_GEMINILAKE(dev_priv)) 1514 return; 1515 1516 for_each_dsi_port(port, intel_dsi->ports) { 1517 /* Panel commands can be sent when clock is in LP11 */ 1518 I915_WRITE(MIPI_DEVICE_READY(port), 0x0); 1519 1520 if (IS_GEN9_LP(dev_priv)) 1521 bxt_dsi_reset_clocks(encoder, port); 1522 else 1523 vlv_dsi_reset_clocks(encoder, port); 1524 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); 1525 1526 val = I915_READ(MIPI_DSI_FUNC_PRG(port)); 1527 val &= ~VID_MODE_FORMAT_MASK; 1528 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); 1529 1530 I915_WRITE(MIPI_DEVICE_READY(port), 0x1); 1531 } 1532 } 1533 1534 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) 1535 { 1536 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1537 1538 /* dispose of the gpios */ 1539 if (intel_dsi->gpio_panel) 1540 gpiod_put(intel_dsi->gpio_panel); 1541 1542 intel_encoder_destroy(encoder); 1543 } 1544 1545 static const struct drm_encoder_funcs intel_dsi_funcs = { 1546 .destroy = intel_dsi_encoder_destroy, 1547 }; 1548 1549 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1550 .get_modes = intel_dsi_get_modes, 1551 .mode_valid = intel_dsi_mode_valid, 1552 .atomic_check = intel_digital_connector_atomic_check, 1553 }; 1554 1555 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1556 .late_register = intel_connector_register, 1557 .early_unregister = intel_connector_unregister, 1558 .destroy = intel_connector_destroy, 1559 .fill_modes = drm_helper_probe_single_connector_modes, 1560 .atomic_get_property = intel_digital_connector_atomic_get_property, 1561 .atomic_set_property = intel_digital_connector_atomic_set_property, 1562 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1563 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1564 }; 1565 1566 static enum drm_panel_orientation 1567 vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector) 1568 { 1569 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1570 struct intel_encoder *encoder = connector->encoder; 1571 enum intel_display_power_domain power_domain; 1572 enum drm_panel_orientation orientation; 1573 struct intel_plane *plane; 1574 struct intel_crtc *crtc; 1575 intel_wakeref_t wakeref; 1576 enum pipe pipe; 1577 u32 val; 1578 1579 if (!encoder->get_hw_state(encoder, &pipe)) 1580 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1581 1582 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1583 plane = to_intel_plane(crtc->base.primary); 1584 1585 power_domain = POWER_DOMAIN_PIPE(pipe); 1586 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1587 if (!wakeref) 1588 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1589 1590 val = I915_READ(DSPCNTR(plane->i9xx_plane)); 1591 1592 if (!(val & DISPLAY_PLANE_ENABLE)) 1593 orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; 1594 else if (val & DISPPLANE_ROTATE_180) 1595 orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; 1596 else 1597 orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; 1598 1599 intel_display_power_put(dev_priv, power_domain, wakeref); 1600 1601 return orientation; 1602 } 1603 1604 static enum drm_panel_orientation 1605 vlv_dsi_get_panel_orientation(struct intel_connector *connector) 1606 { 1607 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1608 enum drm_panel_orientation orientation; 1609 1610 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1611 orientation = vlv_dsi_get_hw_panel_orientation(connector); 1612 if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN) 1613 return orientation; 1614 } 1615 1616 return intel_dsi_get_panel_orientation(connector); 1617 } 1618 1619 static void vlv_dsi_add_properties(struct intel_connector *connector) 1620 { 1621 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1622 1623 if (connector->panel.fixed_mode) { 1624 u32 allowed_scalers; 1625 1626 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); 1627 if (!HAS_GMCH(dev_priv)) 1628 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 1629 1630 drm_connector_attach_scaling_mode_property(&connector->base, 1631 allowed_scalers); 1632 1633 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1634 1635 connector->base.display_info.panel_orientation = 1636 vlv_dsi_get_panel_orientation(connector); 1637 drm_connector_init_panel_orientation_property( 1638 &connector->base, 1639 connector->panel.fixed_mode->hdisplay, 1640 connector->panel.fixed_mode->vdisplay); 1641 } 1642 } 1643 1644 #define NS_KHZ_RATIO 1000000 1645 1646 #define PREPARE_CNT_MAX 0x3F 1647 #define EXIT_ZERO_CNT_MAX 0x3F 1648 #define CLK_ZERO_CNT_MAX 0xFF 1649 #define TRAIL_CNT_MAX 0x1F 1650 1651 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1652 { 1653 struct drm_device *dev = intel_dsi->base.base.dev; 1654 struct drm_i915_private *dev_priv = to_i915(dev); 1655 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1656 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1657 u32 ui_num, ui_den; 1658 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1659 u32 ths_prepare_ns, tclk_trail_ns; 1660 u32 tclk_prepare_clkzero, ths_prepare_hszero; 1661 u32 lp_to_hs_switch, hs_to_lp_switch; 1662 u32 mul; 1663 1664 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1665 1666 switch (intel_dsi->lane_count) { 1667 case 1: 1668 case 2: 1669 extra_byte_count = 2; 1670 break; 1671 case 3: 1672 extra_byte_count = 4; 1673 break; 1674 case 4: 1675 default: 1676 extra_byte_count = 3; 1677 break; 1678 } 1679 1680 /* in Kbps */ 1681 ui_num = NS_KHZ_RATIO; 1682 ui_den = intel_dsi_bitrate(intel_dsi); 1683 1684 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; 1685 ths_prepare_hszero = mipi_config->ths_prepare_hszero; 1686 1687 /* 1688 * B060 1689 * LP byte clock = TLPX/ (8UI) 1690 */ 1691 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); 1692 1693 /* DDR clock period = 2 * UI 1694 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ) 1695 * UI(nsec) = 10^6 / bitrate 1696 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate 1697 * DDR clock count = ns_value / DDR clock period 1698 * 1699 * For GEMINILAKE dphy_param_reg will be programmed in terms of 1700 * HS byte clock count for other platform in HS ddr clock count 1701 */ 1702 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; 1703 ths_prepare_ns = max(mipi_config->ths_prepare, 1704 mipi_config->tclk_prepare); 1705 1706 /* prepare count */ 1707 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); 1708 1709 if (prepare_cnt > PREPARE_CNT_MAX) { 1710 DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt); 1711 prepare_cnt = PREPARE_CNT_MAX; 1712 } 1713 1714 /* exit zero count */ 1715 exit_zero_cnt = DIV_ROUND_UP( 1716 (ths_prepare_hszero - ths_prepare_ns) * ui_den, 1717 ui_num * mul 1718 ); 1719 1720 /* 1721 * Exit zero is unified val ths_zero and ths_exit 1722 * minimum value for ths_exit = 110ns 1723 * min (exit_zero_cnt * 2) = 110/UI 1724 * exit_zero_cnt = 55/UI 1725 */ 1726 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) 1727 exit_zero_cnt += 1; 1728 1729 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { 1730 DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt); 1731 exit_zero_cnt = EXIT_ZERO_CNT_MAX; 1732 } 1733 1734 /* clk zero count */ 1735 clk_zero_cnt = DIV_ROUND_UP( 1736 (tclk_prepare_clkzero - ths_prepare_ns) 1737 * ui_den, ui_num * mul); 1738 1739 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { 1740 DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt); 1741 clk_zero_cnt = CLK_ZERO_CNT_MAX; 1742 } 1743 1744 /* trail count */ 1745 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1746 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); 1747 1748 if (trail_cnt > TRAIL_CNT_MAX) { 1749 DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt); 1750 trail_cnt = TRAIL_CNT_MAX; 1751 } 1752 1753 /* B080 */ 1754 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | 1755 clk_zero_cnt << 8 | prepare_cnt; 1756 1757 /* 1758 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * 1759 * mul + 10UI + Extra Byte Count 1760 * 1761 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count 1762 * Extra Byte Count is calculated according to number of lanes. 1763 * High Low Switch Count is the Max of LP to HS and 1764 * HS to LP switch count 1765 * 1766 */ 1767 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); 1768 1769 /* B044 */ 1770 /* FIXME: 1771 * The comment above does not match with the code */ 1772 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + 1773 exit_zero_cnt * mul + 10, 8); 1774 1775 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); 1776 1777 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); 1778 intel_dsi->hs_to_lp_count += extra_byte_count; 1779 1780 /* B088 */ 1781 /* LP -> HS for clock lanes 1782 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + 1783 * extra byte count 1784 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * 1785 * 2(in UI) + extra byte count 1786 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / 1787 * 8 + extra byte count 1788 */ 1789 intel_dsi->clk_lp_to_hs_count = 1790 DIV_ROUND_UP( 1791 4 * tlpx_ui + prepare_cnt * 2 + 1792 clk_zero_cnt * 2, 1793 8); 1794 1795 intel_dsi->clk_lp_to_hs_count += extra_byte_count; 1796 1797 /* HS->LP for Clock Lanes 1798 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + 1799 * Extra byte count 1800 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count 1801 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + 1802 * Extra byte count 1803 */ 1804 intel_dsi->clk_hs_to_lp_count = 1805 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, 1806 8); 1807 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1808 1809 intel_dsi_log_params(intel_dsi); 1810 } 1811 1812 void vlv_dsi_init(struct drm_i915_private *dev_priv) 1813 { 1814 struct drm_device *dev = &dev_priv->drm; 1815 struct intel_dsi *intel_dsi; 1816 struct intel_encoder *intel_encoder; 1817 struct drm_encoder *encoder; 1818 struct intel_connector *intel_connector; 1819 struct drm_connector *connector; 1820 struct drm_display_mode *current_mode, *fixed_mode; 1821 enum port port; 1822 1823 DRM_DEBUG_KMS("\n"); 1824 1825 /* There is no detection method for MIPI so rely on VBT */ 1826 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1827 return; 1828 1829 if (IS_GEN9_LP(dev_priv)) 1830 dev_priv->mipi_mmio_base = BXT_MIPI_BASE; 1831 else 1832 dev_priv->mipi_mmio_base = VLV_MIPI_BASE; 1833 1834 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1835 if (!intel_dsi) 1836 return; 1837 1838 intel_connector = intel_connector_alloc(); 1839 if (!intel_connector) { 1840 kfree(intel_dsi); 1841 return; 1842 } 1843 1844 intel_encoder = &intel_dsi->base; 1845 encoder = &intel_encoder->base; 1846 intel_dsi->attached_connector = intel_connector; 1847 1848 connector = &intel_connector->base; 1849 1850 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, 1851 "DSI %c", port_name(port)); 1852 1853 intel_encoder->compute_config = intel_dsi_compute_config; 1854 intel_encoder->pre_enable = intel_dsi_pre_enable; 1855 intel_encoder->disable = intel_dsi_disable; 1856 intel_encoder->post_disable = intel_dsi_post_disable; 1857 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 1858 intel_encoder->get_config = intel_dsi_get_config; 1859 intel_encoder->update_pipe = intel_panel_update_backlight; 1860 1861 intel_connector->get_hw_state = intel_connector_get_hw_state; 1862 1863 intel_encoder->port = port; 1864 intel_encoder->type = INTEL_OUTPUT_DSI; 1865 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1866 intel_encoder->cloneable = 0; 1867 1868 /* 1869 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1870 * port C. BXT isn't limited like this. 1871 */ 1872 if (IS_GEN9_LP(dev_priv)) 1873 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); 1874 else if (port == PORT_A) 1875 intel_encoder->crtc_mask = BIT(PIPE_A); 1876 else 1877 intel_encoder->crtc_mask = BIT(PIPE_B); 1878 1879 if (dev_priv->vbt.dsi.config->dual_link) 1880 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1881 else 1882 intel_dsi->ports = BIT(port); 1883 1884 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 1885 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 1886 1887 /* Create a DSI host (and a device) for each port. */ 1888 for_each_dsi_port(port, intel_dsi->ports) { 1889 struct intel_dsi_host *host; 1890 1891 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, 1892 port); 1893 if (!host) 1894 goto err; 1895 1896 intel_dsi->dsi_hosts[port] = host; 1897 } 1898 1899 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1900 DRM_DEBUG_KMS("no device found\n"); 1901 goto err; 1902 } 1903 1904 /* Use clock read-back from current hw-state for fastboot */ 1905 current_mode = intel_encoder_current_mode(intel_encoder); 1906 if (current_mode) { 1907 DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n", 1908 intel_dsi->pclk, current_mode->clock); 1909 if (intel_fuzzy_clock_check(intel_dsi->pclk, 1910 current_mode->clock)) { 1911 DRM_DEBUG_KMS("Using GOP pclk\n"); 1912 intel_dsi->pclk = current_mode->clock; 1913 } 1914 1915 kfree(current_mode); 1916 } 1917 1918 vlv_dphy_param_init(intel_dsi); 1919 1920 /* 1921 * In case of BYT with CRC PMIC, we need to use GPIO for 1922 * Panel control. 1923 */ 1924 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1925 (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) { 1926 intel_dsi->gpio_panel = 1927 gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); 1928 1929 if (IS_ERR(intel_dsi->gpio_panel)) { 1930 DRM_ERROR("Failed to own gpio for panel control\n"); 1931 intel_dsi->gpio_panel = NULL; 1932 } 1933 } 1934 1935 drm_connector_init(dev, connector, &intel_dsi_connector_funcs, 1936 DRM_MODE_CONNECTOR_DSI); 1937 1938 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 1939 1940 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 1941 connector->interlace_allowed = false; 1942 connector->doublescan_allowed = false; 1943 1944 intel_connector_attach_encoder(intel_connector, intel_encoder); 1945 1946 mutex_lock(&dev->mode_config.mutex); 1947 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 1948 mutex_unlock(&dev->mode_config.mutex); 1949 1950 if (!fixed_mode) { 1951 DRM_DEBUG_KMS("no fixed mode\n"); 1952 goto err_cleanup_connector; 1953 } 1954 1955 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1956 intel_panel_setup_backlight(connector, INVALID_PIPE); 1957 1958 vlv_dsi_add_properties(intel_connector); 1959 1960 return; 1961 1962 err_cleanup_connector: 1963 drm_connector_cleanup(&intel_connector->base); 1964 err: 1965 drm_encoder_cleanup(&intel_encoder->base); 1966 kfree(intel_dsi); 1967 kfree(intel_connector); 1968 } 1969