15e5d2e20SChris Wilson /*
25e5d2e20SChris Wilson * SPDX-License-Identifier: MIT
35e5d2e20SChris Wilson *
45e5d2e20SChris Wilson * Copyright © 2016 Intel Corporation
55e5d2e20SChris Wilson */
65e5d2e20SChris Wilson
75e5d2e20SChris Wilson #ifndef __I915_GEM_OBJECT_TYPES_H__
85e5d2e20SChris Wilson #define __I915_GEM_OBJECT_TYPES_H__
95e5d2e20SChris Wilson
10ed29c269SMaarten Lankhorst #include <linux/mmu_notifier.h>
11ed29c269SMaarten Lankhorst
125e5d2e20SChris Wilson #include <drm/drm_gem.h>
13a3185f91SChristian König #include <drm/ttm/ttm_bo.h>
14b1e3177bSChris Wilson #include <uapi/drm/i915_drm.h>
155e5d2e20SChris Wilson
165e5d2e20SChris Wilson #include "i915_active.h"
175e5d2e20SChris Wilson #include "i915_selftest.h"
1839a2bd34SThomas Hellström #include "i915_vma_resource.h"
195e5d2e20SChris Wilson
20d6c531abSChris Wilson #include "gt/intel_gt_defines.h"
21d6c531abSChris Wilson
225e5d2e20SChris Wilson struct drm_i915_gem_object;
238e7cb179SChris Wilson struct intel_fronbuffer;
24b6e913e1SThomas Hellström struct intel_memory_region;
255e5d2e20SChris Wilson
265e5d2e20SChris Wilson /*
275e5d2e20SChris Wilson * struct i915_lut_handle tracks the fast lookups from handle to vma used
285e5d2e20SChris Wilson * for execbuf. Although we use a radixtree for that mapping, in order to
295e5d2e20SChris Wilson * remove them as the object or context is closed, we need a secondary list
305e5d2e20SChris Wilson * and a translation entry (i915_lut_handle).
315e5d2e20SChris Wilson */
325e5d2e20SChris Wilson struct i915_lut_handle {
335e5d2e20SChris Wilson struct list_head obj_link;
345e5d2e20SChris Wilson struct i915_gem_context *ctx;
355e5d2e20SChris Wilson u32 handle;
365e5d2e20SChris Wilson };
375e5d2e20SChris Wilson
385e5d2e20SChris Wilson struct drm_i915_gem_object_ops {
395e5d2e20SChris Wilson unsigned int flags;
400ff37575SThomas Hellström #define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
41ebd4a8ecSMatthew Auld /* Skip the shrinker management in set_pages/unset_pages */
42ebd4a8ecSMatthew Auld #define I915_GEM_OBJECT_SELF_MANAGED_SHRINK_LIST BIT(2)
43ebd4a8ecSMatthew Auld #define I915_GEM_OBJECT_IS_PROXY BIT(3)
44ebd4a8ecSMatthew Auld #define I915_GEM_OBJECT_NO_MMAP BIT(4)
455e5d2e20SChris Wilson
465e5d2e20SChris Wilson /* Interface between the GEM object and its backing storage.
475e5d2e20SChris Wilson * get_pages() is called once prior to the use of the associated set
485e5d2e20SChris Wilson * of pages before to binding them into the GTT, and put_pages() is
495e5d2e20SChris Wilson * called after we no longer need them. As we expect there to be
505e5d2e20SChris Wilson * associated cost with migrating pages between the backing storage
515e5d2e20SChris Wilson * and making them available for the GPU (e.g. clflush), we may hold
525e5d2e20SChris Wilson * onto the pages after they are no longer referenced by the GPU
535e5d2e20SChris Wilson * in case they may be used again shortly (for example migrating the
545e5d2e20SChris Wilson * pages to a different memory domain within the GTT). put_pages()
555e5d2e20SChris Wilson * will therefore most likely be called when the object itself is
565e5d2e20SChris Wilson * being released or under memory pressure (where we attempt to
575e5d2e20SChris Wilson * reap pages for the shrinker).
585e5d2e20SChris Wilson */
595e5d2e20SChris Wilson int (*get_pages)(struct drm_i915_gem_object *obj);
605e5d2e20SChris Wilson void (*put_pages)(struct drm_i915_gem_object *obj,
615e5d2e20SChris Wilson struct sg_table *pages);
627ae03459SMatthew Auld int (*truncate)(struct drm_i915_gem_object *obj);
63ffa3fe08SMatthew Auld /**
64ffa3fe08SMatthew Auld * shrink - Perform further backend specific actions to facilate
65ffa3fe08SMatthew Auld * shrinking.
66ffa3fe08SMatthew Auld * @obj: The gem object
67ffa3fe08SMatthew Auld * @flags: Extra flags to control shrinking behaviour in the backend
68ffa3fe08SMatthew Auld *
69ffa3fe08SMatthew Auld * Possible values for @flags:
70ffa3fe08SMatthew Auld *
71ffa3fe08SMatthew Auld * I915_GEM_OBJECT_SHRINK_WRITEBACK - Try to perform writeback of the
72ffa3fe08SMatthew Auld * backing pages, if supported.
73ffa3fe08SMatthew Auld *
74ffa3fe08SMatthew Auld * I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT - Don't wait for the object to
75ffa3fe08SMatthew Auld * idle. Active objects can be considered later. The TTM backend for
76ffa3fe08SMatthew Auld * example might have aync migrations going on, which don't use any
77ffa3fe08SMatthew Auld * i915_vma to track the active GTT binding, and hence having an unbound
78ffa3fe08SMatthew Auld * object might not be enough.
79ffa3fe08SMatthew Auld */
80ffa3fe08SMatthew Auld #define I915_GEM_OBJECT_SHRINK_WRITEBACK BIT(0)
81ffa3fe08SMatthew Auld #define I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT BIT(1)
82ffa3fe08SMatthew Auld int (*shrink)(struct drm_i915_gem_object *obj, unsigned int flags);
835e5d2e20SChris Wilson
840049b688SMatthew Auld int (*pread)(struct drm_i915_gem_object *obj,
850049b688SMatthew Auld const struct drm_i915_gem_pread *arg);
865e5d2e20SChris Wilson int (*pwrite)(struct drm_i915_gem_object *obj,
875e5d2e20SChris Wilson const struct drm_i915_gem_pwrite *arg);
88cf3e3e86SMaarten Lankhorst u64 (*mmap_offset)(struct drm_i915_gem_object *obj);
89903e0387SMatthew Auld void (*unmap_virtual)(struct drm_i915_gem_object *obj);
905e5d2e20SChris Wilson
915e5d2e20SChris Wilson int (*dmabuf_export)(struct drm_i915_gem_object *obj);
92213d5092SThomas Hellström
93213d5092SThomas Hellström /**
94213d5092SThomas Hellström * adjust_lru - notify that the madvise value was updated
95213d5092SThomas Hellström * @obj: The gem object
96213d5092SThomas Hellström *
97213d5092SThomas Hellström * The madvise value may have been updated, or object was recently
98213d5092SThomas Hellström * referenced so act accordingly (Perhaps changing an LRU list etc).
99213d5092SThomas Hellström */
100213d5092SThomas Hellström void (*adjust_lru)(struct drm_i915_gem_object *obj);
101213d5092SThomas Hellström
102213d5092SThomas Hellström /**
103213d5092SThomas Hellström * delayed_free - Override the default delayed free implementation
104213d5092SThomas Hellström */
105213d5092SThomas Hellström void (*delayed_free)(struct drm_i915_gem_object *obj);
106b6e913e1SThomas Hellström
107b6e913e1SThomas Hellström /**
108b6e913e1SThomas Hellström * migrate - Migrate object to a different region either for
109b6e913e1SThomas Hellström * pinning or for as long as the object lock is held.
110b6e913e1SThomas Hellström */
111b6e913e1SThomas Hellström int (*migrate)(struct drm_i915_gem_object *obj,
112695ddc93SMatthew Auld struct intel_memory_region *mr,
113695ddc93SMatthew Auld unsigned int flags);
114b6e913e1SThomas Hellström
1155e5d2e20SChris Wilson void (*release)(struct drm_i915_gem_object *obj);
1167d192daaSChris Wilson
117cf3e3e86SMaarten Lankhorst const struct vm_operations_struct *mmap_ops;
1187d192daaSChris Wilson const char *name; /* friendly name for debug, e.g. lockdep classes */
1195e5d2e20SChris Wilson };
1205e5d2e20SChris Wilson
1213821cc7fSMatthew Auld /**
1223821cc7fSMatthew Auld * enum i915_cache_level - The supported GTT caching values for system memory
1233821cc7fSMatthew Auld * pages.
1243821cc7fSMatthew Auld *
1253821cc7fSMatthew Auld * These translate to some special GTT PTE bits when binding pages into some
1263821cc7fSMatthew Auld * address space. It also determines whether an object, or rather its pages are
1273821cc7fSMatthew Auld * coherent with the GPU, when also reading or writing through the CPU cache
1283821cc7fSMatthew Auld * with those pages.
1293821cc7fSMatthew Auld *
1303821cc7fSMatthew Auld * Userspace can also control this through struct drm_i915_gem_caching.
1313821cc7fSMatthew Auld */
1323821cc7fSMatthew Auld enum i915_cache_level {
1333821cc7fSMatthew Auld /**
1343821cc7fSMatthew Auld * @I915_CACHE_NONE:
1353821cc7fSMatthew Auld *
1363821cc7fSMatthew Auld * GPU access is not coherent with the CPU cache. If the cache is dirty
1373821cc7fSMatthew Auld * and we need the underlying pages to be coherent with some later GPU
1383821cc7fSMatthew Auld * access then we need to manually flush the pages.
1393821cc7fSMatthew Auld *
1403821cc7fSMatthew Auld * On shared LLC platforms reads and writes through the CPU cache are
1413821cc7fSMatthew Auld * still coherent even with this setting. See also
1423821cc7fSMatthew Auld * &drm_i915_gem_object.cache_coherent for more details. Due to this we
1433821cc7fSMatthew Auld * should only ever use uncached for scanout surfaces, otherwise we end
1443821cc7fSMatthew Auld * up over-flushing in some places.
1453821cc7fSMatthew Auld *
1463821cc7fSMatthew Auld * This is the default on non-LLC platforms.
1473821cc7fSMatthew Auld */
1483821cc7fSMatthew Auld I915_CACHE_NONE = 0,
1493821cc7fSMatthew Auld /**
1503821cc7fSMatthew Auld * @I915_CACHE_LLC:
1513821cc7fSMatthew Auld *
1523821cc7fSMatthew Auld * GPU access is coherent with the CPU cache. If the cache is dirty,
1533821cc7fSMatthew Auld * then the GPU will ensure that access remains coherent, when both
1543821cc7fSMatthew Auld * reading and writing through the CPU cache. GPU writes can dirty the
1553821cc7fSMatthew Auld * CPU cache.
1563821cc7fSMatthew Auld *
1573821cc7fSMatthew Auld * Not used for scanout surfaces.
1583821cc7fSMatthew Auld *
1593821cc7fSMatthew Auld * Applies to both platforms with shared LLC(HAS_LLC), and snooping
1603821cc7fSMatthew Auld * based platforms(HAS_SNOOP).
1613821cc7fSMatthew Auld *
1623821cc7fSMatthew Auld * This is the default on shared LLC platforms. The only exception is
1633821cc7fSMatthew Auld * scanout objects, where the display engine is not coherent with the
1643821cc7fSMatthew Auld * CPU cache. For such objects I915_CACHE_NONE or I915_CACHE_WT is
1653821cc7fSMatthew Auld * automatically applied by the kernel in pin_for_display, if userspace
1663821cc7fSMatthew Auld * has not done so already.
1673821cc7fSMatthew Auld */
1683821cc7fSMatthew Auld I915_CACHE_LLC,
1693821cc7fSMatthew Auld /**
1703821cc7fSMatthew Auld * @I915_CACHE_L3_LLC:
1713821cc7fSMatthew Auld *
1723821cc7fSMatthew Auld * Explicitly enable the Gfx L3 cache, with coherent LLC.
1733821cc7fSMatthew Auld *
1743821cc7fSMatthew Auld * The Gfx L3 sits between the domain specific caches, e.g
1753821cc7fSMatthew Auld * sampler/render caches, and the larger LLC. LLC is coherent with the
1763821cc7fSMatthew Auld * GPU, but L3 is only visible to the GPU, so likely needs to be flushed
1773821cc7fSMatthew Auld * when the workload completes.
1783821cc7fSMatthew Auld *
1793821cc7fSMatthew Auld * Not used for scanout surfaces.
1803821cc7fSMatthew Auld *
1813821cc7fSMatthew Auld * Only exposed on some gen7 + GGTT. More recent hardware has dropped
1823821cc7fSMatthew Auld * this explicit setting, where it should now be enabled by default.
1833821cc7fSMatthew Auld */
1843821cc7fSMatthew Auld I915_CACHE_L3_LLC,
1853821cc7fSMatthew Auld /**
1863821cc7fSMatthew Auld * @I915_CACHE_WT:
1873821cc7fSMatthew Auld *
1883821cc7fSMatthew Auld * Write-through. Used for scanout surfaces.
1893821cc7fSMatthew Auld *
1903821cc7fSMatthew Auld * The GPU can utilise the caches, while still having the display engine
1913821cc7fSMatthew Auld * be coherent with GPU writes, as a result we don't need to flush the
1923821cc7fSMatthew Auld * CPU caches when moving out of the render domain. This is the default
1933821cc7fSMatthew Auld * setting chosen by the kernel, if supported by the HW, otherwise we
1943821cc7fSMatthew Auld * fallback to I915_CACHE_NONE. On the CPU side writes through the CPU
1953821cc7fSMatthew Auld * cache still need to be flushed, to remain coherent with the display
1963821cc7fSMatthew Auld * engine.
1973821cc7fSMatthew Auld */
1983821cc7fSMatthew Auld I915_CACHE_WT,
1995e352e32SFei Yang /**
2005e352e32SFei Yang * @I915_MAX_CACHE_LEVEL:
2015e352e32SFei Yang *
2025e352e32SFei Yang * Mark the last entry in the enum. Used for defining cachelevel_to_pat
2035e352e32SFei Yang * array for cache_level to pat translation table.
2045e352e32SFei Yang */
2055e352e32SFei Yang I915_MAX_CACHE_LEVEL,
2063821cc7fSMatthew Auld };
2073821cc7fSMatthew Auld
208e2f4367aSMatthew Auld enum i915_map_type {
209e2f4367aSMatthew Auld I915_MAP_WB = 0,
210e2f4367aSMatthew Auld I915_MAP_WC,
211e2f4367aSMatthew Auld #define I915_MAP_OVERRIDE BIT(31)
212e2f4367aSMatthew Auld I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
213e2f4367aSMatthew Auld I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
214e2f4367aSMatthew Auld };
215e2f4367aSMatthew Auld
216cc662126SAbdiel Janulgue enum i915_mmap_type {
217cc662126SAbdiel Janulgue I915_MMAP_TYPE_GTT = 0,
218cc662126SAbdiel Janulgue I915_MMAP_TYPE_WC,
219cc662126SAbdiel Janulgue I915_MMAP_TYPE_WB,
220cc662126SAbdiel Janulgue I915_MMAP_TYPE_UC,
2217961c5b6SMaarten Lankhorst I915_MMAP_TYPE_FIXED,
222cc662126SAbdiel Janulgue };
223cc662126SAbdiel Janulgue
224cc662126SAbdiel Janulgue struct i915_mmap_offset {
225cc662126SAbdiel Janulgue struct drm_vma_offset_node vma_node;
226cc662126SAbdiel Janulgue struct drm_i915_gem_object *obj;
227cc662126SAbdiel Janulgue enum i915_mmap_type mmap_type;
228cc662126SAbdiel Janulgue
22978655598SChris Wilson struct rb_node offset;
230cc662126SAbdiel Janulgue };
231cc662126SAbdiel Janulgue
232934941edSTvrtko Ursulin struct i915_gem_object_page_iter {
233934941edSTvrtko Ursulin struct scatterlist *sg_pos;
234934941edSTvrtko Ursulin unsigned int sg_idx; /* in pages, but 32bit eek! */
235934941edSTvrtko Ursulin
236934941edSTvrtko Ursulin struct radix_tree_root radix;
237934941edSTvrtko Ursulin struct mutex lock; /* protects this cache */
238934941edSTvrtko Ursulin };
239934941edSTvrtko Ursulin
2405e5d2e20SChris Wilson struct drm_i915_gem_object {
241f4db23f2SThomas Hellström /*
242f4db23f2SThomas Hellström * We might have reason to revisit the below since it wastes
243f4db23f2SThomas Hellström * a lot of space for non-ttm gem objects.
244f4db23f2SThomas Hellström * In any case, always use the accessors for the ttm_buffer_object
245f4db23f2SThomas Hellström * when accessing it.
246f4db23f2SThomas Hellström */
247f4db23f2SThomas Hellström union {
2485e5d2e20SChris Wilson struct drm_gem_object base;
249f4db23f2SThomas Hellström struct ttm_buffer_object __do_not_access;
250f4db23f2SThomas Hellström };
2515e5d2e20SChris Wilson
2525e5d2e20SChris Wilson const struct drm_i915_gem_object_ops *ops;
2535e5d2e20SChris Wilson
2545e5d2e20SChris Wilson struct {
2555e5d2e20SChris Wilson /**
2565e5d2e20SChris Wilson * @vma.lock: protect the list/tree of vmas
2575e5d2e20SChris Wilson */
2585e5d2e20SChris Wilson spinlock_t lock;
2595e5d2e20SChris Wilson
2605e5d2e20SChris Wilson /**
2615e5d2e20SChris Wilson * @vma.list: List of VMAs backed by this object
2625e5d2e20SChris Wilson *
2635e5d2e20SChris Wilson * The VMA on this list are ordered by type, all GGTT vma are
2645e5d2e20SChris Wilson * placed at the head and all ppGTT vma are placed at the tail.
2655e5d2e20SChris Wilson * The different types of GGTT vma are unordered between
2665e5d2e20SChris Wilson * themselves, use the @vma.tree (which has a defined order
2675e5d2e20SChris Wilson * between all VMA) to quickly find an exact match.
2685e5d2e20SChris Wilson */
2695e5d2e20SChris Wilson struct list_head list;
2705e5d2e20SChris Wilson
2715e5d2e20SChris Wilson /**
2725e5d2e20SChris Wilson * @vma.tree: Ordered tree of VMAs backed by this object
2735e5d2e20SChris Wilson *
2745e5d2e20SChris Wilson * All VMA created for this object are placed in the @vma.tree
2755e5d2e20SChris Wilson * for fast retrieval via a binary search in
2765e5d2e20SChris Wilson * i915_vma_instance(). They are also added to @vma.list for
2775e5d2e20SChris Wilson * easy iteration.
2785e5d2e20SChris Wilson */
2795e5d2e20SChris Wilson struct rb_root tree;
2805e5d2e20SChris Wilson } vma;
2815e5d2e20SChris Wilson
2825e5d2e20SChris Wilson /**
2835e5d2e20SChris Wilson * @lut_list: List of vma lookup entries in use for this object.
2845e5d2e20SChris Wilson *
2855e5d2e20SChris Wilson * If this object is closed, we need to remove all of its VMA from
2865e5d2e20SChris Wilson * the fast lookup index in associated contexts; @lut_list provides
2875e5d2e20SChris Wilson * this translation from object to context->handles_vma.
2885e5d2e20SChris Wilson */
2895e5d2e20SChris Wilson struct list_head lut_list;
290096a42ddSChris Wilson spinlock_t lut_lock; /* guards lut_list */
2915e5d2e20SChris Wilson
29280f0b679SMaarten Lankhorst /**
29380f0b679SMaarten Lankhorst * @obj_link: Link into @i915_gem_ww_ctx.obj_list
29480f0b679SMaarten Lankhorst *
29580f0b679SMaarten Lankhorst * When we lock this object through i915_gem_object_lock() with a
29680f0b679SMaarten Lankhorst * context, we add it to the list to ensure we can unlock everything
29780f0b679SMaarten Lankhorst * when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are called.
29880f0b679SMaarten Lankhorst */
29980f0b679SMaarten Lankhorst struct list_head obj_link;
3004d8151aeSThomas Hellström /**
3014d8151aeSThomas Hellström * @shared_resv_from: The object shares the resv from this vm.
3024d8151aeSThomas Hellström */
3034d8151aeSThomas Hellström struct i915_address_space *shares_resv_from;
30480f0b679SMaarten Lankhorst
305e4ae85e3STvrtko Ursulin #ifdef CONFIG_PROC_FS
306e4ae85e3STvrtko Ursulin /**
307e4ae85e3STvrtko Ursulin * @client: @i915_drm_client which created the object
308e4ae85e3STvrtko Ursulin */
309e4ae85e3STvrtko Ursulin struct i915_drm_client *client;
310e4ae85e3STvrtko Ursulin
311e4ae85e3STvrtko Ursulin /**
312e4ae85e3STvrtko Ursulin * @client_link: Link into @i915_drm_client.objects_list
313e4ae85e3STvrtko Ursulin */
314e4ae85e3STvrtko Ursulin struct list_head client_link;
315e4ae85e3STvrtko Ursulin #endif
316e4ae85e3STvrtko Ursulin
3175e5d2e20SChris Wilson union {
3185e5d2e20SChris Wilson struct rcu_head rcu;
3195e5d2e20SChris Wilson struct llist_node freed;
3205e5d2e20SChris Wilson };
3215e5d2e20SChris Wilson
3225e5d2e20SChris Wilson /**
323ad74457aSAnshuman Gupta * Whether the object is currently in the GGTT or any other supported
324ad74457aSAnshuman Gupta * fake offset mmap backed by lmem.
3255e5d2e20SChris Wilson */
3265e5d2e20SChris Wilson unsigned int userfault_count;
3275e5d2e20SChris Wilson struct list_head userfault_link;
3285e5d2e20SChris Wilson
329cc662126SAbdiel Janulgue struct {
330cc662126SAbdiel Janulgue spinlock_t lock; /* Protects access to mmo offsets */
33178655598SChris Wilson struct rb_root offsets;
332cc662126SAbdiel Janulgue } mmo;
333cc662126SAbdiel Janulgue
3345e5d2e20SChris Wilson I915_SELFTEST_DECLARE(struct list_head st_link);
3355e5d2e20SChris Wilson
3362f0b97caSMatthew Auld unsigned long flags;
3372f0b97caSMatthew Auld #define I915_BO_ALLOC_CONTIGUOUS BIT(0)
3387c98501aSMatthew Auld #define I915_BO_ALLOC_VOLATILE BIT(1)
3390ff37575SThomas Hellström #define I915_BO_ALLOC_CPU_CLEAR BIT(2)
3400ff37575SThomas Hellström #define I915_BO_ALLOC_USER BIT(3)
3410d8ee5baSThomas Hellström /* Object is allowed to lose its contents on suspend / resume, even if pinned */
3420d8ee5baSThomas Hellström #define I915_BO_ALLOC_PM_VOLATILE BIT(4)
343a259cc14SThomas Hellström /* Object needs to be restored early using memcpy during resume */
344a259cc14SThomas Hellström #define I915_BO_ALLOC_PM_EARLY BIT(5)
34530b9d1b3SMatthew Auld /*
34630b9d1b3SMatthew Auld * Object is likely never accessed by the CPU. This will prioritise the BO to be
34730b9d1b3SMatthew Auld * allocated in the non-mappable portion of lmem. This is merely a hint, and if
34830b9d1b3SMatthew Auld * dealing with userspace objects the CPU fault handler is free to ignore this.
34930b9d1b3SMatthew Auld */
35030b9d1b3SMatthew Auld #define I915_BO_ALLOC_GPU_ONLY BIT(6)
351ad0fca2dSMatthew Auld #define I915_BO_ALLOC_CCS_AUX BIT(7)
352ddb24fc5SNirmoy Das /*
353ddb24fc5SNirmoy Das * Object is allowed to retain its initial data and will not be cleared on first
354ddb24fc5SNirmoy Das * access if used along with I915_BO_ALLOC_USER. This is mainly to keep
355ddb24fc5SNirmoy Das * preallocated framebuffer data intact while transitioning it to i915drmfb.
356ddb24fc5SNirmoy Das */
357ddb24fc5SNirmoy Das #define I915_BO_PREALLOC BIT(8)
358c471748dSMaarten Lankhorst #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
359c471748dSMaarten Lankhorst I915_BO_ALLOC_VOLATILE | \
360213d5092SThomas Hellström I915_BO_ALLOC_CPU_CLEAR | \
3610d8ee5baSThomas Hellström I915_BO_ALLOC_USER | \
362a259cc14SThomas Hellström I915_BO_ALLOC_PM_VOLATILE | \
36330b9d1b3SMatthew Auld I915_BO_ALLOC_PM_EARLY | \
364ad0fca2dSMatthew Auld I915_BO_ALLOC_GPU_ONLY | \
365ddb24fc5SNirmoy Das I915_BO_ALLOC_CCS_AUX | \
366ddb24fc5SNirmoy Das I915_BO_PREALLOC)
367ddb24fc5SNirmoy Das #define I915_BO_READONLY BIT(9)
368ddb24fc5SNirmoy Das #define I915_TILING_QUIRK_BIT 10 /* unknown swizzling; do not release! */
369ddb24fc5SNirmoy Das #define I915_BO_PROTECTED BIT(11)
3700ff37575SThomas Hellström /**
3710ff37575SThomas Hellström * @mem_flags - Mutable placement-related flags
3720ff37575SThomas Hellström *
3730ff37575SThomas Hellström * These are flags that indicate specifics of the memory region
3740ff37575SThomas Hellström * the object is currently in. As such they are only stable
3750ff37575SThomas Hellström * either under the object lock or if the object is pinned.
3760ff37575SThomas Hellström */
3770ff37575SThomas Hellström unsigned int mem_flags;
3780ff37575SThomas Hellström #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
3790ff37575SThomas Hellström #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
3803821cc7fSMatthew Auld /**
3819275277dSFei Yang * @pat_index: The desired PAT index.
3823821cc7fSMatthew Auld *
3839275277dSFei Yang * See hardware specification for valid PAT indices for each platform.
3849275277dSFei Yang * This field replaces the @cache_level that contains a value of enum
3859275277dSFei Yang * i915_cache_level since PAT indices are being used by both userspace
3869275277dSFei Yang * and kernel mode driver for caching policy control after GEN12.
3879275277dSFei Yang * In the meantime platform specific tables are created to translate
3889275277dSFei Yang * i915_cache_level into pat index, for more details check the macros
389*326e30e4SLucas De Marchi * defined i915/i915_pci.c, e.g. TGL_CACHELEVEL.
3909275277dSFei Yang * For backward compatibility, this field contains values exactly match
3919275277dSFei Yang * the entries of enum i915_cache_level for pre-GEN12 platforms (See
3929275277dSFei Yang * LEGACY_CACHELEVEL), so that the PTE encode functions for these
3939275277dSFei Yang * legacy platforms can stay the same.
3945e5d2e20SChris Wilson */
3959275277dSFei Yang unsigned int pat_index:6;
3969275277dSFei Yang /**
3979275277dSFei Yang * @pat_set_by_user: Indicate whether pat_index is set by user space
3989275277dSFei Yang *
3999275277dSFei Yang * This field is set to false by default, only set to true if the
4009275277dSFei Yang * pat_index is set by user space. By design, user space is capable of
4019275277dSFei Yang * managing caching behavior by setting pat_index, in which case this
4029275277dSFei Yang * kernel mode driver should never touch the pat_index.
4039275277dSFei Yang */
4049275277dSFei Yang unsigned int pat_set_by_user:1;
4053821cc7fSMatthew Auld /**
4063821cc7fSMatthew Auld * @cache_coherent:
4073821cc7fSMatthew Auld *
4089275277dSFei Yang * Note: with the change above which replaced @cache_level with pat_index,
4099275277dSFei Yang * the use of @cache_coherent is limited to the objects created by kernel
4109275277dSFei Yang * or by userspace without pat index specified.
4119275277dSFei Yang * Check for @pat_set_by_user to find out if an object has pat index set
4129275277dSFei Yang * by userspace. The ioctl's to change cache settings have also been
4139275277dSFei Yang * disabled for the objects with pat index set by userspace. Please don't
4149275277dSFei Yang * assume @cache_coherent having the flags set as describe here. A helper
4159275277dSFei Yang * function i915_gem_object_has_cache_level() provides one way to bypass
4169275277dSFei Yang * the use of this field.
4179275277dSFei Yang *
4183821cc7fSMatthew Auld * Track whether the pages are coherent with the GPU if reading or
4193821cc7fSMatthew Auld * writing through the CPU caches. The largely depends on the
4203821cc7fSMatthew Auld * @cache_level setting.
4213821cc7fSMatthew Auld *
4223821cc7fSMatthew Auld * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom
4233821cc7fSMatthew Auld * platforms, coherency must be explicitly requested with some special
4243821cc7fSMatthew Auld * GTT caching bits(see enum i915_cache_level). When enabling coherency
4253821cc7fSMatthew Auld * it does come at a performance and power cost on such platforms. On
4263821cc7fSMatthew Auld * the flip side the kernel does not need to manually flush any buffers
4273821cc7fSMatthew Auld * which need to be coherent with the GPU, if the object is not coherent
4283821cc7fSMatthew Auld * i.e @cache_coherent is zero.
4293821cc7fSMatthew Auld *
4303821cc7fSMatthew Auld * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory
4313821cc7fSMatthew Auld * access will automatically snoop the CPU caches(even with CACHE_NONE).
4323821cc7fSMatthew Auld * The one exception is when dealing with the display engine, like with
4333821cc7fSMatthew Auld * scanout surfaces. To handle this the kernel will always flush the
4343821cc7fSMatthew Auld * surface out of the CPU caches when preparing it for scanout. Also
4353821cc7fSMatthew Auld * note that since scanout surfaces are only ever read by the display
4363821cc7fSMatthew Auld * engine we only need to care about flushing any writes through the CPU
4373821cc7fSMatthew Auld * cache, reads on the other hand will always be coherent.
4383821cc7fSMatthew Auld *
4393821cc7fSMatthew Auld * Something strange here is why @cache_coherent is not a simple
4403821cc7fSMatthew Auld * boolean, i.e coherent vs non-coherent. The reasoning for this is back
4413821cc7fSMatthew Auld * to the display engine not being fully coherent. As a result scanout
4423821cc7fSMatthew Auld * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT.
4433821cc7fSMatthew Auld * In the case of seeing I915_CACHE_NONE the kernel makes the assumption
4443821cc7fSMatthew Auld * that this is likely a scanout surface, and will set @cache_coherent
4453821cc7fSMatthew Auld * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared
4463821cc7fSMatthew Auld * LLC. The kernel uses this to always flush writes through the CPU
4473821cc7fSMatthew Auld * cache as early as possible, where it can, in effect keeping
4483821cc7fSMatthew Auld * @cache_dirty clean, so we can potentially avoid stalling when
4493821cc7fSMatthew Auld * flushing the surface just before doing the scanout. This does mean
4503821cc7fSMatthew Auld * we might unnecessarily flush non-scanout objects in some places, but
4513821cc7fSMatthew Auld * the default assumption is that all normal objects should be using
4523821cc7fSMatthew Auld * I915_CACHE_LLC, at least on platforms with the shared LLC.
4533821cc7fSMatthew Auld *
4543821cc7fSMatthew Auld * Supported values:
4553821cc7fSMatthew Auld *
4563821cc7fSMatthew Auld * I915_BO_CACHE_COHERENT_FOR_READ:
4573821cc7fSMatthew Auld *
4583821cc7fSMatthew Auld * On shared LLC platforms, we use this for special scanout surfaces,
4593821cc7fSMatthew Auld * where the display engine is not coherent with the CPU cache. As such
4603821cc7fSMatthew Auld * we need to ensure we flush any writes before doing the scanout. As an
4613821cc7fSMatthew Auld * optimisation we try to flush any writes as early as possible to avoid
4623821cc7fSMatthew Auld * stalling later.
4633821cc7fSMatthew Auld *
4643821cc7fSMatthew Auld * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC
4653821cc7fSMatthew Auld * platforms, we use:
4663821cc7fSMatthew Auld *
4673821cc7fSMatthew Auld * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ
4683821cc7fSMatthew Auld *
4693821cc7fSMatthew Auld * While for normal objects that are fully coherent, including special
4703821cc7fSMatthew Auld * scanout surfaces marked as I915_CACHE_WT, we use:
4713821cc7fSMatthew Auld *
4723821cc7fSMatthew Auld * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ |
4733821cc7fSMatthew Auld * I915_BO_CACHE_COHERENT_FOR_WRITE
4743821cc7fSMatthew Auld *
4753821cc7fSMatthew Auld * And then for objects that are not coherent at all we use:
4763821cc7fSMatthew Auld *
4773821cc7fSMatthew Auld * cache_coherent = 0
4783821cc7fSMatthew Auld *
4793821cc7fSMatthew Auld * I915_BO_CACHE_COHERENT_FOR_WRITE:
4803821cc7fSMatthew Auld *
4813821cc7fSMatthew Auld * When writing through the CPU cache, the GPU is still coherent. Note
4823821cc7fSMatthew Auld * that this also implies I915_BO_CACHE_COHERENT_FOR_READ.
4833821cc7fSMatthew Auld */
4845e5d2e20SChris Wilson #define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
4855e5d2e20SChris Wilson #define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
4863821cc7fSMatthew Auld unsigned int cache_coherent:2;
4873821cc7fSMatthew Auld
4883821cc7fSMatthew Auld /**
4893821cc7fSMatthew Auld * @cache_dirty:
4903821cc7fSMatthew Auld *
4919275277dSFei Yang * Note: with the change above which replaced cache_level with pat_index,
4929275277dSFei Yang * the use of @cache_dirty is limited to the objects created by kernel
4939275277dSFei Yang * or by userspace without pat index specified.
4949275277dSFei Yang * Check for @pat_set_by_user to find out if an object has pat index set
4959275277dSFei Yang * by userspace. The ioctl's to change cache settings have also been
4969275277dSFei Yang * disabled for the objects with pat_index set by userspace. Please don't
4979275277dSFei Yang * assume @cache_dirty is set as describe here. Also see helper function
4989275277dSFei Yang * i915_gem_object_has_cache_level() for possible ways to bypass the use
4999275277dSFei Yang * of this field.
5009275277dSFei Yang *
5013821cc7fSMatthew Auld * Track if we are we dirty with writes through the CPU cache for this
5023821cc7fSMatthew Auld * object. As a result reading directly from main memory might yield
5033821cc7fSMatthew Auld * stale data.
5043821cc7fSMatthew Auld *
5053821cc7fSMatthew Auld * This also ties into whether the kernel is tracking the object as
5063821cc7fSMatthew Auld * coherent with the GPU, as per @cache_coherent, as it determines if
5073821cc7fSMatthew Auld * flushing might be needed at various points.
5083821cc7fSMatthew Auld *
5093821cc7fSMatthew Auld * Another part of @cache_dirty is managing flushing when first
5103821cc7fSMatthew Auld * acquiring the pages for system memory, at this point the pages are
5113821cc7fSMatthew Auld * considered foreign, so the default assumption is that the cache is
5123821cc7fSMatthew Auld * dirty, for example the page zeroing done by the kernel might leave
5133821cc7fSMatthew Auld * writes though the CPU cache, or swapping-in, while the actual data in
5143821cc7fSMatthew Auld * main memory is potentially stale. Note that this is a potential
5153821cc7fSMatthew Auld * security issue when dealing with userspace objects and zeroing. Now,
5163821cc7fSMatthew Auld * whether we actually need apply the big sledgehammer of flushing all
5173821cc7fSMatthew Auld * the pages on acquire depends on if @cache_coherent is marked as
5183821cc7fSMatthew Auld * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent
5193821cc7fSMatthew Auld * for both reads and writes though the CPU cache.
5203821cc7fSMatthew Auld *
5213821cc7fSMatthew Auld * Note that on shared LLC platforms we still apply the heavy flush for
5223821cc7fSMatthew Auld * I915_CACHE_NONE objects, under the assumption that this is going to
5233821cc7fSMatthew Auld * be used for scanout.
52413d29c82SMatthew Auld *
52513d29c82SMatthew Auld * Update: On some hardware there is now also the 'Bypass LLC' MOCS
52613d29c82SMatthew Auld * entry, which defeats our @cache_coherent tracking, since userspace
52713d29c82SMatthew Auld * can freely bypass the CPU cache when touching the pages with the GPU,
52813d29c82SMatthew Auld * where the kernel is completely unaware. On such platform we need
52913d29c82SMatthew Auld * apply the sledgehammer-on-acquire regardless of the @cache_coherent.
530df94fd05SMatthew Auld *
531df94fd05SMatthew Auld * Special care is taken on non-LLC platforms, to prevent potential
532df94fd05SMatthew Auld * information leak. The driver currently ensures:
533df94fd05SMatthew Auld *
534df94fd05SMatthew Auld * 1. All userspace objects, by default, have @cache_level set as
535df94fd05SMatthew Auld * I915_CACHE_NONE. The only exception is userptr objects, where we
536df94fd05SMatthew Auld * instead force I915_CACHE_LLC, but we also don't allow userspace to
537df94fd05SMatthew Auld * ever change the @cache_level for such objects. Another special case
538df94fd05SMatthew Auld * is dma-buf, which doesn't rely on @cache_dirty, but there we
539df94fd05SMatthew Auld * always do a forced flush when acquiring the pages, if there is a
540df94fd05SMatthew Auld * chance that the pages can be read directly from main memory with
541df94fd05SMatthew Auld * the GPU.
542df94fd05SMatthew Auld *
543df94fd05SMatthew Auld * 2. All I915_CACHE_NONE objects have @cache_dirty initially true.
544df94fd05SMatthew Auld *
545df94fd05SMatthew Auld * 3. All swapped-out objects(i.e shmem) have @cache_dirty set to
546df94fd05SMatthew Auld * true.
547df94fd05SMatthew Auld *
548df94fd05SMatthew Auld * 4. The @cache_dirty is never freely reset before the initial
549df94fd05SMatthew Auld * flush, even if userspace adjusts the @cache_level through the
550df94fd05SMatthew Auld * i915_gem_set_caching_ioctl.
551df94fd05SMatthew Auld *
552df94fd05SMatthew Auld * 5. All @cache_dirty objects(including swapped-in) are initially
553df94fd05SMatthew Auld * flushed with a synchronous call to drm_clflush_sg in
554df94fd05SMatthew Auld * __i915_gem_object_set_pages. The @cache_dirty can be freely reset
555df94fd05SMatthew Auld * at this point. All further asynchronous clfushes are never security
556df94fd05SMatthew Auld * critical, i.e userspace is free to race against itself.
5573821cc7fSMatthew Auld */
5585e5d2e20SChris Wilson unsigned int cache_dirty:1;
5595e5d2e20SChris Wilson
560779cb5baSVille Syrjälä /* @is_dpt: Object houses a display page table (DPT) */
561779cb5baSVille Syrjälä unsigned int is_dpt:1;
562779cb5baSVille Syrjälä
5635e5d2e20SChris Wilson /**
5645e5d2e20SChris Wilson * @read_domains: Read memory domains.
5655e5d2e20SChris Wilson *
5665e5d2e20SChris Wilson * These monitor which caches contain read/write data related to the
5675e5d2e20SChris Wilson * object. When transitioning from one set of domains to another,
5685e5d2e20SChris Wilson * the driver is called to ensure that caches are suitably flushed and
5695e5d2e20SChris Wilson * invalidated.
5705e5d2e20SChris Wilson */
5715e5d2e20SChris Wilson u16 read_domains;
5725e5d2e20SChris Wilson
5735e5d2e20SChris Wilson /**
5745e5d2e20SChris Wilson * @write_domain: Corresponding unique write memory domain.
5755e5d2e20SChris Wilson */
5765e5d2e20SChris Wilson u16 write_domain;
5775e5d2e20SChris Wilson
578da42104fSChris Wilson struct intel_frontbuffer __rcu *frontbuffer;
5795e5d2e20SChris Wilson
5805e5d2e20SChris Wilson /** Current tiling stride for the object, if it's tiled. */
5815e5d2e20SChris Wilson unsigned int tiling_and_stride;
5825e5d2e20SChris Wilson #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
5835e5d2e20SChris Wilson #define TILING_MASK (FENCE_MINIMUM_STRIDE - 1)
5845e5d2e20SChris Wilson #define STRIDE_MASK (~TILING_MASK)
5855e5d2e20SChris Wilson
5865e5d2e20SChris Wilson struct {
587f86dbacbSDaniel Vetter /*
588f86dbacbSDaniel Vetter * Protects the pages and their use. Do not use directly, but
589f86dbacbSDaniel Vetter * instead go through the pin/unpin interfaces.
590f86dbacbSDaniel Vetter */
5915e5d2e20SChris Wilson atomic_t pages_pin_count;
592e25d1ea4SMatthew Auld
593e25d1ea4SMatthew Auld /**
594e25d1ea4SMatthew Auld * @shrink_pin: Prevents the pages from being made visible to
595e25d1ea4SMatthew Auld * the shrinker, while the shrink_pin is non-zero. Most users
596e25d1ea4SMatthew Auld * should pretty much never have to care about this, outside of
597e25d1ea4SMatthew Auld * some special use cases.
598e25d1ea4SMatthew Auld *
599e25d1ea4SMatthew Auld * By default most objects will start out as visible to the
600e25d1ea4SMatthew Auld * shrinker(if I915_GEM_OBJECT_IS_SHRINKABLE) as soon as the
601e25d1ea4SMatthew Auld * backing pages are attached to the object, like in
602e25d1ea4SMatthew Auld * __i915_gem_object_set_pages(). They will then be removed the
603e25d1ea4SMatthew Auld * shrinker list once the pages are released.
604e25d1ea4SMatthew Auld *
605e25d1ea4SMatthew Auld * The @shrink_pin is incremented by calling
606e25d1ea4SMatthew Auld * i915_gem_object_make_unshrinkable(), which will also remove
607e25d1ea4SMatthew Auld * the object from the shrinker list, if the pin count was zero.
608e25d1ea4SMatthew Auld *
609e25d1ea4SMatthew Auld * Callers will then typically call
610e25d1ea4SMatthew Auld * i915_gem_object_make_shrinkable() or
611e25d1ea4SMatthew Auld * i915_gem_object_make_purgeable() to decrement the pin count,
612e25d1ea4SMatthew Auld * and make the pages visible again.
613e25d1ea4SMatthew Auld */
61499013b10SChris Wilson atomic_t shrink_pin;
6155e5d2e20SChris Wilson
616232a6ebaSMatthew Auld /**
617ebd4a8ecSMatthew Auld * @ttm_shrinkable: True when the object is using shmem pages
618ebd4a8ecSMatthew Auld * underneath. Protected by the object lock.
619ebd4a8ecSMatthew Auld */
620ebd4a8ecSMatthew Auld bool ttm_shrinkable;
621ebd4a8ecSMatthew Auld
622ebd4a8ecSMatthew Auld /**
623bfe53be2SMatthew Auld * @unknown_state: Indicate that the object is effectively
624bfe53be2SMatthew Auld * borked. This is write-once and set if we somehow encounter a
625bfe53be2SMatthew Auld * fatal error when moving/clearing the pages, and we are not
626bfe53be2SMatthew Auld * able to fallback to memcpy/memset, like on small-BAR systems.
627bfe53be2SMatthew Auld * The GPU should also be wedged (or in the process) at this
628bfe53be2SMatthew Auld * point.
629bfe53be2SMatthew Auld *
630bfe53be2SMatthew Auld * Only valid to read this after acquiring the dma-resv lock and
631bfe53be2SMatthew Auld * waiting for all DMA_RESV_USAGE_KERNEL fences to be signalled,
632bfe53be2SMatthew Auld * or if we otherwise know that the moving fence has signalled,
633bfe53be2SMatthew Auld * and we are certain the pages underneath are valid for
634bfe53be2SMatthew Auld * immediate access (under normal operation), like just prior to
635bfe53be2SMatthew Auld * binding the object or when setting up the CPU fault handler.
636bfe53be2SMatthew Auld * See i915_gem_object_has_unknown_state();
637bfe53be2SMatthew Auld */
638bfe53be2SMatthew Auld bool unknown_state;
639bfe53be2SMatthew Auld
640bfe53be2SMatthew Auld /**
6412459e56fSMatthew Auld * Priority list of potential placements for this object.
6422459e56fSMatthew Auld */
6432459e56fSMatthew Auld struct intel_memory_region **placements;
6442459e56fSMatthew Auld int n_placements;
6452459e56fSMatthew Auld
6462459e56fSMatthew Auld /**
647232a6ebaSMatthew Auld * Memory region for this object.
648232a6ebaSMatthew Auld */
649232a6ebaSMatthew Auld struct intel_memory_region *region;
650d1487389SThomas Hellström
651232a6ebaSMatthew Auld /**
652687c7d0fSMatthew Auld * Memory manager resource allocated for this object. Only
653687c7d0fSMatthew Auld * needed for the mock region.
654232a6ebaSMatthew Auld */
655687c7d0fSMatthew Auld struct ttm_resource *res;
656d1487389SThomas Hellström
6577c98501aSMatthew Auld /**
6587c98501aSMatthew Auld * Element within memory_region->objects or region->purgeable
6597c98501aSMatthew Auld * if the object is marked as DONTNEED. Access is protected by
6607c98501aSMatthew Auld * region->obj_lock.
6617c98501aSMatthew Auld */
6627c98501aSMatthew Auld struct list_head region_link;
663232a6ebaSMatthew Auld
664cad7109aSThomas Hellström struct i915_refct_sgt *rsgt;
6655e5d2e20SChris Wilson struct sg_table *pages;
6665e5d2e20SChris Wilson void *mapping;
6675e5d2e20SChris Wilson
66839a2bd34SThomas Hellström struct i915_page_sizes page_sizes;
6695e5d2e20SChris Wilson
6705e5d2e20SChris Wilson I915_SELFTEST_DECLARE(unsigned int page_mask);
6715e5d2e20SChris Wilson
672934941edSTvrtko Ursulin struct i915_gem_object_page_iter get_page;
673934941edSTvrtko Ursulin struct i915_gem_object_page_iter get_dma_page;
6745e5d2e20SChris Wilson
6755e5d2e20SChris Wilson /**
676e25d1ea4SMatthew Auld * Element within i915->mm.shrink_list or i915->mm.purge_list,
6775e5d2e20SChris Wilson * locked by i915->mm.obj_lock.
6785e5d2e20SChris Wilson */
6795e5d2e20SChris Wilson struct list_head link;
6805e5d2e20SChris Wilson
6815e5d2e20SChris Wilson /**
6825e5d2e20SChris Wilson * Advice: are the backing pages purgeable?
6835e5d2e20SChris Wilson */
6845e5d2e20SChris Wilson unsigned int madv:2;
6855e5d2e20SChris Wilson
6865e5d2e20SChris Wilson /**
6875e5d2e20SChris Wilson * This is set if the object has been written to since the
6885e5d2e20SChris Wilson * pages were last acquired.
6895e5d2e20SChris Wilson */
6905e5d2e20SChris Wilson bool dirty:1;
6915d36acb7SChris Wilson
692d6c531abSChris Wilson u32 tlb[I915_MAX_GT];
6935e5d2e20SChris Wilson } mm;
6945e5d2e20SChris Wilson
695213d5092SThomas Hellström struct {
696cad7109aSThomas Hellström struct i915_refct_sgt *cached_io_rsgt;
697cf3e3e86SMaarten Lankhorst struct i915_gem_object_page_iter get_io_page;
698c56ce956SThomas Hellström struct drm_i915_gem_object *backup;
699213d5092SThomas Hellström bool created:1;
700213d5092SThomas Hellström } ttm;
701213d5092SThomas Hellström
702d3ac8d42SDaniele Ceraolo Spurio /*
703d3ac8d42SDaniele Ceraolo Spurio * Record which PXP key instance this object was created against (if
704d3ac8d42SDaniele Ceraolo Spurio * any), so we can use it to determine if the encryption is valid by
705d3ac8d42SDaniele Ceraolo Spurio * comparing against the current key instance.
706d3ac8d42SDaniele Ceraolo Spurio */
707d3ac8d42SDaniele Ceraolo Spurio u32 pxp_key_instance;
708d3ac8d42SDaniele Ceraolo Spurio
7095e5d2e20SChris Wilson /** Record of address bit 17 of each page at last unbind. */
7105e5d2e20SChris Wilson unsigned long *bit_17;
7115e5d2e20SChris Wilson
7125e5d2e20SChris Wilson union {
71320ee27bdSMaarten Lankhorst #ifdef CONFIG_MMU_NOTIFIER
7145e5d2e20SChris Wilson struct i915_gem_userptr {
7155e5d2e20SChris Wilson uintptr_t ptr;
716ed29c269SMaarten Lankhorst unsigned long notifier_seq;
7175e5d2e20SChris Wilson
718ed29c269SMaarten Lankhorst struct mmu_interval_notifier notifier;
719ed29c269SMaarten Lankhorst struct page **pvec;
720ed29c269SMaarten Lankhorst int page_ref;
7215e5d2e20SChris Wilson } userptr;
72220ee27bdSMaarten Lankhorst #endif
7235e5d2e20SChris Wilson
72441a9c75dSChris Wilson struct drm_mm_node *stolen;
72541a9c75dSChris Wilson
726ecbf2060SMatthew Auld resource_size_t bo_offset;
727ecbf2060SMatthew Auld
7285e5d2e20SChris Wilson unsigned long scratch;
72989351925SChris Wilson u64 encode;
7305e5d2e20SChris Wilson
7315e5d2e20SChris Wilson void *gvt_info;
7325e5d2e20SChris Wilson };
7335e5d2e20SChris Wilson };
7345e5d2e20SChris Wilson
73572e31c0aSJouni Högander #define intel_bo_to_drm_bo(bo) (&(bo)->base)
73672e31c0aSJouni Högander #define intel_bo_to_i915(bo) to_i915(intel_bo_to_drm_bo(bo)->dev)
73772e31c0aSJouni Högander
7385e5d2e20SChris Wilson static inline struct drm_i915_gem_object *
to_intel_bo(struct drm_gem_object * gem)7395e5d2e20SChris Wilson to_intel_bo(struct drm_gem_object *gem)
7405e5d2e20SChris Wilson {
7415e5d2e20SChris Wilson /* Assert that to_intel_bo(NULL) == NULL */
7425e5d2e20SChris Wilson BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
7435e5d2e20SChris Wilson
7445e5d2e20SChris Wilson return container_of(gem, struct drm_i915_gem_object, base);
7455e5d2e20SChris Wilson }
7465e5d2e20SChris Wilson
7475e5d2e20SChris Wilson #endif
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