1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_GT_TYPES__ 7 #define __INTEL_GT_TYPES__ 8 9 #include <linux/ktime.h> 10 #include <linux/list.h> 11 #include <linux/llist.h> 12 #include <linux/mutex.h> 13 #include <linux/notifier.h> 14 #include <linux/seqlock.h> 15 #include <linux/spinlock.h> 16 #include <linux/types.h> 17 #include <linux/workqueue.h> 18 19 #include "uc/intel_uc.h" 20 #include "intel_gsc.h" 21 22 #include "i915_vma.h" 23 #include "intel_engine_types.h" 24 #include "intel_gt_buffer_pool_types.h" 25 #include "intel_hwconfig.h" 26 #include "intel_llc_types.h" 27 #include "intel_reset_types.h" 28 #include "intel_rc6_types.h" 29 #include "intel_rps_types.h" 30 #include "intel_migrate_types.h" 31 #include "intel_wakeref.h" 32 #include "pxp/intel_pxp_types.h" 33 34 struct drm_i915_private; 35 struct i915_ggtt; 36 struct intel_engine_cs; 37 struct intel_uncore; 38 39 struct intel_mmio_range { 40 u32 start; 41 u32 end; 42 }; 43 44 /* 45 * The hardware has multiple kinds of multicast register ranges that need 46 * special register steering (and future platforms are expected to add 47 * additional types). 48 * 49 * During driver startup, we initialize the steering control register to 50 * direct reads to a slice/subslice that are valid for the 'subslice' class 51 * of multicast registers. If another type of steering does not have any 52 * overlap in valid steering targets with 'subslice' style registers, we will 53 * need to explicitly re-steer reads of registers of the other type. 54 * 55 * Only the replication types that may need additional non-default steering 56 * are listed here. 57 */ 58 enum intel_steering_type { 59 L3BANK, 60 MSLICE, 61 LNCF, 62 63 /* 64 * On some platforms there are multiple types of MCR registers that 65 * will always return a non-terminated value at instance (0, 0). We'll 66 * lump those all into a single category to keep things simple. 67 */ 68 INSTANCE0, 69 70 NUM_STEERING_TYPES 71 }; 72 73 enum intel_submission_method { 74 INTEL_SUBMISSION_RING, 75 INTEL_SUBMISSION_ELSP, 76 INTEL_SUBMISSION_GUC, 77 }; 78 79 struct gt_defaults { 80 u32 min_freq; 81 u32 max_freq; 82 }; 83 84 enum intel_gt_type { 85 GT_PRIMARY, 86 GT_TILE, 87 GT_MEDIA, 88 }; 89 90 struct intel_gt { 91 struct drm_i915_private *i915; 92 const char *name; 93 enum intel_gt_type type; 94 95 struct intel_uncore *uncore; 96 struct i915_ggtt *ggtt; 97 98 struct intel_uc uc; 99 struct intel_gsc gsc; 100 101 struct { 102 /* Serialize global tlb invalidations */ 103 struct mutex invalidate_lock; 104 105 /* 106 * Batch TLB invalidations 107 * 108 * After unbinding the PTE, we need to ensure the TLB 109 * are invalidated prior to releasing the physical pages. 110 * But we only need one such invalidation for all unbinds, 111 * so we track how many TLB invalidations have been 112 * performed since unbind the PTE and only emit an extra 113 * invalidate if no full barrier has been passed. 114 */ 115 seqcount_mutex_t seqno; 116 } tlb; 117 118 struct i915_wa_list wa_list; 119 120 struct intel_gt_timelines { 121 spinlock_t lock; /* protects active_list */ 122 struct list_head active_list; 123 } timelines; 124 125 struct intel_gt_requests { 126 /** 127 * We leave the user IRQ off as much as possible, 128 * but this means that requests will finish and never 129 * be retired once the system goes idle. Set a timer to 130 * fire periodically while the ring is running. When it 131 * fires, go retire requests. 132 */ 133 struct delayed_work retire_work; 134 } requests; 135 136 struct { 137 struct llist_head list; 138 struct work_struct work; 139 } watchdog; 140 141 struct intel_wakeref wakeref; 142 atomic_t user_wakeref; 143 144 /** 145 * Protects access to lmem usefault list. 146 * It is required, if we are outside of the runtime suspend path, 147 * access to @lmem_userfault_list requires always first grabbing the 148 * runtime pm, to ensure we can't race against runtime suspend. 149 * Once we have that we also need to grab @lmem_userfault_lock, 150 * at which point we have exclusive access. 151 * The runtime suspend path is special since it doesn't really hold any locks, 152 * but instead has exclusive access by virtue of all other accesses requiring 153 * holding the runtime pm wakeref. 154 */ 155 struct mutex lmem_userfault_lock; 156 struct list_head lmem_userfault_list; 157 158 struct list_head closed_vma; 159 spinlock_t closed_lock; /* guards the list of closed_vma */ 160 161 ktime_t last_init_time; 162 struct intel_reset reset; 163 164 /** 165 * Is the GPU currently considered idle, or busy executing 166 * userspace requests? Whilst idle, we allow runtime power 167 * management to power down the hardware and display clocks. 168 * In order to reduce the effect on performance, there 169 * is a slight delay before we do so. 170 */ 171 intel_wakeref_t awake; 172 173 /* Manual runtime pm autosuspend delay for user GGTT/lmem mmaps */ 174 struct intel_wakeref_auto userfault_wakeref; 175 176 u32 clock_frequency; 177 u32 clock_period_ns; 178 179 struct intel_llc llc; 180 struct intel_rc6 rc6; 181 struct intel_rps rps; 182 183 spinlock_t *irq_lock; 184 u32 gt_imr; 185 u32 pm_ier; 186 u32 pm_imr; 187 188 u32 pm_guc_events; 189 190 struct { 191 bool active; 192 193 /** 194 * @lock: Lock protecting the below fields. 195 */ 196 seqcount_mutex_t lock; 197 198 /** 199 * @total: Total time this engine was busy. 200 * 201 * Accumulated time not counting the most recent block in cases 202 * where engine is currently busy (active > 0). 203 */ 204 ktime_t total; 205 206 /** 207 * @start: Timestamp of the last idle to active transition. 208 * 209 * Idle is defined as active == 0, active is active > 0. 210 */ 211 ktime_t start; 212 } stats; 213 214 struct intel_engine_cs *engine[I915_NUM_ENGINES]; 215 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1] 216 [MAX_ENGINE_INSTANCE + 1]; 217 enum intel_submission_method submission_method; 218 219 /* 220 * Default address space (either GGTT or ppGTT depending on arch). 221 * 222 * Reserved for exclusive use by the kernel. 223 */ 224 struct i915_address_space *vm; 225 226 /* 227 * A pool of objects to use as shadow copies of client batch buffers 228 * when the command parser is enabled. Prevents the client from 229 * modifying the batch contents after software parsing. 230 * 231 * Buffers older than 1s are periodically reaped from the pool, 232 * or may be reclaimed by the shrinker before then. 233 */ 234 struct intel_gt_buffer_pool buffer_pool; 235 236 struct i915_vma *scratch; 237 238 struct intel_migrate migrate; 239 240 const struct intel_mmio_range *steering_table[NUM_STEERING_TYPES]; 241 242 struct { 243 u8 groupid; 244 u8 instanceid; 245 } default_steering; 246 247 /* 248 * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT. 249 */ 250 phys_addr_t phys_addr; 251 252 struct intel_gt_info { 253 unsigned int id; 254 255 intel_engine_mask_t engine_mask; 256 257 u32 l3bank_mask; 258 259 u8 num_engines; 260 261 /* General presence of SFC units */ 262 u8 sfc_mask; 263 264 /* Media engine access to SFC per instance */ 265 u8 vdbox_sfc_access; 266 267 /* Slice/subslice/EU info */ 268 struct sseu_dev_info sseu; 269 270 unsigned long mslice_mask; 271 272 /** @hwconfig: hardware configuration data */ 273 struct intel_hwconfig hwconfig; 274 } info; 275 276 struct { 277 u8 uc_index; 278 u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */ 279 } mocs; 280 281 struct intel_pxp pxp; 282 283 /* gt/gtN sysfs */ 284 struct kobject sysfs_gt; 285 286 /* sysfs defaults per gt */ 287 struct gt_defaults defaults; 288 struct kobject *sysfs_defaults; 289 }; 290 291 struct intel_gt_definition { 292 enum intel_gt_type type; 293 char *name; 294 u32 mapping_base; 295 u32 gsi_offset; 296 intel_engine_mask_t engine_mask; 297 }; 298 299 enum intel_gt_scratch_field { 300 /* 8 bytes */ 301 INTEL_GT_SCRATCH_FIELD_DEFAULT = 0, 302 303 /* 8 bytes */ 304 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128, 305 306 /* 8 bytes */ 307 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256, 308 309 /* 6 * 8 bytes */ 310 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048, 311 312 /* 4 bytes */ 313 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096, 314 }; 315 316 #endif /* __INTEL_GT_TYPES_H__ */ 317