1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021-2022 Intel Corporation 4 */ 5 6 #include <linux/types.h> 7 8 #include <drm/drm_print.h> 9 10 #include "gt/intel_engine_regs.h" 11 #include "gt/intel_gt.h" 12 #include "gt/intel_gt_mcr.h" 13 #include "gt/intel_gt_regs.h" 14 #include "gt/intel_lrc.h" 15 #include "guc_capture_fwif.h" 16 #include "intel_guc_capture.h" 17 #include "intel_guc_fwif.h" 18 #include "i915_drv.h" 19 #include "i915_gpu_error.h" 20 #include "i915_irq.h" 21 #include "i915_memcpy.h" 22 #include "i915_reg.h" 23 24 /* 25 * Define all device tables of GuC error capture register lists 26 * NOTE: For engine-registers, GuC only needs the register offsets 27 * from the engine-mmio-base 28 */ 29 #define COMMON_BASE_GLOBAL \ 30 { FORCEWAKE_MT, 0, 0, "FORCEWAKE" } 31 32 #define COMMON_GEN9BASE_GLOBAL \ 33 { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ 34 { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \ 35 { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \ 36 { DONE_REG, 0, 0, "DONE_REG" }, \ 37 { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" } 38 39 #define COMMON_GEN12BASE_GLOBAL \ 40 { GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \ 41 { GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \ 42 { GEN12_AUX_ERR_DBG, 0, 0, "AUX_ERR_DBG" }, \ 43 { GEN12_GAM_DONE, 0, 0, "GAM_DONE" }, \ 44 { GEN12_RING_FAULT_REG, 0, 0, "FAULT_REG" } 45 46 #define COMMON_BASE_ENGINE_INSTANCE \ 47 { RING_PSMI_CTL(0), 0, 0, "RC PSMI" }, \ 48 { RING_ESR(0), 0, 0, "ESR" }, \ 49 { RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LDW" }, \ 50 { RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UDW" }, \ 51 { RING_IPEIR(0), 0, 0, "IPEIR" }, \ 52 { RING_IPEHR(0), 0, 0, "IPEHR" }, \ 53 { RING_INSTPS(0), 0, 0, "INSTPS" }, \ 54 { RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32" }, \ 55 { RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32" }, \ 56 { RING_BBSTATE(0), 0, 0, "BB_STATE" }, \ 57 { CCID(0), 0, 0, "CCID" }, \ 58 { RING_ACTHD(0), 0, 0, "ACTHD_LDW" }, \ 59 { RING_ACTHD_UDW(0), 0, 0, "ACTHD_UDW" }, \ 60 { RING_INSTPM(0), 0, 0, "INSTPM" }, \ 61 { RING_INSTDONE(0), 0, 0, "INSTDONE" }, \ 62 { RING_NOPID(0), 0, 0, "RING_NOPID" }, \ 63 { RING_START(0), 0, 0, "START" }, \ 64 { RING_HEAD(0), 0, 0, "HEAD" }, \ 65 { RING_TAIL(0), 0, 0, "TAIL" }, \ 66 { RING_CTL(0), 0, 0, "CTL" }, \ 67 { RING_MI_MODE(0), 0, 0, "MODE" }, \ 68 { RING_CONTEXT_CONTROL(0), 0, 0, "RING_CONTEXT_CONTROL" }, \ 69 { RING_HWS_PGA(0), 0, 0, "HWS" }, \ 70 { RING_MODE_GEN7(0), 0, 0, "GFX_MODE" }, \ 71 { GEN8_RING_PDP_LDW(0, 0), 0, 0, "PDP0_LDW" }, \ 72 { GEN8_RING_PDP_UDW(0, 0), 0, 0, "PDP0_UDW" }, \ 73 { GEN8_RING_PDP_LDW(0, 1), 0, 0, "PDP1_LDW" }, \ 74 { GEN8_RING_PDP_UDW(0, 1), 0, 0, "PDP1_UDW" }, \ 75 { GEN8_RING_PDP_LDW(0, 2), 0, 0, "PDP2_LDW" }, \ 76 { GEN8_RING_PDP_UDW(0, 2), 0, 0, "PDP2_UDW" }, \ 77 { GEN8_RING_PDP_LDW(0, 3), 0, 0, "PDP3_LDW" }, \ 78 { GEN8_RING_PDP_UDW(0, 3), 0, 0, "PDP3_UDW" } 79 80 #define COMMON_BASE_HAS_EU \ 81 { EIR, 0, 0, "EIR" } 82 83 #define COMMON_BASE_RENDER \ 84 { GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE" } 85 86 #define COMMON_GEN12BASE_RENDER \ 87 { GEN12_SC_INSTDONE_EXTRA, 0, 0, "GEN12_SC_INSTDONE_EXTRA" }, \ 88 { GEN12_SC_INSTDONE_EXTRA2, 0, 0, "GEN12_SC_INSTDONE_EXTRA2" } 89 90 #define COMMON_GEN12BASE_VEC \ 91 { GEN12_SFC_DONE(0), 0, 0, "SFC_DONE[0]" }, \ 92 { GEN12_SFC_DONE(1), 0, 0, "SFC_DONE[1]" }, \ 93 { GEN12_SFC_DONE(2), 0, 0, "SFC_DONE[2]" }, \ 94 { GEN12_SFC_DONE(3), 0, 0, "SFC_DONE[3]" } 95 96 /* XE_LPD - Global */ 97 static const struct __guc_mmio_reg_descr xe_lpd_global_regs[] = { 98 COMMON_BASE_GLOBAL, 99 COMMON_GEN9BASE_GLOBAL, 100 COMMON_GEN12BASE_GLOBAL, 101 }; 102 103 /* XE_LPD - Render / Compute Per-Class */ 104 static const struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = { 105 COMMON_BASE_HAS_EU, 106 COMMON_BASE_RENDER, 107 COMMON_GEN12BASE_RENDER, 108 }; 109 110 /* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */ 111 static const struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = { 112 COMMON_BASE_ENGINE_INSTANCE, 113 }; 114 115 /* GEN9/XE_LPD - Media Decode/Encode Per-Engine-Instance */ 116 static const struct __guc_mmio_reg_descr xe_lpd_vd_inst_regs[] = { 117 COMMON_BASE_ENGINE_INSTANCE, 118 }; 119 120 /* XE_LPD - Video Enhancement Per-Class */ 121 static const struct __guc_mmio_reg_descr xe_lpd_vec_class_regs[] = { 122 COMMON_GEN12BASE_VEC, 123 }; 124 125 /* GEN9/XE_LPD - Video Enhancement Per-Engine-Instance */ 126 static const struct __guc_mmio_reg_descr xe_lpd_vec_inst_regs[] = { 127 COMMON_BASE_ENGINE_INSTANCE, 128 }; 129 130 /* GEN9/XE_LPD - Blitter Per-Engine-Instance */ 131 static const struct __guc_mmio_reg_descr xe_lpd_blt_inst_regs[] = { 132 COMMON_BASE_ENGINE_INSTANCE, 133 }; 134 135 /* GEN9 - Global */ 136 static const struct __guc_mmio_reg_descr default_global_regs[] = { 137 COMMON_BASE_GLOBAL, 138 COMMON_GEN9BASE_GLOBAL, 139 }; 140 141 static const struct __guc_mmio_reg_descr default_rc_class_regs[] = { 142 COMMON_BASE_HAS_EU, 143 COMMON_BASE_RENDER, 144 }; 145 146 /* 147 * Empty lists: 148 * GEN9/XE_LPD - Blitter Per-Class 149 * GEN9/XE_LPD - Media Decode/Encode Per-Class 150 * GEN9 - VEC Class 151 */ 152 static const struct __guc_mmio_reg_descr empty_regs_list[] = { 153 }; 154 155 #define TO_GCAP_DEF_OWNER(x) (GUC_CAPTURE_LIST_INDEX_##x) 156 #define TO_GCAP_DEF_TYPE(x) (GUC_CAPTURE_LIST_TYPE_##x) 157 #define MAKE_REGLIST(regslist, regsowner, regstype, class) \ 158 { \ 159 regslist, \ 160 ARRAY_SIZE(regslist), \ 161 TO_GCAP_DEF_OWNER(regsowner), \ 162 TO_GCAP_DEF_TYPE(regstype), \ 163 class, \ 164 NULL, \ 165 } 166 167 /* List of lists */ 168 static struct __guc_mmio_reg_descr_group default_lists[] = { 169 MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0), 170 MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS), 171 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS), 172 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS), 173 MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS), 174 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS), 175 MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS), 176 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS), 177 MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS), 178 {} 179 }; 180 181 static const struct __guc_mmio_reg_descr_group xe_lpd_lists[] = { 182 MAKE_REGLIST(xe_lpd_global_regs, PF, GLOBAL, 0), 183 MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS), 184 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS), 185 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS), 186 MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS), 187 MAKE_REGLIST(xe_lpd_vec_class_regs, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS), 188 MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS), 189 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS), 190 MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS), 191 {} 192 }; 193 194 static const struct __guc_mmio_reg_descr_group * 195 guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, 196 u32 owner, u32 type, u32 id) 197 { 198 int i; 199 200 if (!reglists) 201 return NULL; 202 203 for (i = 0; reglists[i].list; ++i) { 204 if (reglists[i].owner == owner && reglists[i].type == type && 205 (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL)) 206 return ®lists[i]; 207 } 208 209 return NULL; 210 } 211 212 static struct __guc_mmio_reg_descr_group * 213 guc_capture_get_one_ext_list(struct __guc_mmio_reg_descr_group *reglists, 214 u32 owner, u32 type, u32 id) 215 { 216 int i; 217 218 if (!reglists) 219 return NULL; 220 221 for (i = 0; reglists[i].extlist; ++i) { 222 if (reglists[i].owner == owner && reglists[i].type == type && 223 (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL)) 224 return ®lists[i]; 225 } 226 227 return NULL; 228 } 229 230 static void guc_capture_free_extlists(struct __guc_mmio_reg_descr_group *reglists) 231 { 232 int i = 0; 233 234 if (!reglists) 235 return; 236 237 while (reglists[i].extlist) 238 kfree(reglists[i++].extlist); 239 } 240 241 struct __ext_steer_reg { 242 const char *name; 243 i915_reg_t reg; 244 }; 245 246 static const struct __ext_steer_reg xe_extregs[] = { 247 {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE}, 248 {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE} 249 }; 250 251 static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext, 252 const struct __ext_steer_reg *extlist, 253 int slice_id, int subslice_id) 254 { 255 ext->reg = extlist->reg; 256 ext->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id); 257 ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id); 258 ext->regname = extlist->name; 259 } 260 261 static int 262 __alloc_ext_regs(struct __guc_mmio_reg_descr_group *newlist, 263 const struct __guc_mmio_reg_descr_group *rootlist, int num_regs) 264 { 265 struct __guc_mmio_reg_descr *list; 266 267 list = kcalloc(num_regs, sizeof(struct __guc_mmio_reg_descr), GFP_KERNEL); 268 if (!list) 269 return -ENOMEM; 270 271 newlist->extlist = list; 272 newlist->num_regs = num_regs; 273 newlist->owner = rootlist->owner; 274 newlist->engine = rootlist->engine; 275 newlist->type = rootlist->type; 276 277 return 0; 278 } 279 280 static void 281 guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc *guc, 282 const struct __guc_mmio_reg_descr_group *lists) 283 { 284 struct intel_gt *gt = guc_to_gt(guc); 285 int slice, subslice, iter, i, num_steer_regs, num_tot_regs = 0; 286 const struct __guc_mmio_reg_descr_group *list; 287 struct __guc_mmio_reg_descr_group *extlists; 288 struct __guc_mmio_reg_descr *extarray; 289 struct sseu_dev_info *sseu; 290 291 /* In XE_LPD we only have steered registers for the render-class */ 292 list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF, 293 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS); 294 /* skip if extlists was previously allocated */ 295 if (!list || guc->capture->extlists) 296 return; 297 298 num_steer_regs = ARRAY_SIZE(xe_extregs); 299 300 sseu = >->info.sseu; 301 for_each_ss_steering(iter, gt, slice, subslice) 302 num_tot_regs += num_steer_regs; 303 304 if (!num_tot_regs) 305 return; 306 307 /* allocate an extra for an end marker */ 308 extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL); 309 if (!extlists) 310 return; 311 312 if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) { 313 kfree(extlists); 314 return; 315 } 316 317 extarray = extlists[0].extlist; 318 for_each_ss_steering(iter, gt, slice, subslice) { 319 for (i = 0; i < num_steer_regs; ++i) { 320 __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); 321 ++extarray; 322 } 323 } 324 325 guc->capture->extlists = extlists; 326 } 327 328 static const struct __ext_steer_reg xehpg_extregs[] = { 329 {"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG} 330 }; 331 332 static bool __has_xehpg_extregs(u32 ipver) 333 { 334 return (ipver >= IP_VER(12, 55)); 335 } 336 337 static void 338 guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc, 339 const struct __guc_mmio_reg_descr_group *lists, 340 u32 ipver) 341 { 342 struct intel_gt *gt = guc_to_gt(guc); 343 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 344 struct sseu_dev_info *sseu; 345 int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0; 346 const struct __guc_mmio_reg_descr_group *list; 347 struct __guc_mmio_reg_descr_group *extlists; 348 struct __guc_mmio_reg_descr *extarray; 349 350 /* In XE_LP / HPG we only have render-class steering registers during error-capture */ 351 list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF, 352 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS); 353 /* skip if extlists was previously allocated */ 354 if (!list || guc->capture->extlists) 355 return; 356 357 num_steer_regs = ARRAY_SIZE(xe_extregs); 358 if (__has_xehpg_extregs(ipver)) 359 num_steer_regs += ARRAY_SIZE(xehpg_extregs); 360 361 sseu = >->info.sseu; 362 for_each_ss_steering(iter, gt, slice, subslice) 363 num_tot_regs += num_steer_regs; 364 365 if (!num_tot_regs) 366 return; 367 368 /* allocate an extra for an end marker */ 369 extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL); 370 if (!extlists) 371 return; 372 373 if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) { 374 kfree(extlists); 375 return; 376 } 377 378 extarray = extlists[0].extlist; 379 for_each_ss_steering(iter, gt, slice, subslice) { 380 for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) { 381 __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); 382 ++extarray; 383 } 384 if (__has_xehpg_extregs(ipver)) { 385 for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) { 386 __fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice); 387 ++extarray; 388 } 389 } 390 } 391 392 drm_dbg(&i915->drm, "GuC-capture found %d-ext-regs.\n", num_tot_regs); 393 guc->capture->extlists = extlists; 394 } 395 396 static const struct __guc_mmio_reg_descr_group * 397 guc_capture_get_device_reglist(struct intel_guc *guc) 398 { 399 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 400 401 if (GRAPHICS_VER(i915) > 11) { 402 /* 403 * For certain engine classes, there are slice and subslice 404 * level registers requiring steering. We allocate and populate 405 * these at init time based on hw config add it as an extension 406 * list at the end of the pre-populated render list. 407 */ 408 if (IS_DG2(i915)) 409 guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 55)); 410 else if (IS_XEHPSDV(i915)) 411 guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 50)); 412 else 413 guc_capture_alloc_steered_lists_xe_lpd(guc, xe_lpd_lists); 414 415 return xe_lpd_lists; 416 } 417 418 /* if GuC submission is enabled on a non-POR platform, just use a common baseline */ 419 return default_lists; 420 } 421 422 static int 423 guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 424 struct guc_mmio_reg *ptr, u16 num_entries) 425 { 426 u32 i = 0, j = 0; 427 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 428 const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; 429 struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists; 430 const struct __guc_mmio_reg_descr_group *match; 431 struct __guc_mmio_reg_descr_group *matchext; 432 433 if (!reglists) 434 return -ENODEV; 435 436 match = guc_capture_get_one_list(reglists, owner, type, classid); 437 if (!match) 438 return -ENODATA; 439 440 for (i = 0; i < num_entries && i < match->num_regs; ++i) { 441 ptr[i].offset = match->list[i].reg.reg; 442 ptr[i].value = 0xDEADF00D; 443 ptr[i].flags = match->list[i].flags; 444 ptr[i].mask = match->list[i].mask; 445 } 446 447 matchext = guc_capture_get_one_ext_list(extlists, owner, type, classid); 448 if (matchext) { 449 for (i = match->num_regs, j = 0; i < num_entries && 450 i < (match->num_regs + matchext->num_regs) && 451 j < matchext->num_regs; ++i, ++j) { 452 ptr[i].offset = matchext->extlist[j].reg.reg; 453 ptr[i].value = 0xDEADF00D; 454 ptr[i].flags = matchext->extlist[j].flags; 455 ptr[i].mask = matchext->extlist[j].mask; 456 } 457 } 458 if (i < num_entries) 459 drm_dbg(&i915->drm, "GuC-capture: Init reglist short %d out %d.\n", 460 (int)i, (int)num_entries); 461 462 return 0; 463 } 464 465 static int 466 guc_cap_list_num_regs(struct intel_guc_state_capture *gc, u32 owner, u32 type, u32 classid) 467 { 468 const struct __guc_mmio_reg_descr_group *match; 469 struct __guc_mmio_reg_descr_group *matchext; 470 int num_regs; 471 472 match = guc_capture_get_one_list(gc->reglists, owner, type, classid); 473 if (!match) 474 return 0; 475 476 num_regs = match->num_regs; 477 478 matchext = guc_capture_get_one_ext_list(gc->extlists, owner, type, classid); 479 if (matchext) 480 num_regs += matchext->num_regs; 481 482 return num_regs; 483 } 484 485 int 486 intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 487 size_t *size) 488 { 489 struct intel_guc_state_capture *gc = guc->capture; 490 struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; 491 int num_regs; 492 493 if (!gc->reglists) 494 return -ENODEV; 495 496 if (cache->is_valid) { 497 *size = cache->size; 498 return cache->status; 499 } 500 501 num_regs = guc_cap_list_num_regs(gc, owner, type, classid); 502 if (!num_regs) 503 return -ENODATA; 504 505 *size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) + 506 (num_regs * sizeof(struct guc_mmio_reg))); 507 508 return 0; 509 } 510 511 static void guc_capture_create_prealloc_nodes(struct intel_guc *guc); 512 513 int 514 intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 515 void **outptr) 516 { 517 struct intel_guc_state_capture *gc = guc->capture; 518 struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; 519 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 520 struct guc_debug_capture_list *listnode; 521 int ret, num_regs; 522 u8 *caplist, *tmp; 523 size_t size = 0; 524 525 if (!gc->reglists) 526 return -ENODEV; 527 528 if (cache->is_valid) { 529 *outptr = cache->ptr; 530 return cache->status; 531 } 532 533 /* 534 * ADS population of input registers is a good 535 * time to pre-allocate cachelist output nodes 536 */ 537 guc_capture_create_prealloc_nodes(guc); 538 539 ret = intel_guc_capture_getlistsize(guc, owner, type, classid, &size); 540 if (ret) { 541 cache->is_valid = true; 542 cache->ptr = NULL; 543 cache->size = 0; 544 cache->status = ret; 545 return ret; 546 } 547 548 caplist = kzalloc(size, GFP_KERNEL); 549 if (!caplist) { 550 drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached caplist"); 551 return -ENOMEM; 552 } 553 554 /* populate capture list header */ 555 tmp = caplist; 556 num_regs = guc_cap_list_num_regs(guc->capture, owner, type, classid); 557 listnode = (struct guc_debug_capture_list *)tmp; 558 listnode->header.info = FIELD_PREP(GUC_CAPTURELISTHDR_NUMDESCR, (u32)num_regs); 559 560 /* populate list of register descriptor */ 561 tmp += sizeof(struct guc_debug_capture_list); 562 guc_capture_list_init(guc, owner, type, classid, (struct guc_mmio_reg *)tmp, num_regs); 563 564 /* cache this list */ 565 cache->is_valid = true; 566 cache->ptr = caplist; 567 cache->size = size; 568 cache->status = 0; 569 570 *outptr = caplist; 571 572 return 0; 573 } 574 575 int 576 intel_guc_capture_getnullheader(struct intel_guc *guc, 577 void **outptr, size_t *size) 578 { 579 struct intel_guc_state_capture *gc = guc->capture; 580 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 581 int tmp = sizeof(u32) * 4; 582 void *null_header; 583 584 if (gc->ads_null_cache) { 585 *outptr = gc->ads_null_cache; 586 *size = tmp; 587 return 0; 588 } 589 590 null_header = kzalloc(tmp, GFP_KERNEL); 591 if (!null_header) { 592 drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached nulllist"); 593 return -ENOMEM; 594 } 595 596 gc->ads_null_cache = null_header; 597 *outptr = null_header; 598 *size = tmp; 599 600 return 0; 601 } 602 603 static int 604 guc_capture_output_min_size_est(struct intel_guc *guc) 605 { 606 struct intel_gt *gt = guc_to_gt(guc); 607 struct intel_engine_cs *engine; 608 enum intel_engine_id id; 609 int worst_min_size = 0, num_regs = 0; 610 size_t tmp = 0; 611 612 if (!guc->capture) 613 return -ENODEV; 614 615 /* 616 * If every single engine-instance suffered a failure in quick succession but 617 * were all unrelated, then a burst of multiple error-capture events would dump 618 * registers for every one engine instance, one at a time. In this case, GuC 619 * would even dump the global-registers repeatedly. 620 * 621 * For each engine instance, there would be 1 x guc_state_capture_group_t output 622 * followed by 3 x guc_state_capture_t lists. The latter is how the register 623 * dumps are split across different register types (where the '3' are global vs class 624 * vs instance). 625 */ 626 for_each_engine(engine, gt, id) { 627 worst_min_size += sizeof(struct guc_state_capture_group_header_t) + 628 (3 * sizeof(struct guc_state_capture_header_t)); 629 630 if (!intel_guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &tmp)) 631 num_regs += tmp; 632 633 if (!intel_guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, 634 engine->class, &tmp)) { 635 num_regs += tmp; 636 } 637 if (!intel_guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, 638 engine->class, &tmp)) { 639 num_regs += tmp; 640 } 641 } 642 643 worst_min_size += (num_regs * sizeof(struct guc_mmio_reg)); 644 645 return worst_min_size; 646 } 647 648 /* 649 * Add on a 3x multiplier to allow for multiple back-to-back captures occurring 650 * before the i915 can read the data out and process it 651 */ 652 #define GUC_CAPTURE_OVERBUFFER_MULTIPLIER 3 653 654 static void check_guc_capture_size(struct intel_guc *guc) 655 { 656 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 657 int min_size = guc_capture_output_min_size_est(guc); 658 int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER; 659 u32 buffer_size = intel_guc_log_section_size_capture(&guc->log); 660 661 if (min_size < 0) 662 drm_warn(&i915->drm, "Failed to calculate GuC error state capture buffer minimum size: %d!\n", 663 min_size); 664 else if (min_size > buffer_size) 665 drm_warn(&i915->drm, "GuC error state capture buffer is too small: %d < %d\n", 666 buffer_size, min_size); 667 else if (spare_size > buffer_size) 668 drm_notice(&i915->drm, "GuC error state capture buffer maybe too small: %d < %d (min = %d)\n", 669 buffer_size, spare_size, min_size); 670 } 671 672 /* 673 * KMD Init time flows: 674 * -------------------- 675 * --> alloc A: GuC input capture regs lists (registered to GuC via ADS). 676 * intel_guc_ads acquires the register lists by calling 677 * intel_guc_capture_list_size and intel_guc_capture_list_get 'n' times, 678 * where n = 1 for global-reg-list + 679 * num_engine_classes for class-reg-list + 680 * num_engine_classes for instance-reg-list 681 * (since all instances of the same engine-class type 682 * have an identical engine-instance register-list). 683 * ADS module also calls separately for PF vs VF. 684 * 685 * --> alloc B: GuC output capture buf (registered via guc_init_params(log_param)) 686 * Size = #define CAPTURE_BUFFER_SIZE (warns if on too-small) 687 * Note2: 'x 3' to hold multiple capture groups 688 * 689 * GUC Runtime notify capture: 690 * -------------------------- 691 * --> G2H STATE_CAPTURE_NOTIFICATION 692 * L--> intel_guc_capture_process 693 * L--> Loop through B (head..tail) and for each engine instance's 694 * err-state-captured register-list we find, we alloc 'C': 695 * --> alloc C: A capture-output-node structure that includes misc capture info along 696 * with 3 register list dumps (global, engine-class and engine-instance) 697 * This node is created from a pre-allocated list of blank nodes in 698 * guc->capture->cachelist and populated with the error-capture 699 * data from GuC and then it's added into guc->capture->outlist linked 700 * list. This list is used for matchup and printout by i915_gpu_coredump 701 * and err_print_gt, (when user invokes the error capture sysfs). 702 * 703 * GUC --> notify context reset: 704 * ----------------------------- 705 * --> G2H CONTEXT RESET 706 * L--> guc_handle_context_reset --> i915_capture_error_state 707 * L--> i915_gpu_coredump(..IS_GUC_CAPTURE) --> gt_record_engines 708 * --> capture_engine(..IS_GUC_CAPTURE) 709 * L--> intel_guc_capture_get_matching_node is where 710 * detach C from internal linked list and add it into 711 * intel_engine_coredump struct (if the context and 712 * engine of the event notification matches a node 713 * in the link list). 714 * 715 * User Sysfs / Debugfs 716 * -------------------- 717 * --> i915_gpu_coredump_copy_to_buffer-> 718 * L--> err_print_to_sgl --> err_print_gt 719 * L--> error_print_guc_captures 720 * L--> intel_guc_capture_print_node prints the 721 * register lists values of the attached node 722 * on the error-engine-dump being reported. 723 * L--> i915_reset_error_state ... -->__i915_gpu_coredump_free 724 * L--> ... cleanup_gt --> 725 * L--> intel_guc_capture_free_node returns the 726 * capture-output-node back to the internal 727 * cachelist for reuse. 728 * 729 */ 730 731 static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf) 732 { 733 if (buf->wr >= buf->rd) 734 return (buf->wr - buf->rd); 735 return (buf->size - buf->rd) + buf->wr; 736 } 737 738 static int guc_capture_buf_cnt_to_end(struct __guc_capture_bufstate *buf) 739 { 740 if (buf->rd > buf->wr) 741 return (buf->size - buf->rd); 742 return (buf->wr - buf->rd); 743 } 744 745 /* 746 * GuC's error-capture output is a ring buffer populated in a byte-stream fashion: 747 * 748 * The GuC Log buffer region for error-capture is managed like a ring buffer. 749 * The GuC firmware dumps error capture logs into this ring in a byte-stream flow. 750 * Additionally, as per the current and foreseeable future, all packed error- 751 * capture output structures are dword aligned. 752 * 753 * That said, if the GuC firmware is in the midst of writing a structure that is larger 754 * than one dword but the tail end of the err-capture buffer-region has lesser space left, 755 * we would need to extract that structure one dword at a time straddled across the end, 756 * onto the start of the ring. 757 * 758 * Below function, guc_capture_log_remove_dw is a helper for that. All callers of this 759 * function would typically do a straight-up memcpy from the ring contents and will only 760 * call this helper if their structure-extraction is straddling across the end of the 761 * ring. GuC firmware does not add any padding. The reason for the no-padding is to ease 762 * scalability for future expansion of output data types without requiring a redesign 763 * of the flow controls. 764 */ 765 static int 766 guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 767 u32 *dw) 768 { 769 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 770 int tries = 2; 771 int avail = 0; 772 u32 *src_data; 773 774 if (!guc_capture_buf_cnt(buf)) 775 return 0; 776 777 while (tries--) { 778 avail = guc_capture_buf_cnt_to_end(buf); 779 if (avail >= sizeof(u32)) { 780 src_data = (u32 *)(buf->data + buf->rd); 781 *dw = *src_data; 782 buf->rd += 4; 783 return 4; 784 } 785 if (avail) 786 drm_dbg(&i915->drm, "GuC-Cap-Logs not dword aligned, skipping.\n"); 787 buf->rd = 0; 788 } 789 790 return 0; 791 } 792 793 static bool 794 guc_capture_data_extracted(struct __guc_capture_bufstate *b, 795 int size, void *dest) 796 { 797 if (guc_capture_buf_cnt_to_end(b) >= size) { 798 memcpy(dest, (b->data + b->rd), size); 799 b->rd += size; 800 return true; 801 } 802 return false; 803 } 804 805 static int 806 guc_capture_log_get_group_hdr(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 807 struct guc_state_capture_group_header_t *ghdr) 808 { 809 int read = 0; 810 int fullsize = sizeof(struct guc_state_capture_group_header_t); 811 812 if (fullsize > guc_capture_buf_cnt(buf)) 813 return -1; 814 815 if (guc_capture_data_extracted(buf, fullsize, (void *)ghdr)) 816 return 0; 817 818 read += guc_capture_log_remove_dw(guc, buf, &ghdr->owner); 819 read += guc_capture_log_remove_dw(guc, buf, &ghdr->info); 820 if (read != fullsize) 821 return -1; 822 823 return 0; 824 } 825 826 static int 827 guc_capture_log_get_data_hdr(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 828 struct guc_state_capture_header_t *hdr) 829 { 830 int read = 0; 831 int fullsize = sizeof(struct guc_state_capture_header_t); 832 833 if (fullsize > guc_capture_buf_cnt(buf)) 834 return -1; 835 836 if (guc_capture_data_extracted(buf, fullsize, (void *)hdr)) 837 return 0; 838 839 read += guc_capture_log_remove_dw(guc, buf, &hdr->owner); 840 read += guc_capture_log_remove_dw(guc, buf, &hdr->info); 841 read += guc_capture_log_remove_dw(guc, buf, &hdr->lrca); 842 read += guc_capture_log_remove_dw(guc, buf, &hdr->guc_id); 843 read += guc_capture_log_remove_dw(guc, buf, &hdr->num_mmios); 844 if (read != fullsize) 845 return -1; 846 847 return 0; 848 } 849 850 static int 851 guc_capture_log_get_register(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 852 struct guc_mmio_reg *reg) 853 { 854 int read = 0; 855 int fullsize = sizeof(struct guc_mmio_reg); 856 857 if (fullsize > guc_capture_buf_cnt(buf)) 858 return -1; 859 860 if (guc_capture_data_extracted(buf, fullsize, (void *)reg)) 861 return 0; 862 863 read += guc_capture_log_remove_dw(guc, buf, ®->offset); 864 read += guc_capture_log_remove_dw(guc, buf, ®->value); 865 read += guc_capture_log_remove_dw(guc, buf, ®->flags); 866 read += guc_capture_log_remove_dw(guc, buf, ®->mask); 867 if (read != fullsize) 868 return -1; 869 870 return 0; 871 } 872 873 static void 874 guc_capture_delete_one_node(struct intel_guc *guc, struct __guc_capture_parsed_output *node) 875 { 876 int i; 877 878 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) 879 kfree(node->reginfo[i].regs); 880 list_del(&node->link); 881 kfree(node); 882 } 883 884 static void 885 guc_capture_delete_prealloc_nodes(struct intel_guc *guc) 886 { 887 struct __guc_capture_parsed_output *n, *ntmp; 888 889 /* 890 * NOTE: At the end of driver operation, we must assume that we 891 * have prealloc nodes in both the cachelist as well as outlist 892 * if unclaimed error capture events occurred prior to shutdown. 893 */ 894 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) 895 guc_capture_delete_one_node(guc, n); 896 897 list_for_each_entry_safe(n, ntmp, &guc->capture->cachelist, link) 898 guc_capture_delete_one_node(guc, n); 899 } 900 901 static void 902 guc_capture_add_node_to_list(struct __guc_capture_parsed_output *node, 903 struct list_head *list) 904 { 905 list_add_tail(&node->link, list); 906 } 907 908 static void 909 guc_capture_add_node_to_outlist(struct intel_guc_state_capture *gc, 910 struct __guc_capture_parsed_output *node) 911 { 912 guc_capture_add_node_to_list(node, &gc->outlist); 913 } 914 915 static void 916 guc_capture_add_node_to_cachelist(struct intel_guc_state_capture *gc, 917 struct __guc_capture_parsed_output *node) 918 { 919 guc_capture_add_node_to_list(node, &gc->cachelist); 920 } 921 922 static void 923 guc_capture_init_node(struct intel_guc *guc, struct __guc_capture_parsed_output *node) 924 { 925 struct guc_mmio_reg *tmp[GUC_CAPTURE_LIST_TYPE_MAX]; 926 int i; 927 928 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 929 tmp[i] = node->reginfo[i].regs; 930 memset(tmp[i], 0, sizeof(struct guc_mmio_reg) * 931 guc->capture->max_mmio_per_node); 932 } 933 memset(node, 0, sizeof(*node)); 934 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) 935 node->reginfo[i].regs = tmp[i]; 936 937 INIT_LIST_HEAD(&node->link); 938 } 939 940 static struct __guc_capture_parsed_output * 941 guc_capture_get_prealloc_node(struct intel_guc *guc) 942 { 943 struct __guc_capture_parsed_output *found = NULL; 944 945 if (!list_empty(&guc->capture->cachelist)) { 946 struct __guc_capture_parsed_output *n, *ntmp; 947 948 /* get first avail node from the cache list */ 949 list_for_each_entry_safe(n, ntmp, &guc->capture->cachelist, link) { 950 found = n; 951 list_del(&n->link); 952 break; 953 } 954 } else { 955 struct __guc_capture_parsed_output *n, *ntmp; 956 957 /* traverse down and steal back the oldest node already allocated */ 958 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) { 959 found = n; 960 } 961 if (found) 962 list_del(&found->link); 963 } 964 if (found) 965 guc_capture_init_node(guc, found); 966 967 return found; 968 } 969 970 static struct __guc_capture_parsed_output * 971 guc_capture_alloc_one_node(struct intel_guc *guc) 972 { 973 struct __guc_capture_parsed_output *new; 974 int i; 975 976 new = kzalloc(sizeof(*new), GFP_KERNEL); 977 if (!new) 978 return NULL; 979 980 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 981 new->reginfo[i].regs = kcalloc(guc->capture->max_mmio_per_node, 982 sizeof(struct guc_mmio_reg), GFP_KERNEL); 983 if (!new->reginfo[i].regs) { 984 while (i) 985 kfree(new->reginfo[--i].regs); 986 kfree(new); 987 return NULL; 988 } 989 } 990 guc_capture_init_node(guc, new); 991 992 return new; 993 } 994 995 static struct __guc_capture_parsed_output * 996 guc_capture_clone_node(struct intel_guc *guc, struct __guc_capture_parsed_output *original, 997 u32 keep_reglist_mask) 998 { 999 struct __guc_capture_parsed_output *new; 1000 int i; 1001 1002 new = guc_capture_get_prealloc_node(guc); 1003 if (!new) 1004 return NULL; 1005 if (!original) 1006 return new; 1007 1008 new->is_partial = original->is_partial; 1009 1010 /* copy reg-lists that we want to clone */ 1011 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1012 if (keep_reglist_mask & BIT(i)) { 1013 GEM_BUG_ON(original->reginfo[i].num_regs > 1014 guc->capture->max_mmio_per_node); 1015 1016 memcpy(new->reginfo[i].regs, original->reginfo[i].regs, 1017 original->reginfo[i].num_regs * sizeof(struct guc_mmio_reg)); 1018 1019 new->reginfo[i].num_regs = original->reginfo[i].num_regs; 1020 new->reginfo[i].vfid = original->reginfo[i].vfid; 1021 1022 if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS) { 1023 new->eng_class = original->eng_class; 1024 } else if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) { 1025 new->eng_inst = original->eng_inst; 1026 new->guc_id = original->guc_id; 1027 new->lrca = original->lrca; 1028 } 1029 } 1030 } 1031 1032 return new; 1033 } 1034 1035 static void 1036 __guc_capture_create_prealloc_nodes(struct intel_guc *guc) 1037 { 1038 struct __guc_capture_parsed_output *node = NULL; 1039 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 1040 int i; 1041 1042 for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) { 1043 node = guc_capture_alloc_one_node(guc); 1044 if (!node) { 1045 drm_warn(&i915->drm, "GuC Capture pre-alloc-cache failure\n"); 1046 /* dont free the priors, use what we got and cleanup at shutdown */ 1047 return; 1048 } 1049 guc_capture_add_node_to_cachelist(guc->capture, node); 1050 } 1051 } 1052 1053 static int 1054 guc_get_max_reglist_count(struct intel_guc *guc) 1055 { 1056 int i, j, k, tmp, maxregcount = 0; 1057 1058 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; ++i) { 1059 for (j = 0; j < GUC_CAPTURE_LIST_TYPE_MAX; ++j) { 1060 for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) { 1061 if (j == GUC_CAPTURE_LIST_TYPE_GLOBAL && k > 0) 1062 continue; 1063 1064 tmp = guc_cap_list_num_regs(guc->capture, i, j, k); 1065 if (tmp > maxregcount) 1066 maxregcount = tmp; 1067 } 1068 } 1069 } 1070 if (!maxregcount) 1071 maxregcount = PREALLOC_NODES_DEFAULT_NUMREGS; 1072 1073 return maxregcount; 1074 } 1075 1076 static void 1077 guc_capture_create_prealloc_nodes(struct intel_guc *guc) 1078 { 1079 /* skip if we've already done the pre-alloc */ 1080 if (guc->capture->max_mmio_per_node) 1081 return; 1082 1083 guc->capture->max_mmio_per_node = guc_get_max_reglist_count(guc); 1084 __guc_capture_create_prealloc_nodes(guc); 1085 } 1086 1087 static int 1088 guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstate *buf) 1089 { 1090 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 1091 struct guc_state_capture_group_header_t ghdr = {0}; 1092 struct guc_state_capture_header_t hdr = {0}; 1093 struct __guc_capture_parsed_output *node = NULL; 1094 struct guc_mmio_reg *regs = NULL; 1095 int i, numlists, numregs, ret = 0; 1096 enum guc_capture_type datatype; 1097 struct guc_mmio_reg tmp; 1098 bool is_partial = false; 1099 1100 i = guc_capture_buf_cnt(buf); 1101 if (!i) 1102 return -ENODATA; 1103 if (i % sizeof(u32)) { 1104 drm_warn(&i915->drm, "GuC Capture new entries unaligned\n"); 1105 ret = -EIO; 1106 goto bailout; 1107 } 1108 1109 /* first get the capture group header */ 1110 if (guc_capture_log_get_group_hdr(guc, buf, &ghdr)) { 1111 ret = -EIO; 1112 goto bailout; 1113 } 1114 /* 1115 * we would typically expect a layout as below where n would be expected to be 1116 * anywhere between 3 to n where n > 3 if we are seeing multiple dependent engine 1117 * instances being reset together. 1118 * ____________________________________________ 1119 * | Capture Group | 1120 * | ________________________________________ | 1121 * | | Capture Group Header: | | 1122 * | | - num_captures = 5 | | 1123 * | |______________________________________| | 1124 * | ________________________________________ | 1125 * | | Capture1: | | 1126 * | | Hdr: GLOBAL, numregs=a | | 1127 * | | ____________________________________ | | 1128 * | | | Reglist | | | 1129 * | | | - reg1, reg2, ... rega | | | 1130 * | | |__________________________________| | | 1131 * | |______________________________________| | 1132 * | ________________________________________ | 1133 * | | Capture2: | | 1134 * | | Hdr: CLASS=RENDER/COMPUTE, numregs=b| | 1135 * | | ____________________________________ | | 1136 * | | | Reglist | | | 1137 * | | | - reg1, reg2, ... regb | | | 1138 * | | |__________________________________| | | 1139 * | |______________________________________| | 1140 * | ________________________________________ | 1141 * | | Capture3: | | 1142 * | | Hdr: INSTANCE=RCS, numregs=c | | 1143 * | | ____________________________________ | | 1144 * | | | Reglist | | | 1145 * | | | - reg1, reg2, ... regc | | | 1146 * | | |__________________________________| | | 1147 * | |______________________________________| | 1148 * | ________________________________________ | 1149 * | | Capture4: | | 1150 * | | Hdr: CLASS=RENDER/COMPUTE, numregs=d| | 1151 * | | ____________________________________ | | 1152 * | | | Reglist | | | 1153 * | | | - reg1, reg2, ... regd | | | 1154 * | | |__________________________________| | | 1155 * | |______________________________________| | 1156 * | ________________________________________ | 1157 * | | Capture5: | | 1158 * | | Hdr: INSTANCE=CCS0, numregs=e | | 1159 * | | ____________________________________ | | 1160 * | | | Reglist | | | 1161 * | | | - reg1, reg2, ... rege | | | 1162 * | | |__________________________________| | | 1163 * | |______________________________________| | 1164 * |__________________________________________| 1165 */ 1166 is_partial = FIELD_GET(CAP_GRP_HDR_CAPTURE_TYPE, ghdr.info); 1167 numlists = FIELD_GET(CAP_GRP_HDR_NUM_CAPTURES, ghdr.info); 1168 1169 while (numlists--) { 1170 if (guc_capture_log_get_data_hdr(guc, buf, &hdr)) { 1171 ret = -EIO; 1172 break; 1173 } 1174 1175 datatype = FIELD_GET(CAP_HDR_CAPTURE_TYPE, hdr.info); 1176 if (datatype > GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) { 1177 /* unknown capture type - skip over to next capture set */ 1178 numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); 1179 while (numregs--) { 1180 if (guc_capture_log_get_register(guc, buf, &tmp)) { 1181 ret = -EIO; 1182 break; 1183 } 1184 } 1185 continue; 1186 } else if (node) { 1187 /* 1188 * Based on the current capture type and what we have so far, 1189 * decide if we should add the current node into the internal 1190 * linked list for match-up when i915_gpu_coredump calls later 1191 * (and alloc a blank node for the next set of reglists) 1192 * or continue with the same node or clone the current node 1193 * but only retain the global or class registers (such as the 1194 * case of dependent engine resets). 1195 */ 1196 if (datatype == GUC_CAPTURE_LIST_TYPE_GLOBAL) { 1197 guc_capture_add_node_to_outlist(guc->capture, node); 1198 node = NULL; 1199 } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS && 1200 node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS].num_regs) { 1201 /* Add to list, clone node and duplicate global list */ 1202 guc_capture_add_node_to_outlist(guc->capture, node); 1203 node = guc_capture_clone_node(guc, node, 1204 GCAP_PARSED_REGLIST_INDEX_GLOBAL); 1205 } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE && 1206 node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE].num_regs) { 1207 /* Add to list, clone node and duplicate global + class lists */ 1208 guc_capture_add_node_to_outlist(guc->capture, node); 1209 node = guc_capture_clone_node(guc, node, 1210 (GCAP_PARSED_REGLIST_INDEX_GLOBAL | 1211 GCAP_PARSED_REGLIST_INDEX_ENGCLASS)); 1212 } 1213 } 1214 1215 if (!node) { 1216 node = guc_capture_get_prealloc_node(guc); 1217 if (!node) { 1218 ret = -ENOMEM; 1219 break; 1220 } 1221 if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL) 1222 drm_dbg(&i915->drm, "GuC Capture missing global dump: %08x!\n", 1223 datatype); 1224 } 1225 node->is_partial = is_partial; 1226 node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner); 1227 switch (datatype) { 1228 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE: 1229 node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); 1230 node->eng_inst = FIELD_GET(CAP_HDR_ENGINE_INSTANCE, hdr.info); 1231 node->lrca = hdr.lrca; 1232 node->guc_id = hdr.guc_id; 1233 break; 1234 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS: 1235 node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); 1236 break; 1237 default: 1238 break; 1239 } 1240 1241 numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); 1242 if (numregs > guc->capture->max_mmio_per_node) { 1243 drm_dbg(&i915->drm, "GuC Capture list extraction clipped by prealloc!\n"); 1244 numregs = guc->capture->max_mmio_per_node; 1245 } 1246 node->reginfo[datatype].num_regs = numregs; 1247 regs = node->reginfo[datatype].regs; 1248 i = 0; 1249 while (numregs--) { 1250 if (guc_capture_log_get_register(guc, buf, ®s[i++])) { 1251 ret = -EIO; 1252 break; 1253 } 1254 } 1255 } 1256 1257 bailout: 1258 if (node) { 1259 /* If we have data, add to linked list for match-up when i915_gpu_coredump calls */ 1260 for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1261 if (node->reginfo[i].regs) { 1262 guc_capture_add_node_to_outlist(guc->capture, node); 1263 node = NULL; 1264 break; 1265 } 1266 } 1267 if (node) /* else return it back to cache list */ 1268 guc_capture_add_node_to_cachelist(guc->capture, node); 1269 } 1270 return ret; 1271 } 1272 1273 static int __guc_capture_flushlog_complete(struct intel_guc *guc) 1274 { 1275 u32 action[] = { 1276 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE, 1277 GUC_CAPTURE_LOG_BUFFER 1278 }; 1279 1280 return intel_guc_send_nb(guc, action, ARRAY_SIZE(action), 0); 1281 1282 } 1283 1284 static void __guc_capture_process_output(struct intel_guc *guc) 1285 { 1286 unsigned int buffer_size, read_offset, write_offset, full_count; 1287 struct intel_uc *uc = container_of(guc, typeof(*uc), guc); 1288 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 1289 struct guc_log_buffer_state log_buf_state_local; 1290 struct guc_log_buffer_state *log_buf_state; 1291 struct __guc_capture_bufstate buf; 1292 void *src_data = NULL; 1293 bool new_overflow; 1294 int ret; 1295 1296 log_buf_state = guc->log.buf_addr + 1297 (sizeof(struct guc_log_buffer_state) * GUC_CAPTURE_LOG_BUFFER); 1298 src_data = guc->log.buf_addr + 1299 intel_guc_get_log_buffer_offset(&guc->log, GUC_CAPTURE_LOG_BUFFER); 1300 1301 /* 1302 * Make a copy of the state structure, inside GuC log buffer 1303 * (which is uncached mapped), on the stack to avoid reading 1304 * from it multiple times. 1305 */ 1306 memcpy(&log_buf_state_local, log_buf_state, sizeof(struct guc_log_buffer_state)); 1307 buffer_size = intel_guc_get_log_buffer_size(&guc->log, GUC_CAPTURE_LOG_BUFFER); 1308 read_offset = log_buf_state_local.read_ptr; 1309 write_offset = log_buf_state_local.sampled_write_ptr; 1310 full_count = log_buf_state_local.buffer_full_cnt; 1311 1312 /* Bookkeeping stuff */ 1313 guc->log.stats[GUC_CAPTURE_LOG_BUFFER].flush += log_buf_state_local.flush_to_file; 1314 new_overflow = intel_guc_check_log_buf_overflow(&guc->log, GUC_CAPTURE_LOG_BUFFER, 1315 full_count); 1316 1317 /* Now copy the actual logs. */ 1318 if (unlikely(new_overflow)) { 1319 /* copy the whole buffer in case of overflow */ 1320 read_offset = 0; 1321 write_offset = buffer_size; 1322 } else if (unlikely((read_offset > buffer_size) || 1323 (write_offset > buffer_size))) { 1324 drm_err(&i915->drm, "invalid GuC log capture buffer state!\n"); 1325 /* copy whole buffer as offsets are unreliable */ 1326 read_offset = 0; 1327 write_offset = buffer_size; 1328 } 1329 1330 buf.size = buffer_size; 1331 buf.rd = read_offset; 1332 buf.wr = write_offset; 1333 buf.data = src_data; 1334 1335 if (!uc->reset_in_progress) { 1336 do { 1337 ret = guc_capture_extract_reglists(guc, &buf); 1338 } while (ret >= 0); 1339 } 1340 1341 /* Update the state of log buffer err-cap state */ 1342 log_buf_state->read_ptr = write_offset; 1343 log_buf_state->flush_to_file = 0; 1344 __guc_capture_flushlog_complete(guc); 1345 } 1346 1347 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1348 1349 static const char * 1350 guc_capture_reg_to_str(const struct intel_guc *guc, u32 owner, u32 type, 1351 u32 class, u32 id, u32 offset, u32 *is_ext) 1352 { 1353 const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; 1354 struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists; 1355 const struct __guc_mmio_reg_descr_group *match; 1356 struct __guc_mmio_reg_descr_group *matchext; 1357 int j; 1358 1359 *is_ext = 0; 1360 if (!reglists) 1361 return NULL; 1362 1363 match = guc_capture_get_one_list(reglists, owner, type, id); 1364 if (!match) 1365 return NULL; 1366 1367 for (j = 0; j < match->num_regs; ++j) { 1368 if (offset == match->list[j].reg.reg) 1369 return match->list[j].regname; 1370 } 1371 if (extlists) { 1372 matchext = guc_capture_get_one_ext_list(extlists, owner, type, id); 1373 if (!matchext) 1374 return NULL; 1375 for (j = 0; j < matchext->num_regs; ++j) { 1376 if (offset == matchext->extlist[j].reg.reg) { 1377 *is_ext = 1; 1378 return matchext->extlist[j].regname; 1379 } 1380 } 1381 } 1382 1383 return NULL; 1384 } 1385 1386 #define GCAP_PRINT_INTEL_ENG_INFO(ebuf, eng) \ 1387 do { \ 1388 i915_error_printf(ebuf, " i915-Eng-Name: %s command stream\n", \ 1389 (eng)->name); \ 1390 i915_error_printf(ebuf, " i915-Eng-Inst-Class: 0x%02x\n", (eng)->class); \ 1391 i915_error_printf(ebuf, " i915-Eng-Inst-Id: 0x%02x\n", (eng)->instance); \ 1392 i915_error_printf(ebuf, " i915-Eng-LogicalMask: 0x%08x\n", \ 1393 (eng)->logical_mask); \ 1394 } while (0) 1395 1396 #define GCAP_PRINT_GUC_INST_INFO(ebuf, node) \ 1397 do { \ 1398 i915_error_printf(ebuf, " GuC-Engine-Inst-Id: 0x%08x\n", \ 1399 (node)->eng_inst); \ 1400 i915_error_printf(ebuf, " GuC-Context-Id: 0x%08x\n", (node)->guc_id); \ 1401 i915_error_printf(ebuf, " LRCA: 0x%08x\n", (node)->lrca); \ 1402 } while (0) 1403 1404 int intel_guc_capture_print_engine_node(struct drm_i915_error_state_buf *ebuf, 1405 const struct intel_engine_coredump *ee) 1406 { 1407 const char *grptype[GUC_STATE_CAPTURE_GROUP_TYPE_MAX] = { 1408 "full-capture", 1409 "partial-capture" 1410 }; 1411 const char *datatype[GUC_CAPTURE_LIST_TYPE_MAX] = { 1412 "Global", 1413 "Engine-Class", 1414 "Engine-Instance" 1415 }; 1416 struct intel_guc_state_capture *cap; 1417 struct __guc_capture_parsed_output *node; 1418 struct intel_engine_cs *eng; 1419 struct guc_mmio_reg *regs; 1420 struct intel_guc *guc; 1421 const char *str; 1422 int numregs, i, j; 1423 u32 is_ext; 1424 1425 if (!ebuf || !ee) 1426 return -EINVAL; 1427 cap = ee->capture; 1428 if (!cap || !ee->engine) 1429 return -ENODEV; 1430 1431 guc = &ee->engine->gt->uc.guc; 1432 1433 i915_error_printf(ebuf, "global --- GuC Error Capture on %s command stream:\n", 1434 ee->engine->name); 1435 1436 node = ee->guc_capture_node; 1437 if (!node) { 1438 i915_error_printf(ebuf, " No matching ee-node\n"); 1439 return 0; 1440 } 1441 1442 i915_error_printf(ebuf, "Coverage: %s\n", grptype[node->is_partial]); 1443 1444 for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1445 i915_error_printf(ebuf, " RegListType: %s\n", 1446 datatype[i % GUC_CAPTURE_LIST_TYPE_MAX]); 1447 i915_error_printf(ebuf, " Owner-Id: %d\n", node->reginfo[i].vfid); 1448 1449 switch (i) { 1450 case GUC_CAPTURE_LIST_TYPE_GLOBAL: 1451 default: 1452 break; 1453 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS: 1454 i915_error_printf(ebuf, " GuC-Eng-Class: %d\n", node->eng_class); 1455 i915_error_printf(ebuf, " i915-Eng-Class: %d\n", 1456 guc_class_to_engine_class(node->eng_class)); 1457 break; 1458 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE: 1459 eng = intel_guc_lookup_engine(guc, node->eng_class, node->eng_inst); 1460 if (eng) 1461 GCAP_PRINT_INTEL_ENG_INFO(ebuf, eng); 1462 else 1463 i915_error_printf(ebuf, " i915-Eng-Lookup Fail!\n"); 1464 GCAP_PRINT_GUC_INST_INFO(ebuf, node); 1465 break; 1466 } 1467 1468 numregs = node->reginfo[i].num_regs; 1469 i915_error_printf(ebuf, " NumRegs: %d\n", numregs); 1470 j = 0; 1471 while (numregs--) { 1472 regs = node->reginfo[i].regs; 1473 str = guc_capture_reg_to_str(guc, GUC_CAPTURE_LIST_INDEX_PF, i, 1474 node->eng_class, 0, regs[j].offset, &is_ext); 1475 if (!str) 1476 i915_error_printf(ebuf, " REG-0x%08x", regs[j].offset); 1477 else 1478 i915_error_printf(ebuf, " %s", str); 1479 if (is_ext) 1480 i915_error_printf(ebuf, "[%ld][%ld]", 1481 FIELD_GET(GUC_REGSET_STEERING_GROUP, regs[j].flags), 1482 FIELD_GET(GUC_REGSET_STEERING_INSTANCE, regs[j].flags)); 1483 i915_error_printf(ebuf, ": 0x%08x\n", regs[j].value); 1484 ++j; 1485 } 1486 } 1487 return 0; 1488 } 1489 1490 #endif //CONFIG_DRM_I915_CAPTURE_ERROR 1491 1492 void intel_guc_capture_free_node(struct intel_engine_coredump *ee) 1493 { 1494 if (!ee || !ee->guc_capture_node) 1495 return; 1496 1497 guc_capture_add_node_to_cachelist(ee->capture, ee->guc_capture_node); 1498 ee->capture = NULL; 1499 ee->guc_capture_node = NULL; 1500 } 1501 1502 void intel_guc_capture_get_matching_node(struct intel_gt *gt, 1503 struct intel_engine_coredump *ee, 1504 struct intel_context *ce) 1505 { 1506 struct __guc_capture_parsed_output *n, *ntmp; 1507 struct drm_i915_private *i915; 1508 struct intel_guc *guc; 1509 1510 if (!gt || !ee || !ce) 1511 return; 1512 1513 i915 = gt->i915; 1514 guc = >->uc.guc; 1515 if (!guc->capture) 1516 return; 1517 1518 GEM_BUG_ON(ee->guc_capture_node); 1519 /* 1520 * Look for a matching GuC reported error capture node from 1521 * the internal output link-list based on lrca, guc-id and engine 1522 * identification. 1523 */ 1524 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) { 1525 if (n->eng_inst == GUC_ID_TO_ENGINE_INSTANCE(ee->engine->guc_id) && 1526 n->eng_class == GUC_ID_TO_ENGINE_CLASS(ee->engine->guc_id) && 1527 n->guc_id && n->guc_id == ce->guc_id.id && 1528 (n->lrca & CTX_GTT_ADDRESS_MASK) && (n->lrca & CTX_GTT_ADDRESS_MASK) == 1529 (ce->lrc.lrca & CTX_GTT_ADDRESS_MASK)) { 1530 list_del(&n->link); 1531 ee->guc_capture_node = n; 1532 ee->capture = guc->capture; 1533 return; 1534 } 1535 } 1536 drm_dbg(&i915->drm, "GuC capture can't match ee to node\n"); 1537 } 1538 1539 void intel_guc_capture_process(struct intel_guc *guc) 1540 { 1541 if (guc->capture) 1542 __guc_capture_process_output(guc); 1543 } 1544 1545 static void 1546 guc_capture_free_ads_cache(struct intel_guc_state_capture *gc) 1547 { 1548 int i, j, k; 1549 struct __guc_capture_ads_cache *cache; 1550 1551 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; ++i) { 1552 for (j = 0; j < GUC_CAPTURE_LIST_TYPE_MAX; ++j) { 1553 for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) { 1554 cache = &gc->ads_cache[i][j][k]; 1555 if (cache->is_valid) 1556 kfree(cache->ptr); 1557 } 1558 } 1559 } 1560 kfree(gc->ads_null_cache); 1561 } 1562 1563 void intel_guc_capture_destroy(struct intel_guc *guc) 1564 { 1565 if (!guc->capture) 1566 return; 1567 1568 guc_capture_free_ads_cache(guc->capture); 1569 1570 guc_capture_delete_prealloc_nodes(guc); 1571 1572 guc_capture_free_extlists(guc->capture->extlists); 1573 kfree(guc->capture->extlists); 1574 1575 kfree(guc->capture); 1576 guc->capture = NULL; 1577 } 1578 1579 int intel_guc_capture_init(struct intel_guc *guc) 1580 { 1581 guc->capture = kzalloc(sizeof(*guc->capture), GFP_KERNEL); 1582 if (!guc->capture) 1583 return -ENOMEM; 1584 1585 guc->capture->reglists = guc_capture_get_device_reglist(guc); 1586 1587 INIT_LIST_HEAD(&guc->capture->outlist); 1588 INIT_LIST_HEAD(&guc->capture->cachelist); 1589 1590 check_guc_capture_size(guc); 1591 1592 return 0; 1593 } 1594