1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #ifndef _INTEL_GUC_FWIF_H 7 #define _INTEL_GUC_FWIF_H 8 9 #include <linux/bits.h> 10 #include <linux/compiler.h> 11 #include <linux/types.h> 12 13 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0 14 #define GUC_CLIENT_PRIORITY_HIGH 1 15 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 16 #define GUC_CLIENT_PRIORITY_NORMAL 3 17 #define GUC_CLIENT_PRIORITY_NUM 4 18 19 #define GUC_MAX_STAGE_DESCRIPTORS 1024 20 #define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS 21 22 #define GUC_RENDER_ENGINE 0 23 #define GUC_VIDEO_ENGINE 1 24 #define GUC_BLITTER_ENGINE 2 25 #define GUC_VIDEOENHANCE_ENGINE 3 26 #define GUC_VIDEO_ENGINE2 4 27 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) 28 29 #define GUC_MAX_ENGINE_CLASSES 5 30 #define GUC_MAX_INSTANCES_PER_CLASS 16 31 32 #define GUC_DOORBELL_INVALID 256 33 34 #define GUC_DB_SIZE (PAGE_SIZE) 35 #define GUC_WQ_SIZE (PAGE_SIZE * 2) 36 37 /* Work queue item header definitions */ 38 #define WQ_STATUS_ACTIVE 1 39 #define WQ_STATUS_SUSPENDED 2 40 #define WQ_STATUS_CMD_ERROR 3 41 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 42 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 43 #define WQ_TYPE_SHIFT 0 44 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) 45 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) 46 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) 47 #define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT) 48 #define WQ_TARGET_SHIFT 10 49 #define WQ_LEN_SHIFT 16 50 #define WQ_NO_WCFLUSH_WAIT (1 << 27) 51 #define WQ_PRESENT_WORKLOAD (1 << 28) 52 53 #define WQ_RING_TAIL_SHIFT 20 54 #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */ 55 #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT) 56 57 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) 58 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) 59 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) 60 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) 61 #define GUC_STAGE_DESC_ATTR_RESET BIT(4) 62 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) 63 #define GUC_STAGE_DESC_ATTR_PCH BIT(6) 64 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) 65 66 /* New GuC control data */ 67 #define GUC_CTL_CTXINFO 0 68 #define GUC_CTL_CTXNUM_IN16_SHIFT 0 69 #define GUC_CTL_BASE_ADDR_SHIFT 12 70 71 #define GUC_CTL_LOG_PARAMS 1 72 #define GUC_LOG_VALID (1 << 0) 73 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) 74 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) 75 #define GUC_LOG_CRASH_SHIFT 4 76 #define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT) 77 #define GUC_LOG_DPC_SHIFT 6 78 #define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT) 79 #define GUC_LOG_ISR_SHIFT 9 80 #define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT) 81 #define GUC_LOG_BUF_ADDR_SHIFT 12 82 83 #define GUC_CTL_WA 2 84 #define GUC_CTL_FEATURE 3 85 #define GUC_CTL_DISABLE_SCHEDULER (1 << 14) 86 87 #define GUC_CTL_DEBUG 4 88 #define GUC_LOG_VERBOSITY_SHIFT 0 89 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) 90 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) 91 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) 92 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) 93 /* Verbosity range-check limits, without the shift */ 94 #define GUC_LOG_VERBOSITY_MIN 0 95 #define GUC_LOG_VERBOSITY_MAX 3 96 #define GUC_LOG_VERBOSITY_MASK 0x0000000f 97 #define GUC_LOG_DESTINATION_MASK (3 << 4) 98 #define GUC_LOG_DISABLED (1 << 6) 99 #define GUC_PROFILE_ENABLED (1 << 7) 100 101 #define GUC_CTL_ADS 5 102 #define GUC_ADS_ADDR_SHIFT 1 103 #define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT) 104 105 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ 106 107 /* Work item for submitting workloads into work queue of GuC. */ 108 struct guc_wq_item { 109 u32 header; 110 u32 context_desc; 111 u32 submit_element_info; 112 u32 fence_id; 113 } __packed; 114 115 struct guc_process_desc { 116 u32 stage_id; 117 u64 db_base_addr; 118 u32 head; 119 u32 tail; 120 u32 error_offset; 121 u64 wq_base_addr; 122 u32 wq_size_bytes; 123 u32 wq_status; 124 u32 engine_presence; 125 u32 priority; 126 u32 reserved[30]; 127 } __packed; 128 129 /* engine id and context id is packed into guc_execlist_context.context_id*/ 130 #define GUC_ELC_CTXID_OFFSET 0 131 #define GUC_ELC_ENGINE_OFFSET 29 132 133 /* The execlist context including software and HW information */ 134 struct guc_execlist_context { 135 u32 context_desc; 136 u32 context_id; 137 u32 ring_status; 138 u32 ring_lrca; 139 u32 ring_begin; 140 u32 ring_end; 141 u32 ring_next_free_location; 142 u32 ring_current_tail_pointer_value; 143 u8 engine_state_submit_value; 144 u8 engine_state_wait_value; 145 u16 pagefault_count; 146 u16 engine_submit_queue_count; 147 } __packed; 148 149 /* 150 * This structure describes a stage set arranged for a particular communication 151 * between uKernel (GuC) and Driver (KMD). Technically, this is known as a 152 * "GuC Context descriptor" in the specs, but we use the term "stage descriptor" 153 * to avoid confusion with all the other things already named "context" in the 154 * driver. A static pool of these descriptors are stored inside a GEM object 155 * (stage_desc_pool) which is held for the entire lifetime of our interaction 156 * with the GuC, being allocated before the GuC is loaded with its firmware. 157 */ 158 struct guc_stage_desc { 159 u32 sched_common_area; 160 u32 stage_id; 161 u32 pas_id; 162 u8 engines_used; 163 u64 db_trigger_cpu; 164 u32 db_trigger_uk; 165 u64 db_trigger_phy; 166 u16 db_id; 167 168 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM]; 169 170 u8 attribute; 171 172 u32 priority; 173 174 u32 wq_sampled_tail_offset; 175 u32 wq_total_submit_enqueues; 176 177 u32 process_desc; 178 u32 wq_addr; 179 u32 wq_size; 180 181 u32 engine_presence; 182 183 u8 engine_suspended; 184 185 u8 reserved0[3]; 186 u64 reserved1[1]; 187 188 u64 desc_private; 189 } __packed; 190 191 /** 192 * DOC: CTB based communication 193 * 194 * The CTB (command transport buffer) communication between Host and GuC 195 * is based on u32 data stream written to the shared buffer. One buffer can 196 * be used to transmit data only in one direction (one-directional channel). 197 * 198 * Current status of the each buffer is stored in the buffer descriptor. 199 * Buffer descriptor holds tail and head fields that represents active data 200 * stream. The tail field is updated by the data producer (sender), and head 201 * field is updated by the data consumer (receiver):: 202 * 203 * +------------+ 204 * | DESCRIPTOR | +=================+============+========+ 205 * +============+ | | MESSAGE(s) | | 206 * | address |--------->+=================+============+========+ 207 * +------------+ 208 * | head | ^-----head--------^ 209 * +------------+ 210 * | tail | ^---------tail-----------------^ 211 * +------------+ 212 * | size | ^---------------size--------------------^ 213 * +------------+ 214 * 215 * Each message in data stream starts with the single u32 treated as a header, 216 * followed by optional set of u32 data that makes message specific payload:: 217 * 218 * +------------+---------+---------+---------+ 219 * | MESSAGE | 220 * +------------+---------+---------+---------+ 221 * | msg[0] | [1] | ... | [n-1] | 222 * +------------+---------+---------+---------+ 223 * | MESSAGE | MESSAGE PAYLOAD | 224 * + HEADER +---------+---------+---------+ 225 * | | 0 | ... | n | 226 * +======+=====+=========+=========+=========+ 227 * | 31:16| code| | | | 228 * +------+-----+ | | | 229 * | 15:5|flags| | | | 230 * +------+-----+ | | | 231 * | 4:0| len| | | | 232 * +------+-----+---------+---------+---------+ 233 * 234 * ^-------------len-------------^ 235 * 236 * The message header consists of: 237 * 238 * - **len**, indicates length of the message payload (in u32) 239 * - **code**, indicates message code 240 * - **flags**, holds various bits to control message handling 241 */ 242 243 /* 244 * Describes single command transport buffer. 245 * Used by both guc-master and clients. 246 */ 247 struct guc_ct_buffer_desc { 248 u32 addr; /* gfx address */ 249 u64 host_private; /* host private data */ 250 u32 size; /* size in bytes */ 251 u32 head; /* offset updated by GuC*/ 252 u32 tail; /* offset updated by owner */ 253 u32 is_in_error; /* error indicator */ 254 u32 fence; /* fence updated by GuC */ 255 u32 status; /* status updated by GuC */ 256 u32 owner; /* id of the channel owner */ 257 u32 owner_sub_id; /* owner-defined field for extra tracking */ 258 u32 reserved[5]; 259 } __packed; 260 261 /* Type of command transport buffer */ 262 #define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u 263 #define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u 264 265 /* 266 * Definition of the command transport message header (DW0) 267 * 268 * bit[4..0] message len (in dwords) 269 * bit[7..5] reserved 270 * bit[8] response (G2H only) 271 * bit[8] write fence to desc (H2G only) 272 * bit[9] write status to H2G buff (H2G only) 273 * bit[10] send status back via G2H (H2G only) 274 * bit[15..11] reserved 275 * bit[31..16] action code 276 */ 277 #define GUC_CT_MSG_LEN_SHIFT 0 278 #define GUC_CT_MSG_LEN_MASK 0x1F 279 #define GUC_CT_MSG_IS_RESPONSE (1 << 8) 280 #define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8) 281 #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9) 282 #define GUC_CT_MSG_SEND_STATUS (1 << 10) 283 #define GUC_CT_MSG_ACTION_SHIFT 16 284 #define GUC_CT_MSG_ACTION_MASK 0xFFFF 285 286 #define GUC_FORCEWAKE_RENDER (1 << 0) 287 #define GUC_FORCEWAKE_MEDIA (1 << 1) 288 289 #define GUC_POWER_UNSPECIFIED 0 290 #define GUC_POWER_D0 1 291 #define GUC_POWER_D1 2 292 #define GUC_POWER_D2 3 293 #define GUC_POWER_D3 4 294 295 /* Scheduling policy settings */ 296 297 /* Reset engine upon preempt failure */ 298 #define POLICY_RESET_ENGINE (1<<0) 299 /* Preempt to idle on quantum expiry */ 300 #define POLICY_PREEMPT_TO_IDLE (1<<1) 301 302 #define POLICY_MAX_NUM_WI 15 303 #define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000 304 #define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000 305 #define POLICY_DEFAULT_PREEMPTION_TIME_US 500000 306 #define POLICY_DEFAULT_FAULT_TIME_US 250000 307 308 struct guc_policy { 309 /* Time for one workload to execute. (in micro seconds) */ 310 u32 execution_quantum; 311 /* Time to wait for a preemption request to completed before issuing a 312 * reset. (in micro seconds). */ 313 u32 preemption_time; 314 /* How much time to allow to run after the first fault is observed. 315 * Then preempt afterwards. (in micro seconds) */ 316 u32 fault_time; 317 u32 policy_flags; 318 u32 reserved[8]; 319 } __packed; 320 321 struct guc_policies { 322 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES]; 323 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES]; 324 /* In micro seconds. How much time to allow before DPC processing is 325 * called back via interrupt (to prevent DPC queue drain starving). 326 * Typically 1000s of micro seconds (example only, not granularity). */ 327 u32 dpc_promote_time; 328 329 /* Must be set to take these new values. */ 330 u32 is_valid; 331 332 /* Max number of WIs to process per call. A large value may keep CS 333 * idle. */ 334 u32 max_num_work_items; 335 336 u32 reserved[4]; 337 } __packed; 338 339 /* GuC MMIO reg state struct */ 340 341 342 #define GUC_REGSET_MAX_REGISTERS 64 343 #define GUC_S3_SAVE_SPACE_PAGES 10 344 345 struct guc_mmio_reg { 346 u32 offset; 347 u32 value; 348 u32 flags; 349 #define GUC_REGSET_MASKED (1 << 0) 350 } __packed; 351 352 struct guc_mmio_regset { 353 struct guc_mmio_reg registers[GUC_REGSET_MAX_REGISTERS]; 354 u32 values_valid; 355 u32 number_of_registers; 356 } __packed; 357 358 /* GuC register sets */ 359 struct guc_mmio_reg_state { 360 struct guc_mmio_regset engine_reg[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 361 u32 reserved[98]; 362 } __packed; 363 364 /* HW info */ 365 struct guc_gt_system_info { 366 u32 slice_enabled; 367 u32 rcs_enabled; 368 u32 reserved0; 369 u32 bcs_enabled; 370 u32 vdbox_enable_mask; 371 u32 vdbox_sfc_support_mask; 372 u32 vebox_enable_mask; 373 u32 reserved[9]; 374 } __packed; 375 376 /* Clients info */ 377 struct guc_ct_pool_entry { 378 struct guc_ct_buffer_desc desc; 379 u32 reserved[7]; 380 } __packed; 381 382 #define GUC_CT_POOL_SIZE 2 383 384 struct guc_clients_info { 385 u32 clients_num; 386 u32 reserved0[13]; 387 u32 ct_pool_addr; 388 u32 ct_pool_count; 389 u32 reserved[4]; 390 } __packed; 391 392 /* GuC Additional Data Struct */ 393 struct guc_ads { 394 u32 reg_state_addr; 395 u32 reg_state_buffer; 396 u32 scheduler_policies; 397 u32 gt_system_info; 398 u32 clients_info; 399 u32 control_data; 400 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES]; 401 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES]; 402 u32 reserved[16]; 403 } __packed; 404 405 /* GuC logging structures */ 406 407 enum guc_log_buffer_type { 408 GUC_ISR_LOG_BUFFER, 409 GUC_DPC_LOG_BUFFER, 410 GUC_CRASH_DUMP_LOG_BUFFER, 411 GUC_MAX_LOG_BUFFER 412 }; 413 414 /** 415 * struct guc_log_buffer_state - GuC log buffer state 416 * 417 * Below state structure is used for coordination of retrieval of GuC firmware 418 * logs. Separate state is maintained for each log buffer type. 419 * read_ptr points to the location where i915 read last in log buffer and 420 * is read only for GuC firmware. write_ptr is incremented by GuC with number 421 * of bytes written for each log entry and is read only for i915. 422 * When any type of log buffer becomes half full, GuC sends a flush interrupt. 423 * GuC firmware expects that while it is writing to 2nd half of the buffer, 424 * first half would get consumed by Host and then get a flush completed 425 * acknowledgment from Host, so that it does not end up doing any overwrite 426 * causing loss of logs. So when buffer gets half filled & i915 has requested 427 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr 428 * to the value of write_ptr and raise the interrupt. 429 * On receiving the interrupt i915 should read the buffer, clear flush_to_file 430 * field and also update read_ptr with the value of sample_write_ptr, before 431 * sending an acknowledgment to GuC. marker & version fields are for internal 432 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every 433 * time GuC detects the log buffer overflow. 434 */ 435 struct guc_log_buffer_state { 436 u32 marker[2]; 437 u32 read_ptr; 438 u32 write_ptr; 439 u32 size; 440 u32 sampled_write_ptr; 441 union { 442 struct { 443 u32 flush_to_file:1; 444 u32 buffer_full_cnt:4; 445 u32 reserved:27; 446 }; 447 u32 flags; 448 }; 449 u32 version; 450 } __packed; 451 452 struct guc_ctx_report { 453 u32 report_return_status; 454 u32 reserved1[64]; 455 u32 affected_count; 456 u32 reserved2[2]; 457 } __packed; 458 459 /* GuC Shared Context Data Struct */ 460 struct guc_shared_ctx_data { 461 u32 addr_of_last_preempted_data_low; 462 u32 addr_of_last_preempted_data_high; 463 u32 addr_of_last_preempted_data_high_tmp; 464 u32 padding; 465 u32 is_mapped_to_proxy; 466 u32 proxy_ctx_id; 467 u32 engine_reset_ctx_id; 468 u32 media_reset_count; 469 u32 reserved1[8]; 470 u32 uk_last_ctx_switch_reason; 471 u32 was_reset; 472 u32 lrca_gpu_addr; 473 u64 execlist_ctx; 474 u32 reserved2[66]; 475 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM]; 476 } __packed; 477 478 /** 479 * DOC: MMIO based communication 480 * 481 * The MMIO based communication between Host and GuC uses software scratch 482 * registers, where first register holds data treated as message header, 483 * and other registers are used to hold message payload. 484 * 485 * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8, 486 * but no H2G command takes more than 8 parameters and the GuC FW 487 * itself uses an 8-element array to store the H2G message. 488 * 489 * +-----------+---------+---------+---------+ 490 * | MMIO[0] | MMIO[1] | ... | MMIO[n] | 491 * +-----------+---------+---------+---------+ 492 * | header | optional payload | 493 * +======+====+=========+=========+=========+ 494 * | 31:28|type| | | | 495 * +------+----+ | | | 496 * | 27:16|data| | | | 497 * +------+----+ | | | 498 * | 15:0|code| | | | 499 * +------+----+---------+---------+---------+ 500 * 501 * The message header consists of: 502 * 503 * - **type**, indicates message type 504 * - **code**, indicates message code, is specific for **type** 505 * - **data**, indicates message data, optional, depends on **code** 506 * 507 * The following message **types** are supported: 508 * 509 * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code 510 * must be priovided in **code** field. Optional action specific parameters 511 * can be provided in remaining payload registers or **data** field. 512 * 513 * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request, 514 * action response status will be provided in **code** field. Optional 515 * response data can be returned in remaining payload registers or **data** 516 * field. 517 */ 518 519 #define GUC_MAX_MMIO_MSG_LEN 8 520 521 #define INTEL_GUC_MSG_TYPE_SHIFT 28 522 #define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT) 523 #define INTEL_GUC_MSG_DATA_SHIFT 16 524 #define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT) 525 #define INTEL_GUC_MSG_CODE_SHIFT 0 526 #define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT) 527 528 #define __INTEL_GUC_MSG_GET(T, m) \ 529 (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT) 530 #define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m) 531 #define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m) 532 #define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m) 533 534 enum intel_guc_msg_type { 535 INTEL_GUC_MSG_TYPE_REQUEST = 0x0, 536 INTEL_GUC_MSG_TYPE_RESPONSE = 0xF, 537 }; 538 539 #define __INTEL_GUC_MSG_TYPE_IS(T, m) \ 540 (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T) 541 #define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m) 542 #define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m) 543 544 enum intel_guc_action { 545 INTEL_GUC_ACTION_DEFAULT = 0x0, 546 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2, 547 INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3, 548 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10, 549 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, 550 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30, 551 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302, 552 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, 553 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, 554 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, 555 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005, 556 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, 557 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, 558 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506, 559 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000, 560 INTEL_GUC_ACTION_LIMIT 561 }; 562 563 enum intel_guc_preempt_options { 564 INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4, 565 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8, 566 }; 567 568 enum intel_guc_report_status { 569 INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0, 570 INTEL_GUC_REPORT_STATUS_ACKED = 0x1, 571 INTEL_GUC_REPORT_STATUS_ERROR = 0x2, 572 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4, 573 }; 574 575 enum intel_guc_sleep_state_status { 576 INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1, 577 INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2, 578 INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3 579 #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000 580 }; 581 582 #define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0) 583 #define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4 584 #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT) 585 #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8) 586 587 enum intel_guc_response_status { 588 INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0, 589 INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000, 590 }; 591 592 #define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \ 593 (typecheck(u32, (m)) && \ 594 ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \ 595 ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \ 596 (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT))) 597 598 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ 599 enum intel_guc_recv_message { 600 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), 601 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3) 602 }; 603 604 #endif 605