1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Brad Volkin <bradley.d.volkin@intel.com> 25 * 26 */ 27 28 #include "gt/intel_engine.h" 29 30 #include "i915_drv.h" 31 #include "i915_memcpy.h" 32 33 /** 34 * DOC: batch buffer command parser 35 * 36 * Motivation: 37 * Certain OpenGL features (e.g. transform feedback, performance monitoring) 38 * require userspace code to submit batches containing commands such as 39 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some 40 * generations of the hardware will noop these commands in "unsecure" batches 41 * (which includes all userspace batches submitted via i915) even though the 42 * commands may be safe and represent the intended programming model of the 43 * device. 44 * 45 * The software command parser is similar in operation to the command parsing 46 * done in hardware for unsecure batches. However, the software parser allows 47 * some operations that would be noop'd by hardware, if the parser determines 48 * the operation is safe, and submits the batch as "secure" to prevent hardware 49 * parsing. 50 * 51 * Threats: 52 * At a high level, the hardware (and software) checks attempt to prevent 53 * granting userspace undue privileges. There are three categories of privilege. 54 * 55 * First, commands which are explicitly defined as privileged or which should 56 * only be used by the kernel driver. The parser generally rejects such 57 * commands, though it may allow some from the drm master process. 58 * 59 * Second, commands which access registers. To support correct/enhanced 60 * userspace functionality, particularly certain OpenGL extensions, the parser 61 * provides a whitelist of registers which userspace may safely access (for both 62 * normal and drm master processes). 63 * 64 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). 65 * The parser always rejects such commands. 66 * 67 * The majority of the problematic commands fall in the MI_* range, with only a 68 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW). 69 * 70 * Implementation: 71 * Each engine maintains tables of commands and registers which the parser 72 * uses in scanning batch buffers submitted to that engine. 73 * 74 * Since the set of commands that the parser must check for is significantly 75 * smaller than the number of commands supported, the parser tables contain only 76 * those commands required by the parser. This generally works because command 77 * opcode ranges have standard command length encodings. So for commands that 78 * the parser does not need to check, it can easily skip them. This is 79 * implemented via a per-engine length decoding vfunc. 80 * 81 * Unfortunately, there are a number of commands that do not follow the standard 82 * length encoding for their opcode range, primarily amongst the MI_* commands. 83 * To handle this, the parser provides a way to define explicit "skip" entries 84 * in the per-engine command tables. 85 * 86 * Other command table entries map fairly directly to high level categories 87 * mentioned above: rejected, master-only, register whitelist. The parser 88 * implements a number of checks, including the privileged memory checks, via a 89 * general bitmasking mechanism. 90 */ 91 92 /* 93 * A command that requires special handling by the command parser. 94 */ 95 struct drm_i915_cmd_descriptor { 96 /* 97 * Flags describing how the command parser processes the command. 98 * 99 * CMD_DESC_FIXED: The command has a fixed length if this is set, 100 * a length mask if not set 101 * CMD_DESC_SKIP: The command is allowed but does not follow the 102 * standard length encoding for the opcode range in 103 * which it falls 104 * CMD_DESC_REJECT: The command is never allowed 105 * CMD_DESC_REGISTER: The command should be checked against the 106 * register whitelist for the appropriate ring 107 * CMD_DESC_MASTER: The command is allowed if the submitting process 108 * is the DRM master 109 */ 110 u32 flags; 111 #define CMD_DESC_FIXED (1<<0) 112 #define CMD_DESC_SKIP (1<<1) 113 #define CMD_DESC_REJECT (1<<2) 114 #define CMD_DESC_REGISTER (1<<3) 115 #define CMD_DESC_BITMASK (1<<4) 116 #define CMD_DESC_MASTER (1<<5) 117 118 /* 119 * The command's unique identification bits and the bitmask to get them. 120 * This isn't strictly the opcode field as defined in the spec and may 121 * also include type, subtype, and/or subop fields. 122 */ 123 struct { 124 u32 value; 125 u32 mask; 126 } cmd; 127 128 /* 129 * The command's length. The command is either fixed length (i.e. does 130 * not include a length field) or has a length field mask. The flag 131 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 132 * a length mask. All command entries in a command table must include 133 * length information. 134 */ 135 union { 136 u32 fixed; 137 u32 mask; 138 } length; 139 140 /* 141 * Describes where to find a register address in the command to check 142 * against the ring's register whitelist. Only valid if flags has the 143 * CMD_DESC_REGISTER bit set. 144 * 145 * A non-zero step value implies that the command may access multiple 146 * registers in sequence (e.g. LRI), in that case step gives the 147 * distance in dwords between individual offset fields. 148 */ 149 struct { 150 u32 offset; 151 u32 mask; 152 u32 step; 153 } reg; 154 155 #define MAX_CMD_DESC_BITMASKS 3 156 /* 157 * Describes command checks where a particular dword is masked and 158 * compared against an expected value. If the command does not match 159 * the expected value, the parser rejects it. Only valid if flags has 160 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 161 * are valid. 162 * 163 * If the check specifies a non-zero condition_mask then the parser 164 * only performs the check when the bits specified by condition_mask 165 * are non-zero. 166 */ 167 struct { 168 u32 offset; 169 u32 mask; 170 u32 expected; 171 u32 condition_offset; 172 u32 condition_mask; 173 } bits[MAX_CMD_DESC_BITMASKS]; 174 }; 175 176 /* 177 * A table of commands requiring special handling by the command parser. 178 * 179 * Each engine has an array of tables. Each table consists of an array of 180 * command descriptors, which must be sorted with command opcodes in 181 * ascending order. 182 */ 183 struct drm_i915_cmd_table { 184 const struct drm_i915_cmd_descriptor *table; 185 int count; 186 }; 187 188 #define STD_MI_OPCODE_SHIFT (32 - 9) 189 #define STD_3D_OPCODE_SHIFT (32 - 16) 190 #define STD_2D_OPCODE_SHIFT (32 - 10) 191 #define STD_MFX_OPCODE_SHIFT (32 - 16) 192 #define MIN_OPCODE_SHIFT 16 193 194 #define CMD(op, opm, f, lm, fl, ...) \ 195 { \ 196 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ 197 .cmd = { (op), ~0u << (opm) }, \ 198 .length = { (lm) }, \ 199 __VA_ARGS__ \ 200 } 201 202 /* Convenience macros to compress the tables */ 203 #define SMI STD_MI_OPCODE_SHIFT 204 #define S3D STD_3D_OPCODE_SHIFT 205 #define S2D STD_2D_OPCODE_SHIFT 206 #define SMFX STD_MFX_OPCODE_SHIFT 207 #define F true 208 #define S CMD_DESC_SKIP 209 #define R CMD_DESC_REJECT 210 #define W CMD_DESC_REGISTER 211 #define B CMD_DESC_BITMASK 212 #define M CMD_DESC_MASTER 213 214 /* Command Mask Fixed Len Action 215 ---------------------------------------------------------- */ 216 static const struct drm_i915_cmd_descriptor common_cmds[] = { 217 CMD( MI_NOOP, SMI, F, 1, S ), 218 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), 219 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ), 220 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 221 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 222 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 223 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), 224 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), 225 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 226 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 227 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B, 228 .reg = { .offset = 1, .mask = 0x007FFFFC }, 229 .bits = {{ 230 .offset = 0, 231 .mask = MI_GLOBAL_GTT, 232 .expected = 0, 233 }}, ), 234 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B, 235 .reg = { .offset = 1, .mask = 0x007FFFFC }, 236 .bits = {{ 237 .offset = 0, 238 .mask = MI_GLOBAL_GTT, 239 .expected = 0, 240 }}, ), 241 /* 242 * MI_BATCH_BUFFER_START requires some special handling. It's not 243 * really a 'skip' action but it doesn't seem like it's worth adding 244 * a new action. See i915_parse_cmds(). 245 */ 246 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), 247 }; 248 249 static const struct drm_i915_cmd_descriptor render_cmds[] = { 250 CMD( MI_FLUSH, SMI, F, 1, S ), 251 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 252 CMD( MI_PREDICATE, SMI, F, 1, S ), 253 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), 254 CMD( MI_SET_APPID, SMI, F, 1, S ), 255 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 256 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), 257 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), 258 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, 259 .bits = {{ 260 .offset = 0, 261 .mask = MI_GLOBAL_GTT, 262 .expected = 0, 263 }}, ), 264 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), 265 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, 266 .bits = {{ 267 .offset = 0, 268 .mask = MI_GLOBAL_GTT, 269 .expected = 0, 270 }}, ), 271 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, 272 .bits = {{ 273 .offset = 1, 274 .mask = MI_REPORT_PERF_COUNT_GGTT, 275 .expected = 0, 276 }}, ), 277 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 278 .bits = {{ 279 .offset = 0, 280 .mask = MI_GLOBAL_GTT, 281 .expected = 0, 282 }}, ), 283 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), 284 CMD( PIPELINE_SELECT, S3D, F, 1, S ), 285 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, 286 .bits = {{ 287 .offset = 2, 288 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, 289 .expected = 0, 290 }}, ), 291 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), 292 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), 293 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), 294 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, 295 .bits = {{ 296 .offset = 1, 297 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), 298 .expected = 0, 299 }, 300 { 301 .offset = 1, 302 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | 303 PIPE_CONTROL_STORE_DATA_INDEX), 304 .expected = 0, 305 .condition_offset = 1, 306 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, 307 }}, ), 308 }; 309 310 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { 311 CMD( MI_SET_PREDICATE, SMI, F, 1, S ), 312 CMD( MI_RS_CONTROL, SMI, F, 1, S ), 313 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), 314 CMD( MI_SET_APPID, SMI, F, 1, S ), 315 CMD( MI_RS_CONTEXT, SMI, F, 1, S ), 316 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), 317 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 318 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W, 319 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), 320 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), 321 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), 322 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), 323 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), 324 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), 325 326 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), 327 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), 328 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), 329 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), 330 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), 331 }; 332 333 static const struct drm_i915_cmd_descriptor video_cmds[] = { 334 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 335 CMD( MI_SET_APPID, SMI, F, 1, S ), 336 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 337 .bits = {{ 338 .offset = 0, 339 .mask = MI_GLOBAL_GTT, 340 .expected = 0, 341 }}, ), 342 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 343 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 344 .bits = {{ 345 .offset = 0, 346 .mask = MI_FLUSH_DW_NOTIFY, 347 .expected = 0, 348 }, 349 { 350 .offset = 1, 351 .mask = MI_FLUSH_DW_USE_GTT, 352 .expected = 0, 353 .condition_offset = 0, 354 .condition_mask = MI_FLUSH_DW_OP_MASK, 355 }, 356 { 357 .offset = 0, 358 .mask = MI_FLUSH_DW_STORE_INDEX, 359 .expected = 0, 360 .condition_offset = 0, 361 .condition_mask = MI_FLUSH_DW_OP_MASK, 362 }}, ), 363 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 364 .bits = {{ 365 .offset = 0, 366 .mask = MI_GLOBAL_GTT, 367 .expected = 0, 368 }}, ), 369 /* 370 * MFX_WAIT doesn't fit the way we handle length for most commands. 371 * It has a length field but it uses a non-standard length bias. 372 * It is always 1 dword though, so just treat it as fixed length. 373 */ 374 CMD( MFX_WAIT, SMFX, F, 1, S ), 375 }; 376 377 static const struct drm_i915_cmd_descriptor vecs_cmds[] = { 378 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 379 CMD( MI_SET_APPID, SMI, F, 1, S ), 380 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 381 .bits = {{ 382 .offset = 0, 383 .mask = MI_GLOBAL_GTT, 384 .expected = 0, 385 }}, ), 386 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 387 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 388 .bits = {{ 389 .offset = 0, 390 .mask = MI_FLUSH_DW_NOTIFY, 391 .expected = 0, 392 }, 393 { 394 .offset = 1, 395 .mask = MI_FLUSH_DW_USE_GTT, 396 .expected = 0, 397 .condition_offset = 0, 398 .condition_mask = MI_FLUSH_DW_OP_MASK, 399 }, 400 { 401 .offset = 0, 402 .mask = MI_FLUSH_DW_STORE_INDEX, 403 .expected = 0, 404 .condition_offset = 0, 405 .condition_mask = MI_FLUSH_DW_OP_MASK, 406 }}, ), 407 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 408 .bits = {{ 409 .offset = 0, 410 .mask = MI_GLOBAL_GTT, 411 .expected = 0, 412 }}, ), 413 }; 414 415 static const struct drm_i915_cmd_descriptor blt_cmds[] = { 416 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 417 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, 418 .bits = {{ 419 .offset = 0, 420 .mask = MI_GLOBAL_GTT, 421 .expected = 0, 422 }}, ), 423 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 424 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 425 .bits = {{ 426 .offset = 0, 427 .mask = MI_FLUSH_DW_NOTIFY, 428 .expected = 0, 429 }, 430 { 431 .offset = 1, 432 .mask = MI_FLUSH_DW_USE_GTT, 433 .expected = 0, 434 .condition_offset = 0, 435 .condition_mask = MI_FLUSH_DW_OP_MASK, 436 }, 437 { 438 .offset = 0, 439 .mask = MI_FLUSH_DW_STORE_INDEX, 440 .expected = 0, 441 .condition_offset = 0, 442 .condition_mask = MI_FLUSH_DW_OP_MASK, 443 }}, ), 444 CMD( COLOR_BLT, S2D, !F, 0x3F, S ), 445 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), 446 }; 447 448 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { 449 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), 450 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 451 }; 452 453 static const struct drm_i915_cmd_descriptor noop_desc = 454 CMD(MI_NOOP, SMI, F, 1, S); 455 456 #undef CMD 457 #undef SMI 458 #undef S3D 459 #undef S2D 460 #undef SMFX 461 #undef F 462 #undef S 463 #undef R 464 #undef W 465 #undef B 466 #undef M 467 468 static const struct drm_i915_cmd_table gen7_render_cmds[] = { 469 { common_cmds, ARRAY_SIZE(common_cmds) }, 470 { render_cmds, ARRAY_SIZE(render_cmds) }, 471 }; 472 473 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = { 474 { common_cmds, ARRAY_SIZE(common_cmds) }, 475 { render_cmds, ARRAY_SIZE(render_cmds) }, 476 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, 477 }; 478 479 static const struct drm_i915_cmd_table gen7_video_cmds[] = { 480 { common_cmds, ARRAY_SIZE(common_cmds) }, 481 { video_cmds, ARRAY_SIZE(video_cmds) }, 482 }; 483 484 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = { 485 { common_cmds, ARRAY_SIZE(common_cmds) }, 486 { vecs_cmds, ARRAY_SIZE(vecs_cmds) }, 487 }; 488 489 static const struct drm_i915_cmd_table gen7_blt_cmds[] = { 490 { common_cmds, ARRAY_SIZE(common_cmds) }, 491 { blt_cmds, ARRAY_SIZE(blt_cmds) }, 492 }; 493 494 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = { 495 { common_cmds, ARRAY_SIZE(common_cmds) }, 496 { blt_cmds, ARRAY_SIZE(blt_cmds) }, 497 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, 498 }; 499 500 /* 501 * Register whitelists, sorted by increasing register offset. 502 */ 503 504 /* 505 * An individual whitelist entry granting access to register addr. If 506 * mask is non-zero the argument of immediate register writes will be 507 * AND-ed with mask, and the command will be rejected if the result 508 * doesn't match value. 509 * 510 * Registers with non-zero mask are only allowed to be written using 511 * LRI. 512 */ 513 struct drm_i915_reg_descriptor { 514 i915_reg_t addr; 515 u32 mask; 516 u32 value; 517 }; 518 519 /* Convenience macro for adding 32-bit registers. */ 520 #define REG32(_reg, ...) \ 521 { .addr = (_reg), __VA_ARGS__ } 522 523 /* 524 * Convenience macro for adding 64-bit registers. 525 * 526 * Some registers that userspace accesses are 64 bits. The register 527 * access commands only allow 32-bit accesses. Hence, we have to include 528 * entries for both halves of the 64-bit registers. 529 */ 530 #define REG64(_reg) \ 531 { .addr = _reg }, \ 532 { .addr = _reg ## _UDW } 533 534 #define REG64_IDX(_reg, idx) \ 535 { .addr = _reg(idx) }, \ 536 { .addr = _reg ## _UDW(idx) } 537 538 static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 539 REG64(GPGPU_THREADS_DISPATCHED), 540 REG64(HS_INVOCATION_COUNT), 541 REG64(DS_INVOCATION_COUNT), 542 REG64(IA_VERTICES_COUNT), 543 REG64(IA_PRIMITIVES_COUNT), 544 REG64(VS_INVOCATION_COUNT), 545 REG64(GS_INVOCATION_COUNT), 546 REG64(GS_PRIMITIVES_COUNT), 547 REG64(CL_INVOCATION_COUNT), 548 REG64(CL_PRIMITIVES_COUNT), 549 REG64(PS_INVOCATION_COUNT), 550 REG64(PS_DEPTH_COUNT), 551 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 552 REG64(MI_PREDICATE_SRC0), 553 REG64(MI_PREDICATE_SRC1), 554 REG32(GEN7_3DPRIM_END_OFFSET), 555 REG32(GEN7_3DPRIM_START_VERTEX), 556 REG32(GEN7_3DPRIM_VERTEX_COUNT), 557 REG32(GEN7_3DPRIM_INSTANCE_COUNT), 558 REG32(GEN7_3DPRIM_START_INSTANCE), 559 REG32(GEN7_3DPRIM_BASE_VERTEX), 560 REG32(GEN7_GPGPU_DISPATCHDIMX), 561 REG32(GEN7_GPGPU_DISPATCHDIMY), 562 REG32(GEN7_GPGPU_DISPATCHDIMZ), 563 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 564 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0), 565 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1), 566 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2), 567 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3), 568 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0), 569 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1), 570 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2), 571 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3), 572 REG32(GEN7_SO_WRITE_OFFSET(0)), 573 REG32(GEN7_SO_WRITE_OFFSET(1)), 574 REG32(GEN7_SO_WRITE_OFFSET(2)), 575 REG32(GEN7_SO_WRITE_OFFSET(3)), 576 REG32(GEN7_L3SQCREG1), 577 REG32(GEN7_L3CNTLREG2), 578 REG32(GEN7_L3CNTLREG3), 579 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 580 }; 581 582 static const struct drm_i915_reg_descriptor hsw_render_regs[] = { 583 REG64_IDX(HSW_CS_GPR, 0), 584 REG64_IDX(HSW_CS_GPR, 1), 585 REG64_IDX(HSW_CS_GPR, 2), 586 REG64_IDX(HSW_CS_GPR, 3), 587 REG64_IDX(HSW_CS_GPR, 4), 588 REG64_IDX(HSW_CS_GPR, 5), 589 REG64_IDX(HSW_CS_GPR, 6), 590 REG64_IDX(HSW_CS_GPR, 7), 591 REG64_IDX(HSW_CS_GPR, 8), 592 REG64_IDX(HSW_CS_GPR, 9), 593 REG64_IDX(HSW_CS_GPR, 10), 594 REG64_IDX(HSW_CS_GPR, 11), 595 REG64_IDX(HSW_CS_GPR, 12), 596 REG64_IDX(HSW_CS_GPR, 13), 597 REG64_IDX(HSW_CS_GPR, 14), 598 REG64_IDX(HSW_CS_GPR, 15), 599 REG32(HSW_SCRATCH1, 600 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, 601 .value = 0), 602 REG32(HSW_ROW_CHICKEN3, 603 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 | 604 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 605 .value = 0), 606 }; 607 608 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = { 609 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 610 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 611 REG32(BCS_SWCTRL), 612 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 613 }; 614 615 static const struct drm_i915_reg_descriptor ivb_master_regs[] = { 616 REG32(FORCEWAKE_MT), 617 REG32(DERRMR), 618 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)), 619 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)), 620 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)), 621 }; 622 623 static const struct drm_i915_reg_descriptor hsw_master_regs[] = { 624 REG32(FORCEWAKE_MT), 625 REG32(DERRMR), 626 }; 627 628 #undef REG64 629 #undef REG32 630 631 struct drm_i915_reg_table { 632 const struct drm_i915_reg_descriptor *regs; 633 int num_regs; 634 bool master; 635 }; 636 637 static const struct drm_i915_reg_table ivb_render_reg_tables[] = { 638 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false }, 639 { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true }, 640 }; 641 642 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = { 643 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false }, 644 { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true }, 645 }; 646 647 static const struct drm_i915_reg_table hsw_render_reg_tables[] = { 648 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false }, 649 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false }, 650 { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true }, 651 }; 652 653 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = { 654 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false }, 655 { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true }, 656 }; 657 658 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) 659 { 660 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 661 u32 subclient = 662 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 663 664 if (client == INSTR_MI_CLIENT) 665 return 0x3F; 666 else if (client == INSTR_RC_CLIENT) { 667 if (subclient == INSTR_MEDIA_SUBCLIENT) 668 return 0xFFFF; 669 else 670 return 0xFF; 671 } 672 673 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); 674 return 0; 675 } 676 677 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) 678 { 679 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 680 u32 subclient = 681 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 682 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT; 683 684 if (client == INSTR_MI_CLIENT) 685 return 0x3F; 686 else if (client == INSTR_RC_CLIENT) { 687 if (subclient == INSTR_MEDIA_SUBCLIENT) { 688 if (op == 6) 689 return 0xFFFF; 690 else 691 return 0xFFF; 692 } else 693 return 0xFF; 694 } 695 696 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); 697 return 0; 698 } 699 700 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) 701 { 702 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 703 704 if (client == INSTR_MI_CLIENT) 705 return 0x3F; 706 else if (client == INSTR_BC_CLIENT) 707 return 0xFF; 708 709 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 710 return 0; 711 } 712 713 static bool validate_cmds_sorted(const struct intel_engine_cs *engine, 714 const struct drm_i915_cmd_table *cmd_tables, 715 int cmd_table_count) 716 { 717 int i; 718 bool ret = true; 719 720 if (!cmd_tables || cmd_table_count == 0) 721 return true; 722 723 for (i = 0; i < cmd_table_count; i++) { 724 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 725 u32 previous = 0; 726 int j; 727 728 for (j = 0; j < table->count; j++) { 729 const struct drm_i915_cmd_descriptor *desc = 730 &table->table[j]; 731 u32 curr = desc->cmd.value & desc->cmd.mask; 732 733 if (curr < previous) { 734 DRM_ERROR("CMD: %s [%d] command table not sorted: " 735 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n", 736 engine->name, engine->id, 737 i, j, curr, previous); 738 ret = false; 739 } 740 741 previous = curr; 742 } 743 } 744 745 return ret; 746 } 747 748 static bool check_sorted(const struct intel_engine_cs *engine, 749 const struct drm_i915_reg_descriptor *reg_table, 750 int reg_count) 751 { 752 int i; 753 u32 previous = 0; 754 bool ret = true; 755 756 for (i = 0; i < reg_count; i++) { 757 u32 curr = i915_mmio_reg_offset(reg_table[i].addr); 758 759 if (curr < previous) { 760 DRM_ERROR("CMD: %s [%d] register table not sorted: " 761 "entry=%d reg=0x%08X prev=0x%08X\n", 762 engine->name, engine->id, 763 i, curr, previous); 764 ret = false; 765 } 766 767 previous = curr; 768 } 769 770 return ret; 771 } 772 773 static bool validate_regs_sorted(struct intel_engine_cs *engine) 774 { 775 int i; 776 const struct drm_i915_reg_table *table; 777 778 for (i = 0; i < engine->reg_table_count; i++) { 779 table = &engine->reg_tables[i]; 780 if (!check_sorted(engine, table->regs, table->num_regs)) 781 return false; 782 } 783 784 return true; 785 } 786 787 struct cmd_node { 788 const struct drm_i915_cmd_descriptor *desc; 789 struct hlist_node node; 790 }; 791 792 /* 793 * Different command ranges have different numbers of bits for the opcode. For 794 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The 795 * problem is that, for example, MI commands use bits 22:16 for other fields 796 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when 797 * we mask a command from a batch it could hash to the wrong bucket due to 798 * non-opcode bits being set. But if we don't include those bits, some 3D 799 * commands may hash to the same bucket due to not including opcode bits that 800 * make the command unique. For now, we will risk hashing to the same bucket. 801 */ 802 static inline u32 cmd_header_key(u32 x) 803 { 804 switch (x >> INSTR_CLIENT_SHIFT) { 805 default: 806 case INSTR_MI_CLIENT: 807 return x >> STD_MI_OPCODE_SHIFT; 808 case INSTR_RC_CLIENT: 809 return x >> STD_3D_OPCODE_SHIFT; 810 case INSTR_BC_CLIENT: 811 return x >> STD_2D_OPCODE_SHIFT; 812 } 813 } 814 815 static int init_hash_table(struct intel_engine_cs *engine, 816 const struct drm_i915_cmd_table *cmd_tables, 817 int cmd_table_count) 818 { 819 int i, j; 820 821 hash_init(engine->cmd_hash); 822 823 for (i = 0; i < cmd_table_count; i++) { 824 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 825 826 for (j = 0; j < table->count; j++) { 827 const struct drm_i915_cmd_descriptor *desc = 828 &table->table[j]; 829 struct cmd_node *desc_node = 830 kmalloc(sizeof(*desc_node), GFP_KERNEL); 831 832 if (!desc_node) 833 return -ENOMEM; 834 835 desc_node->desc = desc; 836 hash_add(engine->cmd_hash, &desc_node->node, 837 cmd_header_key(desc->cmd.value)); 838 } 839 } 840 841 return 0; 842 } 843 844 static void fini_hash_table(struct intel_engine_cs *engine) 845 { 846 struct hlist_node *tmp; 847 struct cmd_node *desc_node; 848 int i; 849 850 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) { 851 hash_del(&desc_node->node); 852 kfree(desc_node); 853 } 854 } 855 856 /** 857 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine 858 * @engine: the engine to initialize 859 * 860 * Optionally initializes fields related to batch buffer command parsing in the 861 * struct intel_engine_cs based on whether the platform requires software 862 * command parsing. 863 */ 864 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine) 865 { 866 const struct drm_i915_cmd_table *cmd_tables; 867 int cmd_table_count; 868 int ret; 869 870 if (!IS_GEN(engine->i915, 7)) 871 return; 872 873 switch (engine->class) { 874 case RENDER_CLASS: 875 if (IS_HASWELL(engine->i915)) { 876 cmd_tables = hsw_render_ring_cmds; 877 cmd_table_count = 878 ARRAY_SIZE(hsw_render_ring_cmds); 879 } else { 880 cmd_tables = gen7_render_cmds; 881 cmd_table_count = ARRAY_SIZE(gen7_render_cmds); 882 } 883 884 if (IS_HASWELL(engine->i915)) { 885 engine->reg_tables = hsw_render_reg_tables; 886 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables); 887 } else { 888 engine->reg_tables = ivb_render_reg_tables; 889 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables); 890 } 891 892 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask; 893 break; 894 case VIDEO_DECODE_CLASS: 895 cmd_tables = gen7_video_cmds; 896 cmd_table_count = ARRAY_SIZE(gen7_video_cmds); 897 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 898 break; 899 case COPY_ENGINE_CLASS: 900 if (IS_HASWELL(engine->i915)) { 901 cmd_tables = hsw_blt_ring_cmds; 902 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds); 903 } else { 904 cmd_tables = gen7_blt_cmds; 905 cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); 906 } 907 908 if (IS_HASWELL(engine->i915)) { 909 engine->reg_tables = hsw_blt_reg_tables; 910 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables); 911 } else { 912 engine->reg_tables = ivb_blt_reg_tables; 913 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables); 914 } 915 916 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; 917 break; 918 case VIDEO_ENHANCEMENT_CLASS: 919 cmd_tables = hsw_vebox_cmds; 920 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds); 921 /* VECS can use the same length_mask function as VCS */ 922 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 923 break; 924 default: 925 MISSING_CASE(engine->class); 926 return; 927 } 928 929 if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) { 930 DRM_ERROR("%s: command descriptions are not sorted\n", 931 engine->name); 932 return; 933 } 934 if (!validate_regs_sorted(engine)) { 935 DRM_ERROR("%s: registers are not sorted\n", engine->name); 936 return; 937 } 938 939 ret = init_hash_table(engine, cmd_tables, cmd_table_count); 940 if (ret) { 941 DRM_ERROR("%s: initialised failed!\n", engine->name); 942 fini_hash_table(engine); 943 return; 944 } 945 946 engine->flags |= I915_ENGINE_NEEDS_CMD_PARSER; 947 } 948 949 /** 950 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields 951 * @engine: the engine to clean up 952 * 953 * Releases any resources related to command parsing that may have been 954 * initialized for the specified engine. 955 */ 956 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine) 957 { 958 if (!intel_engine_needs_cmd_parser(engine)) 959 return; 960 961 fini_hash_table(engine); 962 } 963 964 static const struct drm_i915_cmd_descriptor* 965 find_cmd_in_table(struct intel_engine_cs *engine, 966 u32 cmd_header) 967 { 968 struct cmd_node *desc_node; 969 970 hash_for_each_possible(engine->cmd_hash, desc_node, node, 971 cmd_header_key(cmd_header)) { 972 const struct drm_i915_cmd_descriptor *desc = desc_node->desc; 973 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) 974 return desc; 975 } 976 977 return NULL; 978 } 979 980 /* 981 * Returns a pointer to a descriptor for the command specified by cmd_header. 982 * 983 * The caller must supply space for a default descriptor via the default_desc 984 * parameter. If no descriptor for the specified command exists in the engine's 985 * command parser tables, this function fills in default_desc based on the 986 * engine's default length encoding and returns default_desc. 987 */ 988 static const struct drm_i915_cmd_descriptor* 989 find_cmd(struct intel_engine_cs *engine, 990 u32 cmd_header, 991 const struct drm_i915_cmd_descriptor *desc, 992 struct drm_i915_cmd_descriptor *default_desc) 993 { 994 u32 mask; 995 996 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) 997 return desc; 998 999 desc = find_cmd_in_table(engine, cmd_header); 1000 if (desc) 1001 return desc; 1002 1003 mask = engine->get_cmd_length_mask(cmd_header); 1004 if (!mask) 1005 return NULL; 1006 1007 default_desc->cmd.value = cmd_header; 1008 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT; 1009 default_desc->length.mask = mask; 1010 default_desc->flags = CMD_DESC_SKIP; 1011 return default_desc; 1012 } 1013 1014 static const struct drm_i915_reg_descriptor * 1015 __find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr) 1016 { 1017 int start = 0, end = count; 1018 while (start < end) { 1019 int mid = start + (end - start) / 2; 1020 int ret = addr - i915_mmio_reg_offset(table[mid].addr); 1021 if (ret < 0) 1022 end = mid; 1023 else if (ret > 0) 1024 start = mid + 1; 1025 else 1026 return &table[mid]; 1027 } 1028 return NULL; 1029 } 1030 1031 static const struct drm_i915_reg_descriptor * 1032 find_reg(const struct intel_engine_cs *engine, bool is_master, u32 addr) 1033 { 1034 const struct drm_i915_reg_table *table = engine->reg_tables; 1035 int count = engine->reg_table_count; 1036 1037 for (; count > 0; ++table, --count) { 1038 if (!table->master || is_master) { 1039 const struct drm_i915_reg_descriptor *reg; 1040 1041 reg = __find_reg(table->regs, table->num_regs, addr); 1042 if (reg != NULL) 1043 return reg; 1044 } 1045 } 1046 1047 return NULL; 1048 } 1049 1050 /* Returns a vmap'd pointer to dst_obj, which the caller must unmap */ 1051 static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, 1052 struct drm_i915_gem_object *src_obj, 1053 u32 batch_start_offset, 1054 u32 batch_len, 1055 bool *needs_clflush_after) 1056 { 1057 unsigned int src_needs_clflush; 1058 unsigned int dst_needs_clflush; 1059 void *dst, *src; 1060 int ret; 1061 1062 ret = i915_gem_object_prepare_write(dst_obj, &dst_needs_clflush); 1063 if (ret) 1064 return ERR_PTR(ret); 1065 1066 dst = i915_gem_object_pin_map(dst_obj, I915_MAP_FORCE_WB); 1067 i915_gem_object_finish_access(dst_obj); 1068 if (IS_ERR(dst)) 1069 return dst; 1070 1071 ret = i915_gem_object_prepare_read(src_obj, &src_needs_clflush); 1072 if (ret) { 1073 i915_gem_object_unpin_map(dst_obj); 1074 return ERR_PTR(ret); 1075 } 1076 1077 src = ERR_PTR(-ENODEV); 1078 if (src_needs_clflush && 1079 i915_can_memcpy_from_wc(NULL, batch_start_offset, 0)) { 1080 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC); 1081 if (!IS_ERR(src)) { 1082 i915_memcpy_from_wc(dst, 1083 src + batch_start_offset, 1084 ALIGN(batch_len, 16)); 1085 i915_gem_object_unpin_map(src_obj); 1086 } 1087 } 1088 if (IS_ERR(src)) { 1089 void *ptr; 1090 int offset, n; 1091 1092 offset = offset_in_page(batch_start_offset); 1093 1094 /* We can avoid clflushing partial cachelines before the write 1095 * if we only every write full cache-lines. Since we know that 1096 * both the source and destination are in multiples of 1097 * PAGE_SIZE, we can simply round up to the next cacheline. 1098 * We don't care about copying too much here as we only 1099 * validate up to the end of the batch. 1100 */ 1101 if (dst_needs_clflush & CLFLUSH_BEFORE) 1102 batch_len = roundup(batch_len, 1103 boot_cpu_data.x86_clflush_size); 1104 1105 ptr = dst; 1106 for (n = batch_start_offset >> PAGE_SHIFT; batch_len; n++) { 1107 int len = min_t(int, batch_len, PAGE_SIZE - offset); 1108 1109 src = kmap_atomic(i915_gem_object_get_page(src_obj, n)); 1110 if (src_needs_clflush) 1111 drm_clflush_virt_range(src + offset, len); 1112 memcpy(ptr, src + offset, len); 1113 kunmap_atomic(src); 1114 1115 ptr += len; 1116 batch_len -= len; 1117 offset = 0; 1118 } 1119 } 1120 1121 i915_gem_object_finish_access(src_obj); 1122 1123 /* dst_obj is returned with vmap pinned */ 1124 *needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER; 1125 1126 return dst; 1127 } 1128 1129 static bool check_cmd(const struct intel_engine_cs *engine, 1130 const struct drm_i915_cmd_descriptor *desc, 1131 const u32 *cmd, u32 length, 1132 const bool is_master) 1133 { 1134 if (desc->flags & CMD_DESC_SKIP) 1135 return true; 1136 1137 if (desc->flags & CMD_DESC_REJECT) { 1138 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); 1139 return false; 1140 } 1141 1142 if ((desc->flags & CMD_DESC_MASTER) && !is_master) { 1143 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n", 1144 *cmd); 1145 return false; 1146 } 1147 1148 if (desc->flags & CMD_DESC_REGISTER) { 1149 /* 1150 * Get the distance between individual register offset 1151 * fields if the command can perform more than one 1152 * access at a time. 1153 */ 1154 const u32 step = desc->reg.step ? desc->reg.step : length; 1155 u32 offset; 1156 1157 for (offset = desc->reg.offset; offset < length; 1158 offset += step) { 1159 const u32 reg_addr = cmd[offset] & desc->reg.mask; 1160 const struct drm_i915_reg_descriptor *reg = 1161 find_reg(engine, is_master, reg_addr); 1162 1163 if (!reg) { 1164 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n", 1165 reg_addr, *cmd, engine->name); 1166 return false; 1167 } 1168 1169 /* 1170 * Check the value written to the register against the 1171 * allowed mask/value pair given in the whitelist entry. 1172 */ 1173 if (reg->mask) { 1174 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { 1175 DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n", 1176 reg_addr); 1177 return false; 1178 } 1179 1180 if (desc->cmd.value == MI_LOAD_REGISTER_REG) { 1181 DRM_DEBUG_DRIVER("CMD: Rejected LRR to masked register 0x%08X\n", 1182 reg_addr); 1183 return false; 1184 } 1185 1186 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) && 1187 (offset + 2 > length || 1188 (cmd[offset + 1] & reg->mask) != reg->value)) { 1189 DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n", 1190 reg_addr); 1191 return false; 1192 } 1193 } 1194 } 1195 } 1196 1197 if (desc->flags & CMD_DESC_BITMASK) { 1198 int i; 1199 1200 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { 1201 u32 dword; 1202 1203 if (desc->bits[i].mask == 0) 1204 break; 1205 1206 if (desc->bits[i].condition_mask != 0) { 1207 u32 offset = 1208 desc->bits[i].condition_offset; 1209 u32 condition = cmd[offset] & 1210 desc->bits[i].condition_mask; 1211 1212 if (condition == 0) 1213 continue; 1214 } 1215 1216 if (desc->bits[i].offset >= length) { 1217 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X, too short to check bitmask (%s)\n", 1218 *cmd, engine->name); 1219 return false; 1220 } 1221 1222 dword = cmd[desc->bits[i].offset] & 1223 desc->bits[i].mask; 1224 1225 if (dword != desc->bits[i].expected) { 1226 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n", 1227 *cmd, 1228 desc->bits[i].mask, 1229 desc->bits[i].expected, 1230 dword, engine->name); 1231 return false; 1232 } 1233 } 1234 } 1235 1236 return true; 1237 } 1238 1239 #define LENGTH_BIAS 2 1240 1241 /** 1242 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations 1243 * @engine: the engine on which the batch is to execute 1244 * @batch_obj: the batch buffer in question 1245 * @shadow_batch_obj: copy of the batch buffer in question 1246 * @batch_start_offset: byte offset in the batch at which execution starts 1247 * @batch_len: length of the commands in batch_obj 1248 * @is_master: is the submitting process the drm master? 1249 * 1250 * Parses the specified batch buffer looking for privilege violations as 1251 * described in the overview. 1252 * 1253 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES 1254 * if the batch appears legal but should use hardware parsing 1255 */ 1256 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1257 struct drm_i915_gem_object *batch_obj, 1258 struct drm_i915_gem_object *shadow_batch_obj, 1259 u32 batch_start_offset, 1260 u32 batch_len, 1261 bool is_master) 1262 { 1263 u32 *cmd, *batch_end; 1264 struct drm_i915_cmd_descriptor default_desc = noop_desc; 1265 const struct drm_i915_cmd_descriptor *desc = &default_desc; 1266 bool needs_clflush_after = false; 1267 int ret = 0; 1268 1269 cmd = copy_batch(shadow_batch_obj, batch_obj, 1270 batch_start_offset, batch_len, 1271 &needs_clflush_after); 1272 if (IS_ERR(cmd)) { 1273 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n"); 1274 return PTR_ERR(cmd); 1275 } 1276 1277 /* 1278 * We use the batch length as size because the shadow object is as 1279 * large or larger and copy_batch() will write MI_NOPs to the extra 1280 * space. Parsing should be faster in some cases this way. 1281 */ 1282 batch_end = cmd + (batch_len / sizeof(*batch_end)); 1283 do { 1284 u32 length; 1285 1286 if (*cmd == MI_BATCH_BUFFER_END) { 1287 if (needs_clflush_after) { 1288 void *ptr = page_mask_bits(shadow_batch_obj->mm.mapping); 1289 drm_clflush_virt_range(ptr, 1290 (void *)(cmd + 1) - ptr); 1291 } 1292 break; 1293 } 1294 1295 desc = find_cmd(engine, *cmd, desc, &default_desc); 1296 if (!desc) { 1297 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n", 1298 *cmd); 1299 ret = -EINVAL; 1300 break; 1301 } 1302 1303 /* 1304 * If the batch buffer contains a chained batch, return an 1305 * error that tells the caller to abort and dispatch the 1306 * workload as a non-secure batch. 1307 */ 1308 if (desc->cmd.value == MI_BATCH_BUFFER_START) { 1309 ret = -EACCES; 1310 break; 1311 } 1312 1313 if (desc->flags & CMD_DESC_FIXED) 1314 length = desc->length.fixed; 1315 else 1316 length = ((*cmd & desc->length.mask) + LENGTH_BIAS); 1317 1318 if ((batch_end - cmd) < length) { 1319 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", 1320 *cmd, 1321 length, 1322 batch_end - cmd); 1323 ret = -EINVAL; 1324 break; 1325 } 1326 1327 if (!check_cmd(engine, desc, cmd, length, is_master)) { 1328 ret = -EACCES; 1329 break; 1330 } 1331 1332 cmd += length; 1333 if (cmd >= batch_end) { 1334 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); 1335 ret = -EINVAL; 1336 break; 1337 } 1338 } while (1); 1339 1340 i915_gem_object_unpin_map(shadow_batch_obj); 1341 return ret; 1342 } 1343 1344 /** 1345 * i915_cmd_parser_get_version() - get the cmd parser version number 1346 * @dev_priv: i915 device private 1347 * 1348 * The cmd parser maintains a simple increasing integer version number suitable 1349 * for passing to userspace clients to determine what operations are permitted. 1350 * 1351 * Return: the current version number of the cmd parser 1352 */ 1353 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) 1354 { 1355 struct intel_engine_cs *engine; 1356 bool active = false; 1357 1358 /* If the command parser is not enabled, report 0 - unsupported */ 1359 for_each_uabi_engine(engine, dev_priv) { 1360 if (intel_engine_needs_cmd_parser(engine)) { 1361 active = true; 1362 break; 1363 } 1364 } 1365 if (!active) 1366 return 0; 1367 1368 /* 1369 * Command parser version history 1370 * 1371 * 1. Initial version. Checks batches and reports violations, but leaves 1372 * hardware parsing enabled (so does not allow new use cases). 1373 * 2. Allow access to the MI_PREDICATE_SRC0 and 1374 * MI_PREDICATE_SRC1 registers. 1375 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register. 1376 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. 1377 * 5. GPGPU dispatch compute indirect registers. 1378 * 6. TIMESTAMP register and Haswell CS GPR registers 1379 * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers. 1380 * 8. Don't report cmd_check() failures as EINVAL errors to userspace; 1381 * rely on the HW to NOOP disallowed commands as it would without 1382 * the parser enabled. 1383 * 9. Don't whitelist or handle oacontrol specially, as ownership 1384 * for oacontrol state is moving to i915-perf. 1385 */ 1386 return 9; 1387 } 1388