1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/sched/mm.h> 30 #include <linux/sort.h> 31 #include <linux/string_helpers.h> 32 33 #include <drm/drm_debugfs.h> 34 35 #include "gem/i915_gem_context.h" 36 #include "gt/intel_gt.h" 37 #include "gt/intel_gt_buffer_pool.h" 38 #include "gt/intel_gt_clock_utils.h" 39 #include "gt/intel_gt_debugfs.h" 40 #include "gt/intel_gt_pm.h" 41 #include "gt/intel_gt_pm_debugfs.h" 42 #include "gt/intel_gt_regs.h" 43 #include "gt/intel_gt_requests.h" 44 #include "gt/intel_rc6.h" 45 #include "gt/intel_reset.h" 46 #include "gt/intel_rps.h" 47 #include "gt/intel_sseu_debugfs.h" 48 49 #include "i915_debugfs.h" 50 #include "i915_debugfs_params.h" 51 #include "i915_driver.h" 52 #include "i915_irq.h" 53 #include "i915_scheduler.h" 54 #include "intel_mchbar_regs.h" 55 #include "intel_pm.h" 56 57 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 58 { 59 return to_i915(node->minor->dev); 60 } 61 62 static int i915_capabilities(struct seq_file *m, void *data) 63 { 64 struct drm_i915_private *i915 = node_to_i915(m->private); 65 struct drm_printer p = drm_seq_file_printer(m); 66 67 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915)); 68 69 intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p); 70 i915_print_iommu_status(i915, &p); 71 intel_gt_info_print(&to_gt(i915)->info, &p); 72 intel_driver_caps_print(&i915->caps, &p); 73 74 kernel_param_lock(THIS_MODULE); 75 i915_params_dump(&i915->params, &p); 76 kernel_param_unlock(THIS_MODULE); 77 78 return 0; 79 } 80 81 static char get_tiling_flag(struct drm_i915_gem_object *obj) 82 { 83 switch (i915_gem_object_get_tiling(obj)) { 84 default: 85 case I915_TILING_NONE: return ' '; 86 case I915_TILING_X: return 'X'; 87 case I915_TILING_Y: return 'Y'; 88 } 89 } 90 91 static char get_global_flag(struct drm_i915_gem_object *obj) 92 { 93 return READ_ONCE(obj->userfault_count) ? 'g' : ' '; 94 } 95 96 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 97 { 98 return obj->mm.mapping ? 'M' : ' '; 99 } 100 101 static const char * 102 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) 103 { 104 size_t x = 0; 105 106 switch (page_sizes) { 107 case 0: 108 return ""; 109 case I915_GTT_PAGE_SIZE_4K: 110 return "4K"; 111 case I915_GTT_PAGE_SIZE_64K: 112 return "64K"; 113 case I915_GTT_PAGE_SIZE_2M: 114 return "2M"; 115 default: 116 if (!buf) 117 return "M"; 118 119 if (page_sizes & I915_GTT_PAGE_SIZE_2M) 120 x += snprintf(buf + x, len - x, "2M, "); 121 if (page_sizes & I915_GTT_PAGE_SIZE_64K) 122 x += snprintf(buf + x, len - x, "64K, "); 123 if (page_sizes & I915_GTT_PAGE_SIZE_4K) 124 x += snprintf(buf + x, len - x, "4K, "); 125 buf[x-2] = '\0'; 126 127 return buf; 128 } 129 } 130 131 static const char *stringify_vma_type(const struct i915_vma *vma) 132 { 133 if (i915_vma_is_ggtt(vma)) 134 return "ggtt"; 135 136 if (i915_vma_is_dpt(vma)) 137 return "dpt"; 138 139 return "ppgtt"; 140 } 141 142 static const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 143 { 144 switch (type) { 145 case I915_CACHE_NONE: return " uncached"; 146 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 147 case I915_CACHE_L3_LLC: return " L3+LLC"; 148 case I915_CACHE_WT: return " WT"; 149 default: return ""; 150 } 151 } 152 153 void 154 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 155 { 156 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 157 struct i915_vma *vma; 158 int pin_count = 0; 159 160 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s", 161 &obj->base, 162 get_tiling_flag(obj), 163 get_global_flag(obj), 164 get_pin_mapped_flag(obj), 165 obj->base.size / 1024, 166 obj->read_domains, 167 obj->write_domain, 168 i915_cache_level_str(dev_priv, obj->cache_level), 169 obj->mm.dirty ? " dirty" : "", 170 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); 171 if (obj->base.name) 172 seq_printf(m, " (name: %d)", obj->base.name); 173 174 spin_lock(&obj->vma.lock); 175 list_for_each_entry(vma, &obj->vma.list, obj_link) { 176 if (!drm_mm_node_allocated(&vma->node)) 177 continue; 178 179 spin_unlock(&obj->vma.lock); 180 181 if (i915_vma_is_pinned(vma)) 182 pin_count++; 183 184 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s", 185 stringify_vma_type(vma), 186 vma->node.start, vma->node.size, 187 stringify_page_sizes(vma->resource->page_sizes_gtt, 188 NULL, 0)); 189 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) { 190 switch (vma->gtt_view.type) { 191 case I915_GTT_VIEW_NORMAL: 192 seq_puts(m, ", normal"); 193 break; 194 195 case I915_GTT_VIEW_PARTIAL: 196 seq_printf(m, ", partial [%08llx+%x]", 197 vma->gtt_view.partial.offset << PAGE_SHIFT, 198 vma->gtt_view.partial.size << PAGE_SHIFT); 199 break; 200 201 case I915_GTT_VIEW_ROTATED: 202 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 203 vma->gtt_view.rotated.plane[0].width, 204 vma->gtt_view.rotated.plane[0].height, 205 vma->gtt_view.rotated.plane[0].src_stride, 206 vma->gtt_view.rotated.plane[0].dst_stride, 207 vma->gtt_view.rotated.plane[0].offset, 208 vma->gtt_view.rotated.plane[1].width, 209 vma->gtt_view.rotated.plane[1].height, 210 vma->gtt_view.rotated.plane[1].src_stride, 211 vma->gtt_view.rotated.plane[1].dst_stride, 212 vma->gtt_view.rotated.plane[1].offset); 213 break; 214 215 case I915_GTT_VIEW_REMAPPED: 216 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 217 vma->gtt_view.remapped.plane[0].width, 218 vma->gtt_view.remapped.plane[0].height, 219 vma->gtt_view.remapped.plane[0].src_stride, 220 vma->gtt_view.remapped.plane[0].dst_stride, 221 vma->gtt_view.remapped.plane[0].offset, 222 vma->gtt_view.remapped.plane[1].width, 223 vma->gtt_view.remapped.plane[1].height, 224 vma->gtt_view.remapped.plane[1].src_stride, 225 vma->gtt_view.remapped.plane[1].dst_stride, 226 vma->gtt_view.remapped.plane[1].offset); 227 break; 228 229 default: 230 MISSING_CASE(vma->gtt_view.type); 231 break; 232 } 233 } 234 if (vma->fence) 235 seq_printf(m, " , fence: %d", vma->fence->id); 236 seq_puts(m, ")"); 237 238 spin_lock(&obj->vma.lock); 239 } 240 spin_unlock(&obj->vma.lock); 241 242 seq_printf(m, " (pinned x %d)", pin_count); 243 if (i915_gem_object_is_stolen(obj)) 244 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 245 if (i915_gem_object_is_framebuffer(obj)) 246 seq_printf(m, " (fb)"); 247 } 248 249 static int i915_gem_object_info(struct seq_file *m, void *data) 250 { 251 struct drm_i915_private *i915 = node_to_i915(m->private); 252 struct drm_printer p = drm_seq_file_printer(m); 253 struct intel_memory_region *mr; 254 enum intel_region_id id; 255 256 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n", 257 i915->mm.shrink_count, 258 atomic_read(&i915->mm.free_count), 259 i915->mm.shrink_memory); 260 for_each_memory_region(mr, i915, id) 261 intel_memory_region_debug(mr, &p); 262 263 return 0; 264 } 265 266 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 267 static ssize_t gpu_state_read(struct file *file, char __user *ubuf, 268 size_t count, loff_t *pos) 269 { 270 struct i915_gpu_coredump *error; 271 ssize_t ret; 272 void *buf; 273 274 error = file->private_data; 275 if (!error) 276 return 0; 277 278 /* Bounce buffer required because of kernfs __user API convenience. */ 279 buf = kmalloc(count, GFP_KERNEL); 280 if (!buf) 281 return -ENOMEM; 282 283 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count); 284 if (ret <= 0) 285 goto out; 286 287 if (!copy_to_user(ubuf, buf, ret)) 288 *pos += ret; 289 else 290 ret = -EFAULT; 291 292 out: 293 kfree(buf); 294 return ret; 295 } 296 297 static int gpu_state_release(struct inode *inode, struct file *file) 298 { 299 i915_gpu_coredump_put(file->private_data); 300 return 0; 301 } 302 303 static int i915_gpu_info_open(struct inode *inode, struct file *file) 304 { 305 struct drm_i915_private *i915 = inode->i_private; 306 struct i915_gpu_coredump *gpu; 307 intel_wakeref_t wakeref; 308 309 gpu = NULL; 310 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 311 gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE); 312 313 if (IS_ERR(gpu)) 314 return PTR_ERR(gpu); 315 316 file->private_data = gpu; 317 return 0; 318 } 319 320 static const struct file_operations i915_gpu_info_fops = { 321 .owner = THIS_MODULE, 322 .open = i915_gpu_info_open, 323 .read = gpu_state_read, 324 .llseek = default_llseek, 325 .release = gpu_state_release, 326 }; 327 328 static ssize_t 329 i915_error_state_write(struct file *filp, 330 const char __user *ubuf, 331 size_t cnt, 332 loff_t *ppos) 333 { 334 struct i915_gpu_coredump *error = filp->private_data; 335 336 if (!error) 337 return 0; 338 339 drm_dbg(&error->i915->drm, "Resetting error state\n"); 340 i915_reset_error_state(error->i915); 341 342 return cnt; 343 } 344 345 static int i915_error_state_open(struct inode *inode, struct file *file) 346 { 347 struct i915_gpu_coredump *error; 348 349 error = i915_first_error_state(inode->i_private); 350 if (IS_ERR(error)) 351 return PTR_ERR(error); 352 353 file->private_data = error; 354 return 0; 355 } 356 357 static const struct file_operations i915_error_state_fops = { 358 .owner = THIS_MODULE, 359 .open = i915_error_state_open, 360 .read = gpu_state_read, 361 .write = i915_error_state_write, 362 .llseek = default_llseek, 363 .release = gpu_state_release, 364 }; 365 #endif 366 367 static int i915_frequency_info(struct seq_file *m, void *unused) 368 { 369 struct drm_i915_private *i915 = node_to_i915(m->private); 370 struct intel_gt *gt = to_gt(i915); 371 struct drm_printer p = drm_seq_file_printer(m); 372 373 intel_gt_pm_frequency_dump(gt, &p); 374 375 return 0; 376 } 377 378 static const char *swizzle_string(unsigned swizzle) 379 { 380 switch (swizzle) { 381 case I915_BIT_6_SWIZZLE_NONE: 382 return "none"; 383 case I915_BIT_6_SWIZZLE_9: 384 return "bit9"; 385 case I915_BIT_6_SWIZZLE_9_10: 386 return "bit9/bit10"; 387 case I915_BIT_6_SWIZZLE_9_11: 388 return "bit9/bit11"; 389 case I915_BIT_6_SWIZZLE_9_10_11: 390 return "bit9/bit10/bit11"; 391 case I915_BIT_6_SWIZZLE_9_17: 392 return "bit9/bit17"; 393 case I915_BIT_6_SWIZZLE_9_10_17: 394 return "bit9/bit10/bit17"; 395 case I915_BIT_6_SWIZZLE_UNKNOWN: 396 return "unknown"; 397 } 398 399 return "bug"; 400 } 401 402 static int i915_swizzle_info(struct seq_file *m, void *data) 403 { 404 struct drm_i915_private *dev_priv = node_to_i915(m->private); 405 struct intel_uncore *uncore = &dev_priv->uncore; 406 intel_wakeref_t wakeref; 407 408 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 409 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x)); 410 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 411 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y)); 412 413 if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) 414 seq_puts(m, "L-shaped memory detected\n"); 415 416 /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */ 417 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) 418 return 0; 419 420 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 421 422 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) { 423 seq_printf(m, "DDC = 0x%08x\n", 424 intel_uncore_read(uncore, DCC)); 425 seq_printf(m, "DDC2 = 0x%08x\n", 426 intel_uncore_read(uncore, DCC2)); 427 seq_printf(m, "C0DRB3 = 0x%04x\n", 428 intel_uncore_read16(uncore, C0DRB3_BW)); 429 seq_printf(m, "C1DRB3 = 0x%04x\n", 430 intel_uncore_read16(uncore, C1DRB3_BW)); 431 } else if (GRAPHICS_VER(dev_priv) >= 6) { 432 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 433 intel_uncore_read(uncore, MAD_DIMM_C0)); 434 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 435 intel_uncore_read(uncore, MAD_DIMM_C1)); 436 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 437 intel_uncore_read(uncore, MAD_DIMM_C2)); 438 seq_printf(m, "TILECTL = 0x%08x\n", 439 intel_uncore_read(uncore, TILECTL)); 440 if (GRAPHICS_VER(dev_priv) >= 8) 441 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 442 intel_uncore_read(uncore, GAMTARBMODE)); 443 else 444 seq_printf(m, "ARB_MODE = 0x%08x\n", 445 intel_uncore_read(uncore, ARB_MODE)); 446 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 447 intel_uncore_read(uncore, DISP_ARB_CTL)); 448 } 449 450 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 451 452 return 0; 453 } 454 455 static int i915_rps_boost_info(struct seq_file *m, void *data) 456 { 457 struct drm_i915_private *dev_priv = node_to_i915(m->private); 458 struct intel_rps *rps = &to_gt(dev_priv)->rps; 459 460 seq_printf(m, "RPS enabled? %s\n", 461 str_yes_no(intel_rps_is_enabled(rps))); 462 seq_printf(m, "RPS active? %s\n", 463 str_yes_no(intel_rps_is_active(rps))); 464 seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake)); 465 seq_printf(m, "Boosts outstanding? %d\n", 466 atomic_read(&rps->num_waiters)); 467 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 468 seq_printf(m, "Frequency requested %d, actual %d\n", 469 intel_gpu_freq(rps, rps->cur_freq), 470 intel_rps_read_actual_frequency(rps)); 471 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 472 intel_gpu_freq(rps, rps->min_freq), 473 intel_gpu_freq(rps, rps->min_freq_softlimit), 474 intel_gpu_freq(rps, rps->max_freq_softlimit), 475 intel_gpu_freq(rps, rps->max_freq)); 476 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 477 intel_gpu_freq(rps, rps->idle_freq), 478 intel_gpu_freq(rps, rps->efficient_freq), 479 intel_gpu_freq(rps, rps->boost_freq)); 480 481 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 482 483 return 0; 484 } 485 486 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 487 { 488 struct drm_i915_private *dev_priv = node_to_i915(m->private); 489 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 490 491 if (!HAS_RUNTIME_PM(dev_priv)) 492 seq_puts(m, "Runtime power management not supported\n"); 493 494 seq_printf(m, "Runtime power status: %s\n", 495 str_enabled_disabled(!dev_priv->display.power.domains.init_wakeref)); 496 497 seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake)); 498 seq_printf(m, "IRQs disabled: %s\n", 499 str_yes_no(!intel_irqs_enabled(dev_priv))); 500 #ifdef CONFIG_PM 501 seq_printf(m, "Usage count: %d\n", 502 atomic_read(&dev_priv->drm.dev->power.usage_count)); 503 #else 504 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 505 #endif 506 seq_printf(m, "PCI device power state: %s [%d]\n", 507 pci_power_name(pdev->current_state), 508 pdev->current_state); 509 510 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) { 511 struct drm_printer p = drm_seq_file_printer(m); 512 513 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p); 514 } 515 516 return 0; 517 } 518 519 static int i915_engine_info(struct seq_file *m, void *unused) 520 { 521 struct drm_i915_private *i915 = node_to_i915(m->private); 522 struct intel_engine_cs *engine; 523 intel_wakeref_t wakeref; 524 struct drm_printer p; 525 526 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 527 528 seq_printf(m, "GT awake? %s [%d], %llums\n", 529 str_yes_no(to_gt(i915)->awake), 530 atomic_read(&to_gt(i915)->wakeref.count), 531 ktime_to_ms(intel_gt_get_awake_time(to_gt(i915)))); 532 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 533 to_gt(i915)->clock_frequency, 534 to_gt(i915)->clock_period_ns); 535 536 p = drm_seq_file_printer(m); 537 for_each_uabi_engine(engine, i915) 538 intel_engine_dump(engine, &p, "%s\n", engine->name); 539 540 intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule); 541 542 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 543 544 return 0; 545 } 546 547 static int i915_wa_registers(struct seq_file *m, void *unused) 548 { 549 struct drm_i915_private *i915 = node_to_i915(m->private); 550 struct intel_engine_cs *engine; 551 552 for_each_uabi_engine(engine, i915) { 553 const struct i915_wa_list *wal = &engine->ctx_wa_list; 554 const struct i915_wa *wa; 555 unsigned int count; 556 557 count = wal->count; 558 if (!count) 559 continue; 560 561 seq_printf(m, "%s: Workarounds applied: %u\n", 562 engine->name, count); 563 564 for (wa = wal->list; count--; wa++) 565 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", 566 i915_mmio_reg_offset(wa->reg), 567 wa->set, wa->clr); 568 569 seq_printf(m, "\n"); 570 } 571 572 return 0; 573 } 574 575 static int i915_wedged_get(void *data, u64 *val) 576 { 577 struct drm_i915_private *i915 = data; 578 579 return intel_gt_debugfs_reset_show(to_gt(i915), val); 580 } 581 582 static int i915_wedged_set(void *data, u64 val) 583 { 584 struct drm_i915_private *i915 = data; 585 intel_gt_debugfs_reset_store(to_gt(i915), val); 586 587 return 0; 588 } 589 590 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 591 i915_wedged_get, i915_wedged_set, 592 "%llu\n"); 593 594 static int 595 i915_perf_noa_delay_set(void *data, u64 val) 596 { 597 struct drm_i915_private *i915 = data; 598 599 /* 600 * This would lead to infinite waits as we're doing timestamp 601 * difference on the CS with only 32bits. 602 */ 603 if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX) 604 return -EINVAL; 605 606 atomic64_set(&i915->perf.noa_programming_delay, val); 607 return 0; 608 } 609 610 static int 611 i915_perf_noa_delay_get(void *data, u64 *val) 612 { 613 struct drm_i915_private *i915 = data; 614 615 *val = atomic64_read(&i915->perf.noa_programming_delay); 616 return 0; 617 } 618 619 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops, 620 i915_perf_noa_delay_get, 621 i915_perf_noa_delay_set, 622 "%llu\n"); 623 624 #define DROP_UNBOUND BIT(0) 625 #define DROP_BOUND BIT(1) 626 #define DROP_RETIRE BIT(2) 627 #define DROP_ACTIVE BIT(3) 628 #define DROP_FREED BIT(4) 629 #define DROP_SHRINK_ALL BIT(5) 630 #define DROP_IDLE BIT(6) 631 #define DROP_RESET_ACTIVE BIT(7) 632 #define DROP_RESET_SEQNO BIT(8) 633 #define DROP_RCU BIT(9) 634 #define DROP_ALL (DROP_UNBOUND | \ 635 DROP_BOUND | \ 636 DROP_RETIRE | \ 637 DROP_ACTIVE | \ 638 DROP_FREED | \ 639 DROP_SHRINK_ALL |\ 640 DROP_IDLE | \ 641 DROP_RESET_ACTIVE | \ 642 DROP_RESET_SEQNO | \ 643 DROP_RCU) 644 static int 645 i915_drop_caches_get(void *data, u64 *val) 646 { 647 *val = DROP_ALL; 648 649 return 0; 650 } 651 static int 652 gt_drop_caches(struct intel_gt *gt, u64 val) 653 { 654 int ret; 655 656 if (val & DROP_RESET_ACTIVE && 657 wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT)) 658 intel_gt_set_wedged(gt); 659 660 if (val & DROP_RETIRE) 661 intel_gt_retire_requests(gt); 662 663 if (val & (DROP_IDLE | DROP_ACTIVE)) { 664 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); 665 if (ret) 666 return ret; 667 } 668 669 if (val & DROP_IDLE) { 670 ret = intel_gt_pm_wait_for_idle(gt); 671 if (ret) 672 return ret; 673 } 674 675 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt)) 676 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL); 677 678 if (val & DROP_FREED) 679 intel_gt_flush_buffer_pool(gt); 680 681 return 0; 682 } 683 684 static int 685 i915_drop_caches_set(void *data, u64 val) 686 { 687 struct drm_i915_private *i915 = data; 688 unsigned int flags; 689 int ret; 690 691 DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n", 692 val, val & DROP_ALL); 693 694 ret = gt_drop_caches(to_gt(i915), val); 695 if (ret) 696 return ret; 697 698 fs_reclaim_acquire(GFP_KERNEL); 699 flags = memalloc_noreclaim_save(); 700 if (val & DROP_BOUND) 701 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND); 702 703 if (val & DROP_UNBOUND) 704 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND); 705 706 if (val & DROP_SHRINK_ALL) 707 i915_gem_shrink_all(i915); 708 memalloc_noreclaim_restore(flags); 709 fs_reclaim_release(GFP_KERNEL); 710 711 if (val & DROP_RCU) 712 rcu_barrier(); 713 714 if (val & DROP_FREED) 715 i915_gem_drain_freed_objects(i915); 716 717 return 0; 718 } 719 720 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 721 i915_drop_caches_get, i915_drop_caches_set, 722 "0x%08llx\n"); 723 724 static int i915_sseu_status(struct seq_file *m, void *unused) 725 { 726 struct drm_i915_private *i915 = node_to_i915(m->private); 727 struct intel_gt *gt = to_gt(i915); 728 729 return intel_sseu_status(m, gt); 730 } 731 732 static int i915_forcewake_open(struct inode *inode, struct file *file) 733 { 734 struct drm_i915_private *i915 = inode->i_private; 735 intel_gt_pm_debugfs_forcewake_user_open(to_gt(i915)); 736 737 return 0; 738 } 739 740 static int i915_forcewake_release(struct inode *inode, struct file *file) 741 { 742 struct drm_i915_private *i915 = inode->i_private; 743 intel_gt_pm_debugfs_forcewake_user_release(to_gt(i915)); 744 745 return 0; 746 } 747 748 static const struct file_operations i915_forcewake_fops = { 749 .owner = THIS_MODULE, 750 .open = i915_forcewake_open, 751 .release = i915_forcewake_release, 752 }; 753 754 static const struct drm_info_list i915_debugfs_list[] = { 755 {"i915_capabilities", i915_capabilities, 0}, 756 {"i915_gem_objects", i915_gem_object_info, 0}, 757 {"i915_frequency_info", i915_frequency_info, 0}, 758 {"i915_swizzle_info", i915_swizzle_info, 0}, 759 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 760 {"i915_engine_info", i915_engine_info, 0}, 761 {"i915_wa_registers", i915_wa_registers, 0}, 762 {"i915_sseu_status", i915_sseu_status, 0}, 763 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 764 }; 765 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 766 767 static const struct i915_debugfs_files { 768 const char *name; 769 const struct file_operations *fops; 770 } i915_debugfs_files[] = { 771 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, 772 {"i915_wedged", &i915_wedged_fops}, 773 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 774 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 775 {"i915_error_state", &i915_error_state_fops}, 776 {"i915_gpu_info", &i915_gpu_info_fops}, 777 #endif 778 }; 779 780 void i915_debugfs_register(struct drm_i915_private *dev_priv) 781 { 782 struct drm_minor *minor = dev_priv->drm.primary; 783 int i; 784 785 i915_debugfs_params(dev_priv); 786 787 debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root, 788 to_i915(minor->dev), &i915_forcewake_fops); 789 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 790 debugfs_create_file(i915_debugfs_files[i].name, 791 S_IRUGO | S_IWUSR, 792 minor->debugfs_root, 793 to_i915(minor->dev), 794 i915_debugfs_files[i].fops); 795 } 796 797 drm_debugfs_create_files(i915_debugfs_list, 798 I915_DEBUGFS_ENTRIES, 799 minor->debugfs_root, minor); 800 } 801