1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include <linux/pm_qos.h> 36 37 #include <drm/ttm/ttm_device.h> 38 39 #include "display/intel_display_limits.h" 40 #include "display/intel_display_core.h" 41 42 #include "gem/i915_gem_context_types.h" 43 #include "gem/i915_gem_shrinker.h" 44 #include "gem/i915_gem_stolen.h" 45 46 #include "gt/intel_engine.h" 47 #include "gt/intel_gt_types.h" 48 #include "gt/intel_region_lmem.h" 49 #include "gt/intel_workarounds.h" 50 #include "gt/uc/intel_uc.h" 51 52 #include "soc/intel_pch.h" 53 54 #include "i915_drm_client.h" 55 #include "i915_gem.h" 56 #include "i915_gpu_error.h" 57 #include "i915_params.h" 58 #include "i915_perf_types.h" 59 #include "i915_scheduler.h" 60 #include "i915_utils.h" 61 #include "intel_device_info.h" 62 #include "intel_memory_region.h" 63 #include "intel_runtime_pm.h" 64 #include "intel_step.h" 65 #include "intel_uncore.h" 66 67 struct drm_i915_clock_gating_funcs; 68 struct vlv_s0ix_state; 69 struct intel_pxp; 70 71 #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0) 72 73 /* Data Stolen Memory (DSM) aka "i915 stolen memory" */ 74 struct i915_dsm { 75 /* 76 * The start and end of DSM which we can optionally use to create GEM 77 * objects backed by stolen memory. 78 * 79 * Note that usable_size tells us exactly how much of this we are 80 * actually allowed to use, given that some portion of it is in fact 81 * reserved for use by hardware functions. 82 */ 83 struct resource stolen; 84 85 /* 86 * Reserved portion of DSM. 87 */ 88 struct resource reserved; 89 90 /* 91 * Total size minus reserved ranges. 92 * 93 * DSM is segmented in hardware with different portions offlimits to 94 * certain functions. 95 * 96 * The drm_mm is initialised to the total accessible range, as found 97 * from the PCI config. On Broadwell+, this is further restricted to 98 * avoid the first page! The upper end of DSM is reserved for hardware 99 * functions and similarly removed from the accessible range. 100 */ 101 resource_size_t usable_size; 102 }; 103 104 struct i915_suspend_saved_registers { 105 u32 saveDSPARB; 106 u32 saveSWF0[16]; 107 u32 saveSWF1[16]; 108 u32 saveSWF3[3]; 109 u16 saveGCDGMBUS; 110 }; 111 112 #define MAX_L3_SLICES 2 113 struct intel_l3_parity { 114 u32 *remap_info[MAX_L3_SLICES]; 115 struct work_struct error_work; 116 int which_slice; 117 }; 118 119 struct i915_gem_mm { 120 /* 121 * Shortcut for the stolen region. This points to either 122 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 123 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 124 * support stolen. 125 */ 126 struct intel_memory_region *stolen_region; 127 /** Memory allocator for GTT stolen memory */ 128 struct drm_mm stolen; 129 /** Protects the usage of the GTT stolen memory allocator. This is 130 * always the inner lock when overlapping with struct_mutex. */ 131 struct mutex stolen_lock; 132 133 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 134 spinlock_t obj_lock; 135 136 /** 137 * List of objects which are purgeable. 138 */ 139 struct list_head purge_list; 140 141 /** 142 * List of objects which have allocated pages and are shrinkable. 143 */ 144 struct list_head shrink_list; 145 146 /** 147 * List of objects which are pending destruction. 148 */ 149 struct llist_head free_list; 150 struct work_struct free_work; 151 /** 152 * Count of objects pending destructions. Used to skip needlessly 153 * waiting on an RCU barrier if no objects are waiting to be freed. 154 */ 155 atomic_t free_count; 156 157 /** 158 * tmpfs instance used for shmem backed objects 159 */ 160 struct vfsmount *gemfs; 161 162 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 163 164 struct notifier_block oom_notifier; 165 struct notifier_block vmap_notifier; 166 struct shrinker *shrinker; 167 168 #ifdef CONFIG_MMU_NOTIFIER 169 /** 170 * notifier_lock for mmu notifiers, memory may not be allocated 171 * while holding this lock. 172 */ 173 rwlock_t notifier_lock; 174 #endif 175 176 /* shrinker accounting, also useful for userland debugging */ 177 u64 shrink_memory; 178 u32 shrink_count; 179 }; 180 181 struct i915_virtual_gpu { 182 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 183 bool active; 184 u32 caps; 185 u32 *initial_mmio; 186 u8 *initial_cfg_space; 187 struct list_head entry; 188 }; 189 190 struct i915_selftest_stash { 191 atomic_t counter; 192 struct ida mock_region_instances; 193 }; 194 195 struct drm_i915_private { 196 struct drm_device drm; 197 198 struct intel_display display; 199 200 /* FIXME: Device release actions should all be moved to drmm_ */ 201 bool do_release; 202 203 /* i915 device parameters */ 204 struct i915_params params; 205 206 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */ 207 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 208 struct intel_driver_caps caps; 209 210 struct i915_dsm dsm; 211 212 struct intel_uncore uncore; 213 struct intel_uncore_mmio_debug mmio_debug; 214 215 struct i915_virtual_gpu vgpu; 216 217 struct intel_gvt *gvt; 218 219 struct { 220 struct pci_dev *pdev; 221 struct resource mch_res; 222 bool mchbar_need_disable; 223 } gmch; 224 225 /* 226 * Chaining user engines happens in multiple stages, starting with a 227 * simple lock-less linked list created by intel_engine_add_user(), 228 * which later gets sorted and converted to an intermediate regular 229 * list, just to be converted once again to its final rb tree structure 230 * in intel_engines_driver_register(). 231 * 232 * Make sure to use the right iterator helper, depending on if the code 233 * in question runs before or after intel_engines_driver_register() -- 234 * for_each_uabi_engine() can only be used afterwards! 235 */ 236 union { 237 struct llist_head uabi_engines_llist; 238 struct list_head uabi_engines_list; 239 struct rb_root uabi_engines; 240 }; 241 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1]; 242 243 /* protects the irq masks */ 244 spinlock_t irq_lock; 245 246 bool display_irqs_enabled; 247 248 /* Sideband mailbox protection */ 249 struct mutex sb_lock; 250 struct pm_qos_request sb_qos; 251 252 /** Cached value of IMR to avoid reads in updating the bitfield */ 253 union { 254 u32 irq_mask; 255 u32 de_irq_mask[I915_MAX_PIPES]; 256 }; 257 u32 pipestat_irq_mask[I915_MAX_PIPES]; 258 259 bool preserve_bios_swizzle; 260 261 unsigned int fsb_freq, mem_freq, is_ddr3; 262 unsigned int skl_preferred_vco_freq; 263 264 unsigned int max_dotclk_freq; 265 unsigned int hpll_freq; 266 unsigned int czclk_freq; 267 268 /** 269 * wq - Driver workqueue for GEM. 270 * 271 * NOTE: Work items scheduled here are not allowed to grab any modeset 272 * locks, for otherwise the flushing done in the pageflip code will 273 * result in deadlocks. 274 */ 275 struct workqueue_struct *wq; 276 277 /** 278 * unordered_wq - internal workqueue for unordered work 279 * 280 * This workqueue should be used for all unordered work 281 * scheduling within i915, which used to be scheduled on the 282 * system_wq before moving to a driver instance due 283 * deprecation of flush_scheduled_work(). 284 */ 285 struct workqueue_struct *unordered_wq; 286 287 /* pm private clock gating functions */ 288 const struct drm_i915_clock_gating_funcs *clock_gating_funcs; 289 290 /* PCH chipset type */ 291 enum intel_pch pch_type; 292 unsigned short pch_id; 293 294 unsigned long gem_quirks; 295 296 struct i915_gem_mm mm; 297 298 struct intel_l3_parity l3_parity; 299 300 /* 301 * edram size in MB. 302 * Cannot be determined by PCIID. You must always read a register. 303 */ 304 u32 edram_size_mb; 305 306 struct i915_gpu_error gpu_error; 307 308 u32 suspend_count; 309 struct i915_suspend_saved_registers regfile; 310 struct vlv_s0ix_state *vlv_s0ix_state; 311 312 struct dram_info { 313 bool wm_lv_0_adjust_needed; 314 u8 num_channels; 315 bool symmetric_memory; 316 enum intel_dram_type { 317 INTEL_DRAM_UNKNOWN, 318 INTEL_DRAM_DDR3, 319 INTEL_DRAM_DDR4, 320 INTEL_DRAM_LPDDR3, 321 INTEL_DRAM_LPDDR4, 322 INTEL_DRAM_DDR5, 323 INTEL_DRAM_LPDDR5, 324 } type; 325 u8 num_qgv_points; 326 u8 num_psf_gv_points; 327 } dram_info; 328 329 struct intel_runtime_pm runtime_pm; 330 331 struct i915_perf perf; 332 333 struct i915_hwmon *hwmon; 334 335 struct intel_gt *gt[I915_MAX_GT]; 336 337 struct kobject *sysfs_gt; 338 339 /* Quick lookup of media GT (current platforms only have one) */ 340 struct intel_gt *media_gt; 341 342 struct { 343 struct i915_gem_contexts { 344 spinlock_t lock; /* locks list */ 345 struct list_head list; 346 } contexts; 347 348 /* 349 * We replace the local file with a global mappings as the 350 * backing storage for the mmap is on the device and not 351 * on the struct file, and we do not want to prolong the 352 * lifetime of the local fd. To minimise the number of 353 * anonymous inodes we create, we use a global singleton to 354 * share the global mapping. 355 */ 356 struct file *mmap_singleton; 357 } gem; 358 359 struct intel_pxp *pxp; 360 361 /* For i915gm/i945gm vblank irq workaround */ 362 u8 vblank_enabled; 363 364 bool irq_enabled; 365 366 struct i915_pmu pmu; 367 368 /* The TTM device structure. */ 369 struct ttm_device bdev; 370 371 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 372 373 /* 374 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 375 * will be rejected. Instead look for a better place. 376 */ 377 }; 378 379 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 380 { 381 return container_of(dev, struct drm_i915_private, drm); 382 } 383 384 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 385 { 386 return dev_get_drvdata(kdev); 387 } 388 389 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 390 { 391 return pci_get_drvdata(pdev); 392 } 393 394 static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) 395 { 396 return i915->gt[0]; 397 } 398 399 #define rb_to_uabi_engine(rb) \ 400 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 401 402 #define for_each_uabi_engine(engine__, i915__) \ 403 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 404 (engine__); \ 405 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 406 407 #define INTEL_INFO(i915) ((i915)->__info) 408 #define RUNTIME_INFO(i915) (&(i915)->__runtime) 409 #define DRIVER_CAPS(i915) (&(i915)->caps) 410 411 #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) 412 413 #define IP_VER(ver, rel) ((ver) << 8 | (rel)) 414 415 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver) 416 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \ 417 RUNTIME_INFO(i915)->graphics.ip.rel) 418 #define IS_GRAPHICS_VER(i915, from, until) \ 419 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 420 421 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver) 422 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \ 423 RUNTIME_INFO(i915)->media.ip.rel) 424 #define IS_MEDIA_VER(i915, from, until) \ 425 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 426 427 #define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision) 428 429 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) 430 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) 431 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step) 432 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step) 433 434 #define IS_DISPLAY_STEP(__i915, since, until) \ 435 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 436 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until)) 437 438 #define IS_GRAPHICS_STEP(__i915, since, until) \ 439 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ 440 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until)) 441 442 #define IS_MEDIA_STEP(__i915, since, until) \ 443 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ 444 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) 445 446 #define IS_BASEDIE_STEP(__i915, since, until) \ 447 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \ 448 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until)) 449 450 static __always_inline unsigned int 451 __platform_mask_index(const struct intel_runtime_info *info, 452 enum intel_platform p) 453 { 454 const unsigned int pbits = 455 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 456 457 /* Expand the platform_mask array if this fails. */ 458 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 459 pbits * ARRAY_SIZE(info->platform_mask)); 460 461 return p / pbits; 462 } 463 464 static __always_inline unsigned int 465 __platform_mask_bit(const struct intel_runtime_info *info, 466 enum intel_platform p) 467 { 468 const unsigned int pbits = 469 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 470 471 return p % pbits + INTEL_SUBPLATFORM_BITS; 472 } 473 474 static inline u32 475 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 476 { 477 const unsigned int pi = __platform_mask_index(info, p); 478 479 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 480 } 481 482 static __always_inline bool 483 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 484 { 485 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 486 const unsigned int pi = __platform_mask_index(info, p); 487 const unsigned int pb = __platform_mask_bit(info, p); 488 489 BUILD_BUG_ON(!__builtin_constant_p(p)); 490 491 return info->platform_mask[pi] & BIT(pb); 492 } 493 494 static __always_inline bool 495 IS_SUBPLATFORM(const struct drm_i915_private *i915, 496 enum intel_platform p, unsigned int s) 497 { 498 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 499 const unsigned int pi = __platform_mask_index(info, p); 500 const unsigned int pb = __platform_mask_bit(info, p); 501 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 502 const u32 mask = info->platform_mask[pi]; 503 504 BUILD_BUG_ON(!__builtin_constant_p(p)); 505 BUILD_BUG_ON(!__builtin_constant_p(s)); 506 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 507 508 /* Shift and test on the MSB position so sign flag can be used. */ 509 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 510 } 511 512 #define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile) 513 #define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx) 514 515 #define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830) 516 #define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G) 517 #define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X) 518 #define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G) 519 #define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G) 520 #define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM) 521 #define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G) 522 #define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM) 523 #define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G) 524 #define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM) 525 #define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45) 526 #define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45) 527 #define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915)) 528 #define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW) 529 #define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33) 530 #define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE) 531 #define IS_IRONLAKE_M(i915) \ 532 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915)) 533 #define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE) 534 #define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE) 535 #define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \ 536 INTEL_INFO(i915)->gt == 1) 537 #define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW) 538 #define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW) 539 #define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL) 540 #define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL) 541 #define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE) 542 #define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON) 543 #define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE) 544 #define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE) 545 #define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE) 546 #define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE) 547 #define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE) 548 #define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE) 549 #define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE) 550 #define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE) 551 #define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE) 552 #define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1) 553 #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S) 554 #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) 555 #define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV) 556 #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) 557 #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO) 558 #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) 559 #define IS_LUNARLAKE(i915) 0 560 561 #define IS_DG2_G10(i915) \ 562 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) 563 #define IS_DG2_G11(i915) \ 564 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) 565 #define IS_DG2_G12(i915) \ 566 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) 567 #define IS_RAPTORLAKE_S(i915) \ 568 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) 569 #define IS_ALDERLAKE_P_N(i915) \ 570 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) 571 #define IS_RAPTORLAKE_P(i915) \ 572 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) 573 #define IS_RAPTORLAKE_U(i915) \ 574 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) 575 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \ 576 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00) 577 #define IS_BROADWELL_ULT(i915) \ 578 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 579 #define IS_BROADWELL_ULX(i915) \ 580 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 581 #define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \ 582 INTEL_INFO(i915)->gt == 3) 583 #define IS_HASWELL_ULT(i915) \ 584 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 585 #define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \ 586 INTEL_INFO(i915)->gt == 3) 587 #define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \ 588 INTEL_INFO(i915)->gt == 1) 589 /* ULX machines are also considered ULT. */ 590 #define IS_HASWELL_ULX(i915) \ 591 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 592 #define IS_SKYLAKE_ULT(i915) \ 593 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 594 #define IS_SKYLAKE_ULX(i915) \ 595 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 596 #define IS_KABYLAKE_ULT(i915) \ 597 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 598 #define IS_KABYLAKE_ULX(i915) \ 599 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 600 #define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \ 601 INTEL_INFO(i915)->gt == 2) 602 #define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \ 603 INTEL_INFO(i915)->gt == 3) 604 #define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \ 605 INTEL_INFO(i915)->gt == 4) 606 #define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \ 607 INTEL_INFO(i915)->gt == 2) 608 #define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \ 609 INTEL_INFO(i915)->gt == 3) 610 #define IS_COFFEELAKE_ULT(i915) \ 611 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 612 #define IS_COFFEELAKE_ULX(i915) \ 613 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 614 #define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \ 615 INTEL_INFO(i915)->gt == 2) 616 #define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \ 617 INTEL_INFO(i915)->gt == 3) 618 619 #define IS_COMETLAKE_ULT(i915) \ 620 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 621 #define IS_COMETLAKE_ULX(i915) \ 622 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 623 #define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \ 624 INTEL_INFO(i915)->gt == 2) 625 626 #define IS_ICL_WITH_PORT_F(i915) \ 627 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 628 629 #define IS_TIGERLAKE_UY(i915) \ 630 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) 631 632 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \ 633 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until)) 634 635 #define IS_PVC_BD_STEP(__i915, since, until) \ 636 (IS_PONTEVECCHIO(__i915) && \ 637 IS_BASEDIE_STEP(__i915, since, until)) 638 639 #define IS_PVC_CT_STEP(__i915, since, until) \ 640 (IS_PONTEVECCHIO(__i915) && \ 641 IS_GRAPHICS_STEP(__i915, since, until)) 642 643 #define IS_LP(i915) (INTEL_INFO(i915)->is_lp) 644 #define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915)) 645 #define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915)) 646 647 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) 648 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) 649 650 #define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \ 651 unsigned int first__ = (first); \ 652 unsigned int count__ = (count); \ 653 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \ 654 }) 655 656 #define ENGINE_INSTANCES_MASK(gt, first, count) \ 657 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count) 658 659 #define RCS_MASK(gt) \ 660 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS) 661 #define BCS_MASK(gt) \ 662 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS) 663 #define VDBOX_MASK(gt) \ 664 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) 665 #define VEBOX_MASK(gt) \ 666 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) 667 #define CCS_MASK(gt) \ 668 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) 669 670 #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode) 671 672 /* 673 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 674 * All later gens can run the final buffer from the ppgtt 675 */ 676 #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7) 677 678 #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc) 679 #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop) 680 #define HAS_EDRAM(i915) ((i915)->edram_size_mb) 681 #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6) 682 #define HAS_WT(i915) HAS_EDRAM(i915) 683 684 #define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical) 685 686 #define HAS_LOGICAL_RING_CONTEXTS(i915) \ 687 (INTEL_INFO(i915)->has_logical_ring_contexts) 688 #define HAS_LOGICAL_RING_ELSQ(i915) \ 689 (INTEL_INFO(i915)->has_logical_ring_elsq) 690 691 #define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915) 692 693 #define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type) 694 #define HAS_PPGTT(i915) \ 695 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE) 696 #define HAS_FULL_PPGTT(i915) \ 697 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL) 698 699 #define HAS_PAGE_SIZES(i915, sizes) ({ \ 700 GEM_BUG_ON((sizes) == 0); \ 701 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \ 702 }) 703 704 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 705 #define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915)) 706 707 #define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \ 708 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9) 709 710 /* WaRsDisableCoarsePowerGating:skl,cnl */ 711 #define NEEDS_WaRsDisableCoarsePowerGating(i915) \ 712 (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915)) 713 714 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 715 * rows, which changed the alignment requirements and fence programming. 716 */ 717 #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \ 718 !(IS_I915G(i915) || IS_I915GM(i915))) 719 720 #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6) 721 #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p) 722 #define HAS_RC6pp(i915) (false) /* HW was never validated */ 723 724 #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps) 725 726 #define HAS_HECI_PXP(i915) \ 727 (INTEL_INFO(i915)->has_heci_pxp) 728 729 #define HAS_HECI_GSCFI(i915) \ 730 (INTEL_INFO(i915)->has_heci_gscfi) 731 732 #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915)) 733 734 #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm) 735 #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc) 736 737 #define HAS_OA_BPC_REPORTING(i915) \ 738 (INTEL_INFO(i915)->has_oa_bpc_reporting) 739 #define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \ 740 (INTEL_INFO(i915)->has_oa_slice_contrib_limits) 741 #define HAS_OAM(i915) \ 742 (INTEL_INFO(i915)->has_oam) 743 744 /* 745 * Set this flag, when platform requires 64K GTT page sizes or larger for 746 * device local memory access. 747 */ 748 #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages) 749 750 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 751 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 752 753 #define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list) 754 755 /* 756 * Platform has the dedicated compression control state for each lmem surfaces 757 * stored in lmem to support the 3D and media compression formats. 758 */ 759 #define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs) 760 761 #define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc) 762 763 #define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu) 764 765 #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs) 766 767 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) 768 769 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read) 770 771 /* DPF == dynamic parity feature */ 772 #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf) 773 #define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \ 774 2 : HAS_L3_DPF(i915)) 775 776 #define HAS_GUC_DEPRIVILEGE(i915) \ 777 (INTEL_INFO(i915)->has_guc_deprivilege) 778 779 #define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation) 780 781 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) 782 783 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) 784 785 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \ 786 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 787 788 #endif 789