1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "display/intel_de.h" 29 #include "display/intel_display.h" 30 #include "display/intel_display_trace.h" 31 #include "display/intel_display_wa.h" 32 #include "display/skl_watermark.h" 33 34 #include "gt/intel_engine_regs.h" 35 #include "gt/intel_gt.h" 36 #include "gt/intel_gt_mcr.h" 37 #include "gt/intel_gt_regs.h" 38 39 #include "i915_drv.h" 40 #include "i915_reg.h" 41 #include "intel_clock_gating.h" 42 #include "intel_mchbar_regs.h" 43 #include "vlv_sideband.h" 44 45 struct drm_i915_clock_gating_funcs { 46 void (*init_clock_gating)(struct drm_i915_private *i915); 47 }; 48 49 static void gen9_init_clock_gating(struct drm_i915_private *i915) 50 { 51 if (HAS_LLC(i915)) { 52 /* 53 * WaCompressedResourceDisplayNewHashMode:skl,kbl 54 * Display WA #0390: skl,kbl 55 * 56 * Must match Sampler, Pixel Back End, and Media. See 57 * WaCompressedResourceSamplerPbeMediaNewHashMode. 58 */ 59 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE); 60 } 61 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */ 63 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP); 64 65 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */ 66 intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM); 67 68 /* 69 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl 70 * Display WA #0859: skl,bxt,kbl,glk,cfl 71 */ 72 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE); 73 } 74 75 static void bxt_init_clock_gating(struct drm_i915_private *i915) 76 { 77 gen9_init_clock_gating(i915); 78 79 /* WaDisableSDEUnitClockGating:bxt */ 80 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 81 82 /* 83 * FIXME: 84 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. 85 */ 86 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); 87 88 /* 89 * Wa: Backlight PWM may stop in the asserted state, causing backlight 90 * to stay fully on. 91 */ 92 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, 93 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | 94 PWM1_GATING_DIS | PWM2_GATING_DIS); 95 96 /* 97 * Lower the display internal timeout. 98 * This is needed to avoid any hard hangs when DSI port PLL 99 * is off and a MMIO access is attempted by any privilege 100 * application, using batch buffers or any other means. 101 */ 102 intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950)); 103 104 /* 105 * WaFbcTurnOffFbcWatermark:bxt 106 * Display WA #0562: bxt 107 */ 108 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 109 110 /* 111 * WaFbcHighMemBwCorruptionAvoidance:bxt 112 * Display WA #0883: bxt 113 */ 114 intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0); 115 } 116 117 static void glk_init_clock_gating(struct drm_i915_private *i915) 118 { 119 gen9_init_clock_gating(i915); 120 121 /* 122 * WaDisablePWMClockGating:glk 123 * Backlight PWM may stop in the asserted state, causing backlight 124 * to stay fully on. 125 */ 126 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, 127 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | 128 PWM1_GATING_DIS | PWM2_GATING_DIS); 129 } 130 131 static void ibx_init_clock_gating(struct drm_i915_private *i915) 132 { 133 /* 134 * On Ibex Peak and Cougar Point, we need to disable clock 135 * gating for the panel power sequencer or it will fail to 136 * start up when no ports are active. 137 */ 138 intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 139 } 140 141 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) 142 { 143 enum pipe pipe; 144 145 for_each_pipe(dev_priv, pipe) { 146 intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(pipe), 0, DISP_TRICKLE_FEED_DISABLE); 147 148 intel_uncore_rmw(&dev_priv->uncore, DSPSURF(pipe), 0, 0); 149 intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe)); 150 } 151 } 152 153 static void ilk_init_clock_gating(struct drm_i915_private *i915) 154 { 155 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 156 157 /* 158 * Required for FBC 159 * WaFbcDisableDpfcClockGating:ilk 160 */ 161 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 162 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 163 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 164 165 intel_uncore_write(&i915->uncore, PCH_3DCGDIS0, 166 MARIUNIT_CLOCK_GATE_DISABLE | 167 SVSMUNIT_CLOCK_GATE_DISABLE); 168 intel_uncore_write(&i915->uncore, PCH_3DCGDIS1, 169 VFMUNIT_CLOCK_GATE_DISABLE); 170 171 /* 172 * According to the spec the following bits should be set in 173 * order to enable memory self-refresh 174 * The bit 22/21 of 0x42004 175 * The bit 5 of 0x42020 176 * The bit 15 of 0x45000 177 */ 178 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, 179 (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | 180 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 181 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 182 intel_uncore_write(&i915->uncore, DISP_ARB_CTL, 183 (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) | 184 DISP_FBC_WM_DIS)); 185 186 /* 187 * Based on the document from hardware guys the following bits 188 * should be set unconditionally in order to enable FBC. 189 * The bit 22 of 0x42000 190 * The bit 22 of 0x42004 191 * The bit 7,8,9 of 0x42020. 192 */ 193 if (IS_IRONLAKE_M(i915)) { 194 /* WaFbcAsynchFlipDisableFbcQueue:ilk */ 195 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); 196 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE); 197 } 198 199 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); 200 201 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); 202 203 g4x_disable_trickle_feed(i915); 204 205 ibx_init_clock_gating(i915); 206 } 207 208 static void cpt_init_clock_gating(struct drm_i915_private *i915) 209 { 210 enum pipe pipe; 211 u32 val; 212 213 /* 214 * On Ibex Peak and Cougar Point, we need to disable clock 215 * gating for the panel power sequencer or it will fail to 216 * start up when no ports are active. 217 */ 218 intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 219 PCH_DPLUNIT_CLOCK_GATE_DISABLE | 220 PCH_CPUNIT_CLOCK_GATE_DISABLE); 221 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS); 222 /* The below fixes the weird display corruption, a few pixels shifted 223 * downward, on (only) LVDS of some HP laptops with IVY. 224 */ 225 for_each_pipe(i915, pipe) { 226 val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe)); 227 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 228 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 229 if (i915->display.vbt.fdi_rx_polarity_inverted) 230 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 231 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; 232 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; 233 intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val); 234 } 235 /* WADP0ClockGatingDisable */ 236 for_each_pipe(i915, pipe) { 237 intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe), 238 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 239 } 240 } 241 242 static void gen6_check_mch_setup(struct drm_i915_private *i915) 243 { 244 u32 tmp; 245 246 tmp = intel_uncore_read(&i915->uncore, MCH_SSKPD); 247 if (REG_FIELD_GET(SSKPD_WM0_MASK_SNB, tmp) != 12) 248 drm_dbg_kms(&i915->drm, 249 "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", 250 tmp); 251 } 252 253 static void gen6_init_clock_gating(struct drm_i915_private *i915) 254 { 255 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 256 257 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); 258 259 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); 260 261 intel_uncore_write(&i915->uncore, GEN6_UCGCTL1, 262 intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) | 263 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 264 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 265 266 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 267 * gating disable must be set. Failure to set it results in 268 * flickering pixels due to Z write ordering failures after 269 * some amount of runtime in the Mesa "fire" demo, and Unigine 270 * Sanctuary and Tropics, and apparently anything else with 271 * alpha test or pixel discard. 272 * 273 * According to the spec, bit 11 (RCCUNIT) must also be set, 274 * but we didn't debug actual testcases to find it out. 275 * 276 * WaDisableRCCUnitClockGating:snb 277 * WaDisableRCPBUnitClockGating:snb 278 */ 279 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, 280 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 281 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 282 283 /* 284 * According to the spec the following bits should be 285 * set in order to enable memory self-refresh and fbc: 286 * The bit21 and bit22 of 0x42000 287 * The bit21 and bit22 of 0x42004 288 * The bit5 and bit7 of 0x42020 289 * The bit14 of 0x70180 290 * The bit14 of 0x71180 291 * 292 * WaFbcAsynchFlipDisableFbcQueue:snb 293 */ 294 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1, 295 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) | 296 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 297 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, 298 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | 299 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 300 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, 301 intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) | 302 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 303 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 304 305 g4x_disable_trickle_feed(i915); 306 307 cpt_init_clock_gating(i915); 308 309 gen6_check_mch_setup(i915); 310 } 311 312 static void lpt_init_clock_gating(struct drm_i915_private *i915) 313 { 314 /* 315 * TODO: this bit should only be enabled when really needed, then 316 * disabled when not needed anymore in order to save power. 317 */ 318 if (HAS_PCH_LPT_LP(i915)) 319 intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 320 0, PCH_LP_PARTITION_LEVEL_DISABLE); 321 322 /* WADPOClockGatingDisable:hsw */ 323 intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A), 324 0, TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 325 } 326 327 static void gen8_set_l3sqc_credits(struct drm_i915_private *i915, 328 int general_prio_credits, 329 int high_prio_credits) 330 { 331 u32 misccpctl; 332 u32 val; 333 334 /* WaTempDisableDOPClkGating:bdw */ 335 misccpctl = intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, 336 GEN7_DOP_CLOCK_GATE_ENABLE, 0); 337 338 val = intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1); 339 val &= ~L3_PRIO_CREDITS_MASK; 340 val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits); 341 val |= L3_HIGH_PRIO_CREDITS(high_prio_credits); 342 intel_gt_mcr_multicast_write(to_gt(i915), GEN8_L3SQCREG1, val); 343 344 /* 345 * Wait at least 100 clocks before re-enabling clock gating. 346 * See the definition of L3SQCREG1 in BSpec. 347 */ 348 intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1); 349 udelay(1); 350 intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl); 351 } 352 353 static void xehpsdv_init_clock_gating(struct drm_i915_private *i915) 354 { 355 /* Wa_22010146351:xehpsdv */ 356 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 357 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS); 358 } 359 360 static void dg2_init_clock_gating(struct drm_i915_private *i915) 361 { 362 /* Wa_22010954014:dg2 */ 363 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, 364 SGSI_SIDECLK_DIS); 365 366 /* 367 * Wa_14010733611:dg2_g10 368 * Wa_22010146351:dg2_g10 369 */ 370 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) 371 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, 372 SGR_DIS | SGGI_DIS); 373 } 374 375 static void pvc_init_clock_gating(struct drm_i915_private *i915) 376 { 377 /* Wa_14012385139:pvc */ 378 if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0)) 379 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS); 380 381 /* Wa_22010954014:pvc */ 382 if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0)) 383 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 384 } 385 386 static void cnp_init_clock_gating(struct drm_i915_private *i915) 387 { 388 if (!HAS_PCH_CNP(i915)) 389 return; 390 391 /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */ 392 intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE); 393 } 394 395 static void cfl_init_clock_gating(struct drm_i915_private *i915) 396 { 397 cnp_init_clock_gating(i915); 398 gen9_init_clock_gating(i915); 399 400 /* WAC6entrylatency:cfl */ 401 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); 402 403 /* 404 * WaFbcTurnOffFbcWatermark:cfl 405 * Display WA #0562: cfl 406 */ 407 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 408 409 /* 410 * WaFbcNukeOnHostModify:cfl 411 * Display WA #0873: cfl 412 */ 413 intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 414 0, DPFC_NUKE_ON_ANY_MODIFICATION); 415 } 416 417 static void kbl_init_clock_gating(struct drm_i915_private *i915) 418 { 419 gen9_init_clock_gating(i915); 420 421 /* WAC6entrylatency:kbl */ 422 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); 423 424 /* WaDisableSDEUnitClockGating:kbl */ 425 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) 426 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 427 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 428 429 /* WaDisableGamClockGating:kbl */ 430 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) 431 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 432 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE); 433 434 /* 435 * WaFbcTurnOffFbcWatermark:kbl 436 * Display WA #0562: kbl 437 */ 438 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 439 440 /* 441 * WaFbcNukeOnHostModify:kbl 442 * Display WA #0873: kbl 443 */ 444 intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 445 0, DPFC_NUKE_ON_ANY_MODIFICATION); 446 } 447 448 static void skl_init_clock_gating(struct drm_i915_private *i915) 449 { 450 gen9_init_clock_gating(i915); 451 452 /* WaDisableDopClockGating:skl */ 453 intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, 454 GEN7_DOP_CLOCK_GATE_ENABLE, 0); 455 456 /* WAC6entrylatency:skl */ 457 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); 458 459 /* 460 * WaFbcTurnOffFbcWatermark:skl 461 * Display WA #0562: skl 462 */ 463 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 464 465 /* 466 * WaFbcNukeOnHostModify:skl 467 * Display WA #0873: skl 468 */ 469 intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 470 0, DPFC_NUKE_ON_ANY_MODIFICATION); 471 472 /* 473 * WaFbcHighMemBwCorruptionAvoidance:skl 474 * Display WA #0883: skl 475 */ 476 intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0); 477 } 478 479 static void bdw_init_clock_gating(struct drm_i915_private *i915) 480 { 481 enum pipe pipe; 482 483 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 484 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); 485 486 /* WaSwitchSolVfFArbitrationPriority:bdw */ 487 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); 488 489 /* WaPsrDPAMaskVBlankInSRD:bdw */ 490 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); 491 492 for_each_pipe(i915, pipe) { 493 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 494 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), 495 0, BDW_UNMASK_VBL_TO_REGS_IN_SRD); 496 } 497 498 /* WaVSRefCountFullforceMissDisable:bdw */ 499 /* WaDSRefCountFullforceMissDisable:bdw */ 500 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE, 501 GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0); 502 503 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), 504 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 505 506 /* WaDisableSDEUnitClockGating:bdw */ 507 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 508 509 /* WaProgramL3SqcReg1Default:bdw */ 510 gen8_set_l3sqc_credits(i915, 30, 2); 511 512 /* WaKVMNotificationOnConfigChange:bdw */ 513 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1, 514 0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); 515 516 lpt_init_clock_gating(i915); 517 518 /* WaDisableDopClockGating:bdw 519 * 520 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP 521 * clock gating. 522 */ 523 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); 524 } 525 526 static void hsw_init_clock_gating(struct drm_i915_private *i915) 527 { 528 enum pipe pipe; 529 530 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 531 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); 532 533 /* WaPsrDPAMaskVBlankInSRD:hsw */ 534 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); 535 536 for_each_pipe(i915, pipe) { 537 /* WaPsrDPRSUnmaskVBlankInSRD:hsw */ 538 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), 539 0, HSW_UNMASK_VBL_TO_REGS_IN_SRD); 540 } 541 542 /* This is required by WaCatErrorRejectionIssue:hsw */ 543 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 544 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 545 546 /* WaSwitchSolVfFArbitrationPriority:hsw */ 547 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); 548 549 lpt_init_clock_gating(i915); 550 } 551 552 static void ivb_init_clock_gating(struct drm_i915_private *i915) 553 { 554 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 555 556 /* WaFbcAsynchFlipDisableFbcQueue:ivb */ 557 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); 558 559 /* WaDisableBackToBackFlipFix:ivb */ 560 intel_uncore_write(&i915->uncore, IVB_CHICKEN3, 561 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 562 CHICKEN3_DGMG_DONE_FIX_DISABLE); 563 564 if (IS_IVB_GT1(i915)) 565 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, 566 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 567 else { 568 /* must write both registers */ 569 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, 570 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 571 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2_GT2, 572 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 573 } 574 575 /* 576 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 577 * This implements the WaDisableRCZUnitClockGating:ivb workaround. 578 */ 579 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, 580 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 581 582 /* This is required by WaCatErrorRejectionIssue:ivb */ 583 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 584 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 585 586 g4x_disable_trickle_feed(i915); 587 588 intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK, 589 GEN6_MBC_SNPCR_MED); 590 591 if (!HAS_PCH_NOP(i915)) 592 cpt_init_clock_gating(i915); 593 594 gen6_check_mch_setup(i915); 595 } 596 597 static void vlv_init_clock_gating(struct drm_i915_private *i915) 598 { 599 /* WaDisableBackToBackFlipFix:vlv */ 600 intel_uncore_write(&i915->uncore, IVB_CHICKEN3, 601 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 602 CHICKEN3_DGMG_DONE_FIX_DISABLE); 603 604 /* WaDisableDopClockGating:vlv */ 605 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, 606 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 607 608 /* This is required by WaCatErrorRejectionIssue:vlv */ 609 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 610 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 611 612 /* 613 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 614 * This implements the WaDisableRCZUnitClockGating:vlv workaround. 615 */ 616 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, 617 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 618 619 /* WaDisableL3Bank2xClockGate:vlv 620 * Disabling L3 clock gating- MMIO 940c[25] = 1 621 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ 622 intel_uncore_rmw(&i915->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 623 624 /* 625 * WaDisableVLVClockGating_VBIIssue:vlv 626 * Disable clock gating on th GCFG unit to prevent a delay 627 * in the reporting of vblank events. 628 */ 629 intel_uncore_write(&i915->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 630 } 631 632 static void chv_init_clock_gating(struct drm_i915_private *i915) 633 { 634 /* WaVSRefCountFullforceMissDisable:chv */ 635 /* WaDSRefCountFullforceMissDisable:chv */ 636 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE, 637 GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0); 638 639 /* WaDisableSemaphoreAndSyncFlipWait:chv */ 640 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), 641 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 642 643 /* WaDisableCSUnitClockGating:chv */ 644 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE); 645 646 /* WaDisableSDEUnitClockGating:chv */ 647 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 648 649 /* 650 * WaProgramL3SqcReg1Default:chv 651 * See gfxspecs/Related Documents/Performance Guide/ 652 * LSQC Setting Recommendations. 653 */ 654 gen8_set_l3sqc_credits(i915, 38, 2); 655 } 656 657 static void g4x_init_clock_gating(struct drm_i915_private *i915) 658 { 659 u32 dspclk_gate; 660 661 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0); 662 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 663 GS_UNIT_CLOCK_GATE_DISABLE | 664 CL_UNIT_CLOCK_GATE_DISABLE); 665 intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0); 666 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 667 OVRUNIT_CLOCK_GATE_DISABLE | 668 OVCUNIT_CLOCK_GATE_DISABLE; 669 if (IS_GM45(i915)) 670 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 671 intel_uncore_write(&i915->uncore, DSPCLK_GATE_D(i915), dspclk_gate); 672 673 g4x_disable_trickle_feed(i915); 674 } 675 676 static void i965gm_init_clock_gating(struct drm_i915_private *i915) 677 { 678 struct intel_uncore *uncore = &i915->uncore; 679 680 intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 681 intel_uncore_write(uncore, RENCLK_GATE_D2, 0); 682 intel_uncore_write(uncore, DSPCLK_GATE_D(i915), 0); 683 intel_uncore_write(uncore, RAMCLK_GATE_D, 0); 684 intel_uncore_write16(uncore, DEUC, 0); 685 intel_uncore_write(uncore, 686 MI_ARB_STATE, 687 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 688 } 689 690 static void i965g_init_clock_gating(struct drm_i915_private *i915) 691 { 692 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 693 I965_RCC_CLOCK_GATE_DISABLE | 694 I965_RCPB_CLOCK_GATE_DISABLE | 695 I965_ISC_CLOCK_GATE_DISABLE | 696 I965_FBC_CLOCK_GATE_DISABLE); 697 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, 0); 698 intel_uncore_write(&i915->uncore, MI_ARB_STATE, 699 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 700 } 701 702 static void gen3_init_clock_gating(struct drm_i915_private *i915) 703 { 704 u32 dstate = intel_uncore_read(&i915->uncore, D_STATE); 705 706 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 707 DSTATE_DOT_CLOCK_GATING; 708 intel_uncore_write(&i915->uncore, D_STATE, dstate); 709 710 if (IS_PINEVIEW(i915)) 711 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), 712 _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 713 714 /* IIR "flip pending" means done if this bit is set */ 715 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), 716 _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 717 718 /* interrupts should cause a wake up from C3 */ 719 intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); 720 721 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 722 intel_uncore_write(&i915->uncore, MI_ARB_STATE, 723 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 724 725 intel_uncore_write(&i915->uncore, MI_ARB_STATE, 726 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 727 } 728 729 static void i85x_init_clock_gating(struct drm_i915_private *i915) 730 { 731 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 732 733 /* interrupts should cause a wake up from C3 */ 734 intel_uncore_write(&i915->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | 735 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); 736 737 intel_uncore_write(&i915->uncore, MEM_MODE, 738 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); 739 740 /* 741 * Have FBC ignore 3D activity since we use software 742 * render tracking, and otherwise a pure 3D workload 743 * (even if it just renders a single frame and then does 744 * abosultely nothing) would not allow FBC to recompress 745 * until a 2D blit occurs. 746 */ 747 intel_uncore_write(&i915->uncore, SCPD0, 748 _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D)); 749 } 750 751 static void i830_init_clock_gating(struct drm_i915_private *i915) 752 { 753 intel_uncore_write(&i915->uncore, MEM_MODE, 754 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | 755 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); 756 } 757 758 void intel_clock_gating_init(struct drm_i915_private *i915) 759 { 760 i915->clock_gating_funcs->init_clock_gating(i915); 761 762 intel_display_wa_apply(i915); 763 } 764 765 static void nop_init_clock_gating(struct drm_i915_private *i915) 766 { 767 drm_dbg_kms(&i915->drm, 768 "No clock gating settings or workarounds applied.\n"); 769 } 770 771 #define CG_FUNCS(platform) \ 772 static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs = { \ 773 .init_clock_gating = platform##_init_clock_gating, \ 774 } 775 776 CG_FUNCS(pvc); 777 CG_FUNCS(dg2); 778 CG_FUNCS(xehpsdv); 779 CG_FUNCS(cfl); 780 CG_FUNCS(skl); 781 CG_FUNCS(kbl); 782 CG_FUNCS(bxt); 783 CG_FUNCS(glk); 784 CG_FUNCS(bdw); 785 CG_FUNCS(chv); 786 CG_FUNCS(hsw); 787 CG_FUNCS(ivb); 788 CG_FUNCS(vlv); 789 CG_FUNCS(gen6); 790 CG_FUNCS(ilk); 791 CG_FUNCS(g4x); 792 CG_FUNCS(i965gm); 793 CG_FUNCS(i965g); 794 CG_FUNCS(gen3); 795 CG_FUNCS(i85x); 796 CG_FUNCS(i830); 797 CG_FUNCS(nop); 798 #undef CG_FUNCS 799 800 /** 801 * intel_clock_gating_hooks_init - setup the clock gating hooks 802 * @i915: device private 803 * 804 * Setup the hooks that configure which clocks of a given platform can be 805 * gated and also apply various GT and display specific workarounds for these 806 * platforms. Note that some GT specific workarounds are applied separately 807 * when GPU contexts or batchbuffers start their execution. 808 */ 809 void intel_clock_gating_hooks_init(struct drm_i915_private *i915) 810 { 811 if (IS_PONTEVECCHIO(i915)) 812 i915->clock_gating_funcs = &pvc_clock_gating_funcs; 813 else if (IS_DG2(i915)) 814 i915->clock_gating_funcs = &dg2_clock_gating_funcs; 815 else if (IS_XEHPSDV(i915)) 816 i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs; 817 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 818 i915->clock_gating_funcs = &cfl_clock_gating_funcs; 819 else if (IS_SKYLAKE(i915)) 820 i915->clock_gating_funcs = &skl_clock_gating_funcs; 821 else if (IS_KABYLAKE(i915)) 822 i915->clock_gating_funcs = &kbl_clock_gating_funcs; 823 else if (IS_BROXTON(i915)) 824 i915->clock_gating_funcs = &bxt_clock_gating_funcs; 825 else if (IS_GEMINILAKE(i915)) 826 i915->clock_gating_funcs = &glk_clock_gating_funcs; 827 else if (IS_BROADWELL(i915)) 828 i915->clock_gating_funcs = &bdw_clock_gating_funcs; 829 else if (IS_CHERRYVIEW(i915)) 830 i915->clock_gating_funcs = &chv_clock_gating_funcs; 831 else if (IS_HASWELL(i915)) 832 i915->clock_gating_funcs = &hsw_clock_gating_funcs; 833 else if (IS_IVYBRIDGE(i915)) 834 i915->clock_gating_funcs = &ivb_clock_gating_funcs; 835 else if (IS_VALLEYVIEW(i915)) 836 i915->clock_gating_funcs = &vlv_clock_gating_funcs; 837 else if (GRAPHICS_VER(i915) == 6) 838 i915->clock_gating_funcs = &gen6_clock_gating_funcs; 839 else if (GRAPHICS_VER(i915) == 5) 840 i915->clock_gating_funcs = &ilk_clock_gating_funcs; 841 else if (IS_G4X(i915)) 842 i915->clock_gating_funcs = &g4x_clock_gating_funcs; 843 else if (IS_I965GM(i915)) 844 i915->clock_gating_funcs = &i965gm_clock_gating_funcs; 845 else if (IS_I965G(i915)) 846 i915->clock_gating_funcs = &i965g_clock_gating_funcs; 847 else if (GRAPHICS_VER(i915) == 3) 848 i915->clock_gating_funcs = &gen3_clock_gating_funcs; 849 else if (IS_I85X(i915) || IS_I865G(i915)) 850 i915->clock_gating_funcs = &i85x_clock_gating_funcs; 851 else if (GRAPHICS_VER(i915) == 2) 852 i915->clock_gating_funcs = &i830_clock_gating_funcs; 853 else 854 i915->clock_gating_funcs = &nop_clock_gating_funcs; 855 } 856