1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "display/intel_de.h" 29 #include "display/intel_display.h" 30 #include "display/intel_display_trace.h" 31 #include "display/skl_watermark.h" 32 33 #include "gt/intel_engine_regs.h" 34 #include "gt/intel_gt.h" 35 #include "gt/intel_gt_mcr.h" 36 #include "gt/intel_gt_regs.h" 37 38 #include "i915_drv.h" 39 #include "i915_reg.h" 40 #include "intel_clock_gating.h" 41 #include "intel_mchbar_regs.h" 42 #include "vlv_sideband.h" 43 44 struct drm_i915_clock_gating_funcs { 45 void (*init_clock_gating)(struct drm_i915_private *i915); 46 }; 47 48 static void gen9_init_clock_gating(struct drm_i915_private *i915) 49 { 50 if (HAS_LLC(i915)) { 51 /* 52 * WaCompressedResourceDisplayNewHashMode:skl,kbl 53 * Display WA #0390: skl,kbl 54 * 55 * Must match Sampler, Pixel Back End, and Media. See 56 * WaCompressedResourceSamplerPbeMediaNewHashMode. 57 */ 58 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE); 59 } 60 61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */ 62 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP); 63 64 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */ 65 intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM); 66 67 /* 68 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl 69 * Display WA #0859: skl,bxt,kbl,glk,cfl 70 */ 71 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE); 72 } 73 74 static void bxt_init_clock_gating(struct drm_i915_private *i915) 75 { 76 gen9_init_clock_gating(i915); 77 78 /* WaDisableSDEUnitClockGating:bxt */ 79 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 80 81 /* 82 * FIXME: 83 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. 84 */ 85 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); 86 87 /* 88 * Wa: Backlight PWM may stop in the asserted state, causing backlight 89 * to stay fully on. 90 */ 91 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, 92 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | 93 PWM1_GATING_DIS | PWM2_GATING_DIS); 94 95 /* 96 * Lower the display internal timeout. 97 * This is needed to avoid any hard hangs when DSI port PLL 98 * is off and a MMIO access is attempted by any privilege 99 * application, using batch buffers or any other means. 100 */ 101 intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950)); 102 103 /* 104 * WaFbcTurnOffFbcWatermark:bxt 105 * Display WA #0562: bxt 106 */ 107 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 108 } 109 110 static void glk_init_clock_gating(struct drm_i915_private *i915) 111 { 112 gen9_init_clock_gating(i915); 113 114 /* 115 * WaDisablePWMClockGating:glk 116 * Backlight PWM may stop in the asserted state, causing backlight 117 * to stay fully on. 118 */ 119 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0, 120 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | 121 PWM1_GATING_DIS | PWM2_GATING_DIS); 122 } 123 124 static void ibx_init_clock_gating(struct drm_i915_private *i915) 125 { 126 /* 127 * On Ibex Peak and Cougar Point, we need to disable clock 128 * gating for the panel power sequencer or it will fail to 129 * start up when no ports are active. 130 */ 131 intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 132 } 133 134 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) 135 { 136 enum pipe pipe; 137 138 for_each_pipe(dev_priv, pipe) { 139 intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(pipe), 0, DISP_TRICKLE_FEED_DISABLE); 140 141 intel_uncore_rmw(&dev_priv->uncore, DSPSURF(pipe), 0, 0); 142 intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe)); 143 } 144 } 145 146 static void ilk_init_clock_gating(struct drm_i915_private *i915) 147 { 148 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 149 150 /* 151 * Required for FBC 152 * WaFbcDisableDpfcClockGating:ilk 153 */ 154 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 155 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 156 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 157 158 intel_uncore_write(&i915->uncore, PCH_3DCGDIS0, 159 MARIUNIT_CLOCK_GATE_DISABLE | 160 SVSMUNIT_CLOCK_GATE_DISABLE); 161 intel_uncore_write(&i915->uncore, PCH_3DCGDIS1, 162 VFMUNIT_CLOCK_GATE_DISABLE); 163 164 /* 165 * According to the spec the following bits should be set in 166 * order to enable memory self-refresh 167 * The bit 22/21 of 0x42004 168 * The bit 5 of 0x42020 169 * The bit 15 of 0x45000 170 */ 171 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, 172 (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | 173 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 174 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 175 intel_uncore_write(&i915->uncore, DISP_ARB_CTL, 176 (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) | 177 DISP_FBC_WM_DIS)); 178 179 /* 180 * Based on the document from hardware guys the following bits 181 * should be set unconditionally in order to enable FBC. 182 * The bit 22 of 0x42000 183 * The bit 22 of 0x42004 184 * The bit 7,8,9 of 0x42020. 185 */ 186 if (IS_IRONLAKE_M(i915)) { 187 /* WaFbcAsynchFlipDisableFbcQueue:ilk */ 188 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); 189 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE); 190 } 191 192 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); 193 194 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); 195 196 g4x_disable_trickle_feed(i915); 197 198 ibx_init_clock_gating(i915); 199 } 200 201 static void cpt_init_clock_gating(struct drm_i915_private *i915) 202 { 203 enum pipe pipe; 204 u32 val; 205 206 /* 207 * On Ibex Peak and Cougar Point, we need to disable clock 208 * gating for the panel power sequencer or it will fail to 209 * start up when no ports are active. 210 */ 211 intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 212 PCH_DPLUNIT_CLOCK_GATE_DISABLE | 213 PCH_CPUNIT_CLOCK_GATE_DISABLE); 214 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS); 215 /* The below fixes the weird display corruption, a few pixels shifted 216 * downward, on (only) LVDS of some HP laptops with IVY. 217 */ 218 for_each_pipe(i915, pipe) { 219 val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe)); 220 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 221 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 222 if (i915->display.vbt.fdi_rx_polarity_inverted) 223 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 224 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; 225 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; 226 intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val); 227 } 228 /* WADP0ClockGatingDisable */ 229 for_each_pipe(i915, pipe) { 230 intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe), 231 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 232 } 233 } 234 235 static void gen6_check_mch_setup(struct drm_i915_private *i915) 236 { 237 u32 tmp; 238 239 tmp = intel_uncore_read(&i915->uncore, MCH_SSKPD); 240 if (REG_FIELD_GET(SSKPD_WM0_MASK_SNB, tmp) != 12) 241 drm_dbg_kms(&i915->drm, 242 "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", 243 tmp); 244 } 245 246 static void gen6_init_clock_gating(struct drm_i915_private *i915) 247 { 248 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 249 250 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate); 251 252 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT); 253 254 intel_uncore_write(&i915->uncore, GEN6_UCGCTL1, 255 intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) | 256 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 257 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 258 259 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 260 * gating disable must be set. Failure to set it results in 261 * flickering pixels due to Z write ordering failures after 262 * some amount of runtime in the Mesa "fire" demo, and Unigine 263 * Sanctuary and Tropics, and apparently anything else with 264 * alpha test or pixel discard. 265 * 266 * According to the spec, bit 11 (RCCUNIT) must also be set, 267 * but we didn't debug actual testcases to find it out. 268 * 269 * WaDisableRCCUnitClockGating:snb 270 * WaDisableRCPBUnitClockGating:snb 271 */ 272 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, 273 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 274 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 275 276 /* 277 * According to the spec the following bits should be 278 * set in order to enable memory self-refresh and fbc: 279 * The bit21 and bit22 of 0x42000 280 * The bit21 and bit22 of 0x42004 281 * The bit5 and bit7 of 0x42020 282 * The bit14 of 0x70180 283 * The bit14 of 0x71180 284 * 285 * WaFbcAsynchFlipDisableFbcQueue:snb 286 */ 287 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1, 288 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) | 289 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 290 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2, 291 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | 292 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 293 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, 294 intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) | 295 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 296 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 297 298 g4x_disable_trickle_feed(i915); 299 300 cpt_init_clock_gating(i915); 301 302 gen6_check_mch_setup(i915); 303 } 304 305 static void lpt_init_clock_gating(struct drm_i915_private *i915) 306 { 307 /* 308 * TODO: this bit should only be enabled when really needed, then 309 * disabled when not needed anymore in order to save power. 310 */ 311 if (HAS_PCH_LPT_LP(i915)) 312 intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 313 0, PCH_LP_PARTITION_LEVEL_DISABLE); 314 315 /* WADPOClockGatingDisable:hsw */ 316 intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A), 317 0, TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 318 } 319 320 static void gen8_set_l3sqc_credits(struct drm_i915_private *i915, 321 int general_prio_credits, 322 int high_prio_credits) 323 { 324 u32 misccpctl; 325 u32 val; 326 327 /* WaTempDisableDOPClkGating:bdw */ 328 misccpctl = intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, 329 GEN7_DOP_CLOCK_GATE_ENABLE, 0); 330 331 val = intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1); 332 val &= ~L3_PRIO_CREDITS_MASK; 333 val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits); 334 val |= L3_HIGH_PRIO_CREDITS(high_prio_credits); 335 intel_gt_mcr_multicast_write(to_gt(i915), GEN8_L3SQCREG1, val); 336 337 /* 338 * Wait at least 100 clocks before re-enabling clock gating. 339 * See the definition of L3SQCREG1 in BSpec. 340 */ 341 intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1); 342 udelay(1); 343 intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl); 344 } 345 346 static void xehpsdv_init_clock_gating(struct drm_i915_private *i915) 347 { 348 /* Wa_22010146351:xehpsdv */ 349 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 350 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS); 351 } 352 353 static void dg2_init_clock_gating(struct drm_i915_private *i915) 354 { 355 /* Wa_22010954014:dg2 */ 356 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, 357 SGSI_SIDECLK_DIS); 358 } 359 360 static void pvc_init_clock_gating(struct drm_i915_private *i915) 361 { 362 /* Wa_14012385139:pvc */ 363 if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0)) 364 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS); 365 366 /* Wa_22010954014:pvc */ 367 if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0)) 368 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); 369 } 370 371 static void cnp_init_clock_gating(struct drm_i915_private *i915) 372 { 373 if (!HAS_PCH_CNP(i915)) 374 return; 375 376 /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */ 377 intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE); 378 } 379 380 static void cfl_init_clock_gating(struct drm_i915_private *i915) 381 { 382 cnp_init_clock_gating(i915); 383 gen9_init_clock_gating(i915); 384 385 /* WAC6entrylatency:cfl */ 386 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); 387 388 /* 389 * WaFbcTurnOffFbcWatermark:cfl 390 * Display WA #0562: cfl 391 */ 392 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 393 } 394 395 static void kbl_init_clock_gating(struct drm_i915_private *i915) 396 { 397 gen9_init_clock_gating(i915); 398 399 /* WAC6entrylatency:kbl */ 400 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); 401 402 /* WaDisableSDEUnitClockGating:kbl */ 403 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) 404 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 405 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 406 407 /* WaDisableGamClockGating:kbl */ 408 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) 409 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 410 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE); 411 412 /* 413 * WaFbcTurnOffFbcWatermark:kbl 414 * Display WA #0562: kbl 415 */ 416 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 417 } 418 419 static void skl_init_clock_gating(struct drm_i915_private *i915) 420 { 421 gen9_init_clock_gating(i915); 422 423 /* WaDisableDopClockGating:skl */ 424 intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL, 425 GEN7_DOP_CLOCK_GATE_ENABLE, 0); 426 427 /* WAC6entrylatency:skl */ 428 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN); 429 430 /* 431 * WaFbcTurnOffFbcWatermark:skl 432 * Display WA #0562: skl 433 */ 434 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS); 435 } 436 437 static void bdw_init_clock_gating(struct drm_i915_private *i915) 438 { 439 enum pipe pipe; 440 441 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 442 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); 443 444 /* WaSwitchSolVfFArbitrationPriority:bdw */ 445 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); 446 447 /* WaPsrDPAMaskVBlankInSRD:bdw */ 448 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); 449 450 for_each_pipe(i915, pipe) { 451 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 452 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), 453 0, BDW_UNMASK_VBL_TO_REGS_IN_SRD); 454 } 455 456 /* WaVSRefCountFullforceMissDisable:bdw */ 457 /* WaDSRefCountFullforceMissDisable:bdw */ 458 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE, 459 GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0); 460 461 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), 462 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 463 464 /* WaDisableSDEUnitClockGating:bdw */ 465 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 466 467 /* WaProgramL3SqcReg1Default:bdw */ 468 gen8_set_l3sqc_credits(i915, 30, 2); 469 470 /* WaKVMNotificationOnConfigChange:bdw */ 471 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1, 472 0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); 473 474 lpt_init_clock_gating(i915); 475 476 /* WaDisableDopClockGating:bdw 477 * 478 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP 479 * clock gating. 480 */ 481 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); 482 } 483 484 static void hsw_init_clock_gating(struct drm_i915_private *i915) 485 { 486 enum pipe pipe; 487 488 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ 489 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); 490 491 /* WaPsrDPAMaskVBlankInSRD:hsw */ 492 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); 493 494 for_each_pipe(i915, pipe) { 495 /* WaPsrDPRSUnmaskVBlankInSRD:hsw */ 496 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), 497 0, HSW_UNMASK_VBL_TO_REGS_IN_SRD); 498 } 499 500 /* This is required by WaCatErrorRejectionIssue:hsw */ 501 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 502 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 503 504 /* WaSwitchSolVfFArbitrationPriority:hsw */ 505 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL); 506 507 lpt_init_clock_gating(i915); 508 } 509 510 static void ivb_init_clock_gating(struct drm_i915_private *i915) 511 { 512 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 513 514 /* WaFbcAsynchFlipDisableFbcQueue:ivb */ 515 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS); 516 517 /* WaDisableBackToBackFlipFix:ivb */ 518 intel_uncore_write(&i915->uncore, IVB_CHICKEN3, 519 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 520 CHICKEN3_DGMG_DONE_FIX_DISABLE); 521 522 if (IS_IVB_GT1(i915)) 523 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, 524 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 525 else { 526 /* must write both registers */ 527 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, 528 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 529 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2_GT2, 530 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 531 } 532 533 /* 534 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 535 * This implements the WaDisableRCZUnitClockGating:ivb workaround. 536 */ 537 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, 538 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 539 540 /* This is required by WaCatErrorRejectionIssue:ivb */ 541 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 542 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 543 544 g4x_disable_trickle_feed(i915); 545 546 intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK, 547 GEN6_MBC_SNPCR_MED); 548 549 if (!HAS_PCH_NOP(i915)) 550 cpt_init_clock_gating(i915); 551 552 gen6_check_mch_setup(i915); 553 } 554 555 static void vlv_init_clock_gating(struct drm_i915_private *i915) 556 { 557 /* WaDisableBackToBackFlipFix:vlv */ 558 intel_uncore_write(&i915->uncore, IVB_CHICKEN3, 559 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 560 CHICKEN3_DGMG_DONE_FIX_DISABLE); 561 562 /* WaDisableDopClockGating:vlv */ 563 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2, 564 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 565 566 /* This is required by WaCatErrorRejectionIssue:vlv */ 567 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 568 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 569 570 /* 571 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 572 * This implements the WaDisableRCZUnitClockGating:vlv workaround. 573 */ 574 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2, 575 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 576 577 /* WaDisableL3Bank2xClockGate:vlv 578 * Disabling L3 clock gating- MMIO 940c[25] = 1 579 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ 580 intel_uncore_rmw(&i915->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 581 582 /* 583 * WaDisableVLVClockGating_VBIIssue:vlv 584 * Disable clock gating on th GCFG unit to prevent a delay 585 * in the reporting of vblank events. 586 */ 587 intel_uncore_write(&i915->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 588 } 589 590 static void chv_init_clock_gating(struct drm_i915_private *i915) 591 { 592 /* WaVSRefCountFullforceMissDisable:chv */ 593 /* WaDSRefCountFullforceMissDisable:chv */ 594 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE, 595 GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0); 596 597 /* WaDisableSemaphoreAndSyncFlipWait:chv */ 598 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), 599 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 600 601 /* WaDisableCSUnitClockGating:chv */ 602 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE); 603 604 /* WaDisableSDEUnitClockGating:chv */ 605 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 606 607 /* 608 * WaProgramL3SqcReg1Default:chv 609 * See gfxspecs/Related Documents/Performance Guide/ 610 * LSQC Setting Recommendations. 611 */ 612 gen8_set_l3sqc_credits(i915, 38, 2); 613 } 614 615 static void g4x_init_clock_gating(struct drm_i915_private *i915) 616 { 617 u32 dspclk_gate; 618 619 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0); 620 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 621 GS_UNIT_CLOCK_GATE_DISABLE | 622 CL_UNIT_CLOCK_GATE_DISABLE); 623 intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0); 624 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 625 OVRUNIT_CLOCK_GATE_DISABLE | 626 OVCUNIT_CLOCK_GATE_DISABLE; 627 if (IS_GM45(i915)) 628 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 629 intel_uncore_write(&i915->uncore, DSPCLK_GATE_D(i915), dspclk_gate); 630 631 g4x_disable_trickle_feed(i915); 632 } 633 634 static void i965gm_init_clock_gating(struct drm_i915_private *i915) 635 { 636 struct intel_uncore *uncore = &i915->uncore; 637 638 intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 639 intel_uncore_write(uncore, RENCLK_GATE_D2, 0); 640 intel_uncore_write(uncore, DSPCLK_GATE_D(i915), 0); 641 intel_uncore_write(uncore, RAMCLK_GATE_D, 0); 642 intel_uncore_write16(uncore, DEUC, 0); 643 intel_uncore_write(uncore, 644 MI_ARB_STATE, 645 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 646 } 647 648 static void i965g_init_clock_gating(struct drm_i915_private *i915) 649 { 650 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 651 I965_RCC_CLOCK_GATE_DISABLE | 652 I965_RCPB_CLOCK_GATE_DISABLE | 653 I965_ISC_CLOCK_GATE_DISABLE | 654 I965_FBC_CLOCK_GATE_DISABLE); 655 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, 0); 656 intel_uncore_write(&i915->uncore, MI_ARB_STATE, 657 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 658 } 659 660 static void gen3_init_clock_gating(struct drm_i915_private *i915) 661 { 662 u32 dstate = intel_uncore_read(&i915->uncore, D_STATE); 663 664 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 665 DSTATE_DOT_CLOCK_GATING; 666 intel_uncore_write(&i915->uncore, D_STATE, dstate); 667 668 if (IS_PINEVIEW(i915)) 669 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), 670 _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 671 672 /* IIR "flip pending" means done if this bit is set */ 673 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE), 674 _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 675 676 /* interrupts should cause a wake up from C3 */ 677 intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); 678 679 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 680 intel_uncore_write(&i915->uncore, MI_ARB_STATE, 681 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 682 683 intel_uncore_write(&i915->uncore, MI_ARB_STATE, 684 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 685 } 686 687 static void i85x_init_clock_gating(struct drm_i915_private *i915) 688 { 689 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 690 691 /* interrupts should cause a wake up from C3 */ 692 intel_uncore_write(&i915->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | 693 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); 694 695 intel_uncore_write(&i915->uncore, MEM_MODE, 696 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); 697 698 /* 699 * Have FBC ignore 3D activity since we use software 700 * render tracking, and otherwise a pure 3D workload 701 * (even if it just renders a single frame and then does 702 * abosultely nothing) would not allow FBC to recompress 703 * until a 2D blit occurs. 704 */ 705 intel_uncore_write(&i915->uncore, SCPD0, 706 _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D)); 707 } 708 709 static void i830_init_clock_gating(struct drm_i915_private *i915) 710 { 711 intel_uncore_write(&i915->uncore, MEM_MODE, 712 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | 713 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); 714 } 715 716 void intel_clock_gating_init(struct drm_i915_private *i915) 717 { 718 i915->clock_gating_funcs->init_clock_gating(i915); 719 } 720 721 static void nop_init_clock_gating(struct drm_i915_private *i915) 722 { 723 drm_dbg_kms(&i915->drm, 724 "No clock gating settings or workarounds applied.\n"); 725 } 726 727 #define CG_FUNCS(platform) \ 728 static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs = { \ 729 .init_clock_gating = platform##_init_clock_gating, \ 730 } 731 732 CG_FUNCS(pvc); 733 CG_FUNCS(dg2); 734 CG_FUNCS(xehpsdv); 735 CG_FUNCS(cfl); 736 CG_FUNCS(skl); 737 CG_FUNCS(kbl); 738 CG_FUNCS(bxt); 739 CG_FUNCS(glk); 740 CG_FUNCS(bdw); 741 CG_FUNCS(chv); 742 CG_FUNCS(hsw); 743 CG_FUNCS(ivb); 744 CG_FUNCS(vlv); 745 CG_FUNCS(gen6); 746 CG_FUNCS(ilk); 747 CG_FUNCS(g4x); 748 CG_FUNCS(i965gm); 749 CG_FUNCS(i965g); 750 CG_FUNCS(gen3); 751 CG_FUNCS(i85x); 752 CG_FUNCS(i830); 753 CG_FUNCS(nop); 754 #undef CG_FUNCS 755 756 /** 757 * intel_clock_gating_hooks_init - setup the clock gating hooks 758 * @i915: device private 759 * 760 * Setup the hooks that configure which clocks of a given platform can be 761 * gated and also apply various GT and display specific workarounds for these 762 * platforms. Note that some GT specific workarounds are applied separately 763 * when GPU contexts or batchbuffers start their execution. 764 */ 765 void intel_clock_gating_hooks_init(struct drm_i915_private *i915) 766 { 767 if (IS_PONTEVECCHIO(i915)) 768 i915->clock_gating_funcs = &pvc_clock_gating_funcs; 769 else if (IS_DG2(i915)) 770 i915->clock_gating_funcs = &dg2_clock_gating_funcs; 771 else if (IS_XEHPSDV(i915)) 772 i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs; 773 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 774 i915->clock_gating_funcs = &cfl_clock_gating_funcs; 775 else if (IS_SKYLAKE(i915)) 776 i915->clock_gating_funcs = &skl_clock_gating_funcs; 777 else if (IS_KABYLAKE(i915)) 778 i915->clock_gating_funcs = &kbl_clock_gating_funcs; 779 else if (IS_BROXTON(i915)) 780 i915->clock_gating_funcs = &bxt_clock_gating_funcs; 781 else if (IS_GEMINILAKE(i915)) 782 i915->clock_gating_funcs = &glk_clock_gating_funcs; 783 else if (IS_BROADWELL(i915)) 784 i915->clock_gating_funcs = &bdw_clock_gating_funcs; 785 else if (IS_CHERRYVIEW(i915)) 786 i915->clock_gating_funcs = &chv_clock_gating_funcs; 787 else if (IS_HASWELL(i915)) 788 i915->clock_gating_funcs = &hsw_clock_gating_funcs; 789 else if (IS_IVYBRIDGE(i915)) 790 i915->clock_gating_funcs = &ivb_clock_gating_funcs; 791 else if (IS_VALLEYVIEW(i915)) 792 i915->clock_gating_funcs = &vlv_clock_gating_funcs; 793 else if (GRAPHICS_VER(i915) == 6) 794 i915->clock_gating_funcs = &gen6_clock_gating_funcs; 795 else if (GRAPHICS_VER(i915) == 5) 796 i915->clock_gating_funcs = &ilk_clock_gating_funcs; 797 else if (IS_G4X(i915)) 798 i915->clock_gating_funcs = &g4x_clock_gating_funcs; 799 else if (IS_I965GM(i915)) 800 i915->clock_gating_funcs = &i965gm_clock_gating_funcs; 801 else if (IS_I965G(i915)) 802 i915->clock_gating_funcs = &i965g_clock_gating_funcs; 803 else if (GRAPHICS_VER(i915) == 3) 804 i915->clock_gating_funcs = &gen3_clock_gating_funcs; 805 else if (IS_I85X(i915) || IS_I865G(i915)) 806 i915->clock_gating_funcs = &i85x_clock_gating_funcs; 807 else if (GRAPHICS_VER(i915) == 2) 808 i915->clock_gating_funcs = &i830_clock_gating_funcs; 809 else 810 i915->clock_gating_funcs = &nop_clock_gating_funcs; 811 } 812