1 /* 2 * Copyright © 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __INTEL_UNCORE_H__ 26 #define __INTEL_UNCORE_H__ 27 28 #include <linux/spinlock.h> 29 #include <linux/notifier.h> 30 #include <linux/hrtimer.h> 31 #include <linux/io-64-nonatomic-lo-hi.h> 32 33 #include "i915_reg_defs.h" 34 35 struct drm_i915_private; 36 struct intel_runtime_pm; 37 struct intel_uncore; 38 struct intel_gt; 39 40 struct intel_uncore_mmio_debug { 41 spinlock_t lock; /** lock is also taken in irq contexts. */ 42 int unclaimed_mmio_check; 43 int saved_mmio_check; 44 u32 suspend_count; 45 }; 46 47 enum forcewake_domain_id { 48 FW_DOMAIN_ID_RENDER = 0, 49 FW_DOMAIN_ID_GT, /* also includes blitter engine */ 50 FW_DOMAIN_ID_MEDIA, 51 FW_DOMAIN_ID_MEDIA_VDBOX0, 52 FW_DOMAIN_ID_MEDIA_VDBOX1, 53 FW_DOMAIN_ID_MEDIA_VDBOX2, 54 FW_DOMAIN_ID_MEDIA_VDBOX3, 55 FW_DOMAIN_ID_MEDIA_VDBOX4, 56 FW_DOMAIN_ID_MEDIA_VDBOX5, 57 FW_DOMAIN_ID_MEDIA_VDBOX6, 58 FW_DOMAIN_ID_MEDIA_VDBOX7, 59 FW_DOMAIN_ID_MEDIA_VEBOX0, 60 FW_DOMAIN_ID_MEDIA_VEBOX1, 61 FW_DOMAIN_ID_MEDIA_VEBOX2, 62 FW_DOMAIN_ID_MEDIA_VEBOX3, 63 64 FW_DOMAIN_ID_COUNT 65 }; 66 67 enum forcewake_domains { 68 FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER), 69 FORCEWAKE_GT = BIT(FW_DOMAIN_ID_GT), 70 FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA), 71 FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0), 72 FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1), 73 FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2), 74 FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3), 75 FORCEWAKE_MEDIA_VDBOX4 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX4), 76 FORCEWAKE_MEDIA_VDBOX5 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX5), 77 FORCEWAKE_MEDIA_VDBOX6 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX6), 78 FORCEWAKE_MEDIA_VDBOX7 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX7), 79 FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0), 80 FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1), 81 FORCEWAKE_MEDIA_VEBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX2), 82 FORCEWAKE_MEDIA_VEBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX3), 83 84 FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1, 85 }; 86 87 struct intel_uncore_fw_get { 88 void (*force_wake_get)(struct intel_uncore *uncore, 89 enum forcewake_domains domains); 90 }; 91 92 struct intel_uncore_funcs { 93 enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore, 94 i915_reg_t r); 95 enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore, 96 i915_reg_t r); 97 98 u8 (*mmio_readb)(struct intel_uncore *uncore, 99 i915_reg_t r, bool trace); 100 u16 (*mmio_readw)(struct intel_uncore *uncore, 101 i915_reg_t r, bool trace); 102 u32 (*mmio_readl)(struct intel_uncore *uncore, 103 i915_reg_t r, bool trace); 104 u64 (*mmio_readq)(struct intel_uncore *uncore, 105 i915_reg_t r, bool trace); 106 107 void (*mmio_writeb)(struct intel_uncore *uncore, 108 i915_reg_t r, u8 val, bool trace); 109 void (*mmio_writew)(struct intel_uncore *uncore, 110 i915_reg_t r, u16 val, bool trace); 111 void (*mmio_writel)(struct intel_uncore *uncore, 112 i915_reg_t r, u32 val, bool trace); 113 }; 114 115 struct intel_forcewake_range { 116 u32 start; 117 u32 end; 118 119 enum forcewake_domains domains; 120 }; 121 122 /* Other register ranges (e.g., shadow tables, MCR tables, etc.) */ 123 struct i915_range { 124 u32 start; 125 u32 end; 126 }; 127 128 struct intel_uncore { 129 void __iomem *regs; 130 131 struct drm_i915_private *i915; 132 struct intel_gt *gt; 133 struct intel_runtime_pm *rpm; 134 135 spinlock_t lock; /** lock is also taken in irq contexts. */ 136 137 unsigned int flags; 138 #define UNCORE_HAS_FORCEWAKE BIT(0) 139 #define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1) 140 #define UNCORE_HAS_DBG_UNCLAIMED BIT(2) 141 #define UNCORE_HAS_FIFO BIT(3) 142 143 const struct intel_forcewake_range *fw_domains_table; 144 unsigned int fw_domains_table_entries; 145 146 /* 147 * Shadowed registers are special cases where we can safely write 148 * to the register *without* grabbing forcewake. 149 */ 150 const struct i915_range *shadowed_reg_table; 151 unsigned int shadowed_reg_table_entries; 152 153 struct notifier_block pmic_bus_access_nb; 154 const struct intel_uncore_fw_get *fw_get_funcs; 155 struct intel_uncore_funcs funcs; 156 157 unsigned int fifo_count; 158 159 enum forcewake_domains fw_domains; 160 enum forcewake_domains fw_domains_active; 161 enum forcewake_domains fw_domains_timer; 162 enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */ 163 164 struct intel_uncore_forcewake_domain { 165 struct intel_uncore *uncore; 166 enum forcewake_domain_id id; 167 enum forcewake_domains mask; 168 unsigned int wake_count; 169 bool active; 170 struct hrtimer timer; 171 u32 __iomem *reg_set; 172 u32 __iomem *reg_ack; 173 } *fw_domain[FW_DOMAIN_ID_COUNT]; 174 175 unsigned int user_forcewake_count; 176 177 struct intel_uncore_mmio_debug *debug; 178 }; 179 180 /* Iterate over initialised fw domains */ 181 #define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \ 182 for (tmp__ = (mask__); tmp__ ;) \ 183 for_each_if(domain__ = (uncore__)->fw_domain[__mask_next_bit(tmp__)]) 184 185 #define for_each_fw_domain(domain__, uncore__, tmp__) \ 186 for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__) 187 188 static inline bool 189 intel_uncore_has_forcewake(const struct intel_uncore *uncore) 190 { 191 return uncore->flags & UNCORE_HAS_FORCEWAKE; 192 } 193 194 static inline bool 195 intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore) 196 { 197 return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED; 198 } 199 200 static inline bool 201 intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore) 202 { 203 return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED; 204 } 205 206 static inline bool 207 intel_uncore_has_fifo(const struct intel_uncore *uncore) 208 { 209 return uncore->flags & UNCORE_HAS_FIFO; 210 } 211 212 u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore, 213 i915_reg_t reg, 214 int slice, int subslice); 215 u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore, 216 i915_reg_t reg, int slice, int subslice); 217 218 void 219 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug); 220 void intel_uncore_init_early(struct intel_uncore *uncore, 221 struct intel_gt *gt); 222 int intel_uncore_setup_mmio(struct intel_uncore *uncore); 223 int intel_uncore_init_mmio(struct intel_uncore *uncore); 224 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, 225 struct intel_gt *gt); 226 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore); 227 bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore); 228 void intel_uncore_cleanup_mmio(struct intel_uncore *uncore); 229 void intel_uncore_fini_mmio(struct intel_uncore *uncore); 230 void intel_uncore_suspend(struct intel_uncore *uncore); 231 void intel_uncore_resume_early(struct intel_uncore *uncore); 232 void intel_uncore_runtime_resume(struct intel_uncore *uncore); 233 234 void assert_forcewakes_inactive(struct intel_uncore *uncore); 235 void assert_forcewakes_active(struct intel_uncore *uncore, 236 enum forcewake_domains fw_domains); 237 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); 238 239 enum forcewake_domains 240 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, 241 i915_reg_t reg, unsigned int op); 242 #define FW_REG_READ (1) 243 #define FW_REG_WRITE (2) 244 245 void intel_uncore_forcewake_get(struct intel_uncore *uncore, 246 enum forcewake_domains domains); 247 void intel_uncore_forcewake_put(struct intel_uncore *uncore, 248 enum forcewake_domains domains); 249 void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, 250 enum forcewake_domains domains); 251 void intel_uncore_forcewake_flush(struct intel_uncore *uncore, 252 enum forcewake_domains fw_domains); 253 254 /* 255 * Like above but the caller must manage the uncore.lock itself. 256 * Must be used with intel_uncore_read_fw() and friends. 257 */ 258 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, 259 enum forcewake_domains domains); 260 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, 261 enum forcewake_domains domains); 262 263 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore); 264 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore); 265 266 int __intel_wait_for_register(struct intel_uncore *uncore, 267 i915_reg_t reg, 268 u32 mask, 269 u32 value, 270 unsigned int fast_timeout_us, 271 unsigned int slow_timeout_ms, 272 u32 *out_value); 273 static inline int 274 intel_wait_for_register(struct intel_uncore *uncore, 275 i915_reg_t reg, 276 u32 mask, 277 u32 value, 278 unsigned int timeout_ms) 279 { 280 return __intel_wait_for_register(uncore, reg, mask, value, 2, 281 timeout_ms, NULL); 282 } 283 284 int __intel_wait_for_register_fw(struct intel_uncore *uncore, 285 i915_reg_t reg, 286 u32 mask, 287 u32 value, 288 unsigned int fast_timeout_us, 289 unsigned int slow_timeout_ms, 290 u32 *out_value); 291 static inline int 292 intel_wait_for_register_fw(struct intel_uncore *uncore, 293 i915_reg_t reg, 294 u32 mask, 295 u32 value, 296 unsigned int timeout_ms) 297 { 298 return __intel_wait_for_register_fw(uncore, reg, mask, value, 299 2, timeout_ms, NULL); 300 } 301 302 /* register access functions */ 303 #define __raw_read(x__, s__) \ 304 static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \ 305 i915_reg_t reg) \ 306 { \ 307 return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \ 308 } 309 310 #define __raw_write(x__, s__) \ 311 static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \ 312 i915_reg_t reg, u##x__ val) \ 313 { \ 314 write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \ 315 } 316 __raw_read(8, b) 317 __raw_read(16, w) 318 __raw_read(32, l) 319 __raw_read(64, q) 320 321 __raw_write(8, b) 322 __raw_write(16, w) 323 __raw_write(32, l) 324 __raw_write(64, q) 325 326 #undef __raw_read 327 #undef __raw_write 328 329 #define __uncore_read(name__, x__, s__, trace__) \ 330 static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \ 331 i915_reg_t reg) \ 332 { \ 333 return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \ 334 } 335 336 #define __uncore_write(name__, x__, s__, trace__) \ 337 static inline void intel_uncore_##name__(struct intel_uncore *uncore, \ 338 i915_reg_t reg, u##x__ val) \ 339 { \ 340 uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \ 341 } 342 343 __uncore_read(read8, 8, b, true) 344 __uncore_read(read16, 16, w, true) 345 __uncore_read(read, 32, l, true) 346 __uncore_read(read16_notrace, 16, w, false) 347 __uncore_read(read_notrace, 32, l, false) 348 349 __uncore_write(write8, 8, b, true) 350 __uncore_write(write16, 16, w, true) 351 __uncore_write(write, 32, l, true) 352 __uncore_write(write_notrace, 32, l, false) 353 354 /* Be very careful with read/write 64-bit values. On 32-bit machines, they 355 * will be implemented using 2 32-bit writes in an arbitrary order with 356 * an arbitrary delay between them. This can cause the hardware to 357 * act upon the intermediate value, possibly leading to corruption and 358 * machine death. For this reason we do not support intel_uncore_write64, 359 * or uncore->funcs.mmio_writeq. 360 * 361 * When reading a 64-bit value as two 32-bit values, the delay may cause 362 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that 363 * occasionally a 64-bit register does not actually support a full readq 364 * and must be read using two 32-bit reads. 365 * 366 * You have been warned. 367 */ 368 __uncore_read(read64, 64, q, true) 369 370 static inline u64 371 intel_uncore_read64_2x32(struct intel_uncore *uncore, 372 i915_reg_t lower_reg, i915_reg_t upper_reg) 373 { 374 u32 upper, lower, old_upper, loop = 0; 375 upper = intel_uncore_read(uncore, upper_reg); 376 do { 377 old_upper = upper; 378 lower = intel_uncore_read(uncore, lower_reg); 379 upper = intel_uncore_read(uncore, upper_reg); 380 } while (upper != old_upper && loop++ < 2); 381 return (u64)upper << 32 | lower; 382 } 383 384 #define intel_uncore_posting_read(...) ((void)intel_uncore_read_notrace(__VA_ARGS__)) 385 #define intel_uncore_posting_read16(...) ((void)intel_uncore_read16_notrace(__VA_ARGS__)) 386 387 #undef __uncore_read 388 #undef __uncore_write 389 390 /* These are untraced mmio-accessors that are only valid to be used inside 391 * critical sections, such as inside IRQ handlers, where forcewake is explicitly 392 * controlled. 393 * 394 * Think twice, and think again, before using these. 395 * 396 * As an example, these accessors can possibly be used between: 397 * 398 * spin_lock_irq(&uncore->lock); 399 * intel_uncore_forcewake_get__locked(); 400 * 401 * and 402 * 403 * intel_uncore_forcewake_put__locked(); 404 * spin_unlock_irq(&uncore->lock); 405 * 406 * 407 * Note: some registers may not need forcewake held, so 408 * intel_uncore_forcewake_{get,put} can be omitted, see 409 * intel_uncore_forcewake_for_reg(). 410 * 411 * Certain architectures will die if the same cacheline is concurrently accessed 412 * by different clients (e.g. on Ivybridge). Access to registers should 413 * therefore generally be serialised, by either the dev_priv->uncore.lock or 414 * a more localised lock guarding all access to that bank of registers. 415 */ 416 #define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__) 417 #define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__) 418 #define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__) 419 #define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__)) 420 421 static inline void intel_uncore_rmw(struct intel_uncore *uncore, 422 i915_reg_t reg, u32 clear, u32 set) 423 { 424 u32 old, val; 425 426 old = intel_uncore_read(uncore, reg); 427 val = (old & ~clear) | set; 428 if (val != old) 429 intel_uncore_write(uncore, reg, val); 430 } 431 432 static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore, 433 i915_reg_t reg, u32 clear, u32 set) 434 { 435 u32 old, val; 436 437 old = intel_uncore_read_fw(uncore, reg); 438 val = (old & ~clear) | set; 439 if (val != old) 440 intel_uncore_write_fw(uncore, reg, val); 441 } 442 443 static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore, 444 i915_reg_t reg, u32 val, 445 u32 mask, u32 expected_val) 446 { 447 u32 reg_val; 448 449 intel_uncore_write(uncore, reg, val); 450 reg_val = intel_uncore_read(uncore, reg); 451 452 return (reg_val & mask) != expected_val ? -EINVAL : 0; 453 } 454 455 #define raw_reg_read(base, reg) \ 456 readl(base + i915_mmio_reg_offset(reg)) 457 #define raw_reg_write(base, reg, value) \ 458 writel(value, base + i915_mmio_reg_offset(reg)) 459 460 #endif /* !__INTEL_UNCORE_H__ */ 461