1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2019 NXP. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/of.h> 8 #include <linux/of_graph.h> 9 #include <linux/platform_device.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/slab.h> 12 #include <drm/drm_bridge_connector.h> 13 #include <drm/drm_device.h> 14 #include <drm/drm_modeset_helper.h> 15 16 #include "dcss-dev.h" 17 #include "dcss-kms.h" 18 19 static void dcss_clocks_enable(struct dcss_dev *dcss) 20 { 21 clk_prepare_enable(dcss->axi_clk); 22 clk_prepare_enable(dcss->apb_clk); 23 clk_prepare_enable(dcss->rtrm_clk); 24 clk_prepare_enable(dcss->dtrc_clk); 25 clk_prepare_enable(dcss->pix_clk); 26 } 27 28 static void dcss_clocks_disable(struct dcss_dev *dcss) 29 { 30 clk_disable_unprepare(dcss->pix_clk); 31 clk_disable_unprepare(dcss->dtrc_clk); 32 clk_disable_unprepare(dcss->rtrm_clk); 33 clk_disable_unprepare(dcss->apb_clk); 34 clk_disable_unprepare(dcss->axi_clk); 35 } 36 37 static void dcss_disable_dtg_and_ss_cb(void *data) 38 { 39 struct dcss_dev *dcss = data; 40 41 dcss->disable_callback = NULL; 42 43 dcss_ss_shutoff(dcss->ss); 44 dcss_dtg_shutoff(dcss->dtg); 45 46 complete(&dcss->disable_completion); 47 } 48 49 void dcss_disable_dtg_and_ss(struct dcss_dev *dcss) 50 { 51 dcss->disable_callback = dcss_disable_dtg_and_ss_cb; 52 } 53 54 void dcss_enable_dtg_and_ss(struct dcss_dev *dcss) 55 { 56 if (dcss->disable_callback) 57 dcss->disable_callback = NULL; 58 59 dcss_dtg_enable(dcss->dtg); 60 dcss_ss_enable(dcss->ss); 61 } 62 63 static int dcss_submodules_init(struct dcss_dev *dcss) 64 { 65 int ret = 0; 66 u32 base_addr = dcss->start_addr; 67 const struct dcss_type_data *devtype = dcss->devtype; 68 69 dcss_clocks_enable(dcss); 70 71 ret = dcss_blkctl_init(dcss, base_addr + devtype->blkctl_ofs); 72 if (ret) 73 return ret; 74 75 ret = dcss_ctxld_init(dcss, base_addr + devtype->ctxld_ofs); 76 if (ret) 77 goto ctxld_err; 78 79 ret = dcss_dtg_init(dcss, base_addr + devtype->dtg_ofs); 80 if (ret) 81 goto dtg_err; 82 83 ret = dcss_ss_init(dcss, base_addr + devtype->ss_ofs); 84 if (ret) 85 goto ss_err; 86 87 ret = dcss_dpr_init(dcss, base_addr + devtype->dpr_ofs); 88 if (ret) 89 goto dpr_err; 90 91 ret = dcss_scaler_init(dcss, base_addr + devtype->scaler_ofs); 92 if (ret) 93 goto scaler_err; 94 95 dcss_clocks_disable(dcss); 96 97 return 0; 98 99 scaler_err: 100 dcss_dpr_exit(dcss->dpr); 101 102 dpr_err: 103 dcss_ss_exit(dcss->ss); 104 105 ss_err: 106 dcss_dtg_exit(dcss->dtg); 107 108 dtg_err: 109 dcss_ctxld_exit(dcss->ctxld); 110 111 ctxld_err: 112 dcss_clocks_disable(dcss); 113 114 return ret; 115 } 116 117 static void dcss_submodules_stop(struct dcss_dev *dcss) 118 { 119 dcss_clocks_enable(dcss); 120 dcss_scaler_exit(dcss->scaler); 121 dcss_dpr_exit(dcss->dpr); 122 dcss_ss_exit(dcss->ss); 123 dcss_dtg_exit(dcss->dtg); 124 dcss_ctxld_exit(dcss->ctxld); 125 dcss_clocks_disable(dcss); 126 } 127 128 static int dcss_clks_init(struct dcss_dev *dcss) 129 { 130 int i; 131 struct { 132 const char *id; 133 struct clk **clk; 134 } clks[] = { 135 {"apb", &dcss->apb_clk}, 136 {"axi", &dcss->axi_clk}, 137 {"pix", &dcss->pix_clk}, 138 {"rtrm", &dcss->rtrm_clk}, 139 {"dtrc", &dcss->dtrc_clk}, 140 }; 141 142 for (i = 0; i < ARRAY_SIZE(clks); i++) { 143 *clks[i].clk = devm_clk_get(dcss->dev, clks[i].id); 144 if (IS_ERR(*clks[i].clk)) { 145 dev_err(dcss->dev, "failed to get %s clock\n", 146 clks[i].id); 147 return PTR_ERR(*clks[i].clk); 148 } 149 } 150 151 return 0; 152 } 153 154 static void dcss_clks_release(struct dcss_dev *dcss) 155 { 156 devm_clk_put(dcss->dev, dcss->dtrc_clk); 157 devm_clk_put(dcss->dev, dcss->rtrm_clk); 158 devm_clk_put(dcss->dev, dcss->pix_clk); 159 devm_clk_put(dcss->dev, dcss->axi_clk); 160 devm_clk_put(dcss->dev, dcss->apb_clk); 161 } 162 163 struct dcss_dev *dcss_dev_create(struct device *dev, bool hdmi_output) 164 { 165 struct platform_device *pdev = to_platform_device(dev); 166 int ret; 167 struct resource *res; 168 struct dcss_dev *dcss; 169 const struct dcss_type_data *devtype; 170 resource_size_t res_len; 171 172 devtype = of_device_get_match_data(dev); 173 if (!devtype) { 174 dev_err(dev, "no device match found\n"); 175 return ERR_PTR(-ENODEV); 176 } 177 178 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 179 if (!res) { 180 dev_err(dev, "cannot get memory resource\n"); 181 return ERR_PTR(-EINVAL); 182 } 183 184 res_len = res->end - res->start; 185 if (!devm_request_mem_region(dev, res->start, res_len, "dcss")) { 186 dev_err(dev, "cannot request memory region\n"); 187 return ERR_PTR(-EBUSY); 188 } 189 190 dcss = devm_kzalloc(dev, sizeof(*dcss), GFP_KERNEL); 191 if (!dcss) 192 return ERR_PTR(-ENOMEM); 193 194 dcss->dev = dev; 195 dcss->devtype = devtype; 196 dcss->hdmi_output = hdmi_output; 197 198 ret = dcss_clks_init(dcss); 199 if (ret) { 200 dev_err(dev, "clocks initialization failed\n"); 201 return ERR_PTR(ret); 202 } 203 204 dcss->of_port = of_graph_get_port_by_id(dev->of_node, 0); 205 if (!dcss->of_port) { 206 dev_err(dev, "no port@0 node in %pOF\n", dev->of_node); 207 ret = -ENODEV; 208 goto clks_err; 209 } 210 211 dcss->start_addr = res->start; 212 213 ret = dcss_submodules_init(dcss); 214 if (ret) { 215 of_node_put(dcss->of_port); 216 dev_err(dev, "submodules initialization failed\n"); 217 goto clks_err; 218 } 219 220 init_completion(&dcss->disable_completion); 221 222 pm_runtime_set_autosuspend_delay(dev, 100); 223 pm_runtime_use_autosuspend(dev); 224 pm_runtime_set_suspended(dev); 225 pm_runtime_allow(dev); 226 pm_runtime_enable(dev); 227 228 return dcss; 229 230 clks_err: 231 dcss_clks_release(dcss); 232 233 return ERR_PTR(ret); 234 } 235 236 void dcss_dev_destroy(struct dcss_dev *dcss) 237 { 238 if (!pm_runtime_suspended(dcss->dev)) { 239 dcss_ctxld_suspend(dcss->ctxld); 240 dcss_clocks_disable(dcss); 241 } 242 243 of_node_put(dcss->of_port); 244 245 pm_runtime_disable(dcss->dev); 246 247 dcss_submodules_stop(dcss); 248 249 dcss_clks_release(dcss); 250 } 251 252 static int dcss_dev_suspend(struct device *dev) 253 { 254 struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev); 255 struct drm_device *ddev = dcss_drv_dev_to_drm(dev); 256 int ret; 257 258 drm_mode_config_helper_suspend(ddev); 259 260 if (pm_runtime_suspended(dev)) 261 return 0; 262 263 ret = dcss_ctxld_suspend(dcss->ctxld); 264 if (ret) 265 return ret; 266 267 dcss_clocks_disable(dcss); 268 269 return 0; 270 } 271 272 static int dcss_dev_resume(struct device *dev) 273 { 274 struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev); 275 struct drm_device *ddev = dcss_drv_dev_to_drm(dev); 276 277 if (pm_runtime_suspended(dev)) { 278 drm_mode_config_helper_resume(ddev); 279 return 0; 280 } 281 282 dcss_clocks_enable(dcss); 283 284 dcss_blkctl_cfg(dcss->blkctl); 285 286 dcss_ctxld_resume(dcss->ctxld); 287 288 drm_mode_config_helper_resume(ddev); 289 290 return 0; 291 } 292 293 static int dcss_dev_runtime_suspend(struct device *dev) 294 { 295 struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev); 296 int ret; 297 298 ret = dcss_ctxld_suspend(dcss->ctxld); 299 if (ret) 300 return ret; 301 302 dcss_clocks_disable(dcss); 303 304 return 0; 305 } 306 307 static int dcss_dev_runtime_resume(struct device *dev) 308 { 309 struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dev); 310 311 dcss_clocks_enable(dcss); 312 313 dcss_blkctl_cfg(dcss->blkctl); 314 315 dcss_ctxld_resume(dcss->ctxld); 316 317 return 0; 318 } 319 320 EXPORT_GPL_DEV_PM_OPS(dcss_dev_pm_ops) = { 321 RUNTIME_PM_OPS(dcss_dev_runtime_suspend, dcss_dev_runtime_resume, NULL) 322 SYSTEM_SLEEP_PM_OPS(dcss_dev_suspend, dcss_dev_resume) 323 }; 324