1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <drm/drmP.h> 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/of_device.h> 10 #include <linux/of_irq.h> 11 #include <linux/platform_device.h> 12 13 #include "mtk_drm_crtc.h" 14 #include "mtk_drm_ddp_comp.h" 15 16 #define DISP_REG_RDMA_INT_ENABLE 0x0000 17 #define DISP_REG_RDMA_INT_STATUS 0x0004 18 #define RDMA_TARGET_LINE_INT BIT(5) 19 #define RDMA_FIFO_UNDERFLOW_INT BIT(4) 20 #define RDMA_EOF_ABNORMAL_INT BIT(3) 21 #define RDMA_FRAME_END_INT BIT(2) 22 #define RDMA_FRAME_START_INT BIT(1) 23 #define RDMA_REG_UPDATE_INT BIT(0) 24 #define DISP_REG_RDMA_GLOBAL_CON 0x0010 25 #define RDMA_ENGINE_EN BIT(0) 26 #define RDMA_MODE_MEMORY BIT(1) 27 #define DISP_REG_RDMA_SIZE_CON_0 0x0014 28 #define RDMA_MATRIX_ENABLE BIT(17) 29 #define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20) 30 #define RDMA_MATRIX_INT_MTX_BT601_to_RGB (6 << 20) 31 #define DISP_REG_RDMA_SIZE_CON_1 0x0018 32 #define DISP_REG_RDMA_TARGET_LINE 0x001c 33 #define DISP_RDMA_MEM_CON 0x0024 34 #define MEM_MODE_INPUT_FORMAT_RGB565 (0x000 << 4) 35 #define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4) 36 #define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4) 37 #define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4) 38 #define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4) 39 #define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4) 40 #define MEM_MODE_INPUT_SWAP BIT(8) 41 #define DISP_RDMA_MEM_SRC_PITCH 0x002c 42 #define DISP_RDMA_MEM_GMC_SETTING_0 0x0030 43 #define DISP_REG_RDMA_FIFO_CON 0x0040 44 #define RDMA_FIFO_UNDERFLOW_EN BIT(31) 45 #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) 46 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) 47 #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size) 48 #define DISP_RDMA_MEM_START_ADDR 0x0f00 49 50 #define RDMA_MEM_GMC 0x40402020 51 52 struct mtk_disp_rdma_data { 53 unsigned int fifo_size; 54 }; 55 56 /** 57 * struct mtk_disp_rdma - DISP_RDMA driver structure 58 * @ddp_comp - structure containing type enum and hardware resources 59 * @crtc - associated crtc to report irq events to 60 */ 61 struct mtk_disp_rdma { 62 struct mtk_ddp_comp ddp_comp; 63 struct drm_crtc *crtc; 64 const struct mtk_disp_rdma_data *data; 65 }; 66 67 static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) 68 { 69 return container_of(comp, struct mtk_disp_rdma, ddp_comp); 70 } 71 72 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id) 73 { 74 struct mtk_disp_rdma *priv = dev_id; 75 struct mtk_ddp_comp *rdma = &priv->ddp_comp; 76 77 /* Clear frame completion interrupt */ 78 writel(0x0, rdma->regs + DISP_REG_RDMA_INT_STATUS); 79 80 if (!priv->crtc) 81 return IRQ_NONE; 82 83 mtk_crtc_ddp_irq(priv->crtc, rdma); 84 85 return IRQ_HANDLED; 86 } 87 88 static void rdma_update_bits(struct mtk_ddp_comp *comp, unsigned int reg, 89 unsigned int mask, unsigned int val) 90 { 91 unsigned int tmp = readl(comp->regs + reg); 92 93 tmp = (tmp & ~mask) | (val & mask); 94 writel(tmp, comp->regs + reg); 95 } 96 97 static void mtk_rdma_enable_vblank(struct mtk_ddp_comp *comp, 98 struct drm_crtc *crtc) 99 { 100 struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 101 102 rdma->crtc = crtc; 103 rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 104 RDMA_FRAME_END_INT); 105 } 106 107 static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp) 108 { 109 struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 110 111 rdma->crtc = NULL; 112 rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0); 113 } 114 115 static void mtk_rdma_start(struct mtk_ddp_comp *comp) 116 { 117 rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 118 RDMA_ENGINE_EN); 119 } 120 121 static void mtk_rdma_stop(struct mtk_ddp_comp *comp) 122 { 123 rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0); 124 } 125 126 static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, 127 unsigned int height, unsigned int vrefresh, 128 unsigned int bpc) 129 { 130 unsigned int threshold; 131 unsigned int reg; 132 struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 133 134 rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width); 135 rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height); 136 137 /* 138 * Enable FIFO underflow since DSI and DPI can't be blocked. 139 * Keep the FIFO pseudo size reset default of 8 KiB. Set the 140 * output threshold to 6 microseconds with 7/6 overhead to 141 * account for blanking, and with a pixel depth of 4 bytes: 142 */ 143 threshold = width * height * vrefresh * 4 * 7 / 1000000; 144 reg = RDMA_FIFO_UNDERFLOW_EN | 145 RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | 146 RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); 147 writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); 148 } 149 150 static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, 151 unsigned int fmt) 152 { 153 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" 154 * is defined in mediatek HW data sheet. 155 * The alphabet order in XXX is no relation to data 156 * arrangement in memory. 157 */ 158 switch (fmt) { 159 default: 160 case DRM_FORMAT_RGB565: 161 return MEM_MODE_INPUT_FORMAT_RGB565; 162 case DRM_FORMAT_BGR565: 163 return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP; 164 case DRM_FORMAT_RGB888: 165 return MEM_MODE_INPUT_FORMAT_RGB888; 166 case DRM_FORMAT_BGR888: 167 return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP; 168 case DRM_FORMAT_RGBX8888: 169 case DRM_FORMAT_RGBA8888: 170 return MEM_MODE_INPUT_FORMAT_ARGB8888; 171 case DRM_FORMAT_BGRX8888: 172 case DRM_FORMAT_BGRA8888: 173 return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP; 174 case DRM_FORMAT_XRGB8888: 175 case DRM_FORMAT_ARGB8888: 176 return MEM_MODE_INPUT_FORMAT_RGBA8888; 177 case DRM_FORMAT_XBGR8888: 178 case DRM_FORMAT_ABGR8888: 179 return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP; 180 case DRM_FORMAT_UYVY: 181 return MEM_MODE_INPUT_FORMAT_UYVY; 182 case DRM_FORMAT_YUYV: 183 return MEM_MODE_INPUT_FORMAT_YUYV; 184 } 185 } 186 187 static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp) 188 { 189 return 1; 190 } 191 192 static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, 193 struct mtk_plane_state *state) 194 { 195 struct mtk_disp_rdma *rdma = comp_to_rdma(comp); 196 struct mtk_plane_pending_state *pending = &state->pending; 197 unsigned int addr = pending->addr; 198 unsigned int pitch = pending->pitch & 0xffff; 199 unsigned int fmt = pending->format; 200 unsigned int con; 201 202 con = rdma_fmt_convert(rdma, fmt); 203 writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON); 204 205 if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) { 206 rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 207 RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE); 208 rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 209 RDMA_MATRIX_INT_MTX_SEL, 210 RDMA_MATRIX_INT_MTX_BT601_to_RGB); 211 } else { 212 rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 213 RDMA_MATRIX_ENABLE, 0); 214 } 215 216 writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR); 217 writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH); 218 writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0); 219 rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, 220 RDMA_MODE_MEMORY, RDMA_MODE_MEMORY); 221 } 222 223 static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = { 224 .config = mtk_rdma_config, 225 .start = mtk_rdma_start, 226 .stop = mtk_rdma_stop, 227 .enable_vblank = mtk_rdma_enable_vblank, 228 .disable_vblank = mtk_rdma_disable_vblank, 229 .layer_nr = mtk_rdma_layer_nr, 230 .layer_config = mtk_rdma_layer_config, 231 }; 232 233 static int mtk_disp_rdma_bind(struct device *dev, struct device *master, 234 void *data) 235 { 236 struct mtk_disp_rdma *priv = dev_get_drvdata(dev); 237 struct drm_device *drm_dev = data; 238 int ret; 239 240 ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp); 241 if (ret < 0) { 242 dev_err(dev, "Failed to register component %pOF: %d\n", 243 dev->of_node, ret); 244 return ret; 245 } 246 247 return 0; 248 249 } 250 251 static void mtk_disp_rdma_unbind(struct device *dev, struct device *master, 252 void *data) 253 { 254 struct mtk_disp_rdma *priv = dev_get_drvdata(dev); 255 struct drm_device *drm_dev = data; 256 257 mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp); 258 } 259 260 static const struct component_ops mtk_disp_rdma_component_ops = { 261 .bind = mtk_disp_rdma_bind, 262 .unbind = mtk_disp_rdma_unbind, 263 }; 264 265 static int mtk_disp_rdma_probe(struct platform_device *pdev) 266 { 267 struct device *dev = &pdev->dev; 268 struct mtk_disp_rdma *priv; 269 int comp_id; 270 int irq; 271 int ret; 272 273 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 274 if (!priv) 275 return -ENOMEM; 276 277 irq = platform_get_irq(pdev, 0); 278 if (irq < 0) 279 return irq; 280 281 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_RDMA); 282 if (comp_id < 0) { 283 dev_err(dev, "Failed to identify by alias: %d\n", comp_id); 284 return comp_id; 285 } 286 287 ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, 288 &mtk_disp_rdma_funcs); 289 if (ret) { 290 dev_err(dev, "Failed to initialize component: %d\n", ret); 291 return ret; 292 } 293 294 /* Disable and clear pending interrupts */ 295 writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_ENABLE); 296 writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_STATUS); 297 298 ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler, 299 IRQF_TRIGGER_NONE, dev_name(dev), priv); 300 if (ret < 0) { 301 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret); 302 return ret; 303 } 304 305 priv->data = of_device_get_match_data(dev); 306 307 platform_set_drvdata(pdev, priv); 308 309 ret = component_add(dev, &mtk_disp_rdma_component_ops); 310 if (ret) 311 dev_err(dev, "Failed to add component: %d\n", ret); 312 313 return ret; 314 } 315 316 static int mtk_disp_rdma_remove(struct platform_device *pdev) 317 { 318 component_del(&pdev->dev, &mtk_disp_rdma_component_ops); 319 320 return 0; 321 } 322 323 static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = { 324 .fifo_size = SZ_4K, 325 }; 326 327 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { 328 .fifo_size = SZ_8K, 329 }; 330 331 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { 332 { .compatible = "mediatek,mt2701-disp-rdma", 333 .data = &mt2701_rdma_driver_data}, 334 { .compatible = "mediatek,mt8173-disp-rdma", 335 .data = &mt8173_rdma_driver_data}, 336 {}, 337 }; 338 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); 339 340 struct platform_driver mtk_disp_rdma_driver = { 341 .probe = mtk_disp_rdma_probe, 342 .remove = mtk_disp_rdma_remove, 343 .driver = { 344 .name = "mediatek-disp-rdma", 345 .owner = THIS_MODULE, 346 .of_match_table = mtk_disp_rdma_driver_dt_match, 347 }, 348 }; 349