1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 6 * Copyright (C) 2014 Endless Mobile 7 * 8 * Written by: 9 * Jasper St. Pierre <jstpierre@mecheye.net> 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/bitfield.h> 16 #include <linux/platform_device.h> 17 #include <drm/drmP.h> 18 #include <drm/drm_atomic.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_plane_helper.h> 21 #include <drm/drm_gem_cma_helper.h> 22 #include <drm/drm_fb_cma_helper.h> 23 #include <drm/drm_gem_framebuffer_helper.h> 24 #include <drm/drm_rect.h> 25 26 #include "meson_plane.h" 27 #include "meson_vpp.h" 28 #include "meson_viu.h" 29 #include "meson_registers.h" 30 31 /* OSD_SCI_WH_M1 */ 32 #define SCI_WH_M1_W(w) FIELD_PREP(GENMASK(28, 16), w) 33 #define SCI_WH_M1_H(h) FIELD_PREP(GENMASK(12, 0), h) 34 35 /* OSD_SCO_H_START_END */ 36 /* OSD_SCO_V_START_END */ 37 #define SCO_HV_START(start) FIELD_PREP(GENMASK(27, 16), start) 38 #define SCO_HV_END(end) FIELD_PREP(GENMASK(11, 0), end) 39 40 /* OSD_SC_CTRL0 */ 41 #define SC_CTRL0_PATH_EN BIT(3) 42 #define SC_CTRL0_SEL_OSD1 BIT(2) 43 44 /* OSD_VSC_CTRL0 */ 45 #define VSC_BANK_LEN(value) FIELD_PREP(GENMASK(2, 0), value) 46 #define VSC_TOP_INI_RCV_NUM(value) FIELD_PREP(GENMASK(6, 3), value) 47 #define VSC_TOP_RPT_L0_NUM(value) FIELD_PREP(GENMASK(9, 8), value) 48 #define VSC_BOT_INI_RCV_NUM(value) FIELD_PREP(GENMASK(14, 11), value) 49 #define VSC_BOT_RPT_L0_NUM(value) FIELD_PREP(GENMASK(17, 16), value) 50 #define VSC_PROG_INTERLACE BIT(23) 51 #define VSC_VERTICAL_SCALER_EN BIT(24) 52 53 /* OSD_VSC_INI_PHASE */ 54 #define VSC_INI_PHASE_BOT(bottom) FIELD_PREP(GENMASK(31, 16), bottom) 55 #define VSC_INI_PHASE_TOP(top) FIELD_PREP(GENMASK(15, 0), top) 56 57 /* OSD_HSC_CTRL0 */ 58 #define HSC_BANK_LENGTH(value) FIELD_PREP(GENMASK(2, 0), value) 59 #define HSC_INI_RCV_NUM0(value) FIELD_PREP(GENMASK(6, 3), value) 60 #define HSC_RPT_P0_NUM0(value) FIELD_PREP(GENMASK(9, 8), value) 61 #define HSC_HORIZ_SCALER_EN BIT(22) 62 63 /* VPP_OSD_VSC_PHASE_STEP */ 64 /* VPP_OSD_HSC_PHASE_STEP */ 65 #define SC_PHASE_STEP(value) FIELD_PREP(GENMASK(27, 0), value) 66 67 struct meson_plane { 68 struct drm_plane base; 69 struct meson_drm *priv; 70 bool enabled; 71 }; 72 #define to_meson_plane(x) container_of(x, struct meson_plane, base) 73 74 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 75 76 static int meson_plane_atomic_check(struct drm_plane *plane, 77 struct drm_plane_state *state) 78 { 79 struct drm_crtc_state *crtc_state; 80 81 if (!state->crtc) 82 return 0; 83 84 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 85 if (IS_ERR(crtc_state)) 86 return PTR_ERR(crtc_state); 87 88 /* 89 * Only allow : 90 * - Upscaling up to 5x, vertical and horizontal 91 * - Final coordinates must match crtc size 92 */ 93 return drm_atomic_helper_check_plane_state(state, crtc_state, 94 FRAC_16_16(1, 5), 95 DRM_PLANE_HELPER_NO_SCALING, 96 false, true); 97 } 98 99 /* Takes a fixed 16.16 number and converts it to integer. */ 100 static inline int64_t fixed16_to_int(int64_t value) 101 { 102 return value >> 16; 103 } 104 105 static void meson_plane_atomic_update(struct drm_plane *plane, 106 struct drm_plane_state *old_state) 107 { 108 struct meson_plane *meson_plane = to_meson_plane(plane); 109 struct drm_plane_state *state = plane->state; 110 struct drm_rect dest = drm_plane_state_dest(state); 111 struct meson_drm *priv = meson_plane->priv; 112 struct drm_framebuffer *fb = state->fb; 113 struct drm_gem_cma_object *gem; 114 unsigned long flags; 115 int vsc_ini_rcv_num, vsc_ini_rpt_p0_num; 116 int vsc_bot_rcv_num, vsc_bot_rpt_p0_num; 117 int hsc_ini_rcv_num, hsc_ini_rpt_p0_num; 118 int hf_phase_step, vf_phase_step; 119 int src_w, src_h, dst_w, dst_h; 120 int bot_ini_phase; 121 int hf_bank_len; 122 int vf_bank_len; 123 u8 canvas_id_osd1; 124 125 /* 126 * Update Coordinates 127 * Update Formats 128 * Update Buffer 129 * Enable Plane 130 */ 131 spin_lock_irqsave(&priv->drm->event_lock, flags); 132 133 /* Enable OSD and BLK0, set max global alpha */ 134 priv->viu.osd1_ctrl_stat = OSD_ENABLE | 135 (0xFF << OSD_GLOBAL_ALPHA_SHIFT) | 136 OSD_BLK0_ENABLE; 137 138 canvas_id_osd1 = priv->canvas_id_osd1; 139 140 /* Set up BLK0 to point to the right canvas */ 141 priv->viu.osd1_blk0_cfg[0] = ((canvas_id_osd1 << OSD_CANVAS_SEL) | 142 OSD_ENDIANNESS_LE); 143 144 /* On GXBB, Use the old non-HDR RGB2YUV converter */ 145 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) 146 priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; 147 148 switch (fb->format->format) { 149 case DRM_FORMAT_XRGB8888: 150 /* For XRGB, replace the pixel's alpha by 0xFF */ 151 writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, 152 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); 153 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | 154 OSD_COLOR_MATRIX_32_ARGB; 155 break; 156 case DRM_FORMAT_ARGB8888: 157 /* For ARGB, use the pixel's alpha */ 158 writel_bits_relaxed(OSD_REPLACE_EN, 0, 159 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); 160 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | 161 OSD_COLOR_MATRIX_32_ARGB; 162 break; 163 case DRM_FORMAT_RGB888: 164 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 | 165 OSD_COLOR_MATRIX_24_RGB; 166 break; 167 case DRM_FORMAT_RGB565: 168 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 | 169 OSD_COLOR_MATRIX_16_RGB565; 170 break; 171 }; 172 173 /* Default scaler parameters */ 174 vsc_bot_rcv_num = 0; 175 vsc_bot_rpt_p0_num = 0; 176 hf_bank_len = 4; 177 vf_bank_len = 4; 178 179 if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) { 180 vsc_bot_rcv_num = 6; 181 vsc_bot_rpt_p0_num = 2; 182 } 183 184 hsc_ini_rcv_num = hf_bank_len; 185 vsc_ini_rcv_num = vf_bank_len; 186 hsc_ini_rpt_p0_num = (hf_bank_len / 2) - 1; 187 vsc_ini_rpt_p0_num = (vf_bank_len / 2) - 1; 188 189 src_w = fixed16_to_int(state->src_w); 190 src_h = fixed16_to_int(state->src_h); 191 dst_w = state->crtc_w; 192 dst_h = state->crtc_h; 193 194 /* 195 * When the output is interlaced, the OSD must switch between 196 * each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0 197 * at each vsync. 198 * But the vertical scaler can provide such funtionnality if 199 * is configured for 2:1 scaling with interlace options enabled. 200 */ 201 if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) { 202 dest.y1 /= 2; 203 dest.y2 /= 2; 204 dst_h /= 2; 205 } 206 207 hf_phase_step = ((src_w << 18) / dst_w) << 6; 208 vf_phase_step = (src_h << 20) / dst_h; 209 210 if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) 211 bot_ini_phase = ((vf_phase_step / 2) >> 4); 212 else 213 bot_ini_phase = 0; 214 215 vf_phase_step = (vf_phase_step << 4); 216 217 /* In interlaced mode, scaler is always active */ 218 if (src_h != dst_h || src_w != dst_w) { 219 priv->viu.osd_sc_i_wh_m1 = SCI_WH_M1_W(src_w - 1) | 220 SCI_WH_M1_H(src_h - 1); 221 priv->viu.osd_sc_o_h_start_end = SCO_HV_START(dest.x1) | 222 SCO_HV_END(dest.x2 - 1); 223 priv->viu.osd_sc_o_v_start_end = SCO_HV_START(dest.y1) | 224 SCO_HV_END(dest.y2 - 1); 225 /* Enable OSD Scaler */ 226 priv->viu.osd_sc_ctrl0 = SC_CTRL0_PATH_EN | SC_CTRL0_SEL_OSD1; 227 } else { 228 priv->viu.osd_sc_i_wh_m1 = 0; 229 priv->viu.osd_sc_o_h_start_end = 0; 230 priv->viu.osd_sc_o_v_start_end = 0; 231 priv->viu.osd_sc_ctrl0 = 0; 232 } 233 234 /* In interlaced mode, vertical scaler is always active */ 235 if (src_h != dst_h) { 236 priv->viu.osd_sc_v_ctrl0 = 237 VSC_BANK_LEN(vf_bank_len) | 238 VSC_TOP_INI_RCV_NUM(vsc_ini_rcv_num) | 239 VSC_TOP_RPT_L0_NUM(vsc_ini_rpt_p0_num) | 240 VSC_VERTICAL_SCALER_EN; 241 242 if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) 243 priv->viu.osd_sc_v_ctrl0 |= 244 VSC_BOT_INI_RCV_NUM(vsc_bot_rcv_num) | 245 VSC_BOT_RPT_L0_NUM(vsc_bot_rpt_p0_num) | 246 VSC_PROG_INTERLACE; 247 248 priv->viu.osd_sc_v_phase_step = SC_PHASE_STEP(vf_phase_step); 249 priv->viu.osd_sc_v_ini_phase = VSC_INI_PHASE_BOT(bot_ini_phase); 250 } else { 251 priv->viu.osd_sc_v_ctrl0 = 0; 252 priv->viu.osd_sc_v_phase_step = 0; 253 priv->viu.osd_sc_v_ini_phase = 0; 254 } 255 256 /* Horizontal scaler is only used if width does not match */ 257 if (src_w != dst_w) { 258 priv->viu.osd_sc_h_ctrl0 = 259 HSC_BANK_LENGTH(hf_bank_len) | 260 HSC_INI_RCV_NUM0(hsc_ini_rcv_num) | 261 HSC_RPT_P0_NUM0(hsc_ini_rpt_p0_num) | 262 HSC_HORIZ_SCALER_EN; 263 priv->viu.osd_sc_h_phase_step = SC_PHASE_STEP(hf_phase_step); 264 priv->viu.osd_sc_h_ini_phase = 0; 265 } else { 266 priv->viu.osd_sc_h_ctrl0 = 0; 267 priv->viu.osd_sc_h_phase_step = 0; 268 priv->viu.osd_sc_h_ini_phase = 0; 269 } 270 271 /* 272 * The format of these registers is (x2 << 16 | x1), 273 * where x2 is exclusive. 274 * e.g. +30x1920 would be (1919 << 16) | 30 275 */ 276 priv->viu.osd1_blk0_cfg[1] = 277 ((fixed16_to_int(state->src.x2) - 1) << 16) | 278 fixed16_to_int(state->src.x1); 279 priv->viu.osd1_blk0_cfg[2] = 280 ((fixed16_to_int(state->src.y2) - 1) << 16) | 281 fixed16_to_int(state->src.y1); 282 priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1; 283 priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1; 284 285 if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { 286 priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1; 287 priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1; 288 priv->viu.osb_blend0_size = dst_h << 16 | dst_w; 289 priv->viu.osb_blend1_size = dst_h << 16 | dst_w; 290 } 291 292 /* Update Canvas with buffer address */ 293 gem = drm_fb_cma_get_gem_obj(fb, 0); 294 295 priv->viu.osd1_addr = gem->paddr; 296 priv->viu.osd1_stride = fb->pitches[0]; 297 priv->viu.osd1_height = fb->height; 298 299 if (!meson_plane->enabled) { 300 /* Reset OSD1 before enabling it on GXL+ SoCs */ 301 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || 302 meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) 303 meson_viu_osd1_reset(priv); 304 305 meson_plane->enabled = true; 306 } 307 308 priv->viu.osd1_enabled = true; 309 310 spin_unlock_irqrestore(&priv->drm->event_lock, flags); 311 } 312 313 static void meson_plane_atomic_disable(struct drm_plane *plane, 314 struct drm_plane_state *old_state) 315 { 316 struct meson_plane *meson_plane = to_meson_plane(plane); 317 struct meson_drm *priv = meson_plane->priv; 318 319 /* Disable OSD1 */ 320 if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) 321 writel_bits_relaxed(3 << 8, 0, 322 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); 323 else 324 writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0, 325 priv->io_base + _REG(VPP_MISC)); 326 327 meson_plane->enabled = false; 328 priv->viu.osd1_enabled = false; 329 } 330 331 static const struct drm_plane_helper_funcs meson_plane_helper_funcs = { 332 .atomic_check = meson_plane_atomic_check, 333 .atomic_disable = meson_plane_atomic_disable, 334 .atomic_update = meson_plane_atomic_update, 335 .prepare_fb = drm_gem_fb_prepare_fb, 336 }; 337 338 static const struct drm_plane_funcs meson_plane_funcs = { 339 .update_plane = drm_atomic_helper_update_plane, 340 .disable_plane = drm_atomic_helper_disable_plane, 341 .destroy = drm_plane_cleanup, 342 .reset = drm_atomic_helper_plane_reset, 343 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 344 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 345 }; 346 347 static const uint32_t supported_drm_formats[] = { 348 DRM_FORMAT_ARGB8888, 349 DRM_FORMAT_XRGB8888, 350 DRM_FORMAT_RGB888, 351 DRM_FORMAT_RGB565, 352 }; 353 354 int meson_plane_create(struct meson_drm *priv) 355 { 356 struct meson_plane *meson_plane; 357 struct drm_plane *plane; 358 359 meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane), 360 GFP_KERNEL); 361 if (!meson_plane) 362 return -ENOMEM; 363 364 meson_plane->priv = priv; 365 plane = &meson_plane->base; 366 367 drm_universal_plane_init(priv->drm, plane, 0xFF, 368 &meson_plane_funcs, 369 supported_drm_formats, 370 ARRAY_SIZE(supported_drm_formats), 371 NULL, 372 DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane"); 373 374 drm_plane_helper_add(plane, &meson_plane_helper_funcs); 375 376 priv->primary_plane = plane; 377 378 return 0; 379 } 380