1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 7 */ 8 9 #ifndef __ADRENO_GPU_H__ 10 #define __ADRENO_GPU_H__ 11 12 #include <linux/firmware.h> 13 #include <linux/iopoll.h> 14 15 #include "msm_gpu.h" 16 17 #include "adreno_common.xml.h" 18 #include "adreno_pm4.xml.h" 19 20 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1 21 #define REG_SKIP ~0 22 #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP 23 24 /** 25 * adreno_regs: List of registers that are used in across all 26 * 3D devices. Each device type has different offset value for the same 27 * register, so an array of register offsets are declared for every device 28 * and are indexed by the enumeration values defined in this enum 29 */ 30 enum adreno_regs { 31 REG_ADRENO_CP_RB_BASE, 32 REG_ADRENO_CP_RB_BASE_HI, 33 REG_ADRENO_CP_RB_RPTR_ADDR, 34 REG_ADRENO_CP_RB_RPTR_ADDR_HI, 35 REG_ADRENO_CP_RB_RPTR, 36 REG_ADRENO_CP_RB_WPTR, 37 REG_ADRENO_CP_RB_CNTL, 38 REG_ADRENO_REGISTER_MAX, 39 }; 40 41 enum { 42 ADRENO_FW_PM4 = 0, 43 ADRENO_FW_SQE = 0, /* a6xx */ 44 ADRENO_FW_PFP = 1, 45 ADRENO_FW_GMU = 1, /* a6xx */ 46 ADRENO_FW_GPMU = 2, 47 ADRENO_FW_MAX, 48 }; 49 50 enum adreno_quirks { 51 ADRENO_QUIRK_TWO_PASS_USE_WFI = 1, 52 ADRENO_QUIRK_FAULT_DETECT_MASK = 2, 53 }; 54 55 struct adreno_rev { 56 uint8_t core; 57 uint8_t major; 58 uint8_t minor; 59 uint8_t patchid; 60 }; 61 62 #define ADRENO_REV(core, major, minor, patchid) \ 63 ((struct adreno_rev){ core, major, minor, patchid }) 64 65 struct adreno_gpu_funcs { 66 struct msm_gpu_funcs base; 67 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); 68 }; 69 70 struct adreno_info { 71 struct adreno_rev rev; 72 uint32_t revn; 73 const char *name; 74 const char *fw[ADRENO_FW_MAX]; 75 uint32_t gmem; 76 enum adreno_quirks quirks; 77 struct msm_gpu *(*init)(struct drm_device *dev); 78 const char *zapfw; 79 u32 inactive_period; 80 }; 81 82 const struct adreno_info *adreno_info(struct adreno_rev rev); 83 84 struct adreno_gpu { 85 struct msm_gpu base; 86 struct adreno_rev rev; 87 const struct adreno_info *info; 88 uint32_t gmem; /* actual gmem size */ 89 uint32_t revn; /* numeric revision name */ 90 const struct adreno_gpu_funcs *funcs; 91 92 /* interesting register offsets to dump: */ 93 const unsigned int *registers; 94 95 /* 96 * Are we loading fw from legacy path? Prior to addition 97 * of gpu firmware to linux-firmware, the fw files were 98 * placed in toplevel firmware directory, following qcom's 99 * android kernel. But linux-firmware preferred they be 100 * placed in a 'qcom' subdirectory. 101 * 102 * For backwards compatibility, we try first to load from 103 * the new path, using request_firmware_direct() to avoid 104 * any potential timeout waiting for usermode helper, then 105 * fall back to the old path (with direct load). And 106 * finally fall back to request_firmware() with the new 107 * path to allow the usermode helper. 108 */ 109 enum { 110 FW_LOCATION_UNKNOWN = 0, 111 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */ 112 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */ 113 FW_LOCATION_HELPER, 114 } fwloc; 115 116 /* firmware: */ 117 const struct firmware *fw[ADRENO_FW_MAX]; 118 119 /* 120 * Register offsets are different between some GPUs. 121 * GPU specific offsets will be exported by GPU specific 122 * code (a3xx_gpu.c) and stored in this common location. 123 */ 124 const unsigned int *reg_offsets; 125 }; 126 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) 127 128 /* platform config data (ie. from DT, or pdata) */ 129 struct adreno_platform_config { 130 struct adreno_rev rev; 131 }; 132 133 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) 134 135 #define spin_until(X) ({ \ 136 int __ret = -ETIMEDOUT; \ 137 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \ 138 do { \ 139 if (X) { \ 140 __ret = 0; \ 141 break; \ 142 } \ 143 } while (time_before(jiffies, __t)); \ 144 __ret; \ 145 }) 146 147 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu) 148 { 149 return (gpu->revn < 300); 150 } 151 152 static inline bool adreno_is_a20x(struct adreno_gpu *gpu) 153 { 154 return (gpu->revn < 210); 155 } 156 157 static inline bool adreno_is_a225(struct adreno_gpu *gpu) 158 { 159 return gpu->revn == 225; 160 } 161 162 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu) 163 { 164 return (gpu->revn >= 300) && (gpu->revn < 400); 165 } 166 167 static inline bool adreno_is_a305(struct adreno_gpu *gpu) 168 { 169 return gpu->revn == 305; 170 } 171 172 static inline bool adreno_is_a306(struct adreno_gpu *gpu) 173 { 174 /* yes, 307, because a305c is 306 */ 175 return gpu->revn == 307; 176 } 177 178 static inline bool adreno_is_a320(struct adreno_gpu *gpu) 179 { 180 return gpu->revn == 320; 181 } 182 183 static inline bool adreno_is_a330(struct adreno_gpu *gpu) 184 { 185 return gpu->revn == 330; 186 } 187 188 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu) 189 { 190 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0); 191 } 192 193 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu) 194 { 195 return (gpu->revn >= 400) && (gpu->revn < 500); 196 } 197 198 static inline int adreno_is_a420(struct adreno_gpu *gpu) 199 { 200 return gpu->revn == 420; 201 } 202 203 static inline int adreno_is_a430(struct adreno_gpu *gpu) 204 { 205 return gpu->revn == 430; 206 } 207 208 static inline int adreno_is_a530(struct adreno_gpu *gpu) 209 { 210 return gpu->revn == 530; 211 } 212 213 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 214 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu, 215 const char *fwname); 216 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 217 const struct firmware *fw, u64 *iova); 218 int adreno_hw_init(struct msm_gpu *gpu); 219 void adreno_recover(struct msm_gpu *gpu); 220 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 221 struct msm_file_private *ctx); 222 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 223 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 224 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 225 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 226 struct drm_printer *p); 227 #endif 228 void adreno_dump_info(struct msm_gpu *gpu); 229 void adreno_dump(struct msm_gpu *gpu); 230 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords); 231 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu); 232 233 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 234 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, 235 int nr_rings); 236 void adreno_gpu_cleanup(struct adreno_gpu *gpu); 237 int adreno_load_fw(struct adreno_gpu *adreno_gpu); 238 239 void adreno_gpu_state_destroy(struct msm_gpu_state *state); 240 241 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state); 242 int adreno_gpu_state_put(struct msm_gpu_state *state); 243 244 /* 245 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU 246 * out of secure mode 247 */ 248 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid); 249 250 /* ringbuffer helpers (the parts that are adreno specific) */ 251 252 static inline void 253 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 254 { 255 adreno_wait_ring(ring, cnt+1); 256 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); 257 } 258 259 /* no-op packet: */ 260 static inline void 261 OUT_PKT2(struct msm_ringbuffer *ring) 262 { 263 adreno_wait_ring(ring, 1); 264 OUT_RING(ring, CP_TYPE2_PKT); 265 } 266 267 static inline void 268 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 269 { 270 adreno_wait_ring(ring, cnt+1); 271 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); 272 } 273 274 static inline u32 PM4_PARITY(u32 val) 275 { 276 return (0x9669 >> (0xF & (val ^ 277 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^ 278 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^ 279 (val >> 28)))) & 1; 280 } 281 282 /* Maximum number of values that can be executed for one opcode */ 283 #define TYPE4_MAX_PAYLOAD 127 284 285 #define PKT4(_reg, _cnt) \ 286 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \ 287 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27)) 288 289 static inline void 290 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 291 { 292 adreno_wait_ring(ring, cnt + 1); 293 OUT_RING(ring, PKT4(regindx, cnt)); 294 } 295 296 static inline void 297 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 298 { 299 adreno_wait_ring(ring, cnt + 1); 300 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | 301 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23)); 302 } 303 304 /* 305 * adreno_reg_check() - Checks the validity of a register enum 306 * @gpu: Pointer to struct adreno_gpu 307 * @offset_name: The register enum that is checked 308 */ 309 static inline bool adreno_reg_check(struct adreno_gpu *gpu, 310 enum adreno_regs offset_name) 311 { 312 if (offset_name >= REG_ADRENO_REGISTER_MAX || 313 !gpu->reg_offsets[offset_name]) { 314 BUG(); 315 } 316 317 /* 318 * REG_SKIP is a special value that tell us that the register in 319 * question isn't implemented on target but don't trigger a BUG(). This 320 * is used to cleanly implement adreno_gpu_write64() and 321 * adreno_gpu_read64() in a generic fashion 322 */ 323 if (gpu->reg_offsets[offset_name] == REG_SKIP) 324 return false; 325 326 return true; 327 } 328 329 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu, 330 enum adreno_regs offset_name) 331 { 332 u32 reg = gpu->reg_offsets[offset_name]; 333 u32 val = 0; 334 if(adreno_reg_check(gpu,offset_name)) 335 val = gpu_read(&gpu->base, reg - 1); 336 return val; 337 } 338 339 static inline void adreno_gpu_write(struct adreno_gpu *gpu, 340 enum adreno_regs offset_name, u32 data) 341 { 342 u32 reg = gpu->reg_offsets[offset_name]; 343 if(adreno_reg_check(gpu, offset_name)) 344 gpu_write(&gpu->base, reg - 1, data); 345 } 346 347 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev); 348 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); 349 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); 350 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev); 351 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev); 352 353 static inline void adreno_gpu_write64(struct adreno_gpu *gpu, 354 enum adreno_regs lo, enum adreno_regs hi, u64 data) 355 { 356 adreno_gpu_write(gpu, lo, lower_32_bits(data)); 357 adreno_gpu_write(gpu, hi, upper_32_bits(data)); 358 } 359 360 static inline uint32_t get_wptr(struct msm_ringbuffer *ring) 361 { 362 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2); 363 } 364 365 /* 366 * Given a register and a count, return a value to program into 367 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 368 * registers starting at _reg. 369 * 370 * The register base needs to be a multiple of the length. If it is not, the 371 * hardware will quietly mask off the bits for you and shift the size. For 372 * example, if you intend the protection to start at 0x07 for a length of 4 373 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might 374 * expose registers you intended to protect! 375 */ 376 #define ADRENO_PROTECT_RW(_reg, _len) \ 377 ((1 << 30) | (1 << 29) | \ 378 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 379 380 /* 381 * Same as above, but allow reads over the range. For areas of mixed use (such 382 * as performance counters) this allows us to protect a much larger range with a 383 * single register 384 */ 385 #define ADRENO_PROTECT_RDONLY(_reg, _len) \ 386 ((1 << 29) \ 387 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 388 389 390 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \ 391 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \ 392 interval, timeout) 393 394 #endif /* __ADRENO_GPU_H__ */ 395