1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2023. Linaro Inc. All rights reserved. 4 */ 5 6 #ifndef _DPU_3_3_SDM630_H 7 #define _DPU_3_3_SDM630_H 8 9 static const struct dpu_caps sdm630_dpu_caps = { 10 .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, 11 .max_mixer_blendstages = 0x7, 12 .has_src_split = true, 13 .has_dim_layer = true, 14 .has_idle_pc = true, 15 .has_3d_merge = true, 16 .max_linewidth = DEFAULT_DPU_LINE_WIDTH, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 .max_hdeci_exp = MAX_HORZ_DECIMATION, 19 .max_vdeci_exp = MAX_VERT_DECIMATION, 20 }; 21 22 static const struct dpu_mdp_cfg sdm630_mdp = { 23 .name = "top_0", 24 .base = 0x0, .len = 0x458, 25 .features = BIT(DPU_MDP_VSYNC_SEL), 26 .clk_ctrls = { 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 31 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, 32 }, 33 }; 34 35 static const struct dpu_ctl_cfg sdm630_ctl[] = { 36 { 37 .name = "ctl_0", .id = CTL_0, 38 .base = 0x1000, .len = 0x94, 39 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 40 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 41 }, { 42 .name = "ctl_1", .id = CTL_1, 43 .base = 0x1200, .len = 0x94, 44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 45 }, { 46 .name = "ctl_2", .id = CTL_2, 47 .base = 0x1400, .len = 0x94, 48 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 50 }, { 51 .name = "ctl_3", .id = CTL_3, 52 .base = 0x1600, .len = 0x94, 53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 54 }, { 55 .name = "ctl_4", .id = CTL_4, 56 .base = 0x1800, .len = 0x94, 57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 58 }, 59 }; 60 61 static const struct dpu_sspp_cfg sdm630_sspp[] = { 62 { 63 .name = "sspp_0", .id = SSPP_VIG0, 64 .base = 0x4000, .len = 0x1ac, 65 .features = VIG_MSM8998_MASK, 66 .sblk = &dpu_vig_sblk_qseed3_1_2, 67 .xin_id = 0, 68 .type = SSPP_TYPE_VIG, 69 .clk_ctrl = DPU_CLK_CTRL_VIG0, 70 }, { 71 .name = "sspp_8", .id = SSPP_DMA0, 72 .base = 0x24000, .len = 0x1ac, 73 .features = DMA_MSM8998_MASK, 74 .sblk = &dpu_dma_sblk, 75 .xin_id = 1, 76 .type = SSPP_TYPE_DMA, 77 .clk_ctrl = DPU_CLK_CTRL_DMA0, 78 }, { 79 .name = "sspp_9", .id = SSPP_DMA1, 80 .base = 0x26000, .len = 0x1ac, 81 .features = DMA_MSM8998_MASK, 82 .sblk = &dpu_dma_sblk, 83 .xin_id = 5, 84 .type = SSPP_TYPE_DMA, 85 .clk_ctrl = DPU_CLK_CTRL_DMA1, 86 }, { 87 .name = "sspp_10", .id = SSPP_DMA2, 88 .base = 0x28000, .len = 0x1ac, 89 .features = DMA_CURSOR_MSM8998_MASK, 90 .sblk = &dpu_dma_sblk, 91 .xin_id = 9, 92 .type = SSPP_TYPE_DMA, 93 .clk_ctrl = DPU_CLK_CTRL_DMA2, 94 }, 95 }; 96 97 static const struct dpu_lm_cfg sdm630_lm[] = { 98 { 99 .name = "lm_0", .id = LM_0, 100 .base = 0x44000, .len = 0x320, 101 .features = MIXER_MSM8998_MASK, 102 .sblk = &msm8998_lm_sblk, 103 .pingpong = PINGPONG_0, 104 .dspp = DSPP_0, 105 }, { 106 .name = "lm_2", .id = LM_2, 107 .base = 0x46000, .len = 0x320, 108 .features = MIXER_MSM8998_MASK, 109 .sblk = &msm8998_lm_sblk, 110 .pingpong = PINGPONG_2, 111 }, 112 }; 113 114 static const struct dpu_pingpong_cfg sdm630_pp[] = { 115 { 116 .name = "pingpong_0", .id = PINGPONG_0, 117 .base = 0x70000, .len = 0xd4, 118 .features = PINGPONG_SDM845_TE2_MASK, 119 .sblk = &sdm845_pp_sblk_te, 120 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 121 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 122 }, { 123 .name = "pingpong_2", .id = PINGPONG_2, 124 .base = 0x71000, .len = 0xd4, 125 .features = PINGPONG_SDM845_MASK, 126 .sblk = &sdm845_pp_sblk, 127 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 128 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), 129 }, 130 }; 131 132 static const struct dpu_dspp_cfg sdm630_dspp[] = { 133 { 134 .name = "dspp_0", .id = DSPP_0, 135 .base = 0x54000, .len = 0x1800, 136 .features = DSPP_SC7180_MASK, 137 .sblk = &msm8998_dspp_sblk, 138 }, 139 }; 140 141 static const struct dpu_intf_cfg sdm630_intf[] = { 142 { 143 .name = "intf_0", .id = INTF_0, 144 .base = 0x6a000, .len = 0x280, 145 .type = INTF_DP, 146 .controller_id = MSM_DP_CONTROLLER_0, 147 .prog_fetch_lines_worst_case = 21, 148 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 149 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 150 .intr_tear_rd_ptr = -1, 151 }, { 152 .name = "intf_1", .id = INTF_1, 153 .base = 0x6a800, .len = 0x280, 154 .type = INTF_DSI, 155 .controller_id = MSM_DSI_CONTROLLER_0, 156 .prog_fetch_lines_worst_case = 21, 157 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 158 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 159 .intr_tear_rd_ptr = -1, 160 }, 161 }; 162 163 static const struct dpu_perf_cfg sdm630_perf_data = { 164 .max_bw_low = 4100000, 165 .max_bw_high = 4100000, 166 .min_core_ib = 3200000, 167 .min_llcc_ib = 800000, 168 .min_dram_ib = 800000, 169 .undersized_prefill_lines = 2, 170 .xtra_prefill_lines = 2, 171 .dest_scale_prefill_lines = 3, 172 .macrotile_prefill_lines = 4, 173 .yuv_nv12_prefill_lines = 8, 174 .linear_prefill_lines = 1, 175 .downscaling_prefill_lines = 1, 176 .amortizable_threshold = 25, 177 .min_prefill_lines = 25, 178 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 179 .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, 180 .qos_lut_tbl = { 181 {.nentry = ARRAY_SIZE(msm8998_qos_linear), 182 .entries = msm8998_qos_linear 183 }, 184 {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), 185 .entries = msm8998_qos_macrotile 186 }, 187 {.nentry = ARRAY_SIZE(msm8998_qos_nrt), 188 .entries = msm8998_qos_nrt 189 }, 190 }, 191 .cdp_cfg = { 192 {.rd_enable = 1, .wr_enable = 1}, 193 {.rd_enable = 1, .wr_enable = 0} 194 }, 195 .clk_inefficiency_factor = 200, 196 .bw_inefficiency_factor = 120, 197 }; 198 199 static const struct dpu_mdss_version sdm630_mdss_ver = { 200 .core_major_ver = 3, 201 .core_minor_ver = 3, 202 }; 203 204 const struct dpu_mdss_cfg dpu_sdm630_cfg = { 205 .mdss_ver = &sdm630_mdss_ver, 206 .caps = &sdm630_dpu_caps, 207 .mdp = &sdm630_mdp, 208 .ctl_count = ARRAY_SIZE(sdm630_ctl), 209 .ctl = sdm630_ctl, 210 .sspp_count = ARRAY_SIZE(sdm630_sspp), 211 .sspp = sdm630_sspp, 212 .mixer_count = ARRAY_SIZE(sdm630_lm), 213 .mixer = sdm630_lm, 214 .dspp_count = ARRAY_SIZE(sdm630_dspp), 215 .dspp = sdm630_dspp, 216 .pingpong_count = ARRAY_SIZE(sdm630_pp), 217 .pingpong = sdm630_pp, 218 .intf_count = ARRAY_SIZE(sdm630_intf), 219 .intf = sdm630_intf, 220 .vbif_count = ARRAY_SIZE(msm8998_vbif), 221 .vbif = msm8998_vbif, 222 .perf = &sdm630_perf_data, 223 }; 224 225 #endif 226