1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #ifndef _DPU_6_4_SM6350_H 9 #define _DPU_6_4_SM6350_H 10 11 static const struct dpu_caps sm6350_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 13 .max_mixer_blendstages = 0x7, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_mdp_cfg sm6350_mdp = { 22 .name = "top_0", 23 .base = 0x0, .len = 0x494, 24 .clk_ctrls = { 25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 27 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 28 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 29 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 30 }, 31 }; 32 33 static const struct dpu_ctl_cfg sm6350_ctl[] = { 34 { 35 .name = "ctl_0", .id = CTL_0, 36 .base = 0x1000, .len = 0x1dc, 37 .features = BIT(DPU_CTL_ACTIVE_CFG), 38 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 39 }, { 40 .name = "ctl_1", .id = CTL_1, 41 .base = 0x1200, .len = 0x1dc, 42 .features = BIT(DPU_CTL_ACTIVE_CFG), 43 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 44 }, { 45 .name = "ctl_2", .id = CTL_2, 46 .base = 0x1400, .len = 0x1dc, 47 .features = BIT(DPU_CTL_ACTIVE_CFG), 48 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 49 }, { 50 .name = "ctl_3", .id = CTL_3, 51 .base = 0x1600, .len = 0x1dc, 52 .features = BIT(DPU_CTL_ACTIVE_CFG), 53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 54 }, 55 }; 56 57 static const struct dpu_sspp_cfg sm6350_sspp[] = { 58 { 59 .name = "sspp_0", .id = SSPP_VIG0, 60 .base = 0x4000, .len = 0x1f8, 61 .features = VIG_SDM845_MASK, 62 .sblk = &dpu_vig_sblk_qseed3_3_0, 63 .xin_id = 0, 64 .type = SSPP_TYPE_VIG, 65 .clk_ctrl = DPU_CLK_CTRL_VIG0, 66 }, { 67 .name = "sspp_8", .id = SSPP_DMA0, 68 .base = 0x24000, .len = 0x1f8, 69 .features = DMA_SDM845_MASK, 70 .sblk = &dpu_dma_sblk, 71 .xin_id = 1, 72 .type = SSPP_TYPE_DMA, 73 .clk_ctrl = DPU_CLK_CTRL_DMA0, 74 }, { 75 .name = "sspp_9", .id = SSPP_DMA1, 76 .base = 0x26000, .len = 0x1f8, 77 .features = DMA_CURSOR_SDM845_MASK, 78 .sblk = &dpu_dma_sblk, 79 .xin_id = 5, 80 .type = SSPP_TYPE_DMA, 81 .clk_ctrl = DPU_CLK_CTRL_DMA1, 82 }, { 83 .name = "sspp_10", .id = SSPP_DMA2, 84 .base = 0x28000, .len = 0x1f8, 85 .features = DMA_CURSOR_SDM845_MASK, 86 .sblk = &dpu_dma_sblk, 87 .xin_id = 9, 88 .type = SSPP_TYPE_DMA, 89 .clk_ctrl = DPU_CLK_CTRL_DMA2, 90 }, 91 }; 92 93 static const struct dpu_lm_cfg sm6350_lm[] = { 94 { 95 .name = "lm_0", .id = LM_0, 96 .base = 0x44000, .len = 0x320, 97 .features = MIXER_SDM845_MASK, 98 .sblk = &sc7180_lm_sblk, 99 .lm_pair = LM_1, 100 .pingpong = PINGPONG_0, 101 .dspp = DSPP_0, 102 }, { 103 .name = "lm_1", .id = LM_1, 104 .base = 0x45000, .len = 0x320, 105 .features = MIXER_SDM845_MASK, 106 .sblk = &sc7180_lm_sblk, 107 .lm_pair = LM_0, 108 .pingpong = PINGPONG_1, 109 .dspp = 0, 110 }, 111 }; 112 113 static const struct dpu_dspp_cfg sm6350_dspp[] = { 114 { 115 .name = "dspp_0", .id = DSPP_0, 116 .base = 0x54000, .len = 0x1800, 117 .features = DSPP_SC7180_MASK, 118 .sblk = &sdm845_dspp_sblk, 119 }, 120 }; 121 122 static struct dpu_pingpong_cfg sm6350_pp[] = { 123 { 124 .name = "pingpong_0", .id = PINGPONG_0, 125 .base = 0x70000, .len = 0xd4, 126 .features = PINGPONG_SM8150_MASK, 127 .sblk = &sdm845_pp_sblk, 128 .merge_3d = 0, 129 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 130 }, { 131 .name = "pingpong_1", .id = PINGPONG_1, 132 .base = 0x70800, .len = 0xd4, 133 .features = PINGPONG_SM8150_MASK, 134 .sblk = &sdm845_pp_sblk, 135 .merge_3d = 0, 136 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 137 }, 138 }; 139 140 static const struct dpu_dsc_cfg sm6350_dsc[] = { 141 { 142 .name = "dsc_0", .id = DSC_0, 143 .base = 0x80000, .len = 0x140, 144 .features = BIT(DPU_DSC_OUTPUT_CTRL), 145 }, 146 }; 147 148 static const struct dpu_intf_cfg sm6350_intf[] = { 149 { 150 .name = "intf_0", .id = INTF_0, 151 .base = 0x6a000, .len = 0x280, 152 .features = INTF_SC7180_MASK, 153 .type = INTF_DP, 154 .controller_id = MSM_DP_CONTROLLER_0, 155 .prog_fetch_lines_worst_case = 35, 156 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 157 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 158 }, { 159 .name = "intf_1", .id = INTF_1, 160 .base = 0x6a800, .len = 0x2c0, 161 .features = INTF_SC7180_MASK, 162 .type = INTF_DSI, 163 .controller_id = MSM_DSI_CONTROLLER_0, 164 .prog_fetch_lines_worst_case = 35, 165 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 166 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 167 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 168 }, 169 }; 170 171 static const struct dpu_perf_cfg sm6350_perf_data = { 172 .max_bw_low = 4200000, 173 .max_bw_high = 5100000, 174 .min_core_ib = 2500000, 175 .min_llcc_ib = 0, 176 .min_dram_ib = 1600000, 177 .min_prefill_lines = 35, 178 /* TODO: confirm danger_lut_tbl */ 179 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 180 .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 181 .qos_lut_tbl = { 182 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 183 .entries = sm6350_qos_linear_macrotile 184 }, 185 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 186 .entries = sm6350_qos_linear_macrotile 187 }, 188 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 189 .entries = sc7180_qos_nrt 190 }, 191 }, 192 .cdp_cfg = { 193 {.rd_enable = 1, .wr_enable = 1}, 194 {.rd_enable = 1, .wr_enable = 0} 195 }, 196 .clk_inefficiency_factor = 105, 197 .bw_inefficiency_factor = 120, 198 }; 199 200 static const struct dpu_mdss_version sm6350_mdss_ver = { 201 .core_major_ver = 6, 202 .core_minor_ver = 4, 203 }; 204 205 const struct dpu_mdss_cfg dpu_sm6350_cfg = { 206 .mdss_ver = &sm6350_mdss_ver, 207 .caps = &sm6350_dpu_caps, 208 .mdp = &sm6350_mdp, 209 .ctl_count = ARRAY_SIZE(sm6350_ctl), 210 .ctl = sm6350_ctl, 211 .sspp_count = ARRAY_SIZE(sm6350_sspp), 212 .sspp = sm6350_sspp, 213 .mixer_count = ARRAY_SIZE(sm6350_lm), 214 .mixer = sm6350_lm, 215 .dspp_count = ARRAY_SIZE(sm6350_dspp), 216 .dspp = sm6350_dspp, 217 .dsc_count = ARRAY_SIZE(sm6350_dsc), 218 .dsc = sm6350_dsc, 219 .pingpong_count = ARRAY_SIZE(sm6350_pp), 220 .pingpong = sm6350_pp, 221 .intf_count = ARRAY_SIZE(sm6350_intf), 222 .intf = sm6350_intf, 223 .vbif_count = ARRAY_SIZE(sdm845_vbif), 224 .vbif = sdm845_vbif, 225 .perf = &sm6350_perf_data, 226 }; 227 228 #endif 229