1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #ifndef _DPU_6_4_SM6350_H 9 #define _DPU_6_4_SM6350_H 10 11 static const struct dpu_caps sm6350_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 13 .max_mixer_blendstages = 0x7, 14 .qseed_type = DPU_SSPP_SCALER_QSEED4, 15 .has_src_split = true, 16 .has_dim_layer = true, 17 .has_idle_pc = true, 18 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 }; 21 22 static const struct dpu_mdp_cfg sm6350_mdp = { 23 .name = "top_0", 24 .base = 0x0, .len = 0x494, 25 .clk_ctrls = { 26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 28 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 29 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 30 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 31 }, 32 }; 33 34 static const struct dpu_ctl_cfg sm6350_ctl[] = { 35 { 36 .name = "ctl_0", .id = CTL_0, 37 .base = 0x1000, .len = 0x1dc, 38 .features = BIT(DPU_CTL_ACTIVE_CFG), 39 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 40 }, { 41 .name = "ctl_1", .id = CTL_1, 42 .base = 0x1200, .len = 0x1dc, 43 .features = BIT(DPU_CTL_ACTIVE_CFG), 44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 45 }, { 46 .name = "ctl_2", .id = CTL_2, 47 .base = 0x1400, .len = 0x1dc, 48 .features = BIT(DPU_CTL_ACTIVE_CFG), 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 50 }, { 51 .name = "ctl_3", .id = CTL_3, 52 .base = 0x1600, .len = 0x1dc, 53 .features = BIT(DPU_CTL_ACTIVE_CFG), 54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 55 }, 56 }; 57 58 static const struct dpu_sspp_cfg sm6350_sspp[] = { 59 { 60 .name = "sspp_0", .id = SSPP_VIG0, 61 .base = 0x4000, .len = 0x1f8, 62 .features = VIG_SC7180_MASK, 63 .sblk = &sc7180_vig_sblk_0, 64 .xin_id = 0, 65 .type = SSPP_TYPE_VIG, 66 .clk_ctrl = DPU_CLK_CTRL_VIG0, 67 }, { 68 .name = "sspp_8", .id = SSPP_DMA0, 69 .base = 0x24000, .len = 0x1f8, 70 .features = DMA_SDM845_MASK, 71 .sblk = &sdm845_dma_sblk_0, 72 .xin_id = 1, 73 .type = SSPP_TYPE_DMA, 74 .clk_ctrl = DPU_CLK_CTRL_DMA0, 75 }, { 76 .name = "sspp_9", .id = SSPP_DMA1, 77 .base = 0x26000, .len = 0x1f8, 78 .features = DMA_CURSOR_SDM845_MASK, 79 .sblk = &sdm845_dma_sblk_1, 80 .xin_id = 5, 81 .type = SSPP_TYPE_DMA, 82 .clk_ctrl = DPU_CLK_CTRL_DMA1, 83 }, { 84 .name = "sspp_10", .id = SSPP_DMA2, 85 .base = 0x28000, .len = 0x1f8, 86 .features = DMA_CURSOR_SDM845_MASK, 87 .sblk = &sdm845_dma_sblk_2, 88 .xin_id = 9, 89 .type = SSPP_TYPE_DMA, 90 .clk_ctrl = DPU_CLK_CTRL_DMA2, 91 }, 92 }; 93 94 static const struct dpu_lm_cfg sm6350_lm[] = { 95 { 96 .name = "lm_0", .id = LM_0, 97 .base = 0x44000, .len = 0x320, 98 .features = MIXER_SDM845_MASK, 99 .sblk = &sc7180_lm_sblk, 100 .lm_pair = LM_1, 101 .pingpong = PINGPONG_0, 102 .dspp = DSPP_0, 103 }, { 104 .name = "lm_1", .id = LM_1, 105 .base = 0x45000, .len = 0x320, 106 .features = MIXER_SDM845_MASK, 107 .sblk = &sc7180_lm_sblk, 108 .lm_pair = LM_0, 109 .pingpong = PINGPONG_1, 110 .dspp = 0, 111 }, 112 }; 113 114 static const struct dpu_dspp_cfg sm6350_dspp[] = { 115 { 116 .name = "dspp_0", .id = DSPP_0, 117 .base = 0x54000, .len = 0x1800, 118 .features = DSPP_SC7180_MASK, 119 .sblk = &sdm845_dspp_sblk, 120 }, 121 }; 122 123 static struct dpu_pingpong_cfg sm6350_pp[] = { 124 { 125 .name = "pingpong_0", .id = PINGPONG_0, 126 .base = 0x70000, .len = 0xd4, 127 .features = PINGPONG_SM8150_MASK, 128 .sblk = &sdm845_pp_sblk, 129 .merge_3d = 0, 130 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 131 .intr_rdptr = -1, 132 }, { 133 .name = "pingpong_1", .id = PINGPONG_1, 134 .base = 0x70800, .len = 0xd4, 135 .features = PINGPONG_SM8150_MASK, 136 .sblk = &sdm845_pp_sblk, 137 .merge_3d = 0, 138 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 139 .intr_rdptr = -1, 140 }, 141 }; 142 143 static const struct dpu_dsc_cfg sm6350_dsc[] = { 144 { 145 .name = "dsc_0", .id = DSC_0, 146 .base = 0x80000, .len = 0x140, 147 .features = BIT(DPU_DSC_OUTPUT_CTRL), 148 }, 149 }; 150 151 static const struct dpu_intf_cfg sm6350_intf[] = { 152 { 153 .name = "intf_0", .id = INTF_0, 154 .base = 0x6a000, .len = 0x280, 155 .features = INTF_SC7180_MASK, 156 .type = INTF_DP, 157 .controller_id = MSM_DP_CONTROLLER_0, 158 .prog_fetch_lines_worst_case = 35, 159 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 160 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 161 .intr_tear_rd_ptr = -1, 162 }, { 163 .name = "intf_1", .id = INTF_1, 164 .base = 0x6a800, .len = 0x2c0, 165 .features = INTF_SC7180_MASK, 166 .type = INTF_DSI, 167 .controller_id = MSM_DSI_CONTROLLER_0, 168 .prog_fetch_lines_worst_case = 35, 169 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 170 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 171 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 172 }, 173 }; 174 175 static const struct dpu_perf_cfg sm6350_perf_data = { 176 .max_bw_low = 4200000, 177 .max_bw_high = 5100000, 178 .min_core_ib = 2500000, 179 .min_llcc_ib = 0, 180 .min_dram_ib = 1600000, 181 .min_prefill_lines = 35, 182 /* TODO: confirm danger_lut_tbl */ 183 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 184 .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 185 .qos_lut_tbl = { 186 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 187 .entries = sm6350_qos_linear_macrotile 188 }, 189 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 190 .entries = sm6350_qos_linear_macrotile 191 }, 192 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 193 .entries = sc7180_qos_nrt 194 }, 195 }, 196 .cdp_cfg = { 197 {.rd_enable = 1, .wr_enable = 1}, 198 {.rd_enable = 1, .wr_enable = 0} 199 }, 200 .clk_inefficiency_factor = 105, 201 .bw_inefficiency_factor = 120, 202 }; 203 204 static const struct dpu_mdss_version sm6350_mdss_ver = { 205 .core_major_ver = 6, 206 .core_minor_ver = 4, 207 }; 208 209 const struct dpu_mdss_cfg dpu_sm6350_cfg = { 210 .mdss_ver = &sm6350_mdss_ver, 211 .caps = &sm6350_dpu_caps, 212 .mdp = &sm6350_mdp, 213 .ctl_count = ARRAY_SIZE(sm6350_ctl), 214 .ctl = sm6350_ctl, 215 .sspp_count = ARRAY_SIZE(sm6350_sspp), 216 .sspp = sm6350_sspp, 217 .mixer_count = ARRAY_SIZE(sm6350_lm), 218 .mixer = sm6350_lm, 219 .dspp_count = ARRAY_SIZE(sm6350_dspp), 220 .dspp = sm6350_dspp, 221 .dsc_count = ARRAY_SIZE(sm6350_dsc), 222 .dsc = sm6350_dsc, 223 .pingpong_count = ARRAY_SIZE(sm6350_pp), 224 .pingpong = sm6350_pp, 225 .intf_count = ARRAY_SIZE(sm6350_intf), 226 .intf = sm6350_intf, 227 .vbif_count = ARRAY_SIZE(sdm845_vbif), 228 .vbif = sdm845_vbif, 229 .perf = &sm6350_perf_data, 230 }; 231 232 #endif 233