1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_7_2_SC7280_H 8 #define _DPU_7_2_SC7280_H 9 10 static const struct dpu_caps sc7280_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0x7, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = 2400, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 }; 19 20 static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = { 21 .ubwc_version = DPU_HW_UBWC_VER_30, 22 .highest_bank_bit = 0x1, 23 .ubwc_swizzle = 0x6, 24 }; 25 26 static const struct dpu_mdp_cfg sc7280_mdp[] = { 27 { 28 .name = "top_0", .id = MDP_TOP, 29 .base = 0x0, .len = 0x2014, 30 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 31 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 32 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 33 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 34 }, 35 }; 36 37 static const struct dpu_ctl_cfg sc7280_ctl[] = { 38 { 39 .name = "ctl_0", .id = CTL_0, 40 .base = 0x15000, .len = 0x1e8, 41 .features = CTL_SC7280_MASK, 42 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 43 }, 44 { 45 .name = "ctl_1", .id = CTL_1, 46 .base = 0x16000, .len = 0x1e8, 47 .features = CTL_SC7280_MASK, 48 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 49 }, 50 { 51 .name = "ctl_2", .id = CTL_2, 52 .base = 0x17000, .len = 0x1e8, 53 .features = CTL_SC7280_MASK, 54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 55 }, 56 { 57 .name = "ctl_3", .id = CTL_3, 58 .base = 0x18000, .len = 0x1e8, 59 .features = CTL_SC7280_MASK, 60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 61 }, 62 }; 63 64 static const struct dpu_sspp_cfg sc7280_sspp[] = { 65 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK_SDMA, 66 sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 67 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA, 68 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 69 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, 70 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 71 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, 72 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 73 }; 74 75 static const struct dpu_lm_cfg sc7280_lm[] = { 76 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 77 &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0), 78 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 79 &sc7180_lm_sblk, PINGPONG_2, LM_3, 0), 80 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 81 &sc7180_lm_sblk, PINGPONG_3, LM_2, 0), 82 }; 83 84 static const struct dpu_dspp_cfg sc7280_dspp[] = { 85 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 86 &sc7180_dspp_sblk), 87 }; 88 89 static const struct dpu_pingpong_cfg sc7280_pp[] = { 90 PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1), 91 PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), 92 PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), 93 PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), 94 }; 95 96 static const struct dpu_intf_cfg sc7280_intf[] = { 97 INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 98 INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 99 INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), 100 }; 101 102 static const struct dpu_perf_cfg sc7280_perf_data = { 103 .max_bw_low = 4700000, 104 .max_bw_high = 8800000, 105 .min_core_ib = 2500000, 106 .min_llcc_ib = 0, 107 .min_dram_ib = 1600000, 108 .min_prefill_lines = 24, 109 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 110 .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 111 .qos_lut_tbl = { 112 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 113 .entries = sc7180_qos_macrotile 114 }, 115 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 116 .entries = sc7180_qos_macrotile 117 }, 118 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 119 .entries = sc7180_qos_nrt 120 }, 121 }, 122 .cdp_cfg = { 123 {.rd_enable = 1, .wr_enable = 1}, 124 {.rd_enable = 1, .wr_enable = 0} 125 }, 126 .clk_inefficiency_factor = 105, 127 .bw_inefficiency_factor = 120, 128 }; 129 130 const struct dpu_mdss_cfg dpu_sc7280_cfg = { 131 .caps = &sc7280_dpu_caps, 132 .ubwc = &sc7280_ubwc_cfg, 133 .mdp_count = ARRAY_SIZE(sc7280_mdp), 134 .mdp = sc7280_mdp, 135 .ctl_count = ARRAY_SIZE(sc7280_ctl), 136 .ctl = sc7280_ctl, 137 .sspp_count = ARRAY_SIZE(sc7280_sspp), 138 .sspp = sc7280_sspp, 139 .dspp_count = ARRAY_SIZE(sc7280_dspp), 140 .dspp = sc7280_dspp, 141 .mixer_count = ARRAY_SIZE(sc7280_lm), 142 .mixer = sc7280_lm, 143 .pingpong_count = ARRAY_SIZE(sc7280_pp), 144 .pingpong = sc7280_pp, 145 .intf_count = ARRAY_SIZE(sc7280_intf), 146 .intf = sc7280_intf, 147 .vbif_count = ARRAY_SIZE(sdm845_vbif), 148 .vbif = sdm845_vbif, 149 .perf = &sc7280_perf_data, 150 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 151 BIT(MDP_SSPP_TOP0_INTR2) | \ 152 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 153 BIT(MDP_INTF0_7xxx_INTR) | \ 154 BIT(MDP_INTF1_7xxx_INTR) | \ 155 BIT(MDP_INTF5_7xxx_INTR), 156 }; 157 158 #endif 159