1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_7_2_SC7280_H 8 #define _DPU_7_2_SC7280_H 9 10 static const struct dpu_caps sc7280_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0x7, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = 2400, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 }; 19 20 static const struct dpu_mdp_cfg sc7280_mdp = { 21 .name = "top_0", 22 .base = 0x0, .len = 0x2014, 23 .clk_ctrls = { 24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 26 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 27 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 28 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, 29 }, 30 }; 31 32 static const struct dpu_ctl_cfg sc7280_ctl[] = { 33 { 34 .name = "ctl_0", .id = CTL_0, 35 .base = 0x15000, .len = 0x1e8, 36 .features = CTL_SC7280_MASK, 37 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 38 }, { 39 .name = "ctl_1", .id = CTL_1, 40 .base = 0x16000, .len = 0x1e8, 41 .features = CTL_SC7280_MASK, 42 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 43 }, { 44 .name = "ctl_2", .id = CTL_2, 45 .base = 0x17000, .len = 0x1e8, 46 .features = CTL_SC7280_MASK, 47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 48 }, { 49 .name = "ctl_3", .id = CTL_3, 50 .base = 0x18000, .len = 0x1e8, 51 .features = CTL_SC7280_MASK, 52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 53 }, 54 }; 55 56 static const struct dpu_sspp_cfg sc7280_sspp[] = { 57 { 58 .name = "sspp_0", .id = SSPP_VIG0, 59 .base = 0x4000, .len = 0x1f8, 60 .features = VIG_SC7280_MASK_SDMA, 61 .sblk = &sc7280_vig_sblk_0, 62 .xin_id = 0, 63 .type = SSPP_TYPE_VIG, 64 .clk_ctrl = DPU_CLK_CTRL_VIG0, 65 }, { 66 .name = "sspp_8", .id = SSPP_DMA0, 67 .base = 0x24000, .len = 0x1f8, 68 .features = DMA_SDM845_MASK_SDMA, 69 .sblk = &sdm845_dma_sblk_0, 70 .xin_id = 1, 71 .type = SSPP_TYPE_DMA, 72 .clk_ctrl = DPU_CLK_CTRL_DMA0, 73 }, { 74 .name = "sspp_9", .id = SSPP_DMA1, 75 .base = 0x26000, .len = 0x1f8, 76 .features = DMA_CURSOR_SDM845_MASK_SDMA, 77 .sblk = &sdm845_dma_sblk_1, 78 .xin_id = 5, 79 .type = SSPP_TYPE_DMA, 80 .clk_ctrl = DPU_CLK_CTRL_DMA1, 81 }, { 82 .name = "sspp_10", .id = SSPP_DMA2, 83 .base = 0x28000, .len = 0x1f8, 84 .features = DMA_CURSOR_SDM845_MASK_SDMA, 85 .sblk = &sdm845_dma_sblk_2, 86 .xin_id = 9, 87 .type = SSPP_TYPE_DMA, 88 .clk_ctrl = DPU_CLK_CTRL_DMA2, 89 }, 90 }; 91 92 static const struct dpu_lm_cfg sc7280_lm[] = { 93 { 94 .name = "lm_0", .id = LM_0, 95 .base = 0x44000, .len = 0x320, 96 .features = MIXER_SDM845_MASK, 97 .sblk = &sc7180_lm_sblk, 98 .pingpong = PINGPONG_0, 99 .dspp = DSPP_0, 100 }, { 101 .name = "lm_2", .id = LM_2, 102 .base = 0x46000, .len = 0x320, 103 .features = MIXER_SDM845_MASK, 104 .sblk = &sc7180_lm_sblk, 105 .lm_pair = LM_3, 106 .pingpong = PINGPONG_2, 107 }, { 108 .name = "lm_3", .id = LM_3, 109 .base = 0x47000, .len = 0x320, 110 .features = MIXER_SDM845_MASK, 111 .sblk = &sc7180_lm_sblk, 112 .lm_pair = LM_2, 113 .pingpong = PINGPONG_3, 114 }, 115 }; 116 117 static const struct dpu_dspp_cfg sc7280_dspp[] = { 118 { 119 .name = "dspp_0", .id = DSPP_0, 120 .base = 0x54000, .len = 0x1800, 121 .features = DSPP_SC7180_MASK, 122 .sblk = &sdm845_dspp_sblk, 123 }, 124 }; 125 126 static const struct dpu_pingpong_cfg sc7280_pp[] = { 127 { 128 .name = "pingpong_0", .id = PINGPONG_0, 129 .base = 0x69000, .len = 0, 130 .features = BIT(DPU_PINGPONG_DITHER), 131 .sblk = &sc7280_pp_sblk, 132 .merge_3d = 0, 133 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 134 }, { 135 .name = "pingpong_1", .id = PINGPONG_1, 136 .base = 0x6a000, .len = 0, 137 .features = BIT(DPU_PINGPONG_DITHER), 138 .sblk = &sc7280_pp_sblk, 139 .merge_3d = 0, 140 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 141 }, { 142 .name = "pingpong_2", .id = PINGPONG_2, 143 .base = 0x6b000, .len = 0, 144 .features = BIT(DPU_PINGPONG_DITHER), 145 .sblk = &sc7280_pp_sblk, 146 .merge_3d = 0, 147 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 148 }, { 149 .name = "pingpong_3", .id = PINGPONG_3, 150 .base = 0x6c000, .len = 0, 151 .features = BIT(DPU_PINGPONG_DITHER), 152 .sblk = &sc7280_pp_sblk, 153 .merge_3d = 0, 154 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 155 }, 156 }; 157 158 /* NOTE: sc7280 only has one DSC hard slice encoder */ 159 static const struct dpu_dsc_cfg sc7280_dsc[] = { 160 { 161 .name = "dce_0_0", .id = DSC_0, 162 .base = 0x80000, .len = 0x4, 163 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 164 .sblk = &dsc_sblk_0, 165 }, 166 }; 167 168 static const struct dpu_wb_cfg sc7280_wb[] = { 169 { 170 .name = "wb_2", .id = WB_2, 171 .base = 0x65000, .len = 0x2c8, 172 .features = WB_SM8250_MASK, 173 .format_list = wb2_formats, 174 .num_formats = ARRAY_SIZE(wb2_formats), 175 .clk_ctrl = DPU_CLK_CTRL_WB2, 176 .xin_id = 6, 177 .vbif_idx = VBIF_RT, 178 .maxlinewidth = 4096, 179 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 180 }, 181 }; 182 183 static const struct dpu_intf_cfg sc7280_intf[] = { 184 { 185 .name = "intf_0", .id = INTF_0, 186 .base = 0x34000, .len = 0x280, 187 .features = INTF_SC7280_MASK, 188 .type = INTF_DP, 189 .controller_id = MSM_DP_CONTROLLER_0, 190 .prog_fetch_lines_worst_case = 24, 191 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 192 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 193 }, { 194 .name = "intf_1", .id = INTF_1, 195 .base = 0x35000, .len = 0x2c4, 196 .features = INTF_SC7280_MASK, 197 .type = INTF_DSI, 198 .controller_id = MSM_DSI_CONTROLLER_0, 199 .prog_fetch_lines_worst_case = 24, 200 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 201 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 202 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 203 }, { 204 .name = "intf_5", .id = INTF_5, 205 .base = 0x39000, .len = 0x280, 206 .features = INTF_SC7280_MASK, 207 .type = INTF_DP, 208 .controller_id = MSM_DP_CONTROLLER_1, 209 .prog_fetch_lines_worst_case = 24, 210 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), 211 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), 212 }, 213 }; 214 215 static const struct dpu_perf_cfg sc7280_perf_data = { 216 .max_bw_low = 4700000, 217 .max_bw_high = 8800000, 218 .min_core_ib = 2500000, 219 .min_llcc_ib = 0, 220 .min_dram_ib = 1600000, 221 .min_prefill_lines = 24, 222 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 223 .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 224 .qos_lut_tbl = { 225 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 226 .entries = sc7180_qos_macrotile 227 }, 228 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 229 .entries = sc7180_qos_macrotile 230 }, 231 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 232 .entries = sc7180_qos_nrt 233 }, 234 }, 235 .cdp_cfg = { 236 {.rd_enable = 1, .wr_enable = 1}, 237 {.rd_enable = 1, .wr_enable = 0} 238 }, 239 .clk_inefficiency_factor = 105, 240 .bw_inefficiency_factor = 120, 241 }; 242 243 static const struct dpu_mdss_version sc7280_mdss_ver = { 244 .core_major_ver = 7, 245 .core_minor_ver = 2, 246 }; 247 248 const struct dpu_mdss_cfg dpu_sc7280_cfg = { 249 .mdss_ver = &sc7280_mdss_ver, 250 .caps = &sc7280_dpu_caps, 251 .mdp = &sc7280_mdp, 252 .ctl_count = ARRAY_SIZE(sc7280_ctl), 253 .ctl = sc7280_ctl, 254 .sspp_count = ARRAY_SIZE(sc7280_sspp), 255 .sspp = sc7280_sspp, 256 .dspp_count = ARRAY_SIZE(sc7280_dspp), 257 .dspp = sc7280_dspp, 258 .mixer_count = ARRAY_SIZE(sc7280_lm), 259 .mixer = sc7280_lm, 260 .pingpong_count = ARRAY_SIZE(sc7280_pp), 261 .pingpong = sc7280_pp, 262 .dsc_count = ARRAY_SIZE(sc7280_dsc), 263 .dsc = sc7280_dsc, 264 .wb_count = ARRAY_SIZE(sc7280_wb), 265 .wb = sc7280_wb, 266 .intf_count = ARRAY_SIZE(sc7280_intf), 267 .intf = sc7280_intf, 268 .vbif_count = ARRAY_SIZE(sdm845_vbif), 269 .vbif = sdm845_vbif, 270 .perf = &sc7280_perf_data, 271 }; 272 273 #endif 274